From 4aa3b5158f0e70e83cfe44dae79cd75110c52eb7 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 30 Oct 2017 17:08:45 -0400 Subject: Update gpgpusim.config --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'configs/PascalTitanX') diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 2f09ab6..7dfd6d5 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -36,8 +36,8 @@ ## Pascal GP102 has 4 SP SIMD units and 4 SFU units ## we need to scale the number of pipeline registers to be equal to the number of SP units -gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 2 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 -gpgpu_num_dp_units 1 # Instruction latencies and initiation intervals -- cgit v1.3