From 4505c33872fc5c665bee0060be1fdbfa8c77fdb6 Mon Sep 17 00:00:00 2001 From: "Andrew M. B. Boktor" Date: Sat, 5 May 2012 10:50:00 -0800 Subject: Configuring the opcode latencies and the number of function units [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12323] --- configs/QuadroFX5800/gpgpusim.config | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'configs/QuadroFX5800') diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index e14d2f1..1dc09eb 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -13,7 +13,22 @@ -gpgpu_shader_registers 16384 -gpgpu_shader_core_pipeline 1024:32 -gpgpu_shader_cta 8 --gpgpu_simd_model 1 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,1,1,1,1,1,1 +-gpgpu_num_sp_units 1 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 1,1,19,25,145 +-ptx_opcode_initiation_int 1,1,4,4,32 +-ptx_opcode_latency_fp 1,1,1,1,30 +-ptx_opcode_initiation_fp 1,1,1,1,5 +-ptx_opcode_latency_dp 8,8,8,8,335 +-ptx_opcode_initiation_dp 8,8,8,8,130 # memory stage behaviour -gpgpu_cache:il1 4:256:4:L:R:f,A:2:32,4 -- cgit v1.3