From dad9e2a5cfb0f1f49279a6d2746454dd32f6eb85 Mon Sep 17 00:00:00 2001 From: Wilson Fung Date: Mon, 18 Jun 2012 21:59:31 -0800 Subject: Fixed GDDR5 parameters in Fermi config: - Increased burst length to 8 and changed address mapping to reflect 16 banks as suggested by Jungrae. - Decreased the DRAM clock to 924MHz from 1848MHz. - Corrected CAS Latency and Write Latency in the timing constraints. - Added a new option 'dram_data_command_freq_ratio' to configure the frequency ratio between the DRAM data bus and command bus. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13138] --- configs/QuadroFX5800/gpgpusim.config | 1 + 1 file changed, 1 insertion(+) (limited to 'configs/QuadroFX5800') diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index ad1b022..47d3a64 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -49,6 +49,7 @@ -gpgpu_n_mem_per_ctrlr 2 -gpgpu_dram_buswidth 4 -gpgpu_dram_burst_length 4 +-dram_data_command_freq_ratio 2 # GDDR3 is DDR -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS # GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz -- cgit v1.3