From d212d7e5fdcc9f8e10779d5cfb398a451f8ad033 Mon Sep 17 00:00:00 2001 From: boyealKim Date: Sun, 21 Jul 2019 02:28:59 +0900 Subject: take account of shfl latency --- configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'configs/tested-cfgs/SM6_TITANX/gpgpusim.config') diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index 2fe898a..da1af48 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -56,11 +56,11 @@ # Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" +# "ADD,MAX,MUL,MAD,DIV,SHFL" # All Div operations are executed on SFU unit # Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 1,1,1,1,4,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 -- cgit v1.3