From 301be9e59c6c934f4e194cf6c95dd0c60b3894cc Mon Sep 17 00:00:00 2001 From: Fangjia Shen <50934207+FJShen@users.noreply.github.com> Date: Sat, 17 Jun 2023 19:03:31 -0400 Subject: 137 drop sector cache flexibility (#57) Addresses accel-sim issue 137. For sector cache, the sector size must be 32B (hard-coded and not configurable) and cache line size must be set to 128B; a runtime parameter check will terminate simulation if the cache line size is not 128B. --- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs/tested-cfgs/SM75_RTX2060/gpgpusim.config') diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 158b97e..6ff4b6c 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -83,7 +83,7 @@ -gpgpu_dual_issue_diff_exec_units 1 ## L1/shared memory configuration -# ::,::::,::,:** +# :::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo # In adaptive cache, we adaptively assign the remaining shared memory to L1 cache # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x -- cgit v1.3