From b2def455d573f66fbc38dabda4adbc3a56225910 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Sun, 9 Feb 2020 20:39:22 -0500 Subject: adding kepler sass, skip-first-kernel and update config file --- configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'configs/tested-cfgs/SM7_QV100_SASS') diff --git a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config index 0d4a812..ba50287 100644 --- a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config @@ -20,7 +20,6 @@ -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 -gpgpu_kernel_launch_latency 5000 --gpgpu_TB_launch_latency 0 # Compute Capability -gpgpu_compute_capability_major 7 @@ -166,7 +165,7 @@ -gpgpu_dram_burst_length 2 -dram_data_command_freq_ratio 2 # HBM is DDR -gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@6;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.CBCSSSSS +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS # HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) # Timing for 1 GHZ -- cgit v1.3