From 84213ffa0416139c7711eb0784b8a46b0de8c538 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 22 May 2020 20:16:04 -0400 Subject: code reformatting --- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 205 ------------------------- 1 file changed, 205 deletions(-) delete mode 100644 configs/tested-cfgs/SM7_TITANV/gpgpusim.config (limited to 'configs/tested-cfgs/SM7_TITANV/gpgpusim.config') diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config deleted file mode 100644 index 0339b0d..0000000 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ /dev/null @@ -1,205 +0,0 @@ -# This config models the Volta Titan V -# For more info about volta architecture: -# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf -# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) -# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf -# https://devblogs.nvidia.com/inside-volta/ -# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 - - -# Device Limits --gpgpu_stack_size_limit 1024 --gpgpu_heap_size_limit 8388608 --gpgpu_runtime_sync_depth_limit 2 --gpgpu_runtime_pending_launch_count_limit 2048 - -# Compute Capability --gpgpu_compute_capability_major 7 --gpgpu_compute_capability_minor 0 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 40 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 24 --gpgpu_n_sub_partition_per_mchannel 2 - -# volta clock domains -#-gpgpu_clock_domains ::: -# Volta NVIDIA TITANV clock domains are adopted from -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) --gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0 -# boost mode -# -gpgpu_clock_domains 1455.0:1455.0:1455.0:850.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 --gpgpu_registers_per_block 65536 --gpgpu_occupancy_sm_number 70 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE -## Volta TITANV has 4 SP SIMD units, 4 INT units, 4 SFU units, 4 DP units per core, 4 Tensor core units -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 4 --gpgpu_num_int_units 4 --gpgpu_tensor_core_avail 1 --gpgpu_num_tensor_core_units 4 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 2,2,2,2,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,4,4,4,130 --ptx_opcode_latency_sfu 100 --ptx_opcode_initiation_sfu 8 --ptx_opcode_latency_tesnor 64 --ptx_opcode_initiation_tensor 64 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Defualt config is 32KB DL1 and 96KB shared memory -# In Volta, we assign the remaining shared memory to L1 cache -# if the assigned shd mem = 0, then L1 cache = 128KB -# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x -# disable this mode in case of multi kernels/apps execution --adaptive_cache_config 1 -# Volta unified cache has four banks --l1_banks 4 -#-mem_unit_ports 4 --gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_shmem_size 98304 --gpgpu_shmem_sizeDefault 98304 --gpgpu_shmem_per_block 65536 --gmem_skip_L1D 0 --icnt_flit_size 40 --gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 20 --smem_latency 20 --gpgpu_flush_l1_cache 1 - -# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache --gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 1 --memory_partition_indexing 4 - -# 128 KB Inst. --gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 -# 48 KB Tex -# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod --gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 -# 64 KB Const --gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 - -# Volta has sub core model, in which each scheduler has its own register file and EUs -# i.e. schedulers are isolated --sub_core_model 1 -# disable specialized operand collectors and use generic operand collectors instead --enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 8 --gpgpu_operand_collector_num_in_ports_gen 8 --gpgpu_operand_collector_num_out_ports_gen 8 -# volta has 8 banks, 4 schedulers, two banks per scheduler --gpgpu_num_reg_banks 8 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Volta, a warp scheduler can issue 1 inst per cycle --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 - -# interconnection --network_mode 1 --inter_config_file config_volta_islip.icnt -# for local xbar, use: -# "-network_mode 2 -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 -inct_subnets 2" - -# memory partition latency config --rop_latency 160 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 - -# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 # HBM is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS - -# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) -# Timing for 1 GHZ -# tRRDl and tWTR are missing, need to be added -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: -# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" - -# Timing for 850 MHZ, TITANV HBM runs at 850 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3" - -# HBM has dual bus interface, in which it can issue two col and row commands at a time --dual_bus_interface 1 -# select lower bits for bnkgrp to increase bnkgrp parallelism --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Volta has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model for Volta --power_simulation_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - -- cgit v1.3 From 90a36a59f5619790b7f6d80375f69d05a75c0a82 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Sat, 23 May 2020 21:08:12 -0400 Subject: adding back titianC --- .../tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 4 +- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 4 +- .../tested-cfgs/SM7_TITANV/config_volta_islip.icnt | 74 ++++++++++++++++++++++ configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 18 ++++-- 4 files changed, 89 insertions(+), 11 deletions(-) create mode 100644 configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt (limited to 'configs/tested-cfgs/SM7_TITANV/gpgpusim.config') diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config index b7c0edc..9d0862a 100644 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -58,8 +58,8 @@ # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit # Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 1,1,1,1,4,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 75b3c99..5d23d1a 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -61,8 +61,8 @@ # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 2,2,2,2,8,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 2,2,2,2,4 -ptx_opcode_latency_dp 8,19,8,8,330 diff --git a/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt new file mode 100644 index 0000000..615d0a9 --- /dev/null +++ b/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt @@ -0,0 +1,74 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 88; +n = 1; + +// Routing + +routing_function = dest_tag; + + +// Flow control + +num_vcs = 1; +vc_buf_size = 256; +input_buffer_size = 256; +ejection_buffer_size = 256; +boundary_buffer_size = 256; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index eece246..b5f88ce 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -70,8 +70,8 @@ # All Div operations are executed on SFU unit # Throughput (initiation latency) are adopted from # http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 2,2,2,2,8,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 2,2,2,2,4 -ptx_opcode_latency_dp 8,19,8,8,330 @@ -124,7 +124,6 @@ -gpgpu_adaptive_cache_config 1 # Volta unified cache has four banks -gpgpu_l1_banks 4 -#-mem_unit_ports 4 -gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 @@ -153,11 +152,15 @@ -gpgpu_perfect_inst_const_cache 1 # interconnection --network_mode 1 --inter_config_file config_volta_islip.icnt +#-network_mode 1 +#-inter_config_file config_volta_islip.icnt +# use built-in local xbar +-network_mode 2 +-icnt_in_buffer_limit 512 +-icnt_out_buffer_limit 512 +-icnt_subnets 2 -icnt_flit_size 40 -# for local xbar, use: -# "-network_mode 2 -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 -inct_subnets 2" +-icnt_arbiter_algo 1 # memory partition latency config -gpgpu_l2_rop_latency 160 @@ -209,3 +212,4 @@ #-trace_components WARP_SCHEDULER,SCOREBOARD #-trace_sampling_core 0 + -- cgit v1.3 From 6b72554af7018a8dc42e607f6983a070fe5e5a42 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 28 May 2020 09:05:56 -0400 Subject: splitting execution-driven and trace-driven config files --- configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 5 ----- configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config | 4 ++++ configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 7 ------- configs/tested-cfgs/SM6_TITANX/trace.config | 4 ++++ configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 8 -------- configs/tested-cfgs/SM75_RTX2060/trace.config | 5 +++++ configs/tested-cfgs/SM7_QV100/gpgpusim.config | 8 -------- configs/tested-cfgs/SM7_QV100/trace.config | 6 ++++++ configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 8 -------- configs/tested-cfgs/SM7_TITANV/trace.config | 6 ++++++ 10 files changed, 25 insertions(+), 36 deletions(-) create mode 100644 configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config create mode 100644 configs/tested-cfgs/SM6_TITANX/trace.config create mode 100644 configs/tested-cfgs/SM75_RTX2060/trace.config create mode 100644 configs/tested-cfgs/SM7_QV100/trace.config create mode 100644 configs/tested-cfgs/SM7_TITANV/trace.config (limited to 'configs/tested-cfgs/SM7_TITANV/gpgpusim.config') diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config index 9d0862a..b173dd0 100644 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -67,11 +67,6 @@ -ptx_opcode_initiation_sfu 2 -ptx_opcode_latency_sfu 200 --trace_opcode_latency_initiation_int 4,1 --trace_opcode_latency_initiation_sp 4,1 --trace_opcode_latency_initiation_dp 20,2 --trace_opcode_latency_initiation_sfu 200,2 - # enable operand collector -gpgpu_operand_collector_num_units_sp 12 -gpgpu_operand_collector_num_units_sfu 6 diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config new file mode 100644 index 0000000..4c80036 --- /dev/null +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config @@ -0,0 +1,4 @@ +-trace_opcode_latency_initiation_int 4,1 +-trace_opcode_latency_initiation_sp 4,1 +-trace_opcode_latency_initiation_dp 20,2 +-trace_opcode_latency_initiation_sfu 200,2 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index a686238..ce6f745 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -22,8 +22,6 @@ # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 -# SASS trace-driven mode execution -#-trace_driven_mode 1 # high level architecture configuration -gpgpu_n_clusters 28 @@ -66,11 +64,6 @@ -ptx_opcode_initiation_sfu 4 -ptx_opcode_latency_sfu 20 --trace_opcode_latency_initiation_int 4,1 --trace_opcode_latency_initiation_sp 4,1 --trace_opcode_latency_initiation_dp 20,8 --trace_opcode_latency_initiation_sfu 20,4 - # in sub_core_model, schedulers are isolated, each scheduler has its own register file and EUs -gpgpu_sub_core_model 1 # enable operand collector diff --git a/configs/tested-cfgs/SM6_TITANX/trace.config b/configs/tested-cfgs/SM6_TITANX/trace.config new file mode 100644 index 0000000..88bcdc0 --- /dev/null +++ b/configs/tested-cfgs/SM6_TITANX/trace.config @@ -0,0 +1,4 @@ +-trace_opcode_latency_initiation_int 4,1 +-trace_opcode_latency_initiation_sp 4,1 +-trace_opcode_latency_initiation_dp 20,8 +-trace_opcode_latency_initiation_sfu 20,4 diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 5d23d1a..8a4be23 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -22,8 +22,6 @@ # PTX execution-driven -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 -# SASS trace-driven mode execution -#-trace_driven_mode 1 # high level architecture configuration -gpgpu_n_clusters 30 @@ -72,12 +70,6 @@ -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 --trace_opcode_latency_initiation_int 4,2 --trace_opcode_latency_initiation_sp 4,2 --trace_opcode_latency_initiation_dp 8,4 --trace_opcode_latency_initiation_sfu 20,8 --trace_opcode_latency_initiation_tensor 8,4 - # Turing has four schedulers per core -gpgpu_num_sched_per_core 4 # Greedy then oldest scheduler diff --git a/configs/tested-cfgs/SM75_RTX2060/trace.config b/configs/tested-cfgs/SM75_RTX2060/trace.config new file mode 100644 index 0000000..41987cf --- /dev/null +++ b/configs/tested-cfgs/SM75_RTX2060/trace.config @@ -0,0 +1,5 @@ +-trace_opcode_latency_initiation_int 4,2 +-trace_opcode_latency_initiation_sp 4,2 +-trace_opcode_latency_initiation_dp 8,4 +-trace_opcode_latency_initiation_sfu 20,8 +-trace_opcode_latency_initiation_tensor 8,4 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 5856e5d..c31c060 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -28,8 +28,6 @@ # PTX execution-driven -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 -# SASS trace-driven mode support -#-trace_driven_mode 1 # high level architecture configuration -gpgpu_n_clusters 80 @@ -79,12 +77,6 @@ -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 --trace_opcode_latency_initiation_int 4,2 --trace_opcode_latency_initiation_sp 4,2 --trace_opcode_latency_initiation_dp 8,4 --trace_opcode_latency_initiation_sfu 20,8 --trace_opcode_latency_initiation_tensor 8,4 - # Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated -gpgpu_sub_core_model 1 diff --git a/configs/tested-cfgs/SM7_QV100/trace.config b/configs/tested-cfgs/SM7_QV100/trace.config new file mode 100644 index 0000000..04ac009 --- /dev/null +++ b/configs/tested-cfgs/SM7_QV100/trace.config @@ -0,0 +1,6 @@ +-trace_opcode_latency_initiation_int 4,2 +-trace_opcode_latency_initiation_sp 4,2 +-trace_opcode_latency_initiation_dp 8,4 +-trace_opcode_latency_initiation_sfu 20,8 +-trace_opcode_latency_initiation_tensor 8,4 + diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index b5f88ce..ef28dd8 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -26,8 +26,6 @@ # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 -# SASS trace-driven mode support -#-trace_driven_mode 1 # high level architecture configuration -gpgpu_n_clusters 40 @@ -81,12 +79,6 @@ -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 --trace_opcode_latency_initiation_int 4,2 --trace_opcode_latency_initiation_sp 4,2 --trace_opcode_latency_initiation_dp 8,4 --trace_opcode_latency_initiation_sfu 20,8 --trace_opcode_latency_initiation_tensor 8,4 - # Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated -gpgpu_sub_core_model 1 diff --git a/configs/tested-cfgs/SM7_TITANV/trace.config b/configs/tested-cfgs/SM7_TITANV/trace.config new file mode 100644 index 0000000..04ac009 --- /dev/null +++ b/configs/tested-cfgs/SM7_TITANV/trace.config @@ -0,0 +1,6 @@ +-trace_opcode_latency_initiation_int 4,2 +-trace_opcode_latency_initiation_sp 4,2 +-trace_opcode_latency_initiation_dp 8,4 +-trace_opcode_latency_initiation_sfu 20,8 +-trace_opcode_latency_initiation_tensor 8,4 + -- cgit v1.3 From 3e580ee62a9cc8010930f692d8a6201a31ed77e0 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 1 Jun 2020 14:56:30 -0400 Subject: moving all ipoly equstions to one file --- .../tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 2 +- configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 2 +- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 4 +- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 2 +- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- src/gpgpu-sim/addrdec.cc | 149 ++++++--------------- src/gpgpu-sim/addrdec.h | 2 + src/gpgpu-sim/dram.cc | 24 +--- src/gpgpu-sim/gpu-cache.cc | 97 ++++++-------- src/gpgpu-sim/gpu-cache.h | 26 ++-- src/gpgpu-sim/gpu-sim.cc | 6 + 11 files changed, 116 insertions(+), 200 deletions(-) (limited to 'configs/tested-cfgs/SM7_TITANV/gpgpusim.config') diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config index b173dd0..c83159f 100644 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -120,7 +120,7 @@ -gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 1.5MB L2 cache --gpgpu_cache:dl2 S:32:128:16,L:B:m:L:L,A:256:64,16:0,32 +-gpgpu_cache:dl2 S:32:128:16,L:B:m:L:P,A:256:64,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 -gpgpu_perf_sim_memcpy 1 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index ce6f745..5b243a5 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -115,7 +115,7 @@ -gpgpu_flush_l1_cache 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 S:1:128:1024,L:B:m:L:L,A:256:64,16:0,32 +-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:256:64,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 -gpgpu_perf_sim_memcpy 1 diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 8a4be23..6fe04ee 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -111,8 +111,8 @@ -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 -# 32 sets, each 128 bytes 32-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache --gpgpu_cache:dl2 S:32:128:32,L:B:m:L:L,A:192:4,32:0,32 +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives us 3MB L2 cache +-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:192:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -gpgpu_perf_sim_memcpy 1 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index c31c060..c4818d1 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -126,7 +126,7 @@ -gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache --gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 +-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -gpgpu_perf_sim_memcpy 1 diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index ef28dd8..64edc67 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -127,7 +127,7 @@ -gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache --gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 +-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -gpgpu_perf_sim_memcpy 1 diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc index 91ba47f..c01b8fa 100644 --- a/src/gpgpu-sim/addrdec.cc +++ b/src/gpgpu-sim/addrdec.cc @@ -31,9 +31,12 @@ #include #include "../option_parser.h" #include "gpu-sim.h" +#include "hashing.h" static long int powli(long int x, long int y); static unsigned int LOGB2_32(unsigned int v); +static unsigned next_powerOf2(unsigned n); + static new_addr_type addrdec_packbits(new_addr_type mask, new_addr_type val, unsigned char high, unsigned char low); static void addrdec_getmasklimit(new_addr_type mask, unsigned char *high, @@ -133,121 +136,29 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, break; case BITWISE_PERMUTATION: { assert(!gap); - tlx->chip = (tlx->chip) ^ (rest_of_addr_high_bits & (m_n_channel - 1)); + tlx->chip = + bitwise_hash_function(rest_of_addr_high_bits, tlx->chip, m_n_channel); assert(tlx->chip < m_n_channel); break; } case IPOLY: { - /* - * Set Indexing function from "Pseudo-randomly interleaved memory." - * Rau, B. R et al. - * ISCA 1991 - * http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=348DEA37A3E440473B3C075EAABC63B6?doi=10.1.1.12.7149&rep=rep1&type=pdf - * - * equations are corresponding to IPOLY(37) and are adopted from: - * "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu - * cache management scheme." Khairy et al. IEEE TPDS 2017. - * - * equations for 32 banks are corresponding to IPOLY(37) - * equations for 64 banks are corresponding to IPOLY(67) - * To see all the IPOLY equations for all the degrees, see - * http://wireless-systems.ece.gatech.edu/6604/handouts/Peterson's%20Table.pdf - * - * We generate these equations using GF(2) arithmetic: - * http://www.ee.unb.ca/cgi-bin/tervo/calc.pl?num=&den=&f=d&e=1&m=1 - * - * We go through all the strides 128 (10000000), 256 (100000000),... and - * do modular arithmetic in GF(2) Then, we create the H-matrix and group - * each bit together, for more info read the ISCA 1991 paper - * - * IPOLY hashing guarantees conflict-free for all 2^n strides which widely - * exit in GPGPU applications and also show good performance for other - * strides. - */ - assert(!gap); - if (m_n_channel == 32 && m_n_sub_partition_in_channel == 1) { - std::bitset<64> a(rest_of_addr_high_bits); - std::bitset<5> chip(tlx->chip); - chip[0] = a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[6] ^ a[5] ^ a[3] ^ - a[0] ^ chip[0]; - chip[1] = a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[6] ^ a[4] ^ - a[1] ^ chip[1]; - chip[2] = a[14] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[3] ^ a[2] ^ - a[0] ^ chip[2]; - chip[3] = - a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[4] ^ a[3] ^ a[1] ^ chip[3]; - chip[4] = - a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ a[2] ^ chip[4]; - tlx->chip = chip.to_ulong(); - break; - } else if (m_n_channel == 16 && m_n_sub_partition_in_channel == 2) { - std::bitset<64> a(rest_of_addr_high_bits); - std::bitset<4> chip(tlx->chip); - std::bitset<32> bk(tlx->bk); - chip[0] = a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[6] ^ a[5] ^ a[3] ^ - a[0] ^ chip[0]; - chip[1] = a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[6] ^ a[4] ^ - a[1] ^ chip[1]; - chip[2] = a[14] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[3] ^ a[2] ^ - a[0] ^ chip[2]; - chip[3] = - a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[4] ^ a[3] ^ a[1] ^ chip[3]; - tlx->chip = chip.to_ulong(); - unsigned par_id = - a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ a[2] ^ bk[0]; - tlx->sub_partition = tlx->chip * m_n_sub_partition_in_channel + par_id; - assert(tlx->chip < m_n_channel); - assert(tlx->sub_partition < m_n_channel * m_n_sub_partition_in_channel); - return; - break; - } else if (m_n_channel == 32 && m_n_sub_partition_in_channel == 2) { - std::bitset<64> a(rest_of_addr_high_bits); - std::bitset<5> chip(tlx->chip); - std::bitset<32> bk(tlx->bk); - chip[0] = a[18] ^ a[17] ^ a[16] ^ a[15] ^ a[12] ^ a[10] ^ a[6] ^ a[5] ^ - a[0] ^ chip[0]; - chip[1] = a[15] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[5] ^ a[1] ^ - a[0] ^ chip[1]; - chip[2] = a[16] ^ a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[8] ^ a[6] ^ a[2] ^ - a[1] ^ chip[2]; - chip[3] = a[17] ^ a[15] ^ a[14] ^ a[13] ^ a[12] ^ a[9] ^ a[7] ^ a[3] ^ - a[2] ^ chip[3]; - chip[4] = a[18] ^ a[16] ^ a[15] ^ a[14] ^ a[13] ^ a[10] ^ a[8] ^ a[4] ^ - a[3] ^ chip[4]; - tlx->chip = chip.to_ulong(); - unsigned par_id = - a[17] ^ a[16] ^ a[15] ^ a[14] ^ a[11] ^ a[9] ^ a[5] ^ a[4] ^ bk[0]; - tlx->sub_partition = tlx->chip * m_n_sub_partition_in_channel + par_id; - assert(tlx->chip < m_n_channel); - assert(tlx->sub_partition < m_n_channel * m_n_sub_partition_in_channel); - return; - break; - } else { /* Else incorrect number of channels for the hashing function */ - assert( - "\nGPGPU-Sim memory_partition_indexing error: The number of " - "channels should be " - "32 or 64 for the hashing IPOLY index function.\n" && - 0); - } - assert(tlx->chip < m_n_channel); - break; - } - case PAE: { - // Page Address Entropy - // random selected bits from the page and bank bits - // similar to - // Liu, Yuxi, et al. "Get Out of the Valley: Power-Efficient Address - assert(!gap); - std::bitset<64> a(tlx->row); - std::bitset<5> chip(tlx->chip); - std::bitset<4> b(tlx->bk); - chip[0] = a[13] ^ a[10] ^ a[9] ^ a[5] ^ a[0] ^ b[3] ^ b[0] ^ chip[0]; - chip[1] = a[12] ^ a[11] ^ a[6] ^ a[1] ^ b[3] ^ b[2] ^ b[1] ^ chip[1]; - chip[2] = a[14] ^ a[9] ^ a[8] ^ a[7] ^ a[2] ^ b[1] ^ chip[2]; - chip[3] = a[11] ^ a[10] ^ a[8] ^ a[3] ^ b[2] ^ b[3] ^ chip[3]; - chip[4] = a[12] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ b[1] ^ b[0] ^ chip[4]; - tlx->chip = chip.to_ulong(); + // assert(!gap); + unsigned sub_partition_addr_mask = m_n_sub_partition_in_channel - 1; + unsigned sub_partition = tlx->chip * m_n_sub_partition_in_channel + + (tlx->bk & sub_partition_addr_mask); + sub_partition = ipoly_hash_function( + rest_of_addr_high_bits, sub_partition, + nextPowerOf2_m_n_channel * m_n_sub_partition_in_channel); + + if (gap) // if it is not 2^n partitions, then take modular + sub_partition = + sub_partition % (m_n_channel * m_n_sub_partition_in_channel); + + tlx->chip = sub_partition / m_n_channel; + tlx->sub_partition = sub_partition; assert(tlx->chip < m_n_channel); + assert(tlx->sub_partition < m_n_channel * m_n_sub_partition_in_channel); + return; break; } case RANDOM: { @@ -377,6 +288,8 @@ void linear_to_raw_address_translation::init( log2sub_partition = ::LOGB2_32(n_sub_partition_in_channel); m_n_channel = n_channel; m_n_sub_partition_in_channel = n_sub_partition_in_channel; + nextPowerOf2_m_n_channel = ::next_powerOf2(n_channel); + m_n_sub_partition_total = n_channel * n_sub_partition_in_channel; gap = (n_channel - ::powli(2, nchipbits)); if (gap) { @@ -663,6 +576,22 @@ static unsigned int LOGB2_32(unsigned int v) { return r; } +// compute power of two greater than or equal to n +// https://www.techiedelight.com/round-next-highest-power-2/ +unsigned next_powerOf2(unsigned n) { + // decrement n (to handle the case when n itself + // is a power of 2) + n = n - 1; + + // do till only one bit is left + while (n & n - 1) n = n & (n - 1); // unset rightmost bit + + // n is now a power of two (less than n) + + // return next power of 2 + return n << 1; +} + static new_addr_type addrdec_packbits(new_addr_type mask, new_addr_type val, unsigned char high, unsigned char low) { unsigned pos = 0; diff --git a/src/gpgpu-sim/addrdec.h b/src/gpgpu-sim/addrdec.h index dd0e5a0..d8db416 100644 --- a/src/gpgpu-sim/addrdec.h +++ b/src/gpgpu-sim/addrdec.h @@ -87,8 +87,10 @@ class linear_to_raw_address_translation { unsigned int gap; unsigned m_n_channel; int m_n_sub_partition_in_channel; + int m_n_sub_partition_total; unsigned log2channel; unsigned log2sub_partition; + unsigned nextPowerOf2_m_n_channel; }; #endif diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 041cfce..ca47c46 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -31,6 +31,7 @@ #include "dram_sched.h" #include "gpu-misc.h" #include "gpu-sim.h" +#include "hashing.h" #include "l2cache.h" #include "mem_fetch.h" #include "mem_latency_stat.h" @@ -207,8 +208,8 @@ dram_req_t::dram_req_t(class mem_fetch *mf, unsigned banks, } case BITWISE_XORING_BK_INDEX: { // xoring bank bits with lower bits of the page - int lbank = LOGB2(banks); - bk = tlx.bk ^ (tlx.row & ((1 << lbank) - 1)); + bk = bitwise_hash_function(tlx.row, tlx.bk, banks); + assert(bk < banks); break; } case IPOLY_BK_INDEX: { @@ -216,22 +217,9 @@ dram_req_t::dram_req_t(class mem_fetch *mf, unsigned banks, * memory." Rau, B. R et al. ISCA 1991 * http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=348DEA37A3E440473B3C075EAABC63B6?doi=10.1.1.12.7149&rep=rep1&type=pdf */ - if (banks == 16) { - std::bitset<64> a(tlx.row); - std::bitset<4> b(tlx.bk); - b[0] = a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[6] ^ a[4] ^ a[3] ^ a[0] ^ b[0]; - b[1] = a[12] ^ a[8] ^ a[7] ^ a[6] ^ a[5] ^ a[3] ^ a[1] ^ a[0] ^ b[1]; - b[2] = a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[4] ^ a[2] ^ a[1] ^ b[2]; - b[3] = a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[5] ^ a[3] ^ a[2] ^ b[3]; - bk = b.to_ulong(); - assert(bk < banks); - } else { /* Else incorrect number of channels for the hashing function */ - assert( - "\nGPGPU-Sim memory_banking indexing error: The number of banks " - "should be " - "16 for the hashing IPOLY index function.\n" && - 0); - } + // xoring bank bits with lower bits of the page + bk = ipoly_hash_function(tlx.row, tlx.bk, banks); + assert(bk < banks); break; } case CUSTOM_BK_INDEX: diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index adce3a2..75c3691 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -29,6 +29,7 @@ #include "gpu-cache.h" #include #include "gpu-sim.h" +#include "hashing.h" #include "stat-tool.h" // used to allocate memory that is large enough to adapt the changes in cache @@ -62,24 +63,31 @@ unsigned l1d_cache_config::set_bank(new_addr_type addr) const { // For sector cache, we select one sector per bank (sector interleaving) // This is what was found in Volta (one sector per bank, sector interleaving) // otherwise, line interleaving - if (m_cache_type == SECTOR) - return (addr >> m_sector_sz_log2) & (l1_banks - 1); - else - return (addr >> m_line_sz_log2) & (l1_banks - 1); + return cache_config::hash_function(addr, l1_banks, l1_banks_byte_interleaving, + m_l1_banks_log2, + l1_banks_hashing_function); +} + +unsigned cache_config::set_index(new_addr_type addr) const { + return cache_config::hash_function(addr, m_nset, m_line_sz_log2, m_nset_log2, + m_set_index_function); } -unsigned l1d_cache_config::set_index(new_addr_type addr) const { - unsigned set_index = m_nset; // Default to linear set index function - unsigned lower_xor = 0; - unsigned upper_xor = 0; +unsigned cache_config::hash_function(new_addr_type addr, unsigned m_nset, + unsigned m_line_sz_log2, + unsigned m_nset_log2, + unsigned m_index_function) const { + unsigned set_index = 0; - switch (m_set_index_function) { - case FERMI_HASH_SET_FUNCTION: - case BITWISE_XORING_FUNCTION: + switch (m_index_function) { + case FERMI_HASH_SET_FUNCTION: { /* * Set Indexing function from "A Detailed GPU Cache Model Based on Reuse * Distance Theory" Cedric Nugteren et al. HPCA 2014 */ + unsigned lower_xor = 0; + unsigned upper_xor = 0; + if (m_nset == 32 || m_nset == 64) { // Lower xor value is bits 7-11 lower_xor = (addr >> m_line_sz_log2) & 0x1F; @@ -102,54 +110,34 @@ unsigned l1d_cache_config::set_index(new_addr_type addr) const { 0); } break; + } - case HASH_IPOLY_FUNCTION: - /* - * Set Indexing function from "Pseudo-randomly interleaved memory." - * Rau, B. R et al. - * ISCA 1991 - * - * "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu - * cache management scheme." Khairy et al. IEEE TPDS 2017. - */ - if (m_nset == 32 || m_nset == 64) { - std::bitset<64> a(addr); - std::bitset<6> index; - index[0] = a[25] ^ a[24] ^ a[23] ^ a[22] ^ a[21] ^ a[18] ^ a[17] ^ - a[15] ^ a[12] ^ a[7]; // 10 - index[1] = a[26] ^ a[25] ^ a[24] ^ a[23] ^ a[22] ^ a[19] ^ a[18] ^ - a[16] ^ a[13] ^ a[8]; // 10 - index[2] = a[26] ^ a[22] ^ a[21] ^ a[20] ^ a[19] ^ a[18] ^ a[15] ^ - a[14] ^ a[12] ^ a[9]; // 10 - index[3] = a[23] ^ a[22] ^ a[21] ^ a[20] ^ a[19] ^ a[16] ^ a[15] ^ - a[13] ^ a[10]; // 9 - index[4] = a[24] ^ a[23] ^ a[22] ^ a[21] ^ a[20] ^ a[17] ^ a[16] ^ - a[14] ^ a[11]; // 9 - - if (m_nset == 64) index[5] = a[12]; - - set_index = index.to_ulong(); - - } else { /* Else incorrect number of sets for the hashing function */ - assert( - "\nGPGPU-Sim cache configuration error: The number of sets should " - "be " - "32 or 64 for the hashing set index function.\n" && - 0); - } + case BITWISE_XORING_FUNCTION: { + new_addr_type higher_bits = addr >> (m_line_sz_log2 + m_nset_log2); + unsigned index = (addr >> m_line_sz_log2) & (m_nset - 1); + set_index = bitwise_hash_function(higher_bits, index, m_nset); break; - - case CUSTOM_SET_FUNCTION: + } + case HASH_IPOLY_FUNCTION: { + new_addr_type higher_bits = addr >> (m_line_sz_log2 + m_nset_log2); + unsigned index = (addr >> m_line_sz_log2) & (m_nset - 1); + set_index = ipoly_hash_function(higher_bits, index, m_nset); + break; + } + case CUSTOM_SET_FUNCTION: { /* No custom set function implemented */ break; + } - case LINEAR_SET_FUNCTION: + case LINEAR_SET_FUNCTION: { set_index = (addr >> m_line_sz_log2) & (m_nset - 1); break; + } - default: + default: { assert("\nUndefined set index function.\n" && 0); break; + } } // Linear function selected or custom set index function not implemented @@ -166,13 +154,14 @@ void l2_cache_config::init(linear_to_raw_address_translation *address_mapping) { } unsigned l2_cache_config::set_index(new_addr_type addr) const { - if (!m_address_mapping) { - return (addr >> m_line_sz_log2) & (m_nset - 1); - } else { + new_addr_type part_addr = addr; + + if (m_address_mapping) { // Calculate set index without memory partition bits to reduce set camping - new_addr_type part_addr = m_address_mapping->partition_address(addr); - return (part_addr >> m_line_sz_log2) & (m_nset - 1); + part_addr = m_address_mapping->partition_address(addr); } + + return cache_config::set_index(part_addr); } tag_array::~tag_array() { diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 2a37876..5c28b41 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -686,17 +686,11 @@ class cache_config { m_line_sz * m_nset * m_assoc, m_nset, m_assoc, m_line_sz); } - virtual unsigned set_index(new_addr_type addr) const { - if (m_set_index_function != LINEAR_SET_FUNCTION) { - printf( - "\nGPGPU-Sim cache configuration error: Hashing or " - "custom set index function selected in configuration " - "file for a cache that has not overloaded the set_index " - "function\n"); - abort(); - } - return (addr >> m_line_sz_log2) & (m_nset - 1); - } + virtual unsigned set_index(new_addr_type addr) const; + + unsigned hash_function(new_addr_type addr, unsigned m_nset, + unsigned m_line_sz_log2, unsigned m_nset_log2, + unsigned m_index_function) const; new_addr_type tag(new_addr_type addr) const { // For generality, the tag includes both index and tag. This allows for more @@ -793,10 +787,18 @@ class cache_config { class l1d_cache_config : public cache_config { public: l1d_cache_config() : cache_config() {} - virtual unsigned set_index(new_addr_type addr) const; unsigned set_bank(new_addr_type addr) const; + void init(char *config, FuncCache status) { + m_banks_byte_interleaving_log2 = LOGB2(l1_banks_byte_interleaving); + m_l1_banks_log2 = LOGB2(l1_banks); + cache_config::init(config, status); + } unsigned l1_latency; unsigned l1_banks; + unsigned m_l1_banks_log2; + unsigned l1_banks_byte_interleaving; + unsigned m_banks_byte_interleaving_log2; + unsigned l1_banks_hashing_function; }; class l2_cache_config : public cache_config { diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 03aebf3..1650688 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -252,6 +252,12 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32, &m_L1D_config.l1_banks, "The number of L1 cache banks", "1"); + option_parser_register(opp, "-gpgpu_l1_banks_byte_interleaving", OPT_UINT32, + &m_L1D_config.l1_banks_byte_interleaving, + "l1 banks byte interleaving granularity", "32"); + option_parser_register(opp, "-gpgpu_l1_banks_hashing_function", OPT_UINT32, + &m_L1D_config.l1_banks_hashing_function, + "l1 banks hashing function", "0"); option_parser_register(opp, "-gpgpu_l1_latency", OPT_UINT32, &m_L1D_config.l1_latency, "L1 Hit Latency", "1"); option_parser_register(opp, "-gpgpu_smem_latency", OPT_UINT32, &smem_latency, -- cgit v1.3 From ee3c46354c5ce758bf71cfb7bd2e7da7718bcc8a Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 1 Jun 2020 15:09:34 -0400 Subject: renaming the executable --- Makefile | 6 +- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- src/trace-driven/gpgpusim_trace_driven_main.cc | 163 ------------------------- src/trace-driven/main.cc | 163 +++++++++++++++++++++++++ 4 files changed, 167 insertions(+), 167 deletions(-) delete mode 100644 src/trace-driven/gpgpusim_trace_driven_main.cc create mode 100644 src/trace-driven/main.cc (limited to 'configs/tested-cfgs/SM7_TITANV/gpgpusim.config') diff --git a/Makefile b/Makefile index ee48514..feb9dd0 100644 --- a/Makefile +++ b/Makefile @@ -75,7 +75,7 @@ else TARGETS += $(SIM_LIB_DIR)/libOpenCL.so endif TARGETS += cuobjdump_to_ptxplus/cuobjdump_to_ptxplus - TARGETS += $(SIM_LIB_DIR)/gpgpusim.out + TARGETS += $(SIM_LIB_DIR)/accelsim.out MCPAT= MCPAT_OBJ_DIR= @@ -171,7 +171,7 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.10.1 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.10.1; fi -$(SIM_LIB_DIR)/gpgpusim.out: makedirs $(LIBS) cudalib $(SIM_LIB_DIR)/libcudart.so +$(SIM_LIB_DIR)/accelsim.out: makedirs $(LIBS) cudalib $(SIM_LIB_DIR)/libcudart.so ar rvs $(SIM_LIB_DIR)/libgpgpusim_static.a\ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/*.o \ @@ -181,7 +181,7 @@ $(SIM_LIB_DIR)/gpgpusim.out: makedirs $(LIBS) cudalib $(SIM_LIB_DIR)/libcudart.s $(SIM_OBJ_FILES_DIR)/trace-driven/*.o \ $(SIM_OBJ_FILES_DIR)/*.o \ $(MCPAT) - g++ -std=c++0x -o $(SIM_LIB_DIR)/gpgpusim.out src/trace-driven/gpgpusim_trace_driven_main.cc -L$(SIM_LIB_DIR) -I$(CUDA_INSTALL_PATH)/include -lgpgpusim_static -lm -lz -lGL -pthread + g++ -std=c++0x -o $(SIM_LIB_DIR)/accelsim.out src/trace-driven/main.cc -L$(SIM_LIB_DIR) -I$(CUDA_INSTALL_PATH)/include -lgpgpusim_static -lm -lz -lGL -pthread $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 64edc67..3fa51ee 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -131,7 +131,7 @@ -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -gpgpu_perf_sim_memcpy 1 --gpgpu_memory_partition_indexing 0 +-gpgpu_memory_partition_indexing 2 # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc deleted file mode 100644 index f12d39a..0000000 --- a/src/trace-driven/gpgpusim_trace_driven_main.cc +++ /dev/null @@ -1,163 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ -// abdallm@purdue.edu - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../../libcuda/gpgpu_context.h" -#include "../abstract_hardware_model.h" -#include "../cuda-sim/cuda-sim.h" -#include "../gpgpu-sim/gpu-sim.h" -#include "../gpgpu-sim/icnt_wrapper.h" -#include "../gpgpusim_entrypoint.h" -#include "../option_parser.h" -#include "ISA_Def/trace_opcode.h" -#include "trace_driven.h" - -/* TO DO: - * NOTE: the current version of trace-driven is functionally working fine, - * but we still need to improve traces compression and simulation speed. - * This includes: - * 1- Prefetch concurrent thread that prefetches traces from disk (to not be - * limited by disk speed) 2- traces compression format a. cfg format and remove - * thread/block Id from the head b. using zlib library to save in binary format - * - * 3- Efficient memory improvement (save string not objects - parse only 10 in - * the buffer) 4- Seeking capability - thread scheduler (save tb index and warp - * index info in the traces header) 5- Get rid off traces intermediate files - - * change the tracer - */ -gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[], - gpgpu_context* m_gpgpu_context, - class trace_config* m_config); - -int main(int argc, const char** argv) { - gpgpu_context* m_gpgpu_context = new gpgpu_context(); - trace_config tconfig; - - gpgpu_sim* m_gpgpu_sim = - gpgpu_trace_sim_init_perf_model(argc, argv, m_gpgpu_context, &tconfig); - m_gpgpu_sim->init(); - - // for each kernel - // load file - // parse and create kernel info - // launch - // while loop till the end of the end kernel execution - // prints stats - - trace_parser tracer(tconfig.get_traces_filename(), m_gpgpu_sim, - m_gpgpu_context); - tconfig.parse_config(); - - std::vector commandlist = tracer.parse_kernellist_file(); - - for (unsigned i = 0; i < commandlist.size(); ++i) { - trace_kernel_info_t* kernel_info = NULL; - if (commandlist[i].substr(0, 6) == "Memcpy") { - size_t addre, Bcount; - tracer.parse_memcpy_info(commandlist[i], addre, Bcount); - std::cout << commandlist[i] << std::endl; - m_gpgpu_sim->perf_memcpy_to_gpu(addre, Bcount); - continue; - } else { - kernel_info = tracer.parse_kernel_info(commandlist[i], &tconfig); - m_gpgpu_sim->launch(kernel_info); - } - - bool active = false; - bool sim_cycles = false; - bool break_limit = false; - - do { - if (!m_gpgpu_sim->active()) break; - - // performance simulation - if (m_gpgpu_sim->active()) { - m_gpgpu_sim->cycle(); - sim_cycles = true; - m_gpgpu_sim->deadlock_check(); - } else { - if (m_gpgpu_sim->cycle_insn_cta_max_hit()) { - m_gpgpu_context->the_gpgpusim->g_stream_manager - ->stop_all_running_kernels(); - break_limit = true; - } - } - - active = m_gpgpu_sim->active(); - - } while (active); - - if (kernel_info) { - tracer.kernel_finalizer(kernel_info); - m_gpgpu_sim->print_stats(); - } - - if (sim_cycles) { - m_gpgpu_sim->update_stats(); - m_gpgpu_context->print_simulation_time(); - } - - if (break_limit) { - printf( - "GPGPU-Sim: ** break due to reaching the maximum cycles (or " - "instructions) **\n"); - fflush(stdout); - exit(1); - } - } - - // we print this message to inform the gpgpu-simulation stats_collect script - // that we are done - printf("GPGPU-Sim: *** simulation thread exiting ***\n"); - printf("GPGPU-Sim: *** exit detected ***\n"); - - return 1; -} - -gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[], - gpgpu_context* m_gpgpu_context, - trace_config* m_config) { - srand(1); - print_splash(); - - option_parser_t opp = option_parser_create(); - - m_gpgpu_context->ptx_reg_options(opp); - m_gpgpu_context->func_sim->ptx_opcocde_latency_options(opp); - - icnt_reg_options(opp); - - m_gpgpu_context->the_gpgpusim->g_the_gpu_config = - new gpgpu_sim_config(m_gpgpu_context); - m_gpgpu_context->the_gpgpusim->g_the_gpu_config->reg_options( - opp); // register GPU microrachitecture options - m_config->reg_options(opp); - - option_parser_cmdline(opp, argc, argv); // parse configuration options - fprintf(stdout, "GPGPU-Sim: Configuration options:\n\n"); - option_parser_print(opp, stdout); - // Set the Numeric locale to a standard locale where a decimal point is a - // "dot" not a "comma" so it does the parsing correctly independent of the - // system environment variables - assert(setlocale(LC_NUMERIC, "C")); - m_gpgpu_context->the_gpgpusim->g_the_gpu_config->init(); - - m_gpgpu_context->the_gpgpusim->g_the_gpu = new trace_gpgpu_sim( - *(m_gpgpu_context->the_gpgpusim->g_the_gpu_config), m_gpgpu_context); - - m_gpgpu_context->the_gpgpusim->g_stream_manager = - new stream_manager((m_gpgpu_context->the_gpgpusim->g_the_gpu), - m_gpgpu_context->func_sim->g_cuda_launch_blocking); - - m_gpgpu_context->the_gpgpusim->g_simulation_starttime = time((time_t*)NULL); - - return m_gpgpu_context->the_gpgpusim->g_the_gpu; -} diff --git a/src/trace-driven/main.cc b/src/trace-driven/main.cc new file mode 100644 index 0000000..f12d39a --- /dev/null +++ b/src/trace-driven/main.cc @@ -0,0 +1,163 @@ +// developed by Mahmoud Khairy, Purdue Univ +// abdallm@purdue.edu + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../libcuda/gpgpu_context.h" +#include "../abstract_hardware_model.h" +#include "../cuda-sim/cuda-sim.h" +#include "../gpgpu-sim/gpu-sim.h" +#include "../gpgpu-sim/icnt_wrapper.h" +#include "../gpgpusim_entrypoint.h" +#include "../option_parser.h" +#include "ISA_Def/trace_opcode.h" +#include "trace_driven.h" + +/* TO DO: + * NOTE: the current version of trace-driven is functionally working fine, + * but we still need to improve traces compression and simulation speed. + * This includes: + * 1- Prefetch concurrent thread that prefetches traces from disk (to not be + * limited by disk speed) 2- traces compression format a. cfg format and remove + * thread/block Id from the head b. using zlib library to save in binary format + * + * 3- Efficient memory improvement (save string not objects - parse only 10 in + * the buffer) 4- Seeking capability - thread scheduler (save tb index and warp + * index info in the traces header) 5- Get rid off traces intermediate files - + * change the tracer + */ +gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[], + gpgpu_context* m_gpgpu_context, + class trace_config* m_config); + +int main(int argc, const char** argv) { + gpgpu_context* m_gpgpu_context = new gpgpu_context(); + trace_config tconfig; + + gpgpu_sim* m_gpgpu_sim = + gpgpu_trace_sim_init_perf_model(argc, argv, m_gpgpu_context, &tconfig); + m_gpgpu_sim->init(); + + // for each kernel + // load file + // parse and create kernel info + // launch + // while loop till the end of the end kernel execution + // prints stats + + trace_parser tracer(tconfig.get_traces_filename(), m_gpgpu_sim, + m_gpgpu_context); + tconfig.parse_config(); + + std::vector commandlist = tracer.parse_kernellist_file(); + + for (unsigned i = 0; i < commandlist.size(); ++i) { + trace_kernel_info_t* kernel_info = NULL; + if (commandlist[i].substr(0, 6) == "Memcpy") { + size_t addre, Bcount; + tracer.parse_memcpy_info(commandlist[i], addre, Bcount); + std::cout << commandlist[i] << std::endl; + m_gpgpu_sim->perf_memcpy_to_gpu(addre, Bcount); + continue; + } else { + kernel_info = tracer.parse_kernel_info(commandlist[i], &tconfig); + m_gpgpu_sim->launch(kernel_info); + } + + bool active = false; + bool sim_cycles = false; + bool break_limit = false; + + do { + if (!m_gpgpu_sim->active()) break; + + // performance simulation + if (m_gpgpu_sim->active()) { + m_gpgpu_sim->cycle(); + sim_cycles = true; + m_gpgpu_sim->deadlock_check(); + } else { + if (m_gpgpu_sim->cycle_insn_cta_max_hit()) { + m_gpgpu_context->the_gpgpusim->g_stream_manager + ->stop_all_running_kernels(); + break_limit = true; + } + } + + active = m_gpgpu_sim->active(); + + } while (active); + + if (kernel_info) { + tracer.kernel_finalizer(kernel_info); + m_gpgpu_sim->print_stats(); + } + + if (sim_cycles) { + m_gpgpu_sim->update_stats(); + m_gpgpu_context->print_simulation_time(); + } + + if (break_limit) { + printf( + "GPGPU-Sim: ** break due to reaching the maximum cycles (or " + "instructions) **\n"); + fflush(stdout); + exit(1); + } + } + + // we print this message to inform the gpgpu-simulation stats_collect script + // that we are done + printf("GPGPU-Sim: *** simulation thread exiting ***\n"); + printf("GPGPU-Sim: *** exit detected ***\n"); + + return 1; +} + +gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[], + gpgpu_context* m_gpgpu_context, + trace_config* m_config) { + srand(1); + print_splash(); + + option_parser_t opp = option_parser_create(); + + m_gpgpu_context->ptx_reg_options(opp); + m_gpgpu_context->func_sim->ptx_opcocde_latency_options(opp); + + icnt_reg_options(opp); + + m_gpgpu_context->the_gpgpusim->g_the_gpu_config = + new gpgpu_sim_config(m_gpgpu_context); + m_gpgpu_context->the_gpgpusim->g_the_gpu_config->reg_options( + opp); // register GPU microrachitecture options + m_config->reg_options(opp); + + option_parser_cmdline(opp, argc, argv); // parse configuration options + fprintf(stdout, "GPGPU-Sim: Configuration options:\n\n"); + option_parser_print(opp, stdout); + // Set the Numeric locale to a standard locale where a decimal point is a + // "dot" not a "comma" so it does the parsing correctly independent of the + // system environment variables + assert(setlocale(LC_NUMERIC, "C")); + m_gpgpu_context->the_gpgpusim->g_the_gpu_config->init(); + + m_gpgpu_context->the_gpgpusim->g_the_gpu = new trace_gpgpu_sim( + *(m_gpgpu_context->the_gpgpusim->g_the_gpu_config), m_gpgpu_context); + + m_gpgpu_context->the_gpgpusim->g_stream_manager = + new stream_manager((m_gpgpu_context->the_gpgpusim->g_the_gpu), + m_gpgpu_context->func_sim->g_cuda_launch_blocking); + + m_gpgpu_context->the_gpgpusim->g_simulation_starttime = time((time_t*)NULL); + + return m_gpgpu_context->the_gpgpusim->g_the_gpu; +} -- cgit v1.3