From 7baae0e937143e0acfc71382eb432bdc42d4ca41 Mon Sep 17 00:00:00 2001 From: Nick Date: Mon, 18 Feb 2019 11:21:14 -0500 Subject: Fix spelling from adpative -> adaptive for volta cache config --- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 8ed4cd0..b283095 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -75,7 +75,7 @@ # if the assigned shd mem = 0, then L1 cache = 128KB # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution --adpative_volta_cache_config 1 +-adaptive_volta_cache_config 1 # Volta unified cache has four ports -mem_unit_ports 4 -gpgpu_cache:dl1 S:4:128:64,L:L:s:N:L,A:256:8,16:0,32 -- cgit v1.3 From 74289a429633176e37116353347f60c75f2b644a Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Wed, 17 Apr 2019 23:30:20 -0500 Subject: Modified config files to add device limit configurations --- configs/tested-cfgs/SM2_GTX480/gpgpusim.config | 3 +++ configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 6 +++++ configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 6 +++++ libcuda/cuda_runtime_api.cc | 35 ++++++++++++++++++-------- 4 files changed, 40 insertions(+), 10 deletions(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config index d71b2fd..8d54d8b 100644 --- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config +++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config @@ -3,6 +3,9 @@ -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 20 +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index cb23ab3..3371186 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -8,6 +8,12 @@ -gpgpu_ptx_force_max_capability 61 -gpgpu_ignore_resources_limitation 1 +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 +-gpgpu_runtime_sync_depth_limit 2 +-gpgpu_runtime_pending_launch_count_limit 2048 + # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 8ed4cd0..1af64ac 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -13,6 +13,12 @@ -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 70 +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 +-gpgpu_runtime_sync_depth_limit 2 +-gpgpu_runtime_pending_launch_count_limit 2048 + # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 86435b9..6f1ab08 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1121,10 +1121,10 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic *value= 0; break; case 75: - *value= 7 ; + *value= 7 ; //cudaDevAttrComputeCapabilityMajor for Volta architecture break; case 76: - *value= 0 ; + *value= 0 ; //cudaDevAttrComputeCapabilityMinor for Volta architecture break; case 78: *value= 0 ; //TODO: as of now, we dont support stream priorities. @@ -1206,20 +1206,35 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetLimit ( size_t* pValue, cudaLimit li announce_call(__my_func__); } _cuda_device_id *dev = GPGPUSim_Init(); + const struct cudaDeviceProp *prop = dev->get_prop(); const gpgpu_sim_config& config=dev->get_gpgpu()->get_config(); switch(limit) { case 0: // cudaLimitStackSize - *pValue=config.stack_limit(); - break; + *pValue=config.stack_limit(); + break; case 2: // cudaLimitMallocHeapSize - *pValue=config.heap_limit(); - break; + *pValue=config.heap_limit(); + break; +#if (CUDART_VERSION > 5050) case 3: // cudaLimitDevRuntimeSyncDepth - *pValue=config.sync_depth_limit(); - break; + if(prop->major > 2){ + *pValue=config.sync_depth_limit(); + break; + } + else{ + printf("ERROR:Limit %s is not supported on this architecture \n",limit); + abort(); + } case 4: // cudaLimitDevRuntimePendingLaunchCount - *pValue=config.pending_launch_count_limit(); - break; + if(prop->major > 2){ + *pValue=config.pending_launch_count_limit(); + break; + } + else{ + printf("ERROR:Limit %s is not supported on this architecture \n",limit); + abort(); + } +#endif default: printf("ERROR:Limit %s unimplemented \n",limit); abort(); -- cgit v1.3 From 537b342ab102b75a6da694b968b2226719b267c3 Mon Sep 17 00:00:00 2001 From: Preyesh Dalmia Date: Thu, 18 Apr 2019 17:13:06 -0500 Subject: changes for compute capability major/minor --- configs/tested-cfgs/SM2_GTX480/gpgpusim.config | 4 ++++ configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 4 ++++ configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 6 ++++++ libcuda/cuda_runtime_api.cc | 12 ++++++------ src/gpgpu-sim/gpu-sim.cc | 17 +++++++++++++++++ src/gpgpu-sim/gpu-sim.h | 8 ++++++++ 6 files changed, 45 insertions(+), 6 deletions(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config index 8d54d8b..cf3627b 100644 --- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config +++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config @@ -7,6 +7,10 @@ -gpgpu_stack_size_limit 1024 -gpgpu_heap_size_limit 8388608 +# Compute Capability +-gpgpu_compute_capability_major 2 +-gpgpu_compute_capability_minor 0 + # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index 3371186..23d044c 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -14,6 +14,10 @@ -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 +# Compute Capability +-gpgpu_compute_capability_major 6 +-gpgpu_compute_capability_minor 1 + # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 1af64ac..a5b427f 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -13,12 +13,18 @@ -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 70 + # Device Limits -gpgpu_stack_size_limit 1024 -gpgpu_heap_size_limit 8388608 -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 +# Compute Capability +-gpgpu_compute_capability_major 7 +-gpgpu_compute_capability_minor 0 + + # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 6f1ab08..9068700 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -354,8 +354,8 @@ struct _cuda_device_id *GPGPUSim_Init() cudaDeviceProp *prop = (cudaDeviceProp *) calloc(sizeof(cudaDeviceProp),1); snprintf(prop->name,256,"GPGPU-Sim_v%s", g_gpgpusim_version_string ); - prop->major = 5; - prop->minor = 2; + prop->major = the_gpu->compute_capability_major(); + prop->minor = the_gpu->compute_capability_minor(); prop->totalGlobalMem = 0x80000000 /* 2 GB */; prop->memPitch = 0; if(prop->major >= 2) { @@ -1120,11 +1120,11 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 41: *value= 0; break; - case 75: - *value= 7 ; //cudaDevAttrComputeCapabilityMajor for Volta architecture + case 75:// Major compute capability version number + *value= prop->major ; break; - case 76: - *value= 0 ; //cudaDevAttrComputeCapabilityMinor for Volta architecture + case 76:// Minor compute capability version number + *value= prop->minor ; break; case 78: *value= 0 ; //TODO: as of now, we dont support stream priorities. diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 2a862a4..358c0f7 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -499,6 +499,12 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) option_parser_register(opp, "-liveness_message_freq", OPT_INT64, &liveness_message_freq, "Minimum number of seconds between simulation liveness messages (0 = always print)", "1"); + option_parser_register(opp, "-gpgpu_compute_capability_major", OPT_UINT32, &gpgpu_compute_capability_major, + "Major compute capability version number", + "7"); + option_parser_register(opp, "-gpgpu_compute_capability_minor", OPT_UINT32, &gpgpu_compute_capability_minor, + "Minor compute capability version number", + "0"); option_parser_register(opp, "-gpgpu_flush_l1_cache", OPT_BOOL, &gpgpu_flush_l1_cache, "Flush L1 cache at the end of each kernel call", "0"); @@ -802,6 +808,17 @@ void gpgpu_sim::set_prop( cudaDeviceProp *prop ) m_cuda_properties = prop; } +int gpgpu_sim::compute_capability_major() const +{ + printf("Everything works %d\n", m_config.gpgpu_compute_capability_major); + return m_config.gpgpu_compute_capability_major; +} + +int gpgpu_sim::compute_capability_minor() const +{ + return m_config.gpgpu_compute_capability_minor; +} + const struct cudaDeviceProp *gpgpu_sim::get_prop() const { return m_cuda_properties; diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 11ffe49..39e1d9a 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -388,6 +388,10 @@ private: size_t runtime_sync_depth_limit; size_t runtime_pending_launch_count_limit; + //gpu compute capability options + unsigned int gpgpu_compute_capability_major; + unsigned int gpgpu_compute_capability_minor; + unsigned long long liveness_message_freq; friend class gpgpu_sim; @@ -447,6 +451,10 @@ public: int shared_mem_size() const; int shared_mem_per_block() const; + int compute_capability_major() const; + int compute_capability_minor() const; + + int num_registers_per_core() const; int num_registers_per_block() const; int wrp_size() const; -- cgit v1.3 From 73f1a8a424cff7d689c138eaa8a59780b86a76d1 Mon Sep 17 00:00:00 2001 From: Preyesh Dalmia Date: Thu, 18 Apr 2019 17:26:40 -0500 Subject: changes for compute capabilty --- configs/tested-cfgs/SM2_GTX480/gpgpusim.config | 4 ++++ configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 4 ++++ configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 4 ++++ libcuda/cuda_runtime_api.cc | 12 ++++++------ src/gpgpu-sim/gpu-sim.cc | 16 ++++++++++++++++ src/gpgpu-sim/gpu-sim.h | 5 +++++ 6 files changed, 39 insertions(+), 6 deletions(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config index 8d54d8b..cf3627b 100644 --- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config +++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config @@ -7,6 +7,10 @@ -gpgpu_stack_size_limit 1024 -gpgpu_heap_size_limit 8388608 +# Compute Capability +-gpgpu_compute_capability_major 2 +-gpgpu_compute_capability_minor 0 + # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index 3371186..23d044c 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -14,6 +14,10 @@ -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 +# Compute Capability +-gpgpu_compute_capability_major 6 +-gpgpu_compute_capability_minor 1 + # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 1af64ac..f3a5f65 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -19,6 +19,10 @@ -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 +# Compute Capability +-gpgpu_compute_capability_major 7 +-gpgpu_compute_capability_minor 0 + # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 6f1ab08..9068700 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -354,8 +354,8 @@ struct _cuda_device_id *GPGPUSim_Init() cudaDeviceProp *prop = (cudaDeviceProp *) calloc(sizeof(cudaDeviceProp),1); snprintf(prop->name,256,"GPGPU-Sim_v%s", g_gpgpusim_version_string ); - prop->major = 5; - prop->minor = 2; + prop->major = the_gpu->compute_capability_major(); + prop->minor = the_gpu->compute_capability_minor(); prop->totalGlobalMem = 0x80000000 /* 2 GB */; prop->memPitch = 0; if(prop->major >= 2) { @@ -1120,11 +1120,11 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 41: *value= 0; break; - case 75: - *value= 7 ; //cudaDevAttrComputeCapabilityMajor for Volta architecture + case 75:// Major compute capability version number + *value= prop->major ; break; - case 76: - *value= 0 ; //cudaDevAttrComputeCapabilityMinor for Volta architecture + case 76:// Minor compute capability version number + *value= prop->minor ; break; case 78: *value= 0 ; //TODO: as of now, we dont support stream priorities. diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 2a862a4..3687448 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -499,6 +499,12 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) option_parser_register(opp, "-liveness_message_freq", OPT_INT64, &liveness_message_freq, "Minimum number of seconds between simulation liveness messages (0 = always print)", "1"); + option_parser_register(opp, "-gpgpu_compute_capability_major", OPT_UINT32, &gpgpu_compute_capability_major, + "Major compute capability version number", + "7"); + option_parser_register(opp, "-gpgpu_compute_capability_minor", OPT_UINT32, &gpgpu_compute_capability_minor, + "Minor compute capability version number", + "0"); option_parser_register(opp, "-gpgpu_flush_l1_cache", OPT_BOOL, &gpgpu_flush_l1_cache, "Flush L1 cache at the end of each kernel call", "0"); @@ -802,6 +808,16 @@ void gpgpu_sim::set_prop( cudaDeviceProp *prop ) m_cuda_properties = prop; } +int gpgpu_sim::compute_capability_major() const +{ + return m_config.gpgpu_compute_capability_major; +} + +int gpgpu_sim::compute_capability_minor() const +{ + return m_config.gpgpu_compute_capability_minor; +} + const struct cudaDeviceProp *gpgpu_sim::get_prop() const { return m_cuda_properties; diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 11ffe49..d4cc18f 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -388,6 +388,9 @@ private: size_t runtime_sync_depth_limit; size_t runtime_pending_launch_count_limit; + //gpu compute capability options + unsigned int gpgpu_compute_capability_major; + unsigned int gpgpu_compute_capability_minor; unsigned long long liveness_message_freq; friend class gpgpu_sim; @@ -447,6 +450,8 @@ public: int shared_mem_size() const; int shared_mem_per_block() const; + int compute_capability_major() const; + int compute_capability_minor() const; int num_registers_per_core() const; int num_registers_per_block() const; int wrp_size() const; -- cgit v1.3 From 7764a7f373a0f99d714d42fcb380fb48e00b9c54 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 25 Apr 2019 15:39:13 -0400 Subject: updating titanv config file --- .../tested-cfgs/SM7_TITANV/config_fermi_islip.icnt | 74 ---------------------- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 16 ++--- .../SM7_TITANV_fastlocalxbar/gpgpusim.config | 13 ++-- 3 files changed, 14 insertions(+), 89 deletions(-) delete mode 100644 configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt deleted file mode 100644 index 615d0a9..0000000 --- a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt +++ /dev/null @@ -1,74 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 40; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 88; -n = 1; - -// Routing - -routing_function = dest_tag; - - -// Flow control - -num_vcs = 1; -vc_buf_size = 256; -input_buffer_size = 256; -ejection_buffer_size = 256; -boundary_buffer_size = 256; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 1; -output_speedup = 1; -internal_speedup = 2.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 8ed4cd0..f48e897 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -1,4 +1,4 @@ -# This config models the Volta Titan X +# This config models the Volta Titan V # For more info about volta architecture: # http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf # https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# @@ -25,7 +25,7 @@ # volta clock domains #-gpgpu_clock_domains ::: -# Volta NVIDIA V100 clock domains are adopted from +# Volta NVIDIA TITANV clock domains are adopted from # https://en.wikipedia.org/wiki/Volta_(microarchitecture) -gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0 # boost mode @@ -42,7 +42,7 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE -## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core +## Volta TITANV has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units ## we need to scale the number of pipeline registers to be equal to the number of SP units -gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 -gpgpu_num_sp_units 4 @@ -104,7 +104,7 @@ # Volta has sub core model, in which each scheduler has its own reisiter file and EUs # i.e. schedulers are isolated --sub_core_model 0 +-sub_core_model 1 # disable specialized operand collectors and use generic operand collectors instead -enable_specialized_operand_collector 0 -gpgpu_operand_collector_num_units_gen 8 @@ -125,7 +125,7 @@ # interconnection -network_mode 1 --inter_config_file config_fermi_islip.icnt +-inter_config_file config_volta_islip.icnt # memory partition latency config -rop_latency 120 @@ -150,7 +150,7 @@ #-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: # CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" -# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ +# Timing for 850 MHZ, Tesla TITANV HBM runs at 850 MHZ -gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3" @@ -163,7 +163,7 @@ #-Seperate_Write_Queue_Enable 1 #-Write_Queue_Size 64:56:32 -# Pascal has two schedulers per core +# Volta has four schedulers per core -gpgpu_num_sched_per_core 4 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 @@ -178,7 +178,7 @@ -enable_ptx_file_line_stats 1 -visualizer_enabled 0 -# power model configs, disable it untill we create a real energy model for Pascal 100 +# power model configs, disable it untill we create a real energy model for Volta -power_simulation_enabled 0 # tracing functionality diff --git a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config index 73516e1..3e4a8fa 100644 --- a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config @@ -1,4 +1,4 @@ -# This config models the Volta Titan X +# This config models the Volta Titan V # For more info about volta architecture: # http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf # https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# @@ -25,7 +25,7 @@ # volta clock domains #-gpgpu_clock_domains ::: -# Volta NVIDIA V100 clock domains are adopted from +# Volta NVIDIA TITANV clock domains are adopted from # https://en.wikipedia.org/wiki/Volta_(microarchitecture) -gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0 # boost mode @@ -42,7 +42,7 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE -## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core +## Volta TITANV has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units ## we need to scale the number of pipeline registers to be equal to the number of SP units -gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 -gpgpu_num_sp_units 4 @@ -123,9 +123,8 @@ -gpgpu_max_insn_issue_per_warp 1 -gpgpu_dual_issue_diff_exec_units 1 -# interconnection +# use local xbar interconnection -network_mode 2 --inter_config_file config_fermi_islip.icnt -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 -inct_subnets 2 @@ -167,7 +166,7 @@ #-Seperate_Write_Queue_Enable 1 #-Write_Queue_Size 64:56:32 -# Pascal has two schedulers per core +# Volta has four schedulers per core -gpgpu_num_sched_per_core 4 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 @@ -182,7 +181,7 @@ -enable_ptx_file_line_stats 1 -visualizer_enabled 0 -# power model configs, disable it untill we create a real energy model for Pascal 100 +# power model configs, disable it untill we create a real energy model for Volta -power_simulation_enabled 0 # tracing functionality -- cgit v1.3 From 0cf1f587d5bcc449c679371ac966f26db706deca Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 25 Apr 2019 15:39:57 -0400 Subject: change name booksim file --- .../tested-cfgs/SM7_TITANV/config_volta_islip.icnt | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt new file mode 100644 index 0000000..615d0a9 --- /dev/null +++ b/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt @@ -0,0 +1,74 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 88; +n = 1; + +// Routing + +routing_function = dest_tag; + + +// Flow control + +num_vcs = 1; +vc_buf_size = 256; +input_buffer_size = 256; +ejection_buffer_size = 256; +boundary_buffer_size = 256; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + -- cgit v1.3 From ad37c917f8641930f9f58c3f04fa6e22600015cd Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 2 May 2019 15:49:03 -0400 Subject: fixing some typos in config files --- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 4 ++-- configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 13d8c8f..f454240 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -53,7 +53,7 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE -## Volta TITANV has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units +## Volta TITANV has 4 SP SIMD units, 4 INT units, 4 SFU units, 4 DP units per core, 4 Tensor core units ## we need to scale the number of pipeline registers to be equal to the number of SP units -gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 -gpgpu_num_sp_units 4 @@ -113,7 +113,7 @@ # 64 KB Const -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 -# Volta has sub core model, in which each scheduler has its own reisiter file and EUs +# Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated -sub_core_model 1 # disable specialized operand collectors and use generic operand collectors instead diff --git a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config index 3e4a8fa..b1ce11c 100644 --- a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config @@ -102,9 +102,9 @@ # 64 KB Const -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 -# Volta has sub core model, in which each scheduler has its own reisiter file and EUs +# Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated --sub_core_model 0 +-sub_core_model 1 # disable specialized operand collectors and use generic operand collectors instead -enable_specialized_operand_collector 0 -gpgpu_operand_collector_num_units_gen 8 -- cgit v1.3