From f2a7d9ce6cd13977d97a0601d732551a5451ac71 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Sat, 15 May 2021 09:09:20 -0400 Subject: fixing streaming cache based on recent ubench --- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 3fa51ee..3af314c 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -116,7 +116,7 @@ -gpgpu_adaptive_cache_config 1 # Volta unified cache has four banks -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 -gpgpu_shmem_per_block 65536 -- cgit v1.3 From f7833519471ce92619bd1e4807ec07eb55aed76e Mon Sep 17 00:00:00 2001 From: JRPAN <25518778+JRPan@users.noreply.github.com> Date: Mon, 17 May 2021 17:35:06 -0400 Subject: new configs - adaptive cache and cache write ratio --- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 2 ++ configs/tested-cfgs/SM7_QV100/gpgpusim.config | 6 ++++++ configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 3 +++ src/abstract_hardware_model.h | 2 ++ src/gpgpu-sim/gpu-cache.h | 5 +++++ src/gpgpu-sim/gpu-sim.cc | 7 +++++++ 6 files changed, 25 insertions(+) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 6189dca..e006085 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -110,6 +110,8 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 +-gpgpu_shmem_option 0,8,16,32,64,100 +-gpgpu_unified_l1d_size 128 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives us 3MB L2 cache -gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:192:4,32:0,32 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index bc5677c..043fce6 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -124,6 +124,9 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 +-gpgpu_cache_write_ratio 25 +-gpgpu_shmem_option 0,12,24,48,96 +-gpgpu_unified_l1d_size 128 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 @@ -203,3 +206,6 @@ #-trace_components WARP_SCHEDULER,SCOREBOARD #-trace_sampling_core 0 +-gpgpu_cache_write_ratio 25 +-gpgpu_shmem_option 0,12,24,48,96 +-gpgpu_unified_l1d_size 128 \ No newline at end of file diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 3fa51ee..1f0c15f 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -125,6 +125,9 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 +-gpgpu_cache_write_ratio 25 +-gpgpu_shmem_option 0,12,24,48,96 +-gpgpu_unified_l1d_size 128 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 982e416..e796571 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -373,6 +373,8 @@ class core_config { } unsigned mem_warp_parts; mutable unsigned gpgpu_shmem_size; + char *gpgpu_shmem_option; + unsigned gpgpu_unified_l1d_size; unsigned gpgpu_shmem_sizeDefault; unsigned gpgpu_shmem_sizePrefL1; unsigned gpgpu_shmem_sizePrefShared; diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 00c09ae..ccc935b 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -491,6 +491,7 @@ class cache_config { m_data_port_width = 0; m_set_index_function = LINEAR_SET_FUNCTION; m_is_streaming = false; + m_wr_percent = 0; } void init(char *config, FuncCache status) { cache_status = status; @@ -754,6 +755,10 @@ class cache_config { char *m_config_stringPrefL1; char *m_config_stringPrefShared; FuncCache cache_status; + unsigned m_wr_percent; + write_allocate_policy_t get_write_allocate_policy() { + return m_write_alloc_policy; + } protected: void exit_parse_error() { diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index fd36e00..bd09cdb 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -249,6 +249,7 @@ void shader_core_config::reg_options(class OptionParser *opp) { " {::,:::,::, | none}", "none"); + option_parser_register(opp,"-gpgpu_cache_write_ratio",OPT_UINT32,&m_L1D_config.m_wr_percent,"L1D write ratio","0"); option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32, &m_L1D_config.l1_banks, "The number of L1 cache banks", "1"); @@ -326,6 +327,12 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register( opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); + option_parser_register( + opp, "-gpgpu_shmem_option", OPT_CSTR, &gpgpu_shmem_option, + "Option list of shared memory sizes", "0"); + option_parser_register( + opp, "-gpgpu_unified_l1d_size", OPT_UINT32, &gpgpu_unified_l1d_size, + "Size of unified data cache(L1D + shared memory) in KB", "0"); option_parser_register(opp, "-gpgpu_adaptive_cache_config", OPT_BOOL, &adaptive_cache_config, "adaptive_cache_config", "0"); option_parser_register( -- cgit v1.3 From 4a762a933a054b5124fa46a12789ea98f5e2411d Mon Sep 17 00:00:00 2001 From: JRPAN <25518778+JRPan@users.noreply.github.com> Date: Wed, 19 May 2021 15:22:31 -0400 Subject: formatting again --- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 4 ++-- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 8 ++------ configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- src/gpgpu-sim/gpu-sim.cc | 2 +- src/gpgpu-sim/shader.cc | 1 + 5 files changed, 7 insertions(+), 10 deletions(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index e006085..d7573ab 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -100,6 +100,8 @@ # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo -gpgpu_adaptive_cache_config 0 +-gpgpu_shmem_option 0,8,16,32,64,100 +-gpgpu_unified_l1d_size 128 -gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:1:128:512,L:L:m:N:L,A:512:8,16:0,32 -gpgpu_shmem_size 65536 @@ -110,8 +112,6 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 --gpgpu_shmem_option 0,8,16,32,64,100 --gpgpu_unified_l1d_size 128 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives us 3MB L2 cache -gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:192:4,32:0,32 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 043fce6..59c7f43 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -124,7 +124,7 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 --gpgpu_cache_write_ratio 25 +-gpgpu_l1_cache_write_ratio 25 -gpgpu_shmem_option 0,12,24,48,96 -gpgpu_unified_l1d_size 128 @@ -204,8 +204,4 @@ # tracing functionality #-trace_enabled 1 #-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - --gpgpu_cache_write_ratio 25 --gpgpu_shmem_option 0,12,24,48,96 --gpgpu_unified_l1d_size 128 \ No newline at end of file +#-trace_sampling_core 0 \ No newline at end of file diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 1f0c15f..3e080bc 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -125,7 +125,7 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 --gpgpu_cache_write_ratio 25 +-gpgpu_l1_cache_write_ratio 25 -gpgpu_shmem_option 0,12,24,48,96 -gpgpu_unified_l1d_size 128 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index bd09cdb..a2aa929 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -249,7 +249,7 @@ void shader_core_config::reg_options(class OptionParser *opp) { " {::,:::,::, | none}", "none"); - option_parser_register(opp,"-gpgpu_cache_write_ratio",OPT_UINT32,&m_L1D_config.m_wr_percent,"L1D write ratio","0"); + option_parser_register(opp,"-gpgpu_l1_cache_write_ratio",OPT_UINT32,&m_L1D_config.m_wr_percent,"L1D write ratio","0"); option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32, &m_L1D_config.l1_banks, "The number of L1 cache banks", "1"); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index b2adb4f..141c700 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3326,6 +3326,7 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const { // For more info about adaptive cache, see bool l1d_configured = false; unsigned l1_defined = m_L1D_config.get_original_sz() / 1024; + assert(gpgpu_unified_l1d_size % l1_defined == 0); unsigned max_assoc = m_L1D_config.get_original_assoc() * gpgpu_unified_l1d_size / l1_defined; -- cgit v1.3 From a2ba2f57e8a24b9dd6ec6f2568accbbf439a9dca Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Wed, 19 May 2021 19:39:48 -0400 Subject: updating config files with right adaptive cache parameters --- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 18 ++++++++++-------- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 19 ++++++++++--------- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 17 +++++++++-------- configs/tested-cfgs/SM86_RTX3070/gpgpusim.config | 11 +++++++---- 4 files changed, 36 insertions(+), 29 deletions(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index d7573ab..9e50fa3 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -99,19 +99,21 @@ # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo --gpgpu_adaptive_cache_config 0 --gpgpu_shmem_option 0,8,16,32,64,100 --gpgpu_unified_l1d_size 128 +-gpgpu_adaptive_cache_config 1 +-gpgpu_shmem_option 32,64 +-gpgpu_unified_l1d_size 96 +# L1 cache configuration -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:1:128:512,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_l1_latency 20 +-gpgpu_gmem_skip_L1D 0 +-gpgpu_n_cluster_ejection_buffer_size 32 +-gpgpu_flush_l1_cache 1 +# shared memory configuration -gpgpu_shmem_size 65536 -gpgpu_shmem_sizeDefault 65536 -gpgpu_shmem_per_block 65536 --gpgpu_gmem_skip_L1D 0 --gpgpu_n_cluster_ejection_buffer_size 32 --gpgpu_l1_latency 20 -gpgpu_smem_latency 20 --gpgpu_flush_l1_cache 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives us 3MB L2 cache -gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:192:4,32:0,32 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 59c7f43..3750de0 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -94,7 +94,7 @@ -gpgpu_shmem_num_banks 32 -gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 +-gpgpu_coalesce_arch 70 # Volta has four schedulers per core -gpgpu_num_sched_per_core 4 @@ -113,20 +113,21 @@ # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution -gpgpu_adaptive_cache_config 1 -# Volta unified cache has four banks +-gpgpu_shmem_option 0,8,16,32,64,96 +-gpgpu_unified_l1d_size 128 +# L1 cache configuration -gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_l1_cache_write_ratio 25 +-gpgpu_l1_latency 20 +-gpgpu_gmem_skip_L1D 0 +-gpgpu_flush_l1_cache 1 +-gpgpu_n_cluster_ejection_buffer_size 32 +# shared memory configuration -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 -gpgpu_shmem_per_block 65536 --gpgpu_gmem_skip_L1D 0 --gpgpu_n_cluster_ejection_buffer_size 32 --gpgpu_l1_latency 20 -gpgpu_smem_latency 20 --gpgpu_flush_l1_cache 1 --gpgpu_l1_cache_write_ratio 25 --gpgpu_shmem_option 0,12,24,48,96 --gpgpu_unified_l1d_size 128 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 32245d7..e7f7305 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -114,20 +114,21 @@ # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution -gpgpu_adaptive_cache_config 1 -# Volta unified cache has four banks +-gpgpu_shmem_option 0,8,16,32,64,96 +-gpgpu_unified_l1d_size 128 +# L1 cache configuration -gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_l1_cache_write_ratio 25 +-gpgpu_gmem_skip_L1D 0 +-gpgpu_l1_latency 20 +-gpgpu_flush_l1_cache 1 +-gpgpu_n_cluster_ejection_buffer_size 32 +# shared memory configuration -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 -gpgpu_shmem_per_block 65536 --gpgpu_gmem_skip_L1D 0 --gpgpu_n_cluster_ejection_buffer_size 32 --gpgpu_l1_latency 20 -gpgpu_smem_latency 20 --gpgpu_flush_l1_cache 1 --gpgpu_l1_cache_write_ratio 25 --gpgpu_shmem_option 0,12,24,48,96 --gpgpu_unified_l1d_size 128 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 diff --git a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config index f5418ad..3c0db06 100644 --- a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config +++ b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config @@ -107,17 +107,20 @@ # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#global-memory-8-x # disable this mode in case of multi kernels/apps execution -gpgpu_adaptive_cache_config 1 +-gpgpu_shmem_option 0,8,16,32,64,100 +-gpgpu_unified_l1d_size 128 # Ampere unified cache has four banks -gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_gmem_skip_L1D 0 +-gpgpu_l1_latency 20 +-gpgpu_n_cluster_ejection_buffer_size 32 +-gpgpu_flush_l1_cache 1 +# shared memory configuration -gpgpu_shmem_size 102400 -gpgpu_shmem_sizeDefault 102400 -gpgpu_shmem_per_block 102400 --gpgpu_gmem_skip_L1D 0 --gpgpu_n_cluster_ejection_buffer_size 32 --gpgpu_l1_latency 20 -gpgpu_smem_latency 20 --gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 3MB L2 cache -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 -- cgit v1.3 From e3d186bbeade78dec776989ccec2a0c0aea27fb4 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Wed, 19 May 2021 19:43:29 -0400 Subject: chaning @sets to 4 based on recent ubenchs --- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 2 +- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 2 +- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- configs/tested-cfgs/SM86_RTX3070/gpgpusim.config | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 856f5cf..a63d50f 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -104,7 +104,7 @@ -gpgpu_unified_l1d_size 96 # L1 cache configuration -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_cache:dl1 S:4:128:64,L:L:m:N:L,A:512:8,16:0,32 -gpgpu_l1_cache_write_ratio 25 -gpgpu_l1_latency 20 -gpgpu_gmem_skip_L1D 0 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 3750de0..47bf1c8 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -117,7 +117,7 @@ -gpgpu_unified_l1d_size 128 # L1 cache configuration -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_cache:dl1 S:4:128:64,L:L:m:N:L,A:512:8,16:0,32 -gpgpu_l1_cache_write_ratio 25 -gpgpu_l1_latency 20 -gpgpu_gmem_skip_L1D 0 diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index e7f7305..3db64b3 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -118,7 +118,7 @@ -gpgpu_unified_l1d_size 128 # L1 cache configuration -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_cache:dl1 S:4:128:64,L:L:m:N:L,A:512:8,16:0,32 -gpgpu_l1_cache_write_ratio 25 -gpgpu_gmem_skip_L1D 0 -gpgpu_l1_latency 20 diff --git a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config index 9123e20..c70cfe8 100644 --- a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config +++ b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config @@ -111,7 +111,7 @@ -gpgpu_unified_l1d_size 128 # Ampere unified cache has four banks -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_cache:dl1 S:4:128:64,L:L:m:N:L,A:512:8,16:0,32 -gpgpu_l1_cache_write_ratio 25 -gpgpu_gmem_skip_L1D 0 -gpgpu_l1_latency 20 -- cgit v1.3 From 7fac247e3e1c4326081c3ea4d46da6c5dc83ccb9 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Wed, 19 May 2021 22:20:56 -0400 Subject: change L1 cache config in Volta+ to be write-through and write-allocate based on recent ubench --- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 2 +- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 2 +- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- configs/tested-cfgs/SM86_RTX3070/gpgpusim.config | 3 +-- 4 files changed, 4 insertions(+), 5 deletions(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index a63d50f..f715f3a 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -104,7 +104,7 @@ -gpgpu_unified_l1d_size 96 # L1 cache configuration -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:4:128:64,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32 -gpgpu_l1_cache_write_ratio 25 -gpgpu_l1_latency 20 -gpgpu_gmem_skip_L1D 0 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 47bf1c8..5f22a42 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -117,7 +117,7 @@ -gpgpu_unified_l1d_size 128 # L1 cache configuration -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:4:128:64,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32 -gpgpu_l1_cache_write_ratio 25 -gpgpu_l1_latency 20 -gpgpu_gmem_skip_L1D 0 diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 3db64b3..c44563f 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -118,7 +118,7 @@ -gpgpu_unified_l1d_size 128 # L1 cache configuration -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:4:128:64,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32 -gpgpu_l1_cache_write_ratio 25 -gpgpu_gmem_skip_L1D 0 -gpgpu_l1_latency 20 diff --git a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config index c70cfe8..02cdb9e 100644 --- a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config +++ b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config @@ -101,7 +101,6 @@ ## L1/shared memory configuration # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo -# Default config is 28KB DL1 and 100KB shared memory # In Ampere, we assign the remaining shared memory to L1 cache # if the assigned shd mem = 0, then L1 cache = 128KB # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#global-memory-8-x @@ -111,7 +110,7 @@ -gpgpu_unified_l1d_size 128 # Ampere unified cache has four banks -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:4:128:64,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32 -gpgpu_l1_cache_write_ratio 25 -gpgpu_gmem_skip_L1D 0 -gpgpu_l1_latency 20 -- cgit v1.3 From a8256e50a6d25338f659da76ff9c3595132f54b2 Mon Sep 17 00:00:00 2001 From: JRPAN <25518778+JRPan@users.noreply.github.com> Date: Mon, 23 Aug 2021 13:06:13 -0400 Subject: Update volta to use lrr scheduler --- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 2 +- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 5f22a42..425bc16 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -99,7 +99,7 @@ # Volta has four schedulers per core -gpgpu_num_sched_per_core 4 # Greedy then oldest scheduler --gpgpu_scheduler gto +-gpgpu_scheduler lrr ## In Volta, a warp scheduler can issue 1 inst per cycle -gpgpu_max_insn_issue_per_warp 1 -gpgpu_dual_issue_diff_exec_units 1 diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index c44563f..0c69c70 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -100,7 +100,7 @@ # Volta has four schedulers per core -gpgpu_num_sched_per_core 4 # Greedy then oldest scheduler --gpgpu_scheduler gto +-gpgpu_scheduler lrr ## In Volta, a warp scheduler can issue 1 inst per cycle -gpgpu_max_insn_issue_per_warp 1 -gpgpu_dual_issue_diff_exec_units 1 -- cgit v1.3