From 7fac247e3e1c4326081c3ea4d46da6c5dc83ccb9 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Wed, 19 May 2021 22:20:56 -0400 Subject: change L1 cache config in Volta+ to be write-through and write-allocate based on recent ubench --- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs/tested-cfgs/SM7_TITANV') diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 3db64b3..c44563f 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -118,7 +118,7 @@ -gpgpu_unified_l1d_size 128 # L1 cache configuration -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:4:128:64,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32 -gpgpu_l1_cache_write_ratio 25 -gpgpu_gmem_skip_L1D 0 -gpgpu_l1_latency 20 -- cgit v1.3