From b2def455d573f66fbc38dabda4adbc3a56225910 Mon Sep 17 00:00:00 2001
From: "Mahmoud Khairy A. Abdallah" <abdallm@purdue.edu>
Date: Sun, 9 Feb 2020 20:39:22 -0500
Subject: adding kepler sass, skip-first-kernel and update config file

---
 .../Turing_RTX2060/config_pascal_islip.icnt        | 73 ++++++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt

(limited to 'configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt')

diff --git a/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt b/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt
new file mode 100644
index 0000000..dec4789
--- /dev/null
+++ b/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 64;
+input_buffer_size = 256;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
-- 
cgit v1.3