From 1ade3b340c72f65fe01735df0748e13d4c026998 Mon Sep 17 00:00:00 2001
From: Tayler Hetherington <tayler.hetherington@gmail.com>
Date: Mon, 15 Oct 2012 14:49:25 -0800
Subject: - Fixing cache configuration groupings -> Now <cache configs>, <cache
 policies>, <MSHR>, <Miss queue/FIFO sizing> - Fixing default configurations
 to match the new format and additonal parameters - Fixing Fermi's 48kB cache
 configuration

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14370]
---
 configs/GTX480/gpgpusim.config       | 15 ++++++++-------
 configs/QuadroFX5800/gpgpusim.config | 10 ++++++----
 configs/TeslaC2050/gpgpusim.config   | 16 +++++++++-------
 3 files changed, 23 insertions(+), 18 deletions(-)

(limited to 'configs')

diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config
index e5108f8..a8eac01 100644
--- a/configs/GTX480/gpgpusim.config
+++ b/configs/GTX480/gpgpusim.config
@@ -38,21 +38,22 @@
 -ptx_opcode_initiation_dp 8,16,8,8,130
 
 # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>
--gpgpu_cache:dl1  32:128:4:L:L:m:A:N:32:8:8
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+-gpgpu_cache:dl1  32:128:4,L:L:m:N,A:32:8,8
 -gpgpu_shmem_size 49152
 
 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  64:128:6:L:R:m,A:32:8,8
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N,A:32:8,8
 #-gpgpu_shmem_size 16384
 
 # 64 sets, each 256 bytes 8-way for each memory partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:256:8:L:B:m:A:W:32:4:4
+-gpgpu_cache:dl2 64:256:8,L:B:m:W,A:32:4,4
 -gpgpu_cache:dl2_texture_only 0 
 
--gpgpu_cache:il1 4:128:4:L:R:f:A:N:2:32:4
--gpgpu_tex_cache:l1 4:128:24:L:R:m:F:N:128:4:128:2
--gpgpu_const_cache:l1 64:64:2:L:R:f:A:N:2:32:4
+-gpgpu_cache:il1 4:128:4,L:R:f:N,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4
 
 -gpgpu_num_reg_banks 16
 
diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config
index 7f43511..638f362 100644
--- a/configs/QuadroFX5800/gpgpusim.config
+++ b/configs/QuadroFX5800/gpgpusim.config
@@ -31,10 +31,12 @@
 -ptx_opcode_initiation_dp 8,8,8,8,130
 
 # memory stage behaviour
--gpgpu_cache:il1 4:256:4:L:R:f:A:N:2:32:4
--gpgpu_tex_cache:l1 8:128:5:L:R:m:F:N:128:4:128:2
--gpgpu_const_cache:l1 64:64:2:L:R:f:A:N:2:32:4
--gpgpu_cache:dl2 16:256:8:L:B:m:A:W:16:4:4
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+-gpgpu_cache:il1 4:256:4,L:R:f:N,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W,A:16:4,4
 -gpgpu_cache:dl2_texture_only 1
 
 -gpgpu_shmem_warp_parts 2
diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config
index 86944b1..f09e391 100644
--- a/configs/TeslaC2050/gpgpusim.config
+++ b/configs/TeslaC2050/gpgpusim.config
@@ -37,22 +37,24 @@
 -ptx_opcode_latency_dp 8,19,8,8,330
 -ptx_opcode_initiation_dp 8,16,8,8,130
 
+
 # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>
--gpgpu_cache:dl1  32:128:4:L:L:m:A:N:32:8:8
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+-gpgpu_cache:dl1  32:128:4,L:L:m:N,A:32:8,8
 -gpgpu_shmem_size 49152
 
 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  64:128:6:L:R:m,A:32:8,8
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N,A:32:8,8
 #-gpgpu_shmem_size 16384
 
 # 64 sets, each 256 bytes 8-way for each memory partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:256:8:L:B:m:A:W:32:4:4
+-gpgpu_cache:dl2 64:256:8,L:B:m:W,A:32:4,4
 -gpgpu_cache:dl2_texture_only 0 
 
--gpgpu_cache:il1 4:128:4:L:R:f:A:N:2:32:4
--gpgpu_tex_cache:l1 4:128:24:L:R:m:F:N:128:4:128:2
--gpgpu_const_cache:l1 64:64:2:L:R:f:A:N:2:32:4
+-gpgpu_cache:il1 4:128:4,L:R:f:N,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4
 
 -gpgpu_num_reg_banks 16
 
-- 
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