From 36ce0f2243fd0723a746b3c2f5f0651577312400 Mon Sep 17 00:00:00 2001 From: Tayler Hetherington Date: Fri, 30 Nov 2012 21:29:42 -0800 Subject: Merging Power model into Fermi //depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723] --- configs/GTX480/gpgpusim.config | 2 +- configs/GTX480/mcpat.xml | 498 +++++++++++++++++++++++++++++ configs/QuadroFX5600/gpgpusim.config | 81 +++++ configs/QuadroFX5600/icnt_config_islip.txt | 49 +++ configs/QuadroFX5600/mcpat.xml | 494 ++++++++++++++++++++++++++++ 5 files changed, 1123 insertions(+), 1 deletion(-) create mode 100755 configs/GTX480/mcpat.xml create mode 100644 configs/QuadroFX5600/gpgpusim.config create mode 100644 configs/QuadroFX5600/icnt_config_islip.txt create mode 100755 configs/QuadroFX5600/mcpat.xml (limited to 'configs') diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index abd9627..fdb2aa9 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -54,7 +54,7 @@ #-gpgpu_shmem_size 16384 # 64 sets, each 256 bytes 8-way for each memory partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:256:8,L:B:m:W,A:32:4,4 +-gpgpu_cache:dl2 64:128:16,L:B:m:W,A:32:4,4 -gpgpu_cache:dl2_texture_only 0 -gpgpu_cache:il1 4:128:4,L:R:f:N,A:2:32,4 diff --git a/configs/GTX480/mcpat.xml b/configs/GTX480/mcpat.xml new file mode 100755 index 0000000..9a3f8a1 --- /dev/null +++ b/configs/GTX480/mcpat.xml @@ -0,0 +1,498 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config new file mode 100644 index 0000000..d0c567b --- /dev/null +++ b/configs/QuadroFX5600/gpgpusim.config @@ -0,0 +1,81 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 12 + +# high level architecture configuration +-gpgpu_n_clusters 8 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 6 +-gpgpu_clock_domains 337.5:600.0:600.0:800.0 + +# shader core pipeline config +-gpgpu_shader_registers 16384 +#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though) +-gpgpu_shader_core_pipeline 768:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,1,1,1,1,1,1 +-gpgpu_num_sp_units 1 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 1,1,19,25,145 +-ptx_opcode_initiation_int 1,1,4,4,32 +-ptx_opcode_latency_fp 1,1,1,1,30 +-ptx_opcode_initiation_fp 1,1,1,1,5 +-ptx_opcode_latency_dp 8,8,8,8,335 +-ptx_opcode_initiation_dp 8,8,8,8,130 + +# memory stage behaviour +# ::,:::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +-gpgpu_cache:il1 4:256:4,L:R:f:N,A:2:32,4 +-gpgpu_tex_cache:l1 8:128:5,L:R:m:N,F:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4 +-gpgpu_cache:dl2 16:256:8,L:B:m:W,A:16:4,4 +-gpgpu_cache:dl2_texture_only 1 + +-gpgpu_shmem_warp_parts 2 + +# interconnection +-network_mode 1 +-inter_config_file icnt_config_islip.txt + +# dram model config +-gpgpu_dram_scheduler 1 +-gpgpu_dram_sched_queue_size 16 +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 4 +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS +# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz +# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6:11:1:0:0 + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 + + + +# Using cuobjdump to extract ptx/SASS +-gpgpu_ptx_use_cuobjdump 1 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 1 +-gpgpu_ptx_save_converted_ptxplus 1 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 + +-visualizer_enabled 0 +-mcpat_printing_enabled 0 +REPLACE_SWEEP_PARAM diff --git a/configs/QuadroFX5600/icnt_config_islip.txt b/configs/QuadroFX5600/icnt_config_islip.txt new file mode 100644 index 0000000..b321d0a --- /dev/null +++ b/configs/QuadroFX5600/icnt_config_islip.txt @@ -0,0 +1,49 @@ +use_map = 0; +flit_size = 32; + +network_count = 2; + +// Topology +topology = fly; +k = 14; +n = 1; + +// Routing +routing_function = dest_tag;//dim_order;//min_adapt;//dim_order;//_ni; + +// Flow control +num_vcs = 1; //4; +vc_buf_size = 8; //16; +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip;//i1_pim; //islip; //pim +sw_allocator = islip;//i1_pim;//islip; //pim +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 0; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic (DO NOT CHANGE THIS) +traffic = gpgpusim; + +//not used in gpgpusim +// const_flits_per_packet = 3; +injection_process = gpgpu_injector; +// Simulation +//not used in gpgpusim +sim_type = latency; +injection_rate = 0.1; + + +// Statistics for Interconnection (Added for GPGPU-Sim) +MATLAB_OUTPUT = 1; // output data in MATLAB friendly format +DISPLAY_LAT_DIST = 1; // distribution of packet latencies +DISPLAY_HOP_DIST = 1; // distribution of hop counts +DISPLAY_PAIR_LATENCY = 0; diff --git a/configs/QuadroFX5600/mcpat.xml b/configs/QuadroFX5600/mcpat.xml new file mode 100755 index 0000000..6100200 --- /dev/null +++ b/configs/QuadroFX5600/mcpat.xml @@ -0,0 +1,494 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.3