From 3863ad27814eefe2d26b2eba7eb8a4ab65bef5a4 Mon Sep 17 00:00:00 2001 From: Wilson Fung Date: Wed, 24 Oct 2012 23:45:37 -0800 Subject: Updated the option parser to support named sub-options (via a separate instance of option parser). Changed DRAM timing options to use this new format. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14457] --- configs/GTX480/gpgpusim.config | 9 ++------- configs/QuadroFX5800/gpgpusim.config | 3 +-- configs/TeslaC2050/gpgpusim.config | 9 ++------- 3 files changed, 5 insertions(+), 16 deletions(-) (limited to 'configs') diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index a8eac01..fd23e57 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -83,13 +83,8 @@ # GDDR5 timing from hynix H5GQ1H24AFR # to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 -# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} -# -gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:CL=12: -# WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2 --gpgpu_dram_timing_opt 16:2:6:12:28:12:40:12:4:5:12:4:3:2 - -# GDDR3 -#-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6:11 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" # Fermi has two schedulers per core -gpgpu_num_sched_per_core 2 diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index 638f362..903c12e 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -55,8 +55,7 @@ -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS # GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz -# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6:11:1:0:0 +-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 # stat collection -gpgpu_memlatency_stat 14 diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config index f09e391..86f0d85 100644 --- a/configs/TeslaC2050/gpgpusim.config +++ b/configs/TeslaC2050/gpgpusim.config @@ -84,13 +84,8 @@ # GDDR5 timing from hynix H5GQ1H24AFR # to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 -# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} -# -gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:CL=12: -# WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2 --gpgpu_dram_timing_opt 16:2:6:12:28:12:40:12:4:5:12:4:3:2 - -# GDDR3 -#-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6:11 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" # Fermi has two schedulers per core -gpgpu_num_sched_per_core 2 -- cgit v1.3