From bcb7b8f86f7b487ff0b106e3a2f37f95d989fd07 Mon Sep 17 00:00:00 2001
From: tgrogers <tgrogers@purdue.edu>
Date: Wed, 28 Mar 2018 16:55:28 -0400
Subject: 20 makes no sense for this part

---
 configs/GeForceGTX1080Ti/gpgpusim.config | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'configs')

diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config
index 47c2b6a..a5ada34 100644
--- a/configs/GeForceGTX1080Ti/gpgpusim.config
+++ b/configs/GeForceGTX1080Ti/gpgpusim.config
@@ -3,7 +3,7 @@
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 20 
+-gpgpu_ptx_force_max_capability 61
 
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
-- 
cgit v1.3


From e096e97dc6d38e26d21a83347bd0367cb6d78aeb Mon Sep 17 00:00:00 2001
From: Suchita Pati <spati@cs.wisc.edu>
Date: Tue, 1 May 2018 15:18:11 -0500
Subject: Added -save_embedded_ptx 1 to config files

---
 configs/GTX480/gpgpusim.config           | 3 +++
 configs/GeForceGTX1080Ti/gpgpusim.config | 3 +++
 configs/GeForceGTX750Ti/gpgpusim.config  | 3 +++
 configs/QuadroFX5600/gpgpusim.config     | 3 +++
 configs/QuadroFX5800/gpgpusim.config     | 3 +++
 configs/TeslaC2050/gpgpusim.config       | 3 +++
 6 files changed, 18 insertions(+)

(limited to 'configs')

diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config
index 436cb41..580929f 100644
--- a/configs/GTX480/gpgpusim.config
+++ b/configs/GTX480/gpgpusim.config
@@ -1,3 +1,6 @@
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config
index a5ada34..6d8b43a 100644
--- a/configs/GeForceGTX1080Ti/gpgpusim.config
+++ b/configs/GeForceGTX1080Ti/gpgpusim.config
@@ -1,5 +1,8 @@
 # This config models the Pascal GP102 (GeForceGTX 1080Ti)
 
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config
index 8b030b6..b6870b0 100644
--- a/configs/GeForceGTX750Ti/gpgpusim.config
+++ b/configs/GeForceGTX750Ti/gpgpusim.config
@@ -1,3 +1,6 @@
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config
index cb87b65..6f6e032 100644
--- a/configs/QuadroFX5600/gpgpusim.config
+++ b/configs/QuadroFX5600/gpgpusim.config
@@ -1,3 +1,6 @@
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config
index 82243c2..77d9c6d 100644
--- a/configs/QuadroFX5800/gpgpusim.config
+++ b/configs/QuadroFX5800/gpgpusim.config
@@ -1,3 +1,6 @@
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config
index 442ab8b..480aaa4 100644
--- a/configs/TeslaC2050/gpgpusim.config
+++ b/configs/TeslaC2050/gpgpusim.config
@@ -1,3 +1,6 @@
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
-- 
cgit v1.3


From 112a3a2e3c9d17af420d2389f68a35407c692744 Mon Sep 17 00:00:00 2001
From: tgrogers <tgrogers@purdue.edu>
Date: Fri, 29 Jun 2018 17:34:22 -0400
Subject: Allowing modern GPU configrations to properly run PTXPLUS. There are
 several problems with this:

1) To get proper occupancy, based on register file usage, you must querry ptxas with
   the sm version that corresponds to the register usage in the config file. To enable this,
   a new config option has been added that determines what sm version you pass to ptxas to compute reg-usage.
   This configuration option is always required in the gpgpusim.config file
2) If you are running PTXPLUS with a modern card (i.e. volta/pascal), you need ptxas from CUDA 9.1.
   However since PTXPLUS only supports sm_13 - you need a version of CUDA where cudaobjectdump
   supports sm_1x. This ended at CUDA 5 - and PTXPLUS requires CUDA 4.2. Therefore, to run PTXPLUS
   on a modern card, you need CUDA 4.2 + modern CUDA installed. To fascilitate this, a new envronment
   varaible is added and the setup envrionment script prints an appropraite warning if you are using a newer CUDA.

We have tried to make this as fail-proof as possible - and die appropraitely when something is wrong.
---
 configs/GTX480/gpgpusim.config           |  1 +
 configs/GeForceGTX1080Ti/gpgpusim.config |  3 ++-
 configs/GeForceGTX750Ti/gpgpusim.config  |  1 +
 configs/QuadroFX5600/gpgpusim.config     |  3 +++
 configs/QuadroFX5800/gpgpusim.config     |  2 ++
 configs/TeslaC2050/gpgpusim.config       |  1 +
 libcuda/cuda_runtime_api.cc              | 43 +++++++++++++++++++++-----------
 libopencl/opencl_runtime_api.cc          |  2 +-
 setup_environment                        | 13 ++++++++++
 src/cuda-sim/ptx_loader.cc               | 18 ++++++++++---
 src/cuda-sim/ptx_loader.h                |  2 +-
 11 files changed, 67 insertions(+), 22 deletions(-)

(limited to 'configs')

diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config
index 436cb41..ee90c12 100644
--- a/configs/GTX480/gpgpusim.config
+++ b/configs/GTX480/gpgpusim.config
@@ -22,6 +22,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
 
 # This implies a maximum of 48 warps/SM
 -gpgpu_shader_core_pipeline 1536:32 
diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config
index 47c2b6a..fb044c6 100644
--- a/configs/GeForceGTX1080Ti/gpgpusim.config
+++ b/configs/GeForceGTX1080Ti/gpgpusim.config
@@ -3,7 +3,7 @@
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 20 
+-gpgpu_ptx_force_max_capability 60
 
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
@@ -23,6 +23,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 60
 
 # This implies a maximum of 64 warps/SM
 -gpgpu_shader_core_pipeline 2048:32 
diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config
index 8b030b6..c675aab 100644
--- a/configs/GeForceGTX750Ti/gpgpusim.config
+++ b/configs/GeForceGTX750Ti/gpgpusim.config
@@ -21,6 +21,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 52
 
 # This implies a maximum of 64 warps/SM
 -gpgpu_shader_core_pipeline 2048:32 
diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config
index cb87b65..6f836ee 100644
--- a/configs/QuadroFX5600/gpgpusim.config
+++ b/configs/QuadroFX5600/gpgpusim.config
@@ -11,6 +11,9 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 16384
+-gpgpu_occupancy_sm_number 12
+
+-gpgpu_occupancy_sm_number 12
 #8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though)
 -gpgpu_shader_core_pipeline 768:32 
 -gpgpu_shader_cta 8
diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config
index 82243c2..fef1110 100644
--- a/configs/QuadroFX5800/gpgpusim.config
+++ b/configs/QuadroFX5800/gpgpusim.config
@@ -11,6 +11,8 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 16384
+-gpgpu_occupancy_sm_number 13
+
 -gpgpu_shader_core_pipeline 1024:32 
 -gpgpu_shader_cta 8
 -gpgpu_simd_model 1
diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config
index 442ab8b..6ac2c12 100644
--- a/configs/TeslaC2050/gpgpusim.config
+++ b/configs/TeslaC2050/gpgpusim.config
@@ -25,6 +25,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
 
 # This implies a maximum of 48 warps/SM
 -gpgpu_shader_core_pipeline 1536:32 
diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc
index 2b0f944..94705dc 100644
--- a/libcuda/cuda_runtime_api.cc
+++ b/libcuda/cuda_runtime_api.cc
@@ -1350,39 +1350,52 @@ std::string get_app_binary(){
  *	enabled
  * */
 void extract_code_using_cuobjdump(){
-	CUctx_st *context = GPGPUSim_Context();
-	char command[1000];
+    CUctx_st *context = GPGPUSim_Context();
+    std::string command;
 
-   std::string app_binary = get_app_binary(); 
+    std::string app_binary = get_app_binary(); 
 
 	char fname[1024];
 	snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX");
 	int fd=mkstemp(fname);
 	close(fd);
 	// Running cuobjdump using dynamic link to current process
-	snprintf(command,1000,"md5sum %s ", app_binary.c_str());
-	printf("Running md5sum using \"%s\"\n", command);
-	system(command);
+    command = "md5sum " + app_binary;
+	printf("Running md5sum using \"%s\"\n", command.c_str());
+	system(command.c_str());
 	// Running cuobjdump using dynamic link to current process
 	// Needs the option '-all' to extract PTX from CDP-enabled binary 
 	extern bool g_cdp_enabled;
+    const int current_cuda = atoi(getenv("CUDA_VERSION_NUMBER"));
+    if ( context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() && current_cuda > 42 ) {
+        const char* cuda_42_path = getenv("CUDA_42_INSTALL_PATH");
+        if ( NULL == cuda_42_path ) {
+            printf("You are using a new version of CUDA and PTXPLUS. You are required to have CUDA SDK 4.2 and explicitly "
+                   "point to it via the environment variable $CUDA_42_INSTALL_PATH.");
+            exit(1);
+        } else {
+            command = "$CUDA_42_INSTALL_PATH/bin/cuobjdump";
+        }
+    } else {
+        command = "$CUDA_INSTALL_PATH/bin/cuobjdump";
+    }
 	if(!g_cdp_enabled)
-	    snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname);
+        command += " -ptx -elf -sass " + app_binary + " > " + fname;
 	else
-	    snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname);
+        command += " -ptx -elf -sass -all " + app_binary + " > " + fname;
 	bool parse_output = true; 
-	int result = system(command);
+	int result = system(command.c_str());
 	if(result) {
 		if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support() && (result == 65280)) {  
 			// Some CUDA application may exclusively use kernels provided by CUDA
 			// libraries (e.g. CUBLAS).  Skipping cuobjdump extraction from the
 			// executable for this case. 
 			// 65280 is the return code from cuobjdump denoting the specific error (tested on CUDA 4.0/4.1/4.2)
-			printf("WARNING: Failed to execute: %s\n", command); 
+			printf("WARNING: Failed to execute: %s\n", command.c_str()); 
 			printf("         Executable binary does not contain any GPU kernel.\n"); 
 			parse_output = false; 
 		} else {
-			printf("ERROR: Failed to execute: %s\n", command); 
+			printf("ERROR: Failed to execute: %s\n", command.c_str()); 
 			exit(1);
 		}
 	}
@@ -1435,7 +1448,7 @@ void extract_code_using_cuobjdump(){
 			std::cout << "Running cuobjdump on " << line << std::endl;
 			std::cout << "Using command: " << cmd.str() << std::endl;
 			result = system(cmd.str().c_str());
-			if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);}
+			if(result) {printf("ERROR: Failed to execute: %s\n", command.c_str()); exit(1);}
 			std::cout << "Done" << std::endl;
 
 			std::cout << "Trying to parse " << libcodfn.str() << std::endl;
@@ -1737,13 +1750,13 @@ void cuobjdumpParseBinary(unsigned int handle){
         symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxplus_str, handle);
         printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle);
         context->add_binary(symtab, handle);
-        gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability );
+        gpgpu_ptxinfo_load_from_string( ptxcode, handle );
         delete[] ptxplus_str;
     } else {
         symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxcode, handle);
         printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle);
         context->add_binary(symtab, handle);
-        gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability );
+        gpgpu_ptxinfo_load_from_string( ptxcode, handle );
     }
     load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu());
     load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu());
@@ -1847,7 +1860,7 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin )
 			} else {
 				symtab=gpgpu_ptx_sim_load_ptx_from_string(ptx,source_num);
 				context->add_binary(symtab,fat_cubin_handle);
-				gpgpu_ptxinfo_load_from_string( ptx, source_num, max_capability );
+				gpgpu_ptxinfo_load_from_string( ptx, source_num );
 			}
 			source_num++;
 			load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu());
diff --git a/libopencl/opencl_runtime_api.cc b/libopencl/opencl_runtime_api.cc
index 63f7c81..97a54d8 100644
--- a/libopencl/opencl_runtime_api.cc
+++ b/libopencl/opencl_runtime_api.cc
@@ -577,7 +577,7 @@ void _cl_program::Build(const char *options)
       }
       info.m_asm = tmp;
       info.m_symtab = gpgpu_ptx_sim_load_ptx_from_string( tmp, source_num );
-      gpgpu_ptxinfo_load_from_string( tmp, source_num);
+      gpgpu_ptxinfo_load_from_string( tmp, source_num );
       free(tmp);
    }
    printf("GPGPU-Sim OpenCL API: finished compiling OpenCL kernels.\n"); 
diff --git a/setup_environment b/setup_environment
index 3f2476e..939fb85 100644
--- a/setup_environment
+++ b/setup_environment
@@ -53,6 +53,8 @@ if [ $CUDA_VERSION_NUMBER -gt 9100 -o $CUDA_VERSION_NUMBER -lt 2030  ]; then
 	return
 fi
 
+
+
 if [ $# = '1' ] ;
 then
     export GPGPUSIM_CONFIG=gcc-$CC_VERSION/cuda-$CUDA_VERSION_NUMBER/$1
@@ -134,4 +136,15 @@ fi
 
 echo "setup_environment succeeded";
 
+if [ $CUDA_VERSION_NUMBER -gt 4200 ]; then
+    echo ""
+    echo "----------------------------------------------------------------------------"
+    echo "WARNING - If you only care about PTX execution, ignore this warning.";
+    echo "If you are using PTXPLUS, only sm_13 is supported and it requires that the app binaries are compiled in CUDA 4.2 or less.";
+    echo "New versions of CUDA tools have dropped parsing support for sm_1x - therefore to use PTXPLUS with a modern card configuration, you must";
+    echo "have both CUDA 4.2 and a modern CUDA installed. When running PTXPLUS under a CUDA version >= 4.2, the simulator will fail unless \$CUDA_42_INSTALL_PATH";
+    echo "has been set properly. You must set this manually.";
+    echo "----------------------------------------------------------------------------"
+fi
+
 export GPGPUSIM_SETUP_ENVIRONMENT_WAS_RUN=1
diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc
index 6c1b595..99174cf 100644
--- a/src/cuda-sim/ptx_loader.cc
+++ b/src/cuda-sim/ptx_loader.cc
@@ -54,6 +54,7 @@ extern int ptxinfo_debug;
 extern FILE *ptxinfo_in;
 
 static bool g_save_embedded_ptx;
+static int g_occupancy_sm_number;
 bool g_keep_intermediate_files;
 bool m_ptx_save_converted_ptxplus;
 
@@ -71,6 +72,10 @@ void ptx_reg_options(option_parser_t opp)
                 &m_ptx_save_converted_ptxplus,
                 "Saved converted ptxplus to a file",
                 "0");
+   option_parser_register(opp, "-gpgpu_occupancy_sm_number", OPT_INT32, &g_occupancy_sm_number,
+                "The SM number to pass to ptxas when getting register usage for computing GPU occupancy."
+                "This parameter is required in the config.",
+                "0");
 }
 
 void print_ptx_file( const char *p, unsigned source_num, const char *filename )
@@ -287,7 +292,7 @@ void fix_duplicate_errors(char fname2[1024]) {
 	}
 }
 
-void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version )
+void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num )
 {
     char fname[1024];
     snprintf(fname,1024,"_ptx_XXXXXX");
@@ -321,12 +326,17 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num
     extra_flags[0]=0;
 
 #if CUDART_VERSION >= 3000
-    if (sm_version == 0) sm_version = 20;
+    if ( g_occupancy_sm_number == 0 ) {
+        printf( "gpgpusim.config must specify the sm version for the GPU that you use to compute occupancy.\n"
+                "The register file size is specifically tied to the sm version used to querry ptxas for register usage."
+                "A register size/SM mismatch may result in occupancy differences." );
+        exit(1);
+    }
     extern bool g_cdp_enabled;
     if(!g_cdp_enabled)
-        snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version);
+        snprintf(extra_flags,1024,"--gpu-name=sm_%u", g_occupancy_sm_number);
     else
-        snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version);
+        snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",g_occupancy_sm_number);
 #endif
 
     snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file  /dev/null 2> %s",
diff --git a/src/cuda-sim/ptx_loader.h b/src/cuda-sim/ptx_loader.h
index d3d0c92..cb02eda 100644
--- a/src/cuda-sim/ptx_loader.h
+++ b/src/cuda-sim/ptx_loader.h
@@ -32,7 +32,7 @@
 extern bool g_override_embedded_ptx;
  
 class symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source_num );
-void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version=20 );
+void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num );
 char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptx_str, const std::string sass_str, const std::string elf_str);
 bool keep_intermediate_files();
 
-- 
cgit v1.3


From a3e64bb5465b2384c46003947c3b874892ba2f5f Mon Sep 17 00:00:00 2001
From: Mahmoud <k.mkhairy@yahoo.com>
Date: Sun, 1 Jul 2018 20:55:32 -0400
Subject: Adding Pascal_TITANX config files

---
 configs/Pascal_TITANX/config_fermi_islip.icnt |  70 ++++++++++++
 configs/Pascal_TITANX/gpgpusim.config         | 156 ++++++++++++++++++++++++++
 2 files changed, 226 insertions(+)
 create mode 100644 configs/Pascal_TITANX/config_fermi_islip.icnt
 create mode 100644 configs/Pascal_TITANX/gpgpusim.config

(limited to 'configs')

diff --git a/configs/Pascal_TITANX/config_fermi_islip.icnt b/configs/Pascal_TITANX/config_fermi_islip.icnt
new file mode 100644
index 0000000..602daee
--- /dev/null
+++ b/configs/Pascal_TITANX/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/Pascal_TITANX/gpgpusim.config b/configs/Pascal_TITANX/gpgpusim.config
new file mode 100644
index 0000000..f78bd02
--- /dev/null
+++ b/configs/Pascal_TITANX/gpgpusim.config
@@ -0,0 +1,156 @@
+# This config models the Pascal GP102 (NVIDIA TITAN X)
+# For more info about this card, see Nvidia White paper
+# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 61
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# SFU is 32-width in pascal, then dp units initiation is 1 cycle
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,8,4,4,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory
+# Pascal GP102 has 64KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres is used
+-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_shmem_size 98304
+-gpgpu_shmem_size_PrefL1 98304
+-gpgpu_shmem_size_PrefShared 98304
+-gmem_skip_L1D 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
+
+# 4 KB Inst.
+-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+
+# enable operand collector 
+## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
+-gpgpu_operand_collector_num_units_sp 20
+-gpgpu_operand_collector_num_units_sfu 4
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+# gpgpu_num_reg_banks should be increased to 32
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
+# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing from hynix H5GQ1H24AFR
+# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
-- 
cgit v1.3


From 8c81c1d04e8d20b08f122a12ce090b4f926adb4c Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 22 Aug 2018 10:19:52 -0400
Subject: adding lazy-fetch-on-read and invalidate operation to cache

---
 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config |   2 +-
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config |   2 +-
 src/gpgpu-sim/gpu-cache.cc                  | 110 ++++++++++++++++------------
 src/gpgpu-sim/gpu-cache.h                   |  22 ++++--
 src/gpgpu-sim/gpu-sim.cc                    |   6 +-
 src/gpgpu-sim/l2cache.cc                    |  12 ++-
 src/gpgpu-sim/l2cache.h                     |   1 +
 src/gpgpu-sim/shader.cc                     |  16 ++++
 src/gpgpu-sim/shader.h                      |   3 +
 9 files changed, 115 insertions(+), 59 deletions(-)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 3097d19..7368882 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -73,7 +73,7 @@
 -gpgpu_n_cluster_ejection_buffer_size 32
 
 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:128:4,16:0,32
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:128:4,16:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 32:32:32:32
 -perf_sim_memcpy 0
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index 8969168..da98547 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -78,7 +78,7 @@
 -gpgpu_n_cluster_ejection_buffer_size 32
 
 # 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
--gpgpu_cache:dl2 S:64:128:24,L:B:m:F:L,A:256:4,32:0,32
+-gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:256:4,32:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 64:64:64:64
 -perf_sim_memcpy 0
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index 75ec00a..9d81de9 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -382,6 +382,8 @@ void tag_array::fill( unsigned index, unsigned time, mem_fetch* mf)
     m_lines[index]->fill(time, mf->get_access_sector_mask());
 }
 
+
+//TODO: we need write back the flushed data to the upper level
 void tag_array::flush() 
 {
     for (unsigned i=0; i < m_config.get_num_lines(); i++)
@@ -391,6 +393,13 @@ void tag_array::flush()
     	}
 }
 
+void tag_array::invalidate()
+{
+    for (unsigned i=0; i < m_config.get_num_lines(); i++)
+    	for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++)
+    		m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ;
+}
+
 float tag_array::windowed_miss_rate( ) const
 {
     unsigned n_access    = m_access - m_prev_snapshot_access;
@@ -1162,52 +1171,7 @@ data_cache::wr_miss_wa_fetch_on_write( new_addr_type addr,
                         unsigned time, std::list<cache_event> &events,
                         enum cache_request_status status )
 {
-
-	new_addr_type block_addr = m_config.block_addr(addr);
-	    new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr());
-
-
-			//if the request writes to the whole cache line/sector, then, write and set cache line Modified.
-			//and no need to send read request to memory or reserve mshr
-
-			if(miss_queue_full(0)) {
-				m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL);
-				return RESERVATION_FAIL; // cannot handle request this cycle
-			}
-
-			bool wb = false;
-			evicted_block_info evicted;
-
-			cache_request_status m_status =  m_tag_array->access(block_addr,time,cache_index,wb,evicted,mf);
-			assert(m_status != HIT);
-			cache_block_t* block = m_tag_array->get_block(cache_index);
-			block->set_status(MODIFIED, mf->get_access_sector_mask());
-			if(m_status == HIT_RESERVED) {
-				block->set_ignore_on_fill(true, mf->get_access_sector_mask());
-				block->set_modified_on_fill(true, mf->get_access_sector_mask());
-			}
-
-			if(mf->get_access_byte_mask().count() == m_config.get_atom_sz())
-			{
-				block->set_m_readable(true, mf->get_access_sector_mask());
-			} else
-			{
-				block->set_m_readable(false, mf->get_access_sector_mask());
-			}
-
-			if( m_status != RESERVATION_FAIL ){
-				   // If evicted block is modified and not a write-through
-				   // (already modified lower level)
-				   if( wb && (m_config.m_write_policy != WRITE_THROUGH) ) {
-					   mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr,
-						   m_wrbk_type,evicted.m_modified_size,true);
-					   send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events);
-				   }
-				   return MISS;
-			   }
-			return RESERVATION_FAIL;
-
-	/*new_addr_type block_addr = m_config.block_addr(addr);
+    new_addr_type block_addr = m_config.block_addr(addr);
     new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr());
 
 	if(mf->get_access_byte_mask().count() == m_config.get_atom_sz())
@@ -1316,7 +1280,59 @@ data_cache::wr_miss_wa_fetch_on_write( new_addr_type addr,
 				return MISS;
 			}
 	   return RESERVATION_FAIL;
-	}*/
+	}
+}
+
+enum cache_request_status
+data_cache::wr_miss_wa_lazy_fetch_on_read( new_addr_type addr,
+                        unsigned cache_index, mem_fetch *mf,
+                        unsigned time, std::list<cache_event> &events,
+                        enum cache_request_status status )
+{
+
+	    new_addr_type block_addr = m_config.block_addr(addr);
+	    new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr());
+
+
+			//if the request writes to the whole cache line/sector, then, write and set cache line Modified.
+			//and no need to send read request to memory or reserve mshr
+
+			if(miss_queue_full(0)) {
+				m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL);
+				return RESERVATION_FAIL; // cannot handle request this cycle
+			}
+
+			bool wb = false;
+			evicted_block_info evicted;
+
+			cache_request_status m_status =  m_tag_array->access(block_addr,time,cache_index,wb,evicted,mf);
+			assert(m_status != HIT);
+			cache_block_t* block = m_tag_array->get_block(cache_index);
+			block->set_status(MODIFIED, mf->get_access_sector_mask());
+			if(m_status == HIT_RESERVED) {
+				block->set_ignore_on_fill(true, mf->get_access_sector_mask());
+				block->set_modified_on_fill(true, mf->get_access_sector_mask());
+			}
+
+			if(mf->get_access_byte_mask().count() == m_config.get_atom_sz())
+			{
+				block->set_m_readable(true, mf->get_access_sector_mask());
+			} else
+			{
+				block->set_m_readable(false, mf->get_access_sector_mask());
+			}
+
+			if( m_status != RESERVATION_FAIL ){
+				   // If evicted block is modified and not a write-through
+				   // (already modified lower level)
+				   if( wb && (m_config.m_write_policy != WRITE_THROUGH) ) {
+					   mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr,
+						   m_wrbk_type,evicted.m_modified_size,true);
+					   send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events);
+				   }
+				   return MISS;
+			   }
+			return RESERVATION_FAIL;
 }
 
 /// No write-allocate miss: Simply send write request to lower level memory
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index d2b7757..96b9a6d 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -454,7 +454,8 @@ enum allocation_policy_t {
 enum write_allocate_policy_t {
 	NO_WRITE_ALLOCATE,
 	WRITE_ALLOCATE,
-	FETCH_ON_WRITE
+	FETCH_ON_WRITE,
+	LAZY_FETCH_ON_READ
 };
 
 enum mshr_config_t {
@@ -555,6 +556,7 @@ public:
         case 'N': m_write_alloc_policy = NO_WRITE_ALLOCATE; break;
         case 'W': m_write_alloc_policy = WRITE_ALLOCATE; break;
         case 'F': m_write_alloc_policy = FETCH_ON_WRITE; break;
+        case 'L': m_write_alloc_policy = LAZY_FETCH_ON_READ; break;
 		default: exit_parse_error();
         }
 
@@ -572,9 +574,9 @@ public:
             assert(0 && "Invalid cache configuration: Writeback cache cannot allocate new line on fill. "); 
         }
 
-        if(m_write_alloc_policy == FETCH_ON_WRITE && m_alloc_policy == ON_FILL)
+        if((m_write_alloc_policy == FETCH_ON_WRITE || m_write_alloc_policy == LAZY_FETCH_ON_READ )&& m_alloc_policy == ON_FILL)
 		{
-			assert(0 && "Invalid cache configuration: FETCH_ON_WRITE cannot work properly with ON_FILL policy. Cache must be ON_MISS. ");
+			assert(0 && "Invalid cache configuration: FETCH_ON_WRITE and LAZY_FETCH_ON_READ cannot work properly with ON_FILL policy. Cache must be ON_MISS. ");
 		}
         if(m_cache_type == SECTOR)
 		{
@@ -742,7 +744,8 @@ public:
     unsigned size() const { return m_config.get_num_lines();}
     cache_block_t* get_block(unsigned idx) { return m_lines[idx];}
 
-    void flush(); // flash invalidate all entries
+    void flush(); // flush all written entries
+    void invalidate(); // invalidate all entries
     void new_window();
 
     void print( FILE *stream, unsigned &total_access, unsigned &total_misses ) const;
@@ -994,6 +997,7 @@ public:
     mem_fetch *next_access(){return m_mshrs.next_access();}
     // flash invalidate all entries in cache
     void flush(){m_tag_array->flush();}
+    void invalidate(){m_tag_array->invalidate();}
     void print(FILE *fp, unsigned &accesses, unsigned &misses) const;
     void display_state( FILE *fp ) const;
 
@@ -1179,6 +1183,7 @@ public:
         case NO_WRITE_ALLOCATE: m_wr_miss = &data_cache::wr_miss_no_wa; break;
 		case WRITE_ALLOCATE: m_wr_miss = &data_cache::wr_miss_wa_naive; break;
 		case FETCH_ON_WRITE: m_wr_miss = &data_cache::wr_miss_wa_fetch_on_write; break;
+		case LAZY_FETCH_ON_READ: m_wr_miss = &data_cache::wr_miss_wa_lazy_fetch_on_read; break;
         default:
             assert(0 && "Error: Must set valid cache write miss policy\n");
             break; // Need to set a write miss function
@@ -1299,7 +1304,14 @@ protected:
 							mem_fetch *mf,
 							unsigned time,
 							std::list<cache_event> &events,
-							enum cache_request_status status ); // write-allocate with read-fetch-only
+							enum cache_request_status status ); // write-allocate with fetch-on-every-write
+	enum cache_request_status
+				   wr_miss_wa_lazy_fetch_on_read( new_addr_type addr,
+								unsigned cache_index,
+								mem_fetch *mf,
+								unsigned time,
+								std::list<cache_event> &events,
+								enum cache_request_status status ); // write-allocate with read-fetch-only
 	enum cache_request_status
 				wr_miss_wa_write_validate( new_addr_type addr,
 							unsigned cache_index,
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index c5d4464..d48de25 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -1548,12 +1548,12 @@ void gpgpu_sim::cycle()
 
       issue_block2core();
       
-      // Depending on configuration, flush the caches once all of threads are completed.
+      // Depending on configuration, invalidate the caches once all of threads are completed.
       int all_threads_complete = 1;
       if (m_config.gpgpu_flush_l1_cache) {
          for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++) {
             if (m_cluster[i]->get_not_completed() == 0)
-                m_cluster[i]->cache_flush();
+                m_cluster[i]->cache_invalidate();
             else
                all_threads_complete = 0 ;
          }
@@ -1575,7 +1575,7 @@ void gpgpu_sim::cycle()
                int dlc = 0;
                for (unsigned i=0;i<m_memory_config->m_n_mem;i++) {
                   dlc = m_memory_sub_partition[i]->flushL2();
-                  assert (dlc == 0); // need to model actual writes to DRAM here
+                  assert (dlc == 0); // TODO: need to model actual writes to DRAM here
                   printf("Dirty lines flushed from L2 %d is %d\n", i, dlc  );
                }
             }
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index b1465a8..359d3c8 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -428,7 +428,7 @@ void memory_sub_partition::cache_cycle( unsigned cycle )
                         m_icnt_L2_queue->pop();
                     }
                 } else if ( status != RESERVATION_FAIL ) {
-                	if(mf->is_write() && m_config->m_L2_config.m_write_alloc_policy == FETCH_ON_WRITE && !was_writeallocate_sent(events)) {
+                	if(mf->is_write() && (m_config->m_L2_config.m_write_alloc_policy == FETCH_ON_WRITE || m_config->m_L2_config.m_write_alloc_policy == LAZY_FETCH_ON_READ) && !was_writeallocate_sent(events)) {
                 		mf->set_reply();
                 		mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
                 		m_L2_icnt_queue->push(mf);
@@ -568,7 +568,15 @@ unsigned memory_sub_partition::flushL2()
     if (!m_config->m_L2_config.disabled()) {
         m_L2cache->flush(); 
     }
-    return 0; // L2 is read only in this version
+    return 0;   //TODO: write the flushed data to the main memory
+}
+
+unsigned memory_sub_partition::invalidateL2()
+{
+    if (!m_config->m_L2_config.disabled()) {
+        m_L2cache->invalidate();
+    }
+    return 0;
 }
 
 bool memory_sub_partition::busy() const 
diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h
index 2d13918..18c0a8b 100644
--- a/src/gpgpu-sim/l2cache.h
+++ b/src/gpgpu-sim/l2cache.h
@@ -162,6 +162,7 @@ public:
    void set_done( mem_fetch *mf );
 
    unsigned flushL2();
+   unsigned invalidateL2();
 
    // interface to L2_dram_queue
    bool L2_dram_queue_empty() const; 
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index d2f40a1..b660b8c 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1593,6 +1593,11 @@ void ldst_unit::flush(){
 	m_L1D->flush();
 }
 
+void ldst_unit::invalidate(){
+	// Flush L1D cache
+	m_L1D->invalidate();
+}
+
 simd_function_unit::simd_function_unit( const shader_core_config *config )
 { 
     m_config=config;
@@ -2644,6 +2649,11 @@ void shader_core_ctx::cache_flush()
    m_ldst_unit->flush();
 }
 
+void shader_core_ctx::cache_invalidate()
+{
+   m_ldst_unit->invalidate();
+}
+
 // modifiers
 std::list<opndcoll_rfu_t::op_t> opndcoll_rfu_t::arbiter_t::allocate_reads() 
 {
@@ -3461,6 +3471,12 @@ void simt_core_cluster::cache_flush()
         m_core[i]->cache_flush();
 }
 
+void simt_core_cluster::cache_invalidate()
+{
+    for( unsigned i=0; i < m_config->n_simt_cores_per_cluster; i++ )
+        m_core[i]->cache_invalidate();
+}
+
 bool simt_core_cluster::icnt_injection_buffer_full(unsigned size, bool write)
 {
     unsigned request_size = size;
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index ae22eaa..cc441b3 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1155,6 +1155,7 @@ public:
      
     void fill( mem_fetch *mf );
     void flush();
+    void invalidate();
     void writeback();
 
     // accessors
@@ -1655,6 +1656,7 @@ public:
     void issue_block2core( class kernel_info_t &kernel );
 
     void cache_flush();
+    void cache_invalidate();
     void accept_fetch_response( mem_fetch *mf );
     void accept_ldst_unit_response( class mem_fetch * mf );
     void broadcast_barrier_reduction(unsigned cta_id, unsigned bar_id,warp_set_t warps);
@@ -1947,6 +1949,7 @@ public:
     void reinit();
     unsigned issue_block2core();
     void cache_flush();
+    void cache_invalidate();
     bool icnt_injection_buffer_full(unsigned size, bool write);
     void icnt_inject_request_packet(class mem_fetch *mf);
 
-- 
cgit v1.3


From 891fd3e19541d80106686d0e73a5dcb6d0a8536e Mon Sep 17 00:00:00 2001
From: "Mahmoud Khairy A. Abdallah" <abdallm@purdue.edu>
Date: Wed, 22 Aug 2018 10:29:24 -0400
Subject: Update gpgpusim.config

---
 configs/4.x-cfgs/SM6_P100/gpgpusim.config | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_P100/gpgpusim.config b/configs/4.x-cfgs/SM6_P100/gpgpusim.config
index a43c0bb..a4e745d 100644
--- a/configs/4.x-cfgs/SM6_P100/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_P100/gpgpusim.config
@@ -65,7 +65,7 @@
 -gpgpu_n_cluster_ejection_buffer_size 32
 
 # 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives  4MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:256:4,32:0,32
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:4,32:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 64:64:64:64
 -perf_sim_memcpy 0
-- 
cgit v1.3


From 944f6dbf23d792dde360d3a4f2334de3b541de52 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Mon, 27 Aug 2018 20:28:24 -0400
Subject: fixing ead/write buffer and new configs files

---
 configs/3.x-cfgs/GTX480/config_fermi_islip.icnt    |  70 +++
 configs/3.x-cfgs/GTX480/gpgpusim.config            | 133 +++++
 configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml       | 538 ++++++++++++++++++++
 .../GeForceGTX750Ti/config_fermi_islip.icnt        |  70 +++
 configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config   | 130 +++++
 .../GeForceGTX750Ti/gpuwattch_gtx750Ti.xml         | 539 +++++++++++++++++++++
 configs/3.x-cfgs/QuadroFX5600/gpgpusim.config      |  96 ++++
 .../QuadroFX5600/gpuwattch_quadrofx5600.xml        | 538 ++++++++++++++++++++
 .../3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt   |  70 +++
 .../3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt |  69 +++
 configs/3.x-cfgs/QuadroFX5800/gpgpusim.config      |  86 ++++
 .../3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt   |  70 +++
 configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config       | 149 ++++++
 .../3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml   | 538 ++++++++++++++++++++
 .../3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt    |  70 ---
 configs/3.x-cfgs/SM7_TITANV/gpgpusim.config        | 165 -------
 .../3.x-cfgs/TeslaC2050/config_fermi_islip.icnt    |  70 +++
 configs/3.x-cfgs/TeslaC2050/gpgpusim.config        | 132 +++++
 configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config       |  97 ----
 .../SM1_QFX5600/gpuwattch_quadrofx5600.xml         | 538 --------------------
 .../4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt    |  70 ---
 .../4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt  |  69 ---
 configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config       |  87 ----
 configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt |  70 ---
 configs/4.x-cfgs/SM2_C2050/gpgpusim.config         | 133 -----
 .../4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt    |   4 +-
 configs/4.x-cfgs/SM2_GTX480/gpgpusim.config        |  23 +-
 .../4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt    |  70 ---
 configs/4.x-cfgs/SM5_GTX750/gpgpusim.config        | 131 -----
 configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml | 539 ---------------------
 .../4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt   |  70 ---
 configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config       | 149 ------
 .../4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml   | 538 --------------------
 .../SM6_P100_64SMs/config_fermi_islip.icnt         |  73 +++
 configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config    | 174 +++++++
 .../4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt    |  74 ---
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config        | 186 -------
 src/gpgpu-sim/addrdec.cc                           |  17 +-
 src/gpgpu-sim/dram.cc                              |  12 +-
 src/gpgpu-sim/dram_sched.cc                        |   6 +-
 src/gpgpu-sim/gpu-sim.cc                           |   3 +-
 src/gpgpu-sim/shader.cc                            |   4 +-
 42 files changed, 3596 insertions(+), 3074 deletions(-)
 create mode 100644 configs/3.x-cfgs/GTX480/config_fermi_islip.icnt
 create mode 100644 configs/3.x-cfgs/GTX480/gpgpusim.config
 create mode 100755 configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml
 create mode 100644 configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
 create mode 100644 configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
 create mode 100755 configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
 create mode 100644 configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
 create mode 100644 configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
 create mode 100644 configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt
 create mode 100644 configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt
 create mode 100644 configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
 create mode 100644 configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
 create mode 100644 configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
 create mode 100755 configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
 delete mode 100644 configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
 delete mode 100644 configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
 create mode 100644 configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt
 create mode 100644 configs/3.x-cfgs/TeslaC2050/gpgpusim.config
 delete mode 100644 configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config
 delete mode 100644 configs/4.x-cfgs/SM1_QFX5600/gpuwattch_quadrofx5600.xml
 delete mode 100644 configs/4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config
 delete mode 100644 configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM2_C2050/gpgpusim.config
 delete mode 100644 configs/4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM5_GTX750/gpgpusim.config
 delete mode 100755 configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml
 delete mode 100644 configs/4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config
 delete mode 100755 configs/4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
 create mode 100644 configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt
 create mode 100644 configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config

(limited to 'configs')

diff --git a/configs/3.x-cfgs/GTX480/config_fermi_islip.icnt b/configs/3.x-cfgs/GTX480/config_fermi_islip.icnt
new file mode 100644
index 0000000..7820e4e
--- /dev/null
+++ b/configs/3.x-cfgs/GTX480/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 27;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/3.x-cfgs/GTX480/gpgpusim.config b/configs/3.x-cfgs/GTX480/gpgpusim.config
new file mode 100644
index 0000000..436cb41
--- /dev/null
+++ b/configs/3.x-cfgs/GTX480/gpgpusim.config
@@ -0,0 +1,133 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 20 
+
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 15
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 6
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Fermi clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
+# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
+-gpgpu_clock_domains 700.0:700.0:700.0:924.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+
+# This implies a maximum of 48 warps/SM
+-gpgpu_shader_core_pipeline 1536:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,1,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+
+# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+-gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_shmem_size 49152
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_shmem_size 16384
+
+# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
+-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 116
+
+# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml b/configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml
new file mode 100755
index 0000000..304e0fd
--- /dev/null
+++ b/configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
new file mode 100644
index 0000000..069ca02
--- /dev/null
+++ b/configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 7;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config b/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
new file mode 100644
index 0000000..8b030b6
--- /dev/null
+++ b/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
@@ -0,0 +1,130 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 52 
+
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 5
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 2
+-gpgpu_n_sub_partition_per_mchannel 1
+
+# Maxwell clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number.
+-gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
+-gpgpu_num_sp_units 8
+-gpgpu_num_sfu_units 32
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 6,12,13,13,210
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 6,12,6,6,374
+-ptx_opcode_initiation_fp 1,1,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
+-gmem_skip_L1D 1
+-gpgpu_shmem_size 65536
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_shmem_size 16384
+
+# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache
+-gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 150
+-dram_latency 130
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 300
+
+# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 32
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# Maxwell has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy.
+# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present.
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx750Ti.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
new file mode 100755
index 0000000..e2b2324
--- /dev/null
+++ b/configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
@@ -0,0 +1,539 @@
+<!-- THIS CONFIG IS CURRENTLY PRESENT ONLY AS A PLACEHOLDER. IT HAS NOT BEEN TESTED FOR ACCURACY VERSUS GTX750TI HARDWARE. ANY USE OF THIS CONFIG WILL LIKELY GIVE HIGHLY INACCURATE RESULTS. -->
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config b/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
new file mode 100644
index 0000000..cb87b65
--- /dev/null
+++ b/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
@@ -0,0 +1,96 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 12
+
+# high level architecture configuration
+-gpgpu_n_clusters 8 
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 6 
+-gpgpu_clock_domains 337.5:600.0:600.0:800.0 
+
+# shader core pipeline config
+-gpgpu_shader_registers 16384
+#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though)
+-gpgpu_shader_core_pipeline 768:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 1,1,1,1,1,1,1
+-gpgpu_num_sp_units 1
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 1,1,19,25,145
+-ptx_opcode_initiation_int 1,1,4,4,32
+-ptx_opcode_latency_fp 1,1,1,1,30
+-ptx_opcode_initiation_fp 1,1,1,1,5
+-ptx_opcode_latency_dp 8,8,8,8,335
+-ptx_opcode_initiation_dp 8,8,8,8,130
+
+# memory stage behaviour
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
+-gpgpu_cache:dl2_texture_only 1
+
+# TLB parameters
+#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8
+#-gpgpu_tlbl2_latency 45
+
+
+-gpgpu_shmem_warp_parts 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file icnt_config_islip.icnt 
+
+# dram scheduler config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (30 core cycles).  I.e. 
+#   Total buffer space required = 30 x 800MHz / 337.5MHz = 71
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 55
+
+# dram model config
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4 
+-gpgpu_dram_burst_length 4
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
+# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
+# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
+-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+
+
+
+# Using cuobjdump to extract ptx/SASS
+-gpgpu_ptx_use_cuobjdump 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+
+-visualizer_enabled 0
+-power_trace_enabled 0
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_quadrofx5600.xml 
+
+-steady_power_levels_enabled 1
+-steady_state_definition 8,4
diff --git a/configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
new file mode 100644
index 0000000..2c5a6fc
--- /dev/null
+++ b/configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="0"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="2"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="0"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="0"/>
+		<param name="core_tech_node" value="65"/><!-- nm -->
+		<param name="target_core_clockrate" value="650"/><!--MHz -->
+		<param name="temperature" value="400"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.54"/><!-- idle core power for GTX479 -->
+		<param name="TOT_INST" value="2" />
+		<param name="FP_INT" value="5" />
+		<param name="IC_H" value="10" />
+		<param name="IC_M" value="10" />
+		<param name="DC_RH" value="10" />
+		<param name="DC_RM" value="10" />
+		<param name="DC_WH" value="10" />
+		<param name="DC_WM" value="10" />
+		<param name="TC_H" value="20" />
+		<param name="TC_M" value="20" />
+		<param name="CC_H" value="10" />
+		<param name="CC_M" value="10" />
+		<param name="SHRD_ACC" value="20" />
+		<param name="REG_RD" value="0.25" />
+		<param name="REG_WR" value="0.4" />
+		<param name="NON_REG_OPs" value="0.4" />
+		<param name="SP_ACC" value="0.6" />
+		<param name="SFU_ACC" value="0.7" />
+		<param name="FPU_ACC" value="0.25" />
+		<param name="MEM_RD" value="0.3" />
+		<param name="MEM_WR" value="0.4" />
+		<param name="MEM_PRE" value="0.7" />
+		<param name="L2_RH" value="1" />
+		<param name="L2_RM" value="1" />
+		<param name="L2_WH" value="1" />
+		<param name="L2_WM" value="1" />
+		<param name="NOC_A" value="80" />
+		<param name="PIPE_A" value="0.8" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="9" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="650"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="1"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="1"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="1"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="1"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="8"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="16"/>
+			<param name="simd_width" value="8"/>
+			<param name="collector_units" value="16"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="8192"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="1"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="0.4"/>
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="1"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="1"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="65536,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="16384,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1300"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1300"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="100"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="786432,64,16,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1300"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="650"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="4"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="7"/>
+			<param name="output_ports" value="7"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="360000"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="65"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="8"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="800"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="9600"/><!--MB/S  Syed: Quadro FX 5800 has 76.8GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="8"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="1.53846154e-8f"/>
+			<param name="dram_rd_coeff" value="3.07692308e-8f"/>
+			<param name="dram_wr_coeff" value="1.30769231e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt b/configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt
new file mode 100644
index 0000000..de3bcc8
--- /dev/null
+++ b/configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt
@@ -0,0 +1,70 @@
+//14*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we donot use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 14;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt b/configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt
new file mode 100644
index 0000000..cfe9cac
--- /dev/null
+++ b/configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt
@@ -0,0 +1,69 @@
+//18*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we donot use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 18;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config b/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
new file mode 100644
index 0000000..82243c2
--- /dev/null
+++ b/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
@@ -0,0 +1,86 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 13
+
+# high level architecture configuration
+-gpgpu_n_clusters 10 
+-gpgpu_n_cores_per_cluster 3
+-gpgpu_n_mem 8 
+-gpgpu_clock_domains 325.0:650.0:650.0:800.0 
+
+# shader core pipeline config
+-gpgpu_shader_registers 16384
+-gpgpu_shader_core_pipeline 1024:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 1,1,1,1,1,1,1
+-gpgpu_num_sp_units 1
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 1,1,19,25,145
+-ptx_opcode_initiation_int 1,1,4,4,32
+-ptx_opcode_latency_fp 1,1,1,1,30
+-ptx_opcode_initiation_fp 1,1,1,1,5
+-ptx_opcode_latency_dp 8,8,8,8,335
+-ptx_opcode_initiation_dp 8,8,8,8,130
+
+# memory stage behaviour
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
+-gpgpu_cache:dl2_texture_only 1
+
+-gpgpu_shmem_warp_parts 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_quadro_islip.icnt
+
+# dram scheduler config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (30 core cycles).  I.e. 
+#   Total buffer space required = 30 x 800MHz / 325MHz = 74
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 58
+
+# dram model config
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4 
+-gpgpu_dram_burst_length 4
+-dram_data_command_freq_ratio 2  # GDDR3 is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
+# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
+-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+
+-visualizer_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt b/configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
new file mode 100644
index 0000000..2a69ddd
--- /dev/null
+++ b/configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 50;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config b/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
new file mode 100644
index 0000000..47c2b6a
--- /dev/null
+++ b/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
@@ -0,0 +1,149 @@
+# This config models the Pascal GP102 (GeForceGTX 1080Ti)
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 20 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 11
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# SFU is 32-width in pascal, then dp units initiation is 1 cycle
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 1,2,1,1,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory
+# Pascal GP102 has 64KB L1 cache
+# The default is to disable the L1 cache, unless cache modifieres is used
+-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,8
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
+-gpgpu_cache:dl2_texture_only 0 
+
+# 4 KB Inst.
+-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+
+# enable operand collector 
+## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
+-gpgpu_operand_collector_num_units_sp 20
+-gpgpu_operand_collector_num_units_sfu 4
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+# gpgpu_num_reg_banks should be increased to 32, but it gives an error!
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits)
+# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing from hynix H5GQ1H24AFR
+# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
+
+# Pascal has four schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml b/configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
new file mode 100755
index 0000000..02619ff
--- /dev/null
+++ b/configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="28"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="23"/><!-- nm -->
+		<param name="target_core_clockrate" value="1481"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="10" />
+		<param name="FP_INT" value="10" />
+		<param name="IC_H" value="0.001" />
+		<param name="IC_M" value="10" />
+		<param name="DC_RH" value="1" />
+		<param name="DC_RM" value="1" />
+		<param name="DC_WH" value="1" />
+		<param name="DC_WM" value="1" />
+		<param name="TC_H" value="0.001" />
+		<param name="TC_M" value="10" />
+		<param name="CC_H" value="4.5071" />
+		<param name="CC_M" value="10" />
+		<param name="SHRD_ACC" value="10" />
+		<param name="REG_RD" value="1.6294" />
+		<param name="REG_WR" value="0.5031" />
+		<param name="NON_REG_OPs" value="0.01" />
+		<param name="SP_ACC" value="10" />
+		<param name="SFU_ACC" value="0.0082" />
+		<param name="FPU_ACC" value="0.4126" />
+		<param name="MEM_RD" value="0.1234" />
+		<param name="MEM_WR" value="0.001" />
+		<param name="MEM_PRE" value="0.001" />
+		<param name="L2_RH" value="100" />
+		<param name="L2_RM" value="100" />
+		<param name="L2_WH" value="100" />
+		<param name="L2_WM" value="42.6966" />
+		<param name="NOC_A" value="100" />
+		<param name="PIPE_A" value="44.8085" />
+		<param name="IDLE_CORE_N" value="2.0382"/>
+		<param name="CONST_DYNAMICN" value="5.0005" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="1481"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="65536"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="2962"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="23"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
deleted file mode 100644
index fac792a..0000000
--- a/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
deleted file mode 100644
index f1ae2dc..0000000
--- a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
+++ /dev/null
@@ -1,165 +0,0 @@
-# This config models the Volta Titan X
-# For more info about this card:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 1
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA GP100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,1,4,4,1,9
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP100 has 64KB Shared memory
--gpgpu_cache:dl1  64:128:8,L:L:m:N:H,A:256:8,16:0
--gpgpu_cache:dl1PrefL1  64:128:16,L:L:m:N:H,A:256:8,16:0
--gpgpu_cache:dl1PrefShared  32:128:6,L:L:m:N:H,A:256:8,16:0
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 1
--gpgpu_shmem_size_PrefShared 98304
--gmem_skip_L1D 0
-
-# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
--gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
-
-# 128 KB Inst.
--gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4
-
-# enable operand collector
--gpgpu_operand_collector_num_units_sp 14
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_units_mem 10
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt b/configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt
new file mode 100644
index 0000000..a11bd8e
--- /dev/null
+++ b/configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//20*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we donot use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 26;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
diff --git a/configs/3.x-cfgs/TeslaC2050/gpgpusim.config b/configs/3.x-cfgs/TeslaC2050/gpgpusim.config
new file mode 100644
index 0000000..442ab8b
--- /dev/null
+++ b/configs/3.x-cfgs/TeslaC2050/gpgpusim.config
@@ -0,0 +1,132 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 20 
+
+# Using cuobjdump to extract ptx/SASS
+#-gpgpu_ptx_use_cuobjdump 1 # use default
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+
+# high level architecture configuration
+-gpgpu_n_clusters 14
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 6
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Fermi clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
+# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
+-gpgpu_clock_domains 575.0:575.0:575.0:750.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+
+# This implies a maximum of 48 warps/SM
+-gpgpu_shader_core_pipeline 1536:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,1,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+
+# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
+-gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_shmem_size 49152
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_shmem_size 16384
+
+# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
+-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 750MHz / 575MHz = 130
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 114  
+
+# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config b/configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config
deleted file mode 100644
index e3cab18..0000000
--- a/configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config
+++ /dev/null
@@ -1,97 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 12
-
-# high level architecture configuration
--gpgpu_n_clusters 8 
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 6 
--gpgpu_clock_domains 337.5:600.0:600.0:800.0 
-
-# shader core pipeline config
--gpgpu_shader_registers 16384
-#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though)
--gpgpu_shader_core_pipeline 768:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1
--gpgpu_num_sp_units 1
--gpgpu_num_sfu_units 1
--gpgpu_num_dp_units 0
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 1,1,19,25,145
--ptx_opcode_initiation_int 1,1,4,4,32
--ptx_opcode_latency_fp 1,1,1,1,30
--ptx_opcode_initiation_fp 1,1,1,1,5
--ptx_opcode_latency_dp 8,8,8,8,335
--ptx_opcode_initiation_dp 8,8,8,8,130
-
-# memory stage behaviour
--gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
--gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4
--gpgpu_cache:dl2_texture_only 1
-
-# TLB parameters
-#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8
-#-gpgpu_tlbl2_latency 45
-
-
--gpgpu_shmem_warp_parts 2
-
-# interconnection
--network_mode 1 
--inter_config_file icnt_config_islip.icnt 
-
-# dram scheduler config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (30 core cycles).  I.e. 
-#   Total buffer space required = 30 x 800MHz / 337.5MHz = 71
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 55
-
-# dram model config
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4 
--gpgpu_dram_burst_length 4
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
-# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
-# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
--gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
-
-
-
-# Using cuobjdump to extract ptx/SASS
--gpgpu_ptx_use_cuobjdump 1
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
-
--visualizer_enabled 0
--power_trace_enabled 0
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_quadrofx5600.xml 
-
--steady_power_levels_enabled 1
--steady_state_definition 8,4
diff --git a/configs/4.x-cfgs/SM1_QFX5600/gpuwattch_quadrofx5600.xml b/configs/4.x-cfgs/SM1_QFX5600/gpuwattch_quadrofx5600.xml
deleted file mode 100644
index 2c5a6fc..0000000
--- a/configs/4.x-cfgs/SM1_QFX5600/gpuwattch_quadrofx5600.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="0"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="16"/>
-		<param name="architecture" value="2"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="0"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="0"/>
-		<param name="core_tech_node" value="65"/><!-- nm -->
-		<param name="target_core_clockrate" value="650"/><!--MHz -->
-		<param name="temperature" value="400"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.54"/><!-- idle core power for GTX479 -->
-		<param name="TOT_INST" value="2" />
-		<param name="FP_INT" value="5" />
-		<param name="IC_H" value="10" />
-		<param name="IC_M" value="10" />
-		<param name="DC_RH" value="10" />
-		<param name="DC_RM" value="10" />
-		<param name="DC_WH" value="10" />
-		<param name="DC_WM" value="10" />
-		<param name="TC_H" value="20" />
-		<param name="TC_M" value="20" />
-		<param name="CC_H" value="10" />
-		<param name="CC_M" value="10" />
-		<param name="SHRD_ACC" value="20" />
-		<param name="REG_RD" value="0.25" />
-		<param name="REG_WR" value="0.4" />
-		<param name="NON_REG_OPs" value="0.4" />
-		<param name="SP_ACC" value="0.6" />
-		<param name="SFU_ACC" value="0.7" />
-		<param name="FPU_ACC" value="0.25" />
-		<param name="MEM_RD" value="0.3" />
-		<param name="MEM_WR" value="0.4" />
-		<param name="MEM_PRE" value="0.7" />
-		<param name="L2_RH" value="1" />
-		<param name="L2_RM" value="1" />
-		<param name="L2_WH" value="1" />
-		<param name="L2_WM" value="1" />
-		<param name="NOC_A" value="80" />
-		<param name="PIPE_A" value="0.8" />
-		<param name="IDLE_CORE_N" value="1"/>
-		<param name="CONST_DYNAMICN" value="9" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="650"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="1"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="1"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="1"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="1"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="8"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="16"/>
-			<param name="simd_width" value="8"/>
-			<param name="collector_units" value="16"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="8192"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="1"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="0.4"/>
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="1"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="1"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="65536,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="16384,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1300"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1300"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="100"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="786432,64,16,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="1300"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="650"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="4"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="7"/>
-			<param name="output_ports" value="7"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="360000"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="65"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="8"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="800"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="9600"/><!--MB/S  Syed: Quadro FX 5800 has 76.8GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="8"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="1.53846154e-8f"/>
-			<param name="dram_rd_coeff" value="3.07692308e-8f"/>
-			<param name="dram_wr_coeff" value="1.30769231e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt b/configs/4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt
deleted file mode 100644
index de3bcc8..0000000
--- a/configs/4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//14*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we donot use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 14;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt b/configs/4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt
deleted file mode 100644
index cfe9cac..0000000
--- a/configs/4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt
+++ /dev/null
@@ -1,69 +0,0 @@
-//18*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we donot use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 18;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config b/configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config
deleted file mode 100644
index 56dbb17..0000000
--- a/configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config
+++ /dev/null
@@ -1,87 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 13
-
-# high level architecture configuration
--gpgpu_n_clusters 10 
--gpgpu_n_cores_per_cluster 3
--gpgpu_n_mem 8 
--gpgpu_clock_domains 325.0:650.0:650.0:800.0 
-
-# shader core pipeline config
--gpgpu_shader_registers 16384
--gpgpu_shader_core_pipeline 1024:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1
--gpgpu_num_sp_units 1
--gpgpu_num_sfu_units 1
--gpgpu_num_dp_units 0
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 1,1,19,25,145
--ptx_opcode_initiation_int 1,1,4,4,32
--ptx_opcode_latency_fp 1,1,1,1,30
--ptx_opcode_initiation_fp 1,1,1,1,5
--ptx_opcode_latency_dp 8,8,8,8,335
--ptx_opcode_initiation_dp 8,8,8,8,130
-
-# memory stage behaviour
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
--gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
--gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4
--gpgpu_cache:dl2_texture_only 1
-
--gpgpu_shmem_warp_parts 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_quadro_islip.icnt
-
-# dram scheduler config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (30 core cycles).  I.e. 
-#   Total buffer space required = 30 x 800MHz / 325MHz = 74
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 58
-
-# dram model config
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4 
--gpgpu_dram_burst_length 4
--dram_data_command_freq_ratio 2  # GDDR3 is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
-# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
--gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
-
--visualizer_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt b/configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt
deleted file mode 100644
index a11bd8e..0000000
--- a/configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//20*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we donot use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 26;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
diff --git a/configs/4.x-cfgs/SM2_C2050/gpgpusim.config b/configs/4.x-cfgs/SM2_C2050/gpgpusim.config
deleted file mode 100644
index aa5f5f3..0000000
--- a/configs/4.x-cfgs/SM2_C2050/gpgpusim.config
+++ /dev/null
@@ -1,133 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 20 
-
-# Using cuobjdump to extract ptx/SASS
-#-gpgpu_ptx_use_cuobjdump 1 # use default
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-
-# high level architecture configuration
--gpgpu_n_clusters 14
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 6
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Fermi clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
-# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
--gpgpu_clock_domains 575.0:575.0:575.0:750.0
-
-# shader core pipeline config
--gpgpu_shader_registers 32768
-
-# This implies a maximum of 48 warps/SM
--gpgpu_shader_core_pipeline 1536:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 1
--gpgpu_num_dp_units 0
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,1,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,16,8,8,130
-
-
-# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
--gpgpu_cache:dl1  N:32:128:4,L:L:m:N:H,A:32:8,8
--gpgpu_shmem_size 49152
-
-# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,A:32:8,8
-#-gpgpu_shmem_size 16384
-
-# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32
--gpgpu_cache:dl2_texture_only 0 
-
--gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_num_reg_banks 16
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
--gpgpu_max_insn_issue_per_warp 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 750MHz / 575MHz = 130
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 114  
-
-# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5 is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
-
-# GDDR5 timing from hynix H5GQ1H24AFR
-# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
index 7820e4e..d372b26 100644
--- a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
+++ b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
@@ -1,6 +1,6 @@
 //21*1 fly with 32 flits per packet under gpgpusim injection mode
 use_map = 0;
-flit_size = 32; 
+flit_size = 40; 
 
 // currently we do not use this, see subnets below
 network_count = 2;
@@ -17,7 +17,7 @@ routing_function = dest_tag;
 // Flow control
 
 num_vcs     = 1;
-vc_buf_size = 8;
+vc_buf_size = 64;
 
 wait_for_tail_credit = 0;
 
diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
index 03fcda1..7f8da49 100644
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
@@ -50,20 +50,25 @@
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
--gpgpu_cache:dl1  N:32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_cache:dl1  N:32:128:4,L:L:m:N:H,S:128:8,8
 -gpgpu_shmem_size 49152
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
 
 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,S:32:8,8
 #-gpgpu_shmem_size 16384
 
 # 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2 S:64:128:8,L:B:m:L:L,A:256:4,4:0,32
 -gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 0
+-memory_partition_indexing 0
 
--gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4
 -gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,S:2:32,4
 
 # enable operand collector 
 -gpgpu_operand_collector_num_units_sp 6
@@ -76,6 +81,7 @@
 -gpgpu_shmem_num_banks 32
 -gpgpu_shmem_limited_broadcast 0
 -gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 20
 
 -gpgpu_max_insn_issue_per_warp 1
 
@@ -110,6 +116,13 @@
 -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
                         CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
 
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
 # Fermi has two schedulers per core
 -gpgpu_num_sched_per_core 2
 # Two Level Scheduler with active and pending pools
diff --git a/configs/4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt b/configs/4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt
deleted file mode 100644
index 069ca02..0000000
--- a/configs/4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 7;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM5_GTX750/gpgpusim.config b/configs/4.x-cfgs/SM5_GTX750/gpgpusim.config
deleted file mode 100644
index 9366f93..0000000
--- a/configs/4.x-cfgs/SM5_GTX750/gpgpusim.config
+++ /dev/null
@@ -1,131 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 52 
-
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 5
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 2
--gpgpu_n_sub_partition_per_mchannel 1
-
-# Maxwell clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number.
--gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
--gpgpu_num_sp_units 8
--gpgpu_num_sfu_units 32
--gpgpu_num_dp_units 0
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 6,12,13,13,210
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 6,12,6,6,374
--ptx_opcode_initiation_fp 1,1,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,16,8,8,130
-
--gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8
--gmem_skip_L1D 1
--gpgpu_shmem_size 65536
-
-# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,A:32:8,8
-#-gpgpu_shmem_size 16384
-
-# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache
--gpgpu_cache:dl2 N:1024:128:8,L:B:m:W:L,A:32:4,4:0,32
--gpgpu_cache:dl2_texture_only 0 
-
--gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 N:16:128:32,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_num_reg_banks 16
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 150
--dram_latency 130
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 300
-
-# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 32
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5 is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
-
-# GDDR5 timing from hynix H5GQ1H24AFR
-# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
-
-# Maxwell has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
-# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy.
-# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present.
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx750Ti.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml b/configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml
deleted file mode 100755
index e2b2324..0000000
--- a/configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml
+++ /dev/null
@@ -1,539 +0,0 @@
-<!-- THIS CONFIG IS CURRENTLY PRESENT ONLY AS A PLACEHOLDER. IT HAS NOT BEEN TESTED FOR ACCURACY VERSUS GTX750TI HARDWARE. ANY USE OF THIS CONFIG WILL LIKELY GIVE HIGHLY INACCURATE RESULTS. -->
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="16"/>
-		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="1"/>
-		<param name="core_tech_node" value="40"/><!-- nm -->
-		<param name="target_core_clockrate" value="700"/><!--MHz -->
-		<param name="temperature" value="380"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
-		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
-		<param name="TOT_INST" value="2.00" />
-		<param name="FP_INT" value="4.57" />
-		<param name="IC_H" value="2.14" />
-		<param name="IC_M" value="22.47" />
-		<param name="DC_RH" value="22.14" />
-		<param name="DC_RM" value="24.66" />
-		<param name="DC_WH" value="1.53" />
-		<param name="DC_WM" value="39.79" />
-		<param name="TC_H" value="10.21" />
-		<param name="TC_M" value="24.66" />
-		<param name="CC_H" value="11.07" />
-		<param name="CC_M" value="12.33" />
-		<param name="SHRD_ACC" value="7.04" />
-		<param name="REG_RD" value="0.14" />
-		<param name="REG_WR" value="0.21" />
-		<param name="NON_REG_OPs" value="2.11" />
-		<param name="SP_ACC" value="2.38" />
-		<param name="SFU_ACC" value="0.51" />
-		<param name="FPU_ACC" value="0.64" />
-		<param name="MEM_RD" value="0.33" />
-		<param name="MEM_WR" value="0.40" />
-		<param name="MEM_PRE" value="0.11" />
-		<param name="L2_RH" value="13.79" />
-		<param name="L2_RM" value="35.18" />
-		<param name="L2_WH" value="43.07" />
-		<param name="L2_WM" value="28.72" />
-		<param name="NOC_A" value="305.48" />
-		<param name="PIPE_A" value="2.57" />
-		<param name="IDLE_CORE_N" value="1"/>
-		<param name="CONST_DYNAMICN" value="11" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="700"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="2"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="2"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="32"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="4"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="32"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="32"/>
-			<param name="simd_width" value="32"/>
-			<param name="collector_units" value="32"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="32768"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="2"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="15"/>	
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="0"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="700"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="2"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="6"/>
-			<param name="output_ports" value="6"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="0"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="40"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="6"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="3.8475e-8f"/>
-			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
-			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
deleted file mode 100644
index 2a69ddd..0000000
--- a/configs/4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 50;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config b/configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config
deleted file mode 100644
index 47c2b6a..0000000
--- a/configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config
+++ /dev/null
@@ -1,149 +0,0 @@
-# This config models the Pascal GP102 (GeForceGTX 1080Ti)
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 20 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 11
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,4,1,1,6
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# SFU is 32-width in pascal, then dp units initiation is 1 cycle
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 1,2,1,1,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory
-# Pascal GP102 has 64KB L1 cache
-# The default is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,8
--gpgpu_shmem_size 98304
--gmem_skip_L1D 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
--gpgpu_cache:dl2_texture_only 0 
-
-# 4 KB Inst.
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
-
-# enable operand collector 
-## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
--gpgpu_operand_collector_num_units_sp 20
--gpgpu_operand_collector_num_units_sfu 4
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
-# gpgpu_num_reg_banks should be increased to 32, but it gives an error!
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits)
-# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes 
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing from hynix H5GQ1H24AFR
-# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
-
-# Pascal has four schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml b/configs/4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
deleted file mode 100755
index 02619ff..0000000
--- a/configs/4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="28"/>
-		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="1"/>
-		<param name="core_tech_node" value="23"/><!-- nm -->
-		<param name="target_core_clockrate" value="1481"/><!--MHz -->
-		<param name="temperature" value="380"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
-		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
-		<param name="TOT_INST" value="10" />
-		<param name="FP_INT" value="10" />
-		<param name="IC_H" value="0.001" />
-		<param name="IC_M" value="10" />
-		<param name="DC_RH" value="1" />
-		<param name="DC_RM" value="1" />
-		<param name="DC_WH" value="1" />
-		<param name="DC_WM" value="1" />
-		<param name="TC_H" value="0.001" />
-		<param name="TC_M" value="10" />
-		<param name="CC_H" value="4.5071" />
-		<param name="CC_M" value="10" />
-		<param name="SHRD_ACC" value="10" />
-		<param name="REG_RD" value="1.6294" />
-		<param name="REG_WR" value="0.5031" />
-		<param name="NON_REG_OPs" value="0.01" />
-		<param name="SP_ACC" value="10" />
-		<param name="SFU_ACC" value="0.0082" />
-		<param name="FPU_ACC" value="0.4126" />
-		<param name="MEM_RD" value="0.1234" />
-		<param name="MEM_WR" value="0.001" />
-		<param name="MEM_PRE" value="0.001" />
-		<param name="L2_RH" value="100" />
-		<param name="L2_RM" value="100" />
-		<param name="L2_WH" value="100" />
-		<param name="L2_WM" value="42.6966" />
-		<param name="NOC_A" value="100" />
-		<param name="PIPE_A" value="44.8085" />
-		<param name="IDLE_CORE_N" value="2.0382"/>
-		<param name="CONST_DYNAMICN" value="5.0005" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="1481"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="2"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="2"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="32"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="4"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="32"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="32"/>
-			<param name="simd_width" value="32"/>
-			<param name="collector_units" value="32"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="65536"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="2"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="15"/>	
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="0"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="2962"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="700"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="2"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="6"/>
-			<param name="output_ports" value="6"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="0"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="23"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="6"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="3.8475e-8f"/>
-			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
-			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt
new file mode 100644
index 0000000..81153b0
--- /dev/null
+++ b/configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 128;
+input_buffer_size = 256;
+ejection_buffer_size = 128;
+boundary_buffer_size = 128;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config b/configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config
new file mode 100644
index 0000000..edcd919
--- /dev/null
+++ b/configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config
@@ -0,0 +1,174 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 60 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 32
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 32
+-gpgpu_n_sub_partition_per_mchannel 1 
+
+# Pscal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA GP100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Nvidia_Tesla
+-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 2,2,2,1,2,2,2,1,6
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 2
+-gpgpu_num_dp_units 2
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 2,2,2,2,130
+-ptx_opcode_latency_sfu 8
+-ptx_opcode_initiation_sfu 4
+
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP100 has 64KB Shared memory
+-gpgpu_cache:dl1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_shmem_size 65536
+-gpgpu_shmem_size_PrefL1 65536
+-gpgpu_shmem_size_PrefShared 65536
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+
+# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives  4MB L2 cache
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 0
+-memory_partition_indexing 2
+
+# 4 KB Inst.
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 100
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
deleted file mode 100644
index 616e9f3..0000000
--- a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ /dev/null
@@ -1,74 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 128;
-input_buffer_size = 256;
-ejection_buffer_size = 128;
-boundary_buffer_size = 128;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
deleted file mode 100644
index da98547..0000000
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ /dev/null
@@ -1,186 +0,0 @@
-# This config models the Volta Titan X
-# For more info about this card:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 1 
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA GP100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
-
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP100 has 64KB Shared memory
--gpgpu_cache:dl1  S:64:128:8,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:64:128:16,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 1
--gpgpu_shmem_size_PrefShared 98304
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
-
-# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
--gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:256:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 0
-
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 100
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index cfd90ec..e7e27b7 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -132,7 +132,7 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_
 				chip[0] = a[13]^a[12]^a[11]^a[10]^a[9]^a[6]^a[5]^a[3]^a[0]^chip[0];
 				chip[1] = a[14]^a[13]^a[12]^a[11]^a[10]^a[7]^a[6]^a[4]^a[1]^chip[1];
 				chip[2] = a[14]^a[10]^a[9]^a[8]^a[7]^a[6]^a[3]^a[2]^a[0]^chip[2];
-				chip[3] = a[11]^a[10]^a[9]^a[8]^a[7]^a[4]^a[3]^a[1]^chip[3]; 
+				chip[3] = a[11]^a[10]^a[9]^a[8]^a[7]^a[4]^a[3]^a[1]^chip[3];
 				chip[4] = a[12]^a[11]^a[10]^a[9]^a[8]^a[5]^a[4]^a[2]^chip[4];
 				tlx->chip = chip.to_ulong();
 				
@@ -144,8 +144,21 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_
 			assert(tlx->chip < m_n_channel);
 			break;
 		case CUSTOM:
-			/* No custom set function implemented */
+		{
+			//random selected bits
+			//do you custom hashing function here, similar to
+			//Liu, Yuxi, et al. "Get Out of the Valley: Power-Efficient Address Mapping for GPUs." ISCA 2018
+			std::bitset<64> b(tlx->row);
+			std::bitset<5> chip(tlx->chip);
+			chip[0] = b[13]^b[10]^b[9]^b[5]^b[0]^chip[0];
+			chip[1] = b[12]^b[11]^b[6]^b[1]^chip[1];
+			chip[2] = b[14]^b[9]^b[8]^b[7]^b[2]^chip[2];
+			chip[3] = b[11]^b[10]^b[8]^b[3]^chip[3];
+			chip[4] = b[12]^b[9]^b[8]^b[5]^b[4]^chip[4];
+			tlx->chip = chip.to_ulong();
+			assert(tlx->chip < m_n_channel);
 			break;
+		}
 		default:
 			 assert("\nUndefined set index function.\n" && 0);
 			 break;
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index 92aa819..ac63327 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -730,13 +730,15 @@ void dram_t::print( FILE* simFile) const
    printf("\nwrite_to_read_ratio_blp_rw_average = %.6f", write_to_read_ratio_blp_rw_average /banks_access_rw_total);
    printf("\nGrpLevelPara = %.6f \n", (float)bkgrp_parallsim_rw /banks_access_rw_total);
 
-   printf("\nbwutil = %.6f \n", (float)bwutil/n_cmd);
+   printf("\nBW Util details:\n");
+   printf("bwutil = %.6f \n", (float)bwutil/n_cmd);
    printf("total_CMD = %d \n", n_cmd);
    printf("util_bw = %d \n", util_bw);
    printf("Wasted_Col = %d \n", wasted_bw_col);
-   printf("Wasted_Row %d \n", wasted_bw_row);
-   printf("Idle = %d \n\n", idle_bw);
+   printf("Wasted_Row = %d \n", wasted_bw_row);
+   printf("Idle = %d \n", idle_bw);
 
+   printf("\nBW Util Bottlenecks: \n");
    printf("RCDc_limit = %d \n", RCDc_limit);
    printf("RCDWRc_limit = %d \n", RCDWRc_limit);
    printf("WTRc_limit = %d \n", WTRc_limit);
@@ -747,6 +749,7 @@ void dram_t::print( FILE* simFile) const
    printf("WTRc_limit_alone = %d \n", WTRc_limit_alone);
    printf("RTWc_limit_alone = %d \n", RTWc_limit_alone);
 
+   printf("\nCommands details: \n");
    printf("total_CMD = %d \n", n_cmd);
    printf("n_nop = %d \n", n_nop);
    printf("Read = %d \n", n_rd);
@@ -757,8 +760,9 @@ void dram_t::print( FILE* simFile) const
    printf("n_pre = %d \n", n_pre);
    printf("n_ref = %d \n", n_ref);
    printf("n_req = %d \n", n_req );
-   printf("total_req = %d \n\n", n_rd+n_wr+n_rd_L2_A+n_wr_WB);
+   printf("total_req = %d \n", n_rd+n_wr+n_rd_L2_A+n_wr_WB);
 
+   printf("\nDual Bus Interface Util: \n");
    printf("issued_total_row = %lu \n", issued_total_row);
    printf("issued_total_col = %lu \n", issued_total_col);
    printf("Row_Bus_Util =  %.6f \n", (float)issued_total_row / n_cmd);
diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc
index f754d36..ff50050 100644
--- a/src/gpgpu-sim/dram_sched.cc
+++ b/src/gpgpu-sim/dram_sched.cc
@@ -109,12 +109,14 @@ dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row )
    if(m_config->seperate_write_queue_enabled) {
 	   if(m_mode == READ_MODE &&
 			  ((m_num_write_pending >= m_config->write_high_watermark )
-			   || (m_queue[bank].empty() && !m_write_queue[bank].empty()))) {
+			  // || (m_queue[bank].empty() && !m_write_queue[bank].empty())
+			   )) {
 		   m_mode = WRITE_MODE;
 	   }
 	   else if(m_mode == WRITE_MODE &&
 				  (( m_num_write_pending < m_config->write_low_watermark )
-				   || (!m_queue[bank].empty() && m_write_queue[bank].empty()))){
+				 //  || (!m_queue[bank].empty() && m_write_queue[bank].empty())
+				   )){
 		   m_mode = READ_MODE;
 	   }
    }
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index d48de25..ea2dfba 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -1495,7 +1495,8 @@ void gpgpu_sim::cycle()
           } else {
               mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) );
               m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle );
-              partiton_reqs_in_parallel_per_cycle++;
+              if(mf)
+            	  partiton_reqs_in_parallel_per_cycle++;
           }
           m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle);
           m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]);
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 4828875..b59e5d2 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -451,7 +451,7 @@ void shader_core_stats::print( FILE* fout ) const
    fprintf(fout, "gpgpu_n_intrawarp_mshr_merge = %d\n", gpgpu_n_intrawarp_mshr_merge);
    fprintf(fout, "gpgpu_n_cmem_portconflict = %d\n", gpgpu_n_cmem_portconflict);
 
-   fprintf(fout, "gpgpu_stall_shd_mem[c_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]);
+   fprintf(fout, "gpgpu_stall_shd_mem[c_mem][resource_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]);
    //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][MSHR_RC_FAIL]);
    //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][ICNT_RC_FAIL]);
    //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][DATA_PORT_STALL]);
@@ -459,7 +459,7 @@ void shader_core_stats::print( FILE* fout ) const
    //fprintf(fout, "gpgpu_stall_shd_mem[t_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][ICNT_RC_FAIL]);
    //fprintf(fout, "gpgpu_stall_shd_mem[t_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][DATA_PORT_STALL]);
    fprintf(fout, "gpgpu_stall_shd_mem[s_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[S_MEM][BK_CONF]);
-   fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][bk_conf] = %d\n", 
+   fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][resource_stall] = %d\n",
            gpu_stall_shd_mem_breakdown[G_MEM_LD][BK_CONF] + 
            gpu_stall_shd_mem_breakdown[G_MEM_ST][BK_CONF] + 
            gpu_stall_shd_mem_breakdown[L_MEM_LD][BK_CONF] + 
-- 
cgit v1.3


From f852a7108e691045dd3910065836a817babcde8c Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Fri, 7 Sep 2018 22:01:31 -0400
Subject: adding streamin cache + fixing TEX cache + adding l1 latency and smem
 latency

---
 configs/4.x-cfgs/SM2_GTX480/gpgpusim.config        |   2 +-
 configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt  |  73 ---------
 configs/4.x-cfgs/SM6_P100/gpgpusim.config          | 174 ---------------------
 .../SM6_P100_64SMs/config_fermi_islip.icnt         |  73 ---------
 configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config    | 174 ---------------------
 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config        |  27 ++--
 src/abstract_hardware_model.h                      |   1 +
 src/gpgpu-sim/gpu-cache.cc                         |  20 ++-
 src/gpgpu-sim/gpu-cache.h                          |  36 ++++-
 src/gpgpu-sim/gpu-sim.cc                           |   6 +
 src/gpgpu-sim/l2cache.cc                           |   8 +-
 src/gpgpu-sim/shader.cc                            | 126 ++++++++++++++-
 src/gpgpu-sim/shader.h                             |   6 +
 13 files changed, 207 insertions(+), 519 deletions(-)
 delete mode 100644 configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM6_P100/gpgpusim.config
 delete mode 100644 configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
index 7f8da49..35341f7 100644
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
@@ -67,7 +67,7 @@
 -memory_partition_indexing 0
 
 -gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4
--gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,T:128:4,128:2
 -gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,S:2:32,4
 
 # enable operand collector 
diff --git a/configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt
deleted file mode 100644
index e7c2c3b..0000000
--- a/configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt
+++ /dev/null
@@ -1,73 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 60;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 128;
-input_buffer_size = 256;
-ejection_buffer_size = 128;
-boundary_buffer_size = 128;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM6_P100/gpgpusim.config b/configs/4.x-cfgs/SM6_P100/gpgpusim.config
deleted file mode 100644
index a4e745d..0000000
--- a/configs/4.x-cfgs/SM6_P100/gpgpusim.config
+++ /dev/null
@@ -1,174 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 60 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 32
--gpgpu_n_sub_partition_per_mchannel 1 
-
-# Pscal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA GP100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Nvidia_Tesla
--gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,2,2,1,2,2,2,1,6
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 2
--gpgpu_num_dp_units 2
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 2,2,2,2,130
--ptx_opcode_latency_sfu 8
--ptx_opcode_initiation_sfu 4
-
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP100 has 64KB Shared memory
--gpgpu_cache:dl1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 65536
--gpgpu_shmem_size_PrefShared 65536
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
-
-# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives  4MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 0
--memory_partition_indexing 2
-
-# 4 KB Inst.
--gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 100
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt
deleted file mode 100644
index 81153b0..0000000
--- a/configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt
+++ /dev/null
@@ -1,73 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 128;
-input_buffer_size = 256;
-ejection_buffer_size = 128;
-boundary_buffer_size = 128;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config b/configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config
deleted file mode 100644
index edcd919..0000000
--- a/configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config
+++ /dev/null
@@ -1,174 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 60 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 32
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 32
--gpgpu_n_sub_partition_per_mchannel 1 
-
-# Pscal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA GP100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Nvidia_Tesla
--gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,2,2,1,2,2,2,1,6
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 2
--gpgpu_num_dp_units 2
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 2,2,2,2,130
--ptx_opcode_latency_sfu 8
--ptx_opcode_initiation_sfu 4
-
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP100 has 64KB Shared memory
--gpgpu_cache:dl1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 65536
--gpgpu_shmem_size_PrefShared 65536
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
-
-# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives  4MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 0
--memory_partition_indexing 2
-
-# 4 KB Inst.
--gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 100
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 7368882..9ea7202 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -56,24 +56,29 @@
 -ptx_opcode_initiation_sfu 4
 -ptx_opcode_latency_sfu 8
 
+
+# latencies and cache configs are adopted from:
+# https://arxiv.org/pdf/1804.06826.pdf
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory
-# Pascal GP102 has 24KB L1 cache
-# The defulat is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
+# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
+# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres are used
+-gpgpu_cache:dl1  S:48:128:4,L:L:s:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:48:128:4,L:L:s:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:48:128:4,L:L:s:N:H,A:256:8,16:0,32
 -gpgpu_shmem_size 49152
 -gpgpu_shmem_size_PrefL1 49152
 -gpgpu_shmem_size_PrefShared 49152
 -gmem_skip_L1D 1
 -icnt_flit_size 40
 -gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 82
+-smem_latency 24
 
 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:128:4,16:0,32
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 32:32:32:32
 -perf_sim_memcpy 0
@@ -81,8 +86,7 @@
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
 # 48 KB Tex 
-# this is unused
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
 # 12 KB Const
 -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
 
@@ -99,7 +103,6 @@
 -gpgpu_operand_collector_num_out_ports_mem 1
 -gpgpu_operand_collector_num_in_ports_dp 1
 -gpgpu_operand_collector_num_out_ports_dp 1
-# gpgpu_num_reg_banks should be increased to 32
 -gpgpu_num_reg_banks 32
 
 # shared memory bankconflict detection 
@@ -118,7 +121,7 @@
 -inter_config_file config_fermi_islip.icnt
 
 # memory partition latency config 
--rop_latency 100
+-rop_latency 120
 -dram_latency 100
 
 # dram model config
@@ -128,7 +131,7 @@
 # To allow 100% DRAM utility, there should at least be enough buffer to sustain
 # the minimum DRAM latency (100 core cycles).  I.e. 
 #   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_frfcfs_dram_sched_queue_size 64
 -gpgpu_dram_return_queue_size 240
 
 # for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 1b764e2..a70b077 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -392,6 +392,7 @@ protected:
 #define LOCAL_MEM_SIZE_MAX (8*1024)
 #define MAX_STREAMING_MULTIPROCESSORS 64
 #define MAX_THREAD_PER_SM 2048
+#define MAX_WARP_PER_SM 64
 #define TOTAL_LOCAL_MEM_PER_SM (MAX_THREAD_PER_SM*LOCAL_MEM_SIZE_MAX)
 #define TOTAL_SHARED_MEM (MAX_STREAMING_MULTIPROCESSORS*SHARED_MEM_SIZE_MAX)
 #define TOTAL_LOCAL_MEM (MAX_STREAMING_MULTIPROCESSORS*MAX_THREAD_PER_SM*LOCAL_MEM_SIZE_MAX)
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index f181f20..a11853a 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -71,6 +71,7 @@ unsigned l1d_cache_config::set_index(new_addr_type addr) const{
 
     switch(m_set_index_function){
     case FERMI_HASH_SET_FUNCTION:
+    case BITWISE_XORING_FUNCTION:
         /*
         * Set Indexing function from "A Detailed GPU Cache Model Based on Reuse Distance Theory"
         * Cedric Nugteren et al.
@@ -1581,7 +1582,7 @@ enum cache_request_status tex_cache::access( new_addr_type addr, mem_fetch *mf,
     if ( status == MISS ) {
         // we need to send a memory request...
         unsigned rob_index = m_rob.push( rob_entry(cache_index, mf, block_addr) );
-        m_extra_mf_fields[mf] = extra_mf_fields(rob_index);
+        m_extra_mf_fields[mf] = extra_mf_fields(rob_index, m_config);
         mf->set_data_size(m_config.get_line_sz());
         m_tags.fill(cache_index,time,mf); // mark block as valid
         m_request_fifo.push(mf);
@@ -1636,6 +1637,23 @@ void tex_cache::cycle(){
 /// Place returning cache block into reorder buffer
 void tex_cache::fill( mem_fetch *mf, unsigned time )
 {
+	if(m_config.m_mshr_type == SECTOR_TEX_FIFO) {
+	assert(mf->get_original_mf());
+	extra_mf_fields_lookup::iterator e = m_extra_mf_fields.find(mf->get_original_mf());
+    assert( e != m_extra_mf_fields.end() );
+    e->second.pending_read--;
+
+    if(e->second.pending_read > 0) {
+    	//wait for the other requests to come back
+    	delete mf;
+    	return;
+      } else {
+    	mem_fetch *temp = mf;
+    	mf = mf->get_original_mf();
+    	delete temp;
+      }
+	}
+
     extra_mf_fields_lookup::iterator e = m_extra_mf_fields.find(mf);
     assert( e != m_extra_mf_fields.end() );
     assert( e->second.m_valid );
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index dee43f2..4ed382c 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -455,7 +455,8 @@ enum write_policy_t {
 
 enum allocation_policy_t {
     ON_MISS,
-    ON_FILL
+    ON_FILL,
+	STREAMING
 };
 
 
@@ -467,8 +468,9 @@ enum write_allocate_policy_t {
 };
 
 enum mshr_config_t {
-    TEX_FIFO,
+    TEX_FIFO, // Tex cache
     ASSOC, // normal cache
+	SECTOR_TEX_FIFO,  //Tex cache sends requests to high-level sector cache
 	SECTOR_ASSOC // normal cache sends requests to high-level sector cache
 };
 
@@ -485,6 +487,12 @@ enum cache_type{
     SECTOR
 };
 
+#define MAX_WARP_PER_SHADER 64
+#define INCT_TOTAL_BUFFER 64
+#define L2_TOTAL 64
+#define MAX_WARP_PER_SHADER 64
+#define MAX_WARP_PER_SHADER 64
+
 class cache_config {
 public:
     cache_config() 
@@ -544,10 +552,27 @@ public:
         switch (ap) {
         case 'm': m_alloc_policy = ON_MISS; break;
         case 'f': m_alloc_policy = ON_FILL; break;
+        case 's': m_alloc_policy = STREAMING; break;
         default: exit_parse_error();
         }
+        if(m_alloc_policy == STREAMING) {
+        	//For streaming cache, we set the alloc policy to be on-fill to remove all line_alloc_fail stalls
+        	//we set the MSHRs to be equal to the cache line. This is possible by moving TAG to be shared between cache line and MSHR enrty (i.e. for each cache line, there is an MSHR rntey associated with it)
+        	// This is the easiest think we can think about to model (mimics) L1 streaming cache in Pascal and Volta
+        	//Based on our microbenchmakrs, MSHRs entries have been increasing substantially in Pascal and Volta
+        	//For more information about streaming cache, see:
+        	// http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+        	// https://ieeexplore.ieee.org/document/8344474/
+
+			m_alloc_policy = ON_FILL;
+			m_mshr_entries = m_nset*m_assoc;
+			if(m_cache_type == SECTOR)
+				m_mshr_entries *=  SECTOR_CHUNCK_SIZE;
+			m_mshr_max_merge = MAX_WARP_PER_SM;
+        }
         switch (mshr_type) {
         case 'F': m_mshr_type = TEX_FIFO; assert(ntok==14); break;
+        case 'T': m_mshr_type = SECTOR_TEX_FIFO; assert(ntok==14); break;
         case 'A': m_mshr_type = ASSOC; break;
         case 'S' : m_mshr_type = SECTOR_ASSOC; break;
         default: exit_parse_error();
@@ -722,6 +747,7 @@ class l1d_cache_config : public cache_config{
 public:
 	l1d_cache_config() : cache_config(){}
 	virtual unsigned set_index(new_addr_type addr) const;
+	unsigned l1_latency;
 };
 
 class l2_cache_config : public cache_config {
@@ -1442,7 +1468,7 @@ public:
     m_result_fifo(config.m_result_fifo_entries)
     {
         m_name = name;
-        assert(config.m_mshr_type == TEX_FIFO);
+        assert(config.m_mshr_type == TEX_FIFO || config.m_mshr_type == SECTOR_TEX_FIFO );
         assert(config.m_write_policy == READ_ONLY);
         assert(config.m_alloc_policy == ON_MISS);
         m_memport=memport;
@@ -1595,13 +1621,15 @@ private:
 
     struct extra_mf_fields {
         extra_mf_fields()  { m_valid = false;}
-        extra_mf_fields( unsigned i ) 
+        extra_mf_fields( unsigned i, const cache_config &m_config )
         {
             m_valid = true;
             m_rob_index = i;
+            pending_read = m_config.m_mshr_type == SECTOR_TEX_FIFO? m_config.m_line_sz/SECTOR_SIZE : 0;
         }
         bool m_valid;
         unsigned m_rob_index;
+        unsigned pending_read;
     };
 
     cache_stats m_stats;
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index ea2dfba..08d4525 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -250,6 +250,12 @@ void shader_core_config::reg_options(class OptionParser * opp)
                    "per-shader L1 data cache config "
                    " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
                    "none" );
+    option_parser_register(opp, "-l1_latency", OPT_UINT32, &m_L1D_config.l1_latency,
+                 "L1 Hit Latency",
+                 "0");
+    option_parser_register(opp, "-smem_latency", OPT_UINT32, &smem_latency,
+                 "smem Latency",
+                 "3");
     option_parser_register(opp, "-gpgpu_cache:dl1PrefL1", OPT_CSTR, &m_L1D_config.m_config_stringPrefL1,
                    "per-shader L1 data cache config "
                    " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index f42610f..25da107 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -609,7 +609,7 @@ std::vector<mem_fetch*> memory_sub_partition::breakdown_request_to_sector_reques
 		} else
 			{
 			    printf("Invalid sector received, address = 0x%06x, sector mask = %s, data size = %d",
-			    		mf->get_addr(), mf->get_access_sector_mask(), mf->get_data_size(), mf->get_data_size());
+			    		mf->get_addr(), mf->get_access_sector_mask(), mf->get_data_size());
 				assert(0 && "Undefined sector mask is received");
 			}
 
@@ -640,7 +640,11 @@ std::vector<mem_fetch*> memory_sub_partition::breakdown_request_to_sector_reques
 			 result.push_back(n_mf);
 			 byte_sector_mask <<= SECTOR_SIZE;
 		}
-	} else assert(0 && "Undefined data size is received");
+	} else {
+		 printf("Invalid sector received, address = 0x%06x, sector mask = %d, byte mask = , data size = %d",
+					    		mf->get_addr(), mf->get_access_sector_mask().count(), mf->get_data_size());
+		 assert(0 && "Undefined data size is received");
+	}
 
 	return result;
 }
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index b59e5d2..51689e3 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1488,6 +1488,111 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue( cache_t *cache, war
     return process_cache_access( cache, mf->get_addr(), inst, events, mf, status );
 }
 
+mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache( l1_cache *cache, warp_inst_t &inst )
+{
+    mem_stage_stall_type result = NO_RC_FAIL;
+    if( inst.accessq_empty() )
+        return result;
+
+    mem_fetch *mf = m_mf_allocator->alloc(inst,inst.accessq_back());
+
+    if(m_config->m_L1D_config.l1_latency > 0)
+	{
+    	if((l1_latency_queue[m_config->m_L1D_config.l1_latency-1]) == NULL)
+    	{
+    		l1_latency_queue[m_config->m_L1D_config.l1_latency-1] = mf;
+
+    		if( mf->get_inst().is_store() ) {
+				unsigned inc_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)?
+						(mf->get_data_size()/SECTOR_SIZE) : 1;
+
+				for(unsigned i=0; i< inc_ack; ++i)
+					m_core->inc_store_req( inst.warp_id() );
+			}
+
+    		inst.accessq_pop_back();
+    	}
+    	else
+        {
+        	result = BK_CONF;
+        	delete mf;
+        }
+        if( !inst.accessq_empty() &&  result !=BK_CONF)
+		   result = COAL_STALL;
+	   return result;
+	}
+    else
+    {
+		std::list<cache_event> events;
+		enum cache_request_status status = cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle,events);
+		return process_cache_access( cache, mf->get_addr(), inst, events, mf, status );
+    }
+}
+
+void ldst_unit::L1_latency_queue_cycle()
+{
+	//std::deque< std::pair<mem_fetch*,bool> >::iterator it = m_latency_queue.begin();
+	if((l1_latency_queue[0]) != NULL)
+    {
+		    mem_fetch* mf_next = l1_latency_queue[0];
+			std::list<cache_event> events;
+			enum cache_request_status status = m_L1D->access(mf_next->get_addr(),mf_next,gpu_sim_cycle+gpu_tot_sim_cycle,events);
+
+		   bool write_sent = was_write_sent(events);
+		   bool read_sent = was_read_sent(events);
+
+		   if ( status == HIT ) {
+			   assert( !read_sent );
+			   l1_latency_queue[0] = NULL;
+			   if ( mf_next->get_inst().is_load() ) {
+				   for ( unsigned r=0; r < 4; r++)
+					   if (mf_next->get_inst().out[r] > 0)
+					   {
+						   assert(m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]]>0);
+						   unsigned still_pending = --m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]];
+						   if(!still_pending)
+						   {
+							m_pending_writes[mf_next->get_inst().warp_id()].erase(mf_next->get_inst().out[r]);
+							m_scoreboard->releaseRegister(mf_next->get_inst().warp_id(),mf_next->get_inst().out[r]);
+							m_core->warp_inst_complete(mf_next->get_inst());
+						   }
+					   }
+			   }
+
+			   //For write hit in WB policy
+			   if(mf_next->get_inst().is_store() && !write_sent)
+			   {
+				   unsigned dec_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)?
+				   						(mf_next->get_data_size()/SECTOR_SIZE) : 1;
+
+				   mf_next->set_reply();
+
+				   for(unsigned i=0; i< dec_ack; ++i)
+				      m_core->store_ack(mf_next);
+			   }
+
+			   if( !write_sent )
+				   delete mf_next;
+
+		   } else if ( status == RESERVATION_FAIL ) {
+			   assert( !read_sent );
+			   assert( !write_sent );
+		   } else {
+			   assert( status == MISS || status == HIT_RESERVED );
+			   l1_latency_queue[0] = NULL;
+	   }
+    }
+
+	 for( unsigned stage = 0; stage<m_config->m_L1D_config.l1_latency-1; ++stage)
+	  if( l1_latency_queue[stage] == NULL) {
+		   l1_latency_queue[stage] = l1_latency_queue[stage+1] ;
+		   l1_latency_queue[stage+1] = NULL;
+	   }
+
+}
+
+
+
 bool ldst_unit::constant_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type)
 {
    if( inst.empty() || ((inst.space.get_type() != const_space) && (inst.space.get_type() != param_space_kernel)) )
@@ -1561,7 +1666,7 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea
        }
    } else {
        assert( CACHE_UNDEFINED != inst.cache_op );
-       stall_cond = process_memory_access_queue(m_L1D,inst);
+       stall_cond = process_memory_access_queue_l1cache(m_L1D,inst);
    }
    if( !inst.accessq_empty() && stall_cond == NO_RC_FAIL)
        stall_cond = COAL_STALL;
@@ -1771,8 +1876,9 @@ ldst_unit::ldst_unit( mem_fetch_interface *icnt,
                       const memory_config *mem_config,  
                       shader_core_stats *stats,
                       unsigned sid,
-                      unsigned tpc ) : pipelined_simd_unit(NULL,config,3,core), m_next_wb(config)
+                      unsigned tpc ) : pipelined_simd_unit(NULL,config,config->smem_latency,core), m_next_wb(config)
 {
+	assert(config->smem_latency > 1);
     init( icnt,
           mf_allocator,
           core, 
@@ -1793,6 +1899,12 @@ ldst_unit::ldst_unit( mem_fetch_interface *icnt,
                               m_icnt,
                               m_mf_allocator,
                               IN_L1D_MISS_QUEUE );
+
+        if(m_config->m_L1D_config.l1_latency > 0)
+	    {
+        	for(int i=0; i<m_config->m_L1D_config.l1_latency; i++ )
+        		l1_latency_queue.push_back((mem_fetch*)NULL);
+	    }
     }
 }
 
@@ -2019,7 +2131,11 @@ void ldst_unit::cycle()
 
    m_L1T->cycle();
    m_L1C->cycle();
-   if( m_L1D ) m_L1D->cycle();
+   if( m_L1D ) {
+	   m_L1D->cycle();
+	   if(m_config->m_L1D_config.l1_latency > 0)
+	   		L1_latency_queue_cycle();
+   }
 
    warp_inst_t &pipe_reg = *m_dispatch_reg;
    enum mem_stage_stall_type rc_fail = NO_RC_FAIL;
@@ -2042,9 +2158,9 @@ void ldst_unit::cycle()
        unsigned warp_id = pipe_reg.warp_id();
        if( pipe_reg.is_load() ) {
            if( pipe_reg.space.get_type() == shared_space ) {
-               if( m_pipeline_reg[2]->empty() ) {
+               if( m_pipeline_reg[m_config->smem_latency-1]->empty() ) {
                    // new shared memory request
-                   move_warp(m_pipeline_reg[2],m_dispatch_reg);
+                   move_warp(m_pipeline_reg[m_config->smem_latency-1],m_dispatch_reg);
                    m_dispatch_reg->clear();
                }
            } else {
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index cc441b3..e07096e 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1220,6 +1220,7 @@ protected:
                                                       mem_fetch *mf,
                                                       enum cache_request_status status );
    mem_stage_stall_type process_memory_access_queue( cache_t *cache, warp_inst_t &inst );
+   mem_stage_stall_type process_memory_access_queue_l1cache( l1_cache *cache, warp_inst_t &inst );
 
    const memory_config *m_memory_config;
    class mem_fetch_interface *m_icnt;
@@ -1248,6 +1249,9 @@ protected:
    // for debugging
    unsigned long long m_last_inst_gpu_sim_cycle;
    unsigned long long m_last_inst_gpu_tot_sim_cycle;
+
+   std::deque<mem_fetch* > l1_latency_queue;
+   void L1_latency_queue_cycle();
 };
 
 enum pipeline_stage_name_t {
@@ -1399,6 +1403,8 @@ struct shader_core_config : public core_config
 
     int simt_core_sim_order; 
     
+    unsigned smem_latency;
+
     unsigned mem2device(unsigned memid) const { return memid + n_simt_clusters; }
 
     //Jin: concurrent kernel on sm
-- 
cgit v1.3


From 46817ba62f475ba1202c31a8939ea1a1de81a410 Mon Sep 17 00:00:00 2001
From: tgrogers <tgrogers@purdue.edu>
Date: Tue, 11 Sep 2018 21:46:07 -0400
Subject: Adding in the occupancy nymber

---
 configs/3.x-cfgs/SM6_TITANX/gpgpusim.config | 1 +
 1 file changed, 1 insertion(+)

(limited to 'configs')

diff --git a/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config
index f78bd02..28912a3 100644
--- a/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -25,6 +25,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 61
 
 # This implies a maximum of 64 warps/SM
 -gpgpu_shader_core_pipeline 2048:32 
-- 
cgit v1.3


From 96bbd0063b479ad51f3d296f5e87a56151536d86 Mon Sep 17 00:00:00 2001
From: "Mahmoud Khairy A. Abdallah" <abdallm@purdue.edu>
Date: Wed, 12 Sep 2018 21:03:00 -0400
Subject: change L1 indexing to linear for TITANX

---
 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 9ea7202..8b47f98 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -65,9 +65,9 @@
 # Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
 # Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
 # The defulat is to disable the L1 cache, unless cache modifieres are used
--gpgpu_cache:dl1  S:48:128:4,L:L:s:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:48:128:4,L:L:s:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:48:128:4,L:L:s:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1  S:48:128:4,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:48:128:4,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:48:128:4,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_shmem_size 49152
 -gpgpu_shmem_size_PrefL1 49152
 -gpgpu_shmem_size_PrefShared 49152
-- 
cgit v1.3


From dd0a4eef2ae526984ac3e7dc93a0d1cf92a9a6a8 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Tue, 18 Sep 2018 10:52:10 -0400
Subject: removing some comments from config files

---
 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 9ea7202..4c0586d 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -109,7 +109,7 @@
 -gpgpu_shmem_num_banks 32
 -gpgpu_shmem_limited_broadcast 0
 -gpgpu_shmem_warp_parts 1
-# Use Fermi Coalsce arhitetecture which is the same as Pascal
+# Use Pascal Coalsce arhitetecture
 -gpgpu_coalesce_arch 61
 
 ## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
@@ -144,8 +144,7 @@
 -gpgpu_mem_address_mask 1
 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
 
-# Use the same GDDR5 timing from hynix H5GQ1H24AFR
-# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
+# Use the same GDDR5 timing
 -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
                         CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
 
-- 
cgit v1.3


From 9463cf92f121f8cc18a7e601c5838c3911d303b0 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Tue, 18 Sep 2018 12:40:36 -0400
Subject: double internal speedup for TITANX router

---
 configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt
index 714d933..dec4789 100644
--- a/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt
+++ b/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt
@@ -35,9 +35,9 @@ routing_delay  = 0;
 vc_alloc_delay = 1;
 sw_alloc_delay = 1;
 
-input_speedup     = 2;
+input_speedup     = 1;
 output_speedup    = 1;
-internal_speedup  = 1.0;
+internal_speedup  = 2.0;
 
 // Traffic, GPGPU-Sim does not use this
 
-- 
cgit v1.3


From 79a890fc4c22135a368504a5112a0f0a9982659e Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Thu, 20 Sep 2018 16:48:23 -0400
Subject: fixing some config file

---
 configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt | 4 ++--
 configs/4.x-cfgs/SM2_GTX480/gpgpusim.config         | 9 ++++++---
 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config         | 6 +++---
 3 files changed, 11 insertions(+), 8 deletions(-)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
index d372b26..c399db9 100644
--- a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
+++ b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
@@ -32,9 +32,9 @@ routing_delay  = 0;
 vc_alloc_delay = 1;
 sw_alloc_delay = 1;
 
-input_speedup     = 2;
+input_speedup     = 1;
 output_speedup    = 1;
-internal_speedup  = 1.0;
+internal_speedup  = 2.0;
 
 // Traffic, GPGPU-Sim does not use this
 
diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
index 35341f7..c96432b 100644
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
@@ -50,13 +50,16 @@
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
--gpgpu_cache:dl1  N:32:128:4,L:L:m:N:H,S:128:8,8
+-gpgpu_cache:dl1  N:32:128:4,L:L:m:N:H,S:64:8,8
 -gpgpu_shmem_size 49152
 -icnt_flit_size 40
+-gmem_skip_L1D 0
 -gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 35
+-smem_latency 26
 
 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,S:32:8,8
+#-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,S:64:8,8
 #-gpgpu_shmem_size 16384
 
 # 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
@@ -100,7 +103,7 @@
 # To allow 100% DRAM utility, there should at least be enough buffer to sustain
 # the minimum DRAM latency (100 core cycles).  I.e. 
 #   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_frfcfs_dram_sched_queue_size 64
 -gpgpu_dram_return_queue_size 116
 
 # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 8e93723..45a87cd 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -65,9 +65,9 @@
 # Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
 # Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
 # The defulat is to disable the L1 cache, unless cache modifieres are used
--gpgpu_cache:dl1  S:48:128:4,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:48:128:4,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:48:128:4,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_shmem_size 49152
 -gpgpu_shmem_size_PrefL1 49152
 -gpgpu_shmem_size_PrefShared 49152
-- 
cgit v1.3


From 7e414028b3754d40ab92d10205dc412316c4ab29 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Sun, 7 Oct 2018 13:37:24 -0400
Subject: adding Volta V100 config

---
 .../4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt    |  74 ++++++++
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config        | 187 +++++++++++++++++++++
 2 files changed, 261 insertions(+)
 create mode 100644 configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
 create mode 100644 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
new file mode 100644
index 0000000..cea3acf
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 128;
+boundary_buffer_size = 128;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
new file mode 100644
index 0000000..de3558a
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -0,0 +1,187 @@
+# This config models the Volta Titan X
+# For more info about this card:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 24
+-gpgpu_n_sub_partition_per_mchannel 1 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA GV100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 64KB DL1 and 64KB shared memory
+-gpgpu_cache:dl1  S:4:128:128,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:4:128:192,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 65536
+-gpgpu_shmem_size_PrefL1 32768
+-gpgpu_shmem_size_PrefShared 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+
+# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
+-gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 0
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 100
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
-- 
cgit v1.3


From fdbb4aef32a36ff625612c82c58039699af2b23b Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Tue, 9 Oct 2018 12:07:25 -0400
Subject: flushing L1 cache

---
 configs/4.x-cfgs/SM2_GTX480/gpgpusim.config | 1 +
 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 1 +
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config | 1 +
 3 files changed, 3 insertions(+)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
index c96432b..b965aff 100644
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
@@ -57,6 +57,7 @@
 -gpgpu_n_cluster_ejection_buffer_size 32
 -l1_latency 35
 -smem_latency 26
+-gpgpu_flush_l1_cache 1
 
 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
 #-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,S:64:8,8
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 45a87cd..3723163 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -76,6 +76,7 @@
 -gpgpu_n_cluster_ejection_buffer_size 32
 -l1_latency 82
 -smem_latency 24
+-gpgpu_flush_l1_cache 1
 
 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
 -gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index de3558a..cc4c931 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -77,6 +77,7 @@
 -gpgpu_n_cluster_ejection_buffer_size 32
 -l1_latency 28
 -smem_latency 19
+-gpgpu_flush_l1_cache 1
 
 # 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
 -gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
-- 
cgit v1.3


From 0e46a261dfeba9c19d1637f46277986d7eb1b9d8 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Tue, 9 Oct 2018 17:12:57 -0400
Subject: adding adaptive volta cache config

---
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config | 19 ++++++++++--------
 src/abstract_hardware_model.cc              |  2 ++
 src/abstract_hardware_model.h               |  2 ++
 src/gpgpu-sim/gpu-cache.cc                  |  9 ++++-----
 src/gpgpu-sim/gpu-cache.h                   | 31 +++++++++++++++++++++++++----
 src/gpgpu-sim/gpu-sim.cc                    |  3 +++
 src/gpgpu-sim/shader.cc                     | 29 +++++++++++++++++++++++++++
 src/gpgpu-sim/shader.h                      |  2 ++
 8 files changed, 80 insertions(+), 17 deletions(-)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index cc4c931..a7056db 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -65,19 +65,21 @@
 
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 64KB DL1 and 64KB shared memory
--gpgpu_cache:dl1  S:4:128:128,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:4:128:192,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 32768
--gpgpu_shmem_size_PrefShared 98304
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
 -gmem_skip_L1D 0
 -icnt_flit_size 40
 -gpgpu_n_cluster_ejection_buffer_size 32
 -l1_latency 28
 -smem_latency 19
 -gpgpu_flush_l1_cache 1
+-adpative_volta_cache_config 1
 
 # 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
 -gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
@@ -87,7 +89,8 @@
 
 # 128 KB Inst.
 -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex 
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
 -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
 # 64 KB Const
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index d2a155c..39ed81c 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -591,6 +591,8 @@ kernel_info_t::kernel_info_t( dim3 gridDim, dim3 blockDim, class function_info *
    
     //Jin: launch latency management
     m_launch_latency = g_kernel_launch_latency;
+
+    volta_cache_config_set=false;
 }
 
 kernel_info_t::~kernel_info_t()
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index e708fa7..6fa2ba0 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -301,6 +301,8 @@ public:
    unsigned long long start_cycle;
    unsigned long long end_cycle;
    unsigned m_launch_latency;
+
+   mutable bool volta_cache_config_set;
 };
 
 struct core_config {
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index a11853a..8ae4702 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -29,7 +29,6 @@
 #include "stat-tool.h"
 #include <assert.h>
 
-#define MAX_DEFAULT_CACHE_SIZE_MULTIBLIER 4
 // used to allocate memory that is large enough to adapt the changes in cache size across kernels
 
 const char * cache_request_status_str(enum cache_request_status status) 
@@ -165,7 +164,7 @@ unsigned l2_cache_config::set_index(new_addr_type addr) const{
 
 tag_array::~tag_array() 
 {
-	unsigned cache_lines_num = MAX_DEFAULT_CACHE_SIZE_MULTIBLIER*m_config.get_num_lines();
+	unsigned cache_lines_num = m_config.get_max_num_lines();
 	for(unsigned i=0; i<cache_lines_num; ++i)
 		delete m_lines[i];
     delete[] m_lines;
@@ -192,7 +191,7 @@ tag_array::tag_array( cache_config &config,
     : m_config( config )
 {
     //assert( m_config.m_write_policy == READ_ONLY ); Old assert
-	unsigned cache_lines_num = MAX_DEFAULT_CACHE_SIZE_MULTIBLIER*config.get_num_lines();
+	unsigned cache_lines_num = config.get_max_num_lines();
 	m_lines = new cache_block_t*[cache_lines_num];
 	if(config.m_cache_type == NORMAL)
 	{
@@ -387,7 +386,7 @@ void tag_array::fill( unsigned index, unsigned time, mem_fetch* mf)
 //TODO: we need write back the flushed data to the upper level
 void tag_array::flush() 
 {
-    for (unsigned i=0; i < m_config.get_num_lines(); i++)
+    for (unsigned i=0; i < m_config.get_max_num_lines(); i++)
     	if(m_lines[i]->is_modified_line()) {
     	for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++)
     		m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ;
@@ -396,7 +395,7 @@ void tag_array::flush()
 
 void tag_array::invalidate()
 {
-    for (unsigned i=0; i < m_config.get_num_lines(); i++)
+    for (unsigned i=0; i < m_config.get_max_num_lines(); i++)
     	for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++)
     		m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ;
 }
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 4ed382c..9174d7f 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -38,6 +38,8 @@
 #include "addrdec.h"
 #include <iostream>
 
+#define MAX_DEFAULT_CACHE_SIZE_MULTIBLIER 4
+
 enum cache_block_state {
     INVALID=0,
     RESERVED,
@@ -557,15 +559,15 @@ public:
         }
         if(m_alloc_policy == STREAMING) {
         	//For streaming cache, we set the alloc policy to be on-fill to remove all line_alloc_fail stalls
-        	//we set the MSHRs to be equal to the cache line. This is possible by moving TAG to be shared between cache line and MSHR enrty (i.e. for each cache line, there is an MSHR rntey associated with it)
-        	// This is the easiest think we can think about to model (mimics) L1 streaming cache in Pascal and Volta
+        	//we set the MSHRs to be equal to max allocated cache lines. This is possible by moving TAG to be shared between cache line and MSHR enrty (i.e. for each cache line, there is an MSHR rntey associated with it)
+        	//This is the easiest think we can think about to model (mimic) L1 streaming cache in Pascal and Volta
         	//Based on our microbenchmakrs, MSHRs entries have been increasing substantially in Pascal and Volta
         	//For more information about streaming cache, see:
         	// http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
         	// https://ieeexplore.ieee.org/document/8344474/
 
 			m_alloc_policy = ON_FILL;
-			m_mshr_entries = m_nset*m_assoc;
+			m_mshr_entries = m_nset*m_assoc*MAX_DEFAULT_CACHE_SIZE_MULTIBLIER;
 			if(m_cache_type == SECTOR)
 				m_mshr_entries *=  SECTOR_CHUNCK_SIZE;
 			m_mshr_max_merge = MAX_WARP_PER_SM;
@@ -581,6 +583,7 @@ public:
         m_nset_log2 = LOGB2(m_nset);
         m_valid = true;
         m_atom_sz = (m_cache_type == SECTOR)? SECTOR_SIZE : m_line_sz;
+        original_m_assoc = m_assoc;
 
         //For more details about difference between FETCH_ON_WRITE and WRITE VALIDAE policies
         //Read: Jouppi, Norman P. "Cache write policies and performance". ISCA 93.
@@ -646,7 +649,11 @@ public:
         assert( m_valid );
         return m_nset * m_assoc;
     }
-
+    unsigned get_max_num_lines() const
+    {
+        assert( m_valid );
+        return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * m_nset * original_m_assoc;
+    }
     void print( FILE *fp ) const
     {
         fprintf( fp, "Size = %d B (%d Set x %d-way x %d byte line)\n", 
@@ -687,6 +694,21 @@ public:
 	{
     	return m_mshr_type;
 	}
+    void set_assoc(unsigned n)
+	{
+    	//set new assoc. L1 cache dynamically resized in Volta
+    	m_assoc = n;
+	}
+    unsigned get_nset() const
+	{
+		assert( m_valid );
+		return m_nset;
+	}
+    unsigned get_total_size_inKB() const
+	{
+		assert( m_valid );
+		return (m_assoc*m_nset*m_line_sz)/1024;
+	}
     FuncCache get_cache_status() {return cache_status;}
     char *m_config_string;
     char *m_config_stringPrefL1;
@@ -708,6 +730,7 @@ protected:
     unsigned m_nset_log2;
     unsigned m_assoc;
     unsigned m_atom_sz;
+    unsigned original_m_assoc;
 
     enum replacement_policy_t m_replacement_policy; // 'L' = LRU, 'F' = FIFO
     enum write_policy_t m_write_policy;             // 'T' = write through, 'B' = write back, 'R' = read only
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 08d4525..080cbac 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -307,6 +307,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size,
                  "Size of shared memory per shader core (default 16kB)",
                  "16384");
+    option_parser_register(opp, "-adpative_volta_cache_config", OPT_BOOL, &adpative_volta_cache_config,
+                 "adpative_volta_cache_config",
+                 "0");
     option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_sizeDefault,
                  "Size of shared memory per shader core (default 16kB)",
                  "16384");
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 0e2e1c2..2cc8a2e 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -2744,6 +2744,35 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const
        abort();
     }
 
+    if(adpative_volta_cache_config && !k.volta_cache_config_set) {
+    	//For Volta, we assign the remaining shared memory to L1 cache
+    	//For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
+    	unsigned total_shmed = kernel_info->smem * result;
+    	assert(total_shmed >=0 && total_shmed <= gpgpu_shmem_size);
+    	assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
+    	assert(m_L1D_config.get_nset() == 4);  //Volta L1 has four sets
+    	if(total_shmed < gpgpu_shmem_size){
+    		if(total_shmed == 0)
+    			m_L1D_config.set_assoc(256);  //L1 is 128KB ans shd=0
+    		else if(total_shmed > 0 && total_shmed <= 8192)
+    			m_L1D_config.set_assoc(240);  //L1 is 120KB ans shd=8KB
+    		else if(total_shmed > 8192 && total_shmed <= 16384)
+    		    m_L1D_config.set_assoc(224);  //L1 is 112KB ans shd=16KB
+    		else if(total_shmed > 16384 && total_shmed <= 32768)
+    		    m_L1D_config.set_assoc(192);  //L1 is 96KB ans shd=32KB
+    		else if(total_shmed > 32768 && total_shmed <= 65536)
+    		    m_L1D_config.set_assoc(128);	//L1 is 64KB ans shd=64KB
+    		else if(total_shmed > 65536 && total_shmed <= gpgpu_shmem_size)
+    		     m_L1D_config.set_assoc(64); //L1 is 32KB and shd=96KB
+    		else
+    			assert(0);
+
+    		 printf ("GPGPU-Sim: Reconfigure L1 cache in Volta Archi to %uKB\n", m_L1D_config.get_total_size_inKB());
+    	}
+
+    	k.volta_cache_config_set = true;
+    }
+
     return result;
 }
 
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index e07096e..92b4159 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1409,6 +1409,8 @@ struct shader_core_config : public core_config
 
     //Jin: concurrent kernel on sm
     bool gpgpu_concurrent_kernel_sm;
+
+    bool adpative_volta_cache_config;
 };
 
 struct shader_core_stats_pod {
-- 
cgit v1.3


From dff0779550852ea3eba72c8b113feb3c4978823f Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 10 Oct 2018 17:48:52 -0400
Subject: adding some comment to config files

---
 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 3723163..cc7419c 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -71,6 +71,8 @@
 -gpgpu_shmem_size 49152
 -gpgpu_shmem_size_PrefL1 49152
 -gpgpu_shmem_size_PrefShared 49152
+# By default, L1 cache is disabled in Pascal P102.
+# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
 -gmem_skip_L1D 1
 -icnt_flit_size 40
 -gpgpu_n_cluster_ejection_buffer_size 32
@@ -87,6 +89,7 @@
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
 # 48 KB Tex 
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
 -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
 # 12 KB Const
 -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-- 
cgit v1.3


From 9321b08f408ca7f0af9f0fad14a03f1b23a7b670 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 10 Oct 2018 17:49:28 -0400
Subject: adding TITANV 3.x config files

---
 .../3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt    |  70 +++++++++
 configs/3.x-cfgs/SM7_TITANV/gpgpusim.config        | 165 +++++++++++++++++++++
 2 files changed, 235 insertions(+)
 create mode 100644 configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
 create mode 100644 configs/3.x-cfgs/SM7_TITANV/gpgpusim.config

(limited to 'configs')

diff --git a/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
new file mode 100644
index 0000000..fac792a
--- /dev/null
+++ b/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
new file mode 100644
index 0000000..738c881
--- /dev/null
+++ b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -0,0 +1,165 @@
+# This config models the Volta Titan X
+# For more info about this card:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 24
+-gpgpu_n_sub_partition_per_mchannel 1
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA GP100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,1,4,4,1,9
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Volta GV100 has 64KB Shared memory
+-gpgpu_cache:dl1  64:128:8,L:L:m:N:H,A:256:8,16:0
+-gpgpu_cache:dl1PrefL1  64:128:16,L:L:m:N:H,A:256:8,16:0
+-gpgpu_cache:dl1PrefShared  32:128:6,L:L:m:N:H,A:256:8,16:0
+-gpgpu_shmem_size 65536
+-gpgpu_shmem_size_PrefL1 1
+-gpgpu_shmem_size_PrefShared 98304
+-gmem_skip_L1D 0
+
+# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
+-gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+
+# 128 KB Inst.
+-gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4
+
+# enable operand collector
+-gpgpu_operand_collector_num_units_sp 14
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_units_mem 10
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
-- 
cgit v1.3


From 99634600280d64ec2a346c1d729d0e7a94a95337 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 10 Oct 2018 17:53:56 -0400
Subject: fixing freq

---
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index a7056db..b4576dc 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -27,7 +27,7 @@
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
 # Volta NVIDIA GV100  clock domains are adopted from 
 # https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
 # boost mode
 # -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
 
-- 
cgit v1.3


From c58ee08f0e7ec7c7ee6794d8ce2616ed1b0c10f2 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 10 Oct 2018 17:56:50 -0400
Subject: fixing freq of TITANV

---
 configs/3.x-cfgs/SM7_TITANV/gpgpusim.config | 4 ++--
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'configs')

diff --git a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
index 738c881..aefb04a 100644
--- a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -27,9 +27,9 @@
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
 # Pascal NVIDIA GP100  clock domains are adopted from 
 # https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
 # boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index b4576dc..41757f8 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -27,9 +27,9 @@
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
 # Volta NVIDIA GV100  clock domains are adopted from 
 # https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
+-gpgpu_clock_domains 1200.0:2000.0:1200.0:850.0
 # boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
-- 
cgit v1.3


From b1c00ed4369c648c2059cb6ecfdab48126ce574b Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 10 Oct 2018 18:13:23 -0400
Subject: adding new config files

---
 .../SM6_TITANX_1Xintes/config_fermi_islip.icnt     |  73 ++++++++
 .../4.x-cfgs/SM6_TITANX_1Xintes/gpgpusim.config    | 184 ++++++++++++++++++++
 .../SM7_TITANV_1Xicnt/config_fermi_islip.icnt      |  74 ++++++++
 configs/4.x-cfgs/SM7_TITANV_1Xicnt/gpgpusim.config | 191 +++++++++++++++++++++
 .../config_fermi_islip.icnt                        |  74 ++++++++
 .../SM7_TITANV_1Xicnt_1Xintes/gpgpusim.config      | 191 +++++++++++++++++++++
 6 files changed, 787 insertions(+)
 create mode 100644 configs/4.x-cfgs/SM6_TITANX_1Xintes/config_fermi_islip.icnt
 create mode 100644 configs/4.x-cfgs/SM6_TITANX_1Xintes/gpgpusim.config
 create mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt
 create mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt/gpgpusim.config
 create mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt
 create mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/gpgpusim.config

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX_1Xintes/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_TITANX_1Xintes/config_fermi_islip.icnt
new file mode 100644
index 0000000..85ac0d7
--- /dev/null
+++ b/configs/4.x-cfgs/SM6_TITANX_1Xintes/config_fermi_islip.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 64;
+input_buffer_size = 256;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM6_TITANX_1Xintes/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX_1Xintes/gpgpusim.config
new file mode 100644
index 0000000..cc7419c
--- /dev/null
+++ b/configs/4.x-cfgs/SM6_TITANX_1Xintes/gpgpusim.config
@@ -0,0 +1,184 @@
+# This config models the Pascal GP102 (NVIDIA TITAN X)
+# For more info about this card, see Nvidia White paper
+# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 61 
+-gpgpu_ignore_resources_limitation 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+# P102 has two semi-indp scheds per core, and two cores per cluster 
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+
+# This implies a maximum of 32 warps/SM
+-gpgpu_shader_core_pipeline 1024:32 
+-gpgpu_shader_cta 16
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 2
+-gpgpu_num_dp_units 1
+
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,8,8,8,130
+-ptx_opcode_initiation_sfu 4
+-ptx_opcode_latency_sfu 8
+
+
+# latencies and cache configs are adopted from:
+# https://arxiv.org/pdf/1804.06826.pdf
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
+# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres are used
+-gpgpu_cache:dl1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 49152
+-gpgpu_shmem_size_PrefL1 49152
+-gpgpu_shmem_size_PrefShared 49152
+# By default, L1 cache is disabled in Pascal P102.
+# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
+-gmem_skip_L1D 1
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 82
+-smem_latency 24
+-gpgpu_flush_l1_cache 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
+-perf_sim_memcpy 0
+
+# 4 KB Inst.
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+# 48 KB Tex 
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_operand_collector_num_in_ports_sfu 2
+-gpgpu_operand_collector_num_out_ports_sfu 2
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+# Use Pascal Coalsce arhitetecture
+-gpgpu_coalesce_arch 61
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 240
+
+# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
+# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
+                        CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
+
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal 102 has four schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 102
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt
new file mode 100644
index 0000000..cea3acf
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 128;
+boundary_buffer_size = 128;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV_1Xicnt/gpgpusim.config
new file mode 100644
index 0000000..a25e329
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV_1Xicnt/gpgpusim.config
@@ -0,0 +1,191 @@
+# This config models the Volta Titan X
+# For more info about this card:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 24
+-gpgpu_n_sub_partition_per_mchannel 1 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA GV100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+-gpgpu_flush_l1_cache 1
+-adpative_volta_cache_config 1
+
+# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
+-gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 0
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 100
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt
new file mode 100644
index 0000000..dba0e76
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 128;
+boundary_buffer_size = 128;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/gpgpusim.config
new file mode 100644
index 0000000..a25e329
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/gpgpusim.config
@@ -0,0 +1,191 @@
+# This config models the Volta Titan X
+# For more info about this card:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 24
+-gpgpu_n_sub_partition_per_mchannel 1 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA GV100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+-gpgpu_flush_l1_cache 1
+-adpative_volta_cache_config 1
+
+# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
+-gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 0
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 100
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
-- 
cgit v1.3


From 2ff5a7fc23b35490d155807191650de2cf073e71 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 10 Oct 2018 20:19:13 -0400
Subject: fixing TITANV inct buffer error

---
 configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
index cea3acf..2f25889 100644
--- a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
@@ -20,8 +20,8 @@ routing_function = dest_tag;
 num_vcs     = 1;
 vc_buf_size = 256;
 input_buffer_size = 256;
-ejection_buffer_size = 128;
-boundary_buffer_size = 128;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
 
 wait_for_tail_credit = 0;
 
-- 
cgit v1.3


From 8a728aa50ea27765e90fc346731aa5e083f29929 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 10 Oct 2018 20:23:19 -0400
Subject: fixing TITANV buffer error

---
 configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt         | 4 ++--
 configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt
index cea3acf..2f25889 100644
--- a/configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt
+++ b/configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt
@@ -20,8 +20,8 @@ routing_function = dest_tag;
 num_vcs     = 1;
 vc_buf_size = 256;
 input_buffer_size = 256;
-ejection_buffer_size = 128;
-boundary_buffer_size = 128;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
 
 wait_for_tail_credit = 0;
 
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt
index dba0e76..fca9ffe 100644
--- a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt
+++ b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt
@@ -20,8 +20,8 @@ routing_function = dest_tag;
 num_vcs     = 1;
 vc_buf_size = 256;
 input_buffer_size = 256;
-ejection_buffer_size = 128;
-boundary_buffer_size = 128;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
 
 wait_for_tail_credit = 0;
 
-- 
cgit v1.3


From fcaf5f1217e7349e2239f51a7bce1fad13df920c Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 10 Oct 2018 20:46:45 -0400
Subject: adding new config files

---
 .../SM6_TITANX_1Xintes_LB/config_fermi_islip.icnt  |  73 ++++++++
 .../4.x-cfgs/SM6_TITANX_1Xintes_LB/gpgpusim.config | 184 ++++++++++++++++++++
 .../config_fermi_islip.icnt                        |  74 ++++++++
 .../SM7_TITANV_1Xicnt_1Xintes_LB/gpgpusim.config   | 191 +++++++++++++++++++++
 4 files changed, 522 insertions(+)
 create mode 100644 configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/config_fermi_islip.icnt
 create mode 100644 configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/gpgpusim.config
 create mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/config_fermi_islip.icnt
 create mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/gpgpusim.config

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/config_fermi_islip.icnt
new file mode 100644
index 0000000..d4e3467
--- /dev/null
+++ b/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/config_fermi_islip.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 32;
+input_buffer_size = 32;
+ejection_buffer_size = 32;
+boundary_buffer_size = 32;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/gpgpusim.config
new file mode 100644
index 0000000..cc7419c
--- /dev/null
+++ b/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/gpgpusim.config
@@ -0,0 +1,184 @@
+# This config models the Pascal GP102 (NVIDIA TITAN X)
+# For more info about this card, see Nvidia White paper
+# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 61 
+-gpgpu_ignore_resources_limitation 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+# P102 has two semi-indp scheds per core, and two cores per cluster 
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+
+# This implies a maximum of 32 warps/SM
+-gpgpu_shader_core_pipeline 1024:32 
+-gpgpu_shader_cta 16
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 2
+-gpgpu_num_dp_units 1
+
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,8,8,8,130
+-ptx_opcode_initiation_sfu 4
+-ptx_opcode_latency_sfu 8
+
+
+# latencies and cache configs are adopted from:
+# https://arxiv.org/pdf/1804.06826.pdf
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
+# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres are used
+-gpgpu_cache:dl1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 49152
+-gpgpu_shmem_size_PrefL1 49152
+-gpgpu_shmem_size_PrefShared 49152
+# By default, L1 cache is disabled in Pascal P102.
+# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
+-gmem_skip_L1D 1
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 82
+-smem_latency 24
+-gpgpu_flush_l1_cache 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
+-perf_sim_memcpy 0
+
+# 4 KB Inst.
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+# 48 KB Tex 
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_operand_collector_num_in_ports_sfu 2
+-gpgpu_operand_collector_num_out_ports_sfu 2
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+# Use Pascal Coalsce arhitetecture
+-gpgpu_coalesce_arch 61
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 240
+
+# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
+# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
+                        CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
+
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal 102 has four schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 102
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/config_fermi_islip.icnt
new file mode 100644
index 0000000..c6badd3
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/config_fermi_islip.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 32;
+input_buffer_size = 32;
+ejection_buffer_size = 32;
+boundary_buffer_size = 32;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/gpgpusim.config
new file mode 100644
index 0000000..a25e329
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/gpgpusim.config
@@ -0,0 +1,191 @@
+# This config models the Volta Titan X
+# For more info about this card:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 24
+-gpgpu_n_sub_partition_per_mchannel 1 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA GV100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+-gpgpu_flush_l1_cache 1
+-adpative_volta_cache_config 1
+
+# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
+-gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 0
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 100
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
-- 
cgit v1.3


From 6f345dd40ed6c73eefec2a52858ce62f72a6fa25 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 10 Oct 2018 20:58:14 -0400
Subject: adding some new inct config files and delete oterhs

---
 configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt           |  73 ++++++++
 configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt        |  73 ++++++++
 .../4.x-cfgs/SM6_TITANX_1Xintes/gpgpusim.config    | 184 --------------------
 .../SM6_TITANX_1Xintes_LB/config_fermi_islip.icnt  |  73 --------
 .../4.x-cfgs/SM6_TITANX_1Xintes_LB/gpgpusim.config | 184 --------------------
 configs/4.x-cfgs/SM7_TITANV/.icnt                  |  74 ++++++++
 configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt           |  74 ++++++++
 configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt        |  74 ++++++++
 .../SM7_TITANV_1Xicnt/config_fermi_islip.icnt      |  74 --------
 configs/4.x-cfgs/SM7_TITANV_1Xicnt/gpgpusim.config | 191 ---------------------
 .../config_fermi_islip.icnt                        |  74 --------
 .../SM7_TITANV_1Xicnt_1Xintes/gpgpusim.config      | 191 ---------------------
 .../config_fermi_islip.icnt                        |  74 --------
 .../SM7_TITANV_1Xicnt_1Xintes_LB/gpgpusim.config   | 191 ---------------------
 14 files changed, 368 insertions(+), 1236 deletions(-)
 create mode 100644 configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt
 create mode 100644 configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt
 delete mode 100644 configs/4.x-cfgs/SM6_TITANX_1Xintes/gpgpusim.config
 delete mode 100644 configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/gpgpusim.config
 create mode 100644 configs/4.x-cfgs/SM7_TITANV/.icnt
 create mode 100644 configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt
 create mode 100644 configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt/gpgpusim.config
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/gpgpusim.config
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/gpgpusim.config

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt b/configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt
new file mode 100644
index 0000000..85ac0d7
--- /dev/null
+++ b/configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 64;
+input_buffer_size = 256;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt b/configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt
new file mode 100644
index 0000000..d4e3467
--- /dev/null
+++ b/configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 32;
+input_buffer_size = 32;
+ejection_buffer_size = 32;
+boundary_buffer_size = 32;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM6_TITANX_1Xintes/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX_1Xintes/gpgpusim.config
deleted file mode 100644
index cc7419c..0000000
--- a/configs/4.x-cfgs/SM6_TITANX_1Xintes/gpgpusim.config
+++ /dev/null
@@ -1,184 +0,0 @@
-# This config models the Pascal GP102 (NVIDIA TITAN X)
-# For more info about this card, see Nvidia White paper
-# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 61 
--gpgpu_ignore_resources_limitation 1
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
-# P102 has two semi-indp scheds per core, and two cores per cluster 
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 12
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
-
-# shader core pipeline config
--gpgpu_shader_registers 32768
-
-# This implies a maximum of 32 warps/SM
--gpgpu_shader_core_pipeline 1024:32 
--gpgpu_shader_cta 16
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 4 SFU units
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 2
--gpgpu_num_dp_units 1
-
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,8,8,8,130
--ptx_opcode_initiation_sfu 4
--ptx_opcode_latency_sfu 8
-
-
-# latencies and cache configs are adopted from:
-# https://arxiv.org/pdf/1804.06826.pdf
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
-# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
-# The defulat is to disable the L1 cache, unless cache modifieres are used
--gpgpu_cache:dl1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 49152
--gpgpu_shmem_size_PrefL1 49152
--gpgpu_shmem_size_PrefShared 49152
-# By default, L1 cache is disabled in Pascal P102.
-# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
--gmem_skip_L1D 1
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 82
--smem_latency 24
--gpgpu_flush_l1_cache 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 32:32:32:32
--perf_sim_memcpy 0
-
-# 4 KB Inst.
--gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
-# 48 KB Tex 
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_operand_collector_num_in_ports_sfu 2
--gpgpu_operand_collector_num_out_ports_sfu 2
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-# Use Pascal Coalsce arhitetecture
--gpgpu_coalesce_arch 61
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 240
-
-# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
-# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes 
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
-                        CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
-
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal 102 has four schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 102
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/config_fermi_islip.icnt
deleted file mode 100644
index d4e3467..0000000
--- a/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/config_fermi_islip.icnt
+++ /dev/null
@@ -1,73 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 52;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 32;
-input_buffer_size = 32;
-ejection_buffer_size = 32;
-boundary_buffer_size = 32;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/gpgpusim.config
deleted file mode 100644
index cc7419c..0000000
--- a/configs/4.x-cfgs/SM6_TITANX_1Xintes_LB/gpgpusim.config
+++ /dev/null
@@ -1,184 +0,0 @@
-# This config models the Pascal GP102 (NVIDIA TITAN X)
-# For more info about this card, see Nvidia White paper
-# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 61 
--gpgpu_ignore_resources_limitation 1
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
-# P102 has two semi-indp scheds per core, and two cores per cluster 
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 12
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
-
-# shader core pipeline config
--gpgpu_shader_registers 32768
-
-# This implies a maximum of 32 warps/SM
--gpgpu_shader_core_pipeline 1024:32 
--gpgpu_shader_cta 16
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 4 SFU units
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 2
--gpgpu_num_dp_units 1
-
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,8,8,8,130
--ptx_opcode_initiation_sfu 4
--ptx_opcode_latency_sfu 8
-
-
-# latencies and cache configs are adopted from:
-# https://arxiv.org/pdf/1804.06826.pdf
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
-# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
-# The defulat is to disable the L1 cache, unless cache modifieres are used
--gpgpu_cache:dl1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 49152
--gpgpu_shmem_size_PrefL1 49152
--gpgpu_shmem_size_PrefShared 49152
-# By default, L1 cache is disabled in Pascal P102.
-# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
--gmem_skip_L1D 1
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 82
--smem_latency 24
--gpgpu_flush_l1_cache 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 32:32:32:32
--perf_sim_memcpy 0
-
-# 4 KB Inst.
--gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
-# 48 KB Tex 
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_operand_collector_num_in_ports_sfu 2
--gpgpu_operand_collector_num_out_ports_sfu 2
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-# Use Pascal Coalsce arhitetecture
--gpgpu_coalesce_arch 61
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 240
-
-# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
-# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes 
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
-                        CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
-
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal 102 has four schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 102
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/4.x-cfgs/SM7_TITANV/.icnt b/configs/4.x-cfgs/SM7_TITANV/.icnt
new file mode 100644
index 0000000..2f25889
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV/.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt b/configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt
new file mode 100644
index 0000000..fca9ffe
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt b/configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt
new file mode 100644
index 0000000..c6badd3
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 32;
+input_buffer_size = 32;
+ejection_buffer_size = 32;
+boundary_buffer_size = 32;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt
deleted file mode 100644
index 2f25889..0000000
--- a/configs/4.x-cfgs/SM7_TITANV_1Xicnt/config_fermi_islip.icnt
+++ /dev/null
@@ -1,74 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 256;
-input_buffer_size = 256;
-ejection_buffer_size = 256;
-boundary_buffer_size = 256;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 2.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV_1Xicnt/gpgpusim.config
deleted file mode 100644
index a25e329..0000000
--- a/configs/4.x-cfgs/SM7_TITANV_1Xicnt/gpgpusim.config
+++ /dev/null
@@ -1,191 +0,0 @@
-# This config models the Volta Titan X
-# For more info about this card:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 1 
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA GV100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
-
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 32KB DL1 and 96KB shared memory
-# In Volta, we assign the remaining shared memory to L1 cache 
-# if the assigned shd mem = 0, then L1 cache = 128KB
-# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
-# disable this mode in case of multi kernels/apps execution
--adpative_volta_cache_config 1
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 98304
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 28
--smem_latency 19
--gpgpu_flush_l1_cache 1
--adpative_volta_cache_config 1
-
-# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
--gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 0
-
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal has two schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 100
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt
deleted file mode 100644
index fca9ffe..0000000
--- a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/config_fermi_islip.icnt
+++ /dev/null
@@ -1,74 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 256;
-input_buffer_size = 256;
-ejection_buffer_size = 256;
-boundary_buffer_size = 256;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/gpgpusim.config
deleted file mode 100644
index a25e329..0000000
--- a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes/gpgpusim.config
+++ /dev/null
@@ -1,191 +0,0 @@
-# This config models the Volta Titan X
-# For more info about this card:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 1 
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA GV100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
-
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 32KB DL1 and 96KB shared memory
-# In Volta, we assign the remaining shared memory to L1 cache 
-# if the assigned shd mem = 0, then L1 cache = 128KB
-# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
-# disable this mode in case of multi kernels/apps execution
--adpative_volta_cache_config 1
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 98304
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 28
--smem_latency 19
--gpgpu_flush_l1_cache 1
--adpative_volta_cache_config 1
-
-# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
--gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 0
-
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal has two schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 100
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/config_fermi_islip.icnt
deleted file mode 100644
index c6badd3..0000000
--- a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/config_fermi_islip.icnt
+++ /dev/null
@@ -1,74 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 32;
-input_buffer_size = 32;
-ejection_buffer_size = 32;
-boundary_buffer_size = 32;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/gpgpusim.config
deleted file mode 100644
index a25e329..0000000
--- a/configs/4.x-cfgs/SM7_TITANV_1Xicnt_1Xintes_LB/gpgpusim.config
+++ /dev/null
@@ -1,191 +0,0 @@
-# This config models the Volta Titan X
-# For more info about this card:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 1 
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA GV100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
-
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 32KB DL1 and 96KB shared memory
-# In Volta, we assign the remaining shared memory to L1 cache 
-# if the assigned shd mem = 0, then L1 cache = 128KB
-# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
-# disable this mode in case of multi kernels/apps execution
--adpative_volta_cache_config 1
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 98304
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 28
--smem_latency 19
--gpgpu_flush_l1_cache 1
--adpative_volta_cache_config 1
-
-# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
--gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 0
-
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal has two schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 100
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
-- 
cgit v1.3


From 3d0f3691c6ccff4a912fc0fb751291a96832cd13 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 10 Oct 2018 21:04:24 -0400
Subject: removing unnecassery files

---
 .../SM6_TITANX_1Xintes/config_fermi_islip.icnt     | 73 ----------------------
 1 file changed, 73 deletions(-)
 delete mode 100644 configs/4.x-cfgs/SM6_TITANX_1Xintes/config_fermi_islip.icnt

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX_1Xintes/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_TITANX_1Xintes/config_fermi_islip.icnt
deleted file mode 100644
index 85ac0d7..0000000
--- a/configs/4.x-cfgs/SM6_TITANX_1Xintes/config_fermi_islip.icnt
+++ /dev/null
@@ -1,73 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 52;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 64;
-input_buffer_size = 256;
-ejection_buffer_size = 64;
-boundary_buffer_size = 64;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
-- 
cgit v1.3


From a6b9171a158d29d5d1ad415d087f483feb1af965 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Thu, 11 Oct 2018 12:58:35 -0400
Subject: enable memcpu-perf by deafault

---
 configs/4.x-cfgs/SM2_GTX480/gpgpusim.config |  2 +-
 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config |  2 +-
 configs/4.x-cfgs/SM7_TITANV/.icnt           | 74 -----------------------------
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config |  3 +-
 4 files changed, 3 insertions(+), 78 deletions(-)
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV/.icnt

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
index b965aff..05663c2 100644
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
@@ -67,7 +67,7 @@
 -gpgpu_cache:dl2 S:64:128:8,L:B:m:L:L,A:256:4,4:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 0
+-perf_sim_memcpy 1
 -memory_partition_indexing 0
 
 -gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index cc7419c..1b4e6e3 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -84,7 +84,7 @@
 -gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 32:32:32:32
--perf_sim_memcpy 0
+-perf_sim_memcpy 1
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
diff --git a/configs/4.x-cfgs/SM7_TITANV/.icnt b/configs/4.x-cfgs/SM7_TITANV/.icnt
deleted file mode 100644
index 2f25889..0000000
--- a/configs/4.x-cfgs/SM7_TITANV/.icnt
+++ /dev/null
@@ -1,74 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 256;
-input_buffer_size = 256;
-ejection_buffer_size = 256;
-boundary_buffer_size = 256;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 2.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index 41757f8..6fe441b 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -79,13 +79,12 @@
 -l1_latency 28
 -smem_latency 19
 -gpgpu_flush_l1_cache 1
--adpative_volta_cache_config 1
 
 # 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
 -gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 0
+-perf_sim_memcpy 1
 
 # 128 KB Inst.
 -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-- 
cgit v1.3


From 0f435a57674d5839a413bec5292eca66a6389dff Mon Sep 17 00:00:00 2001
From: tgrogers <tgrogers@purdue.edu>
Date: Thu, 11 Oct 2018 23:28:08 -0400
Subject: must specify occupancy number

---
 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 1 +
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config | 1 +
 2 files changed, 2 insertions(+)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 1b4e6e3..3842508 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -27,6 +27,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 62
 
 # This implies a maximum of 32 warps/SM
 -gpgpu_shader_core_pipeline 1024:32 
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index 6fe441b..c8351da 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -33,6 +33,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 70
 
 # This implies a maximum of 64 warps/SM
 -gpgpu_shader_core_pipeline 2048:32 
-- 
cgit v1.3


From 74c939d205c0eff341f80f5867183dfa3e70c114 Mon Sep 17 00:00:00 2001
From: tgrogers <tgrogers@purdue.edu>
Date: Mon, 15 Oct 2018 20:16:06 -0400
Subject: Specify the register sm occpancy number for 480

---
 configs/4.x-cfgs/SM2_GTX480/gpgpusim.config | 1 +
 1 file changed, 1 insertion(+)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
index 05663c2..4096b09 100644
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
@@ -22,6 +22,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
 
 # This implies a maximum of 48 warps/SM
 -gpgpu_shader_core_pipeline 1536:32 
-- 
cgit v1.3


From b37069409322cac50161e96f198f689bb6de88a8 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Tue, 16 Oct 2018 16:57:25 -0400
Subject: delete unnecssary config files

---
 configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt    | 73 ----------------------------
 configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt | 73 ----------------------------
 configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt    | 74 -----------------------------
 configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt | 74 -----------------------------
 4 files changed, 294 deletions(-)
 delete mode 100644 configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt
 delete mode 100644 configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt b/configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt
deleted file mode 100644
index 85ac0d7..0000000
--- a/configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt
+++ /dev/null
@@ -1,73 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 52;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 64;
-input_buffer_size = 256;
-ejection_buffer_size = 64;
-boundary_buffer_size = 64;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt b/configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt
deleted file mode 100644
index d4e3467..0000000
--- a/configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt
+++ /dev/null
@@ -1,73 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 52;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 32;
-input_buffer_size = 32;
-ejection_buffer_size = 32;
-boundary_buffer_size = 32;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt b/configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt
deleted file mode 100644
index fca9ffe..0000000
--- a/configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt
+++ /dev/null
@@ -1,74 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 256;
-input_buffer_size = 256;
-ejection_buffer_size = 256;
-boundary_buffer_size = 256;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt b/configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt
deleted file mode 100644
index c6badd3..0000000
--- a/configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt
+++ /dev/null
@@ -1,74 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 32;
-input_buffer_size = 32;
-ejection_buffer_size = 32;
-boundary_buffer_size = 32;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
-- 
cgit v1.3


From e41955fb2b2041c67f5a4a5627d4870c4cda13aa Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Tue, 16 Oct 2018 17:28:41 -0400
Subject: remove pascal titianx

---
 configs/Pascal_TITANX/config_fermi_islip.icnt |  70 ------------
 configs/Pascal_TITANX/gpgpusim.config         | 156 --------------------------
 2 files changed, 226 deletions(-)
 delete mode 100644 configs/Pascal_TITANX/config_fermi_islip.icnt
 delete mode 100644 configs/Pascal_TITANX/gpgpusim.config

(limited to 'configs')

diff --git a/configs/Pascal_TITANX/config_fermi_islip.icnt b/configs/Pascal_TITANX/config_fermi_islip.icnt
deleted file mode 100644
index 602daee..0000000
--- a/configs/Pascal_TITANX/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 52;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/Pascal_TITANX/gpgpusim.config b/configs/Pascal_TITANX/gpgpusim.config
deleted file mode 100644
index f78bd02..0000000
--- a/configs/Pascal_TITANX/gpgpusim.config
+++ /dev/null
@@ -1,156 +0,0 @@
-# This config models the Pascal GP102 (NVIDIA TITAN X)
-# For more info about this card, see Nvidia White paper
-# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 61
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 12
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,4,1,1,6
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# SFU is 32-width in pascal, then dp units initiation is 1 cycle
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,8,4,4,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory
-# Pascal GP102 has 64KB L1 cache
-# The defulat is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_shmem_size 98304
--gpgpu_shmem_size_PrefL1 98304
--gpgpu_shmem_size_PrefShared 98304
--gmem_skip_L1D 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 32:32:32:32
-
-# 4 KB Inst.
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
-
-# enable operand collector 
-## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
--gpgpu_operand_collector_num_units_sp 20
--gpgpu_operand_collector_num_units_sfu 4
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
-# gpgpu_num_reg_banks should be increased to 32
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
-# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes 
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing from hynix H5GQ1H24AFR
-# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
-- 
cgit v1.3


From ab0d5d829d3f825736c5f91a365e755b2c2752c9 Mon Sep 17 00:00:00 2001
From: tgrogers <tgrogers@purdue.edu>
Date: Tue, 23 Oct 2018 11:14:22 -0400
Subject: Moving configs to folders with better names

---
 configs/3.x-cfgs/GTX480/config_fermi_islip.icnt    |  70 ---
 configs/3.x-cfgs/GTX480/gpgpusim.config            | 134 -----
 configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml       | 538 --------------------
 .../GeForceGTX750Ti/config_fermi_islip.icnt        |  70 ---
 configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config   | 131 -----
 .../GeForceGTX750Ti/gpuwattch_gtx750Ti.xml         | 539 ---------------------
 configs/3.x-cfgs/QuadroFX5600/gpgpusim.config      |  99 ----
 .../QuadroFX5600/gpuwattch_quadrofx5600.xml        | 538 --------------------
 .../3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt   |  70 ---
 .../3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt |  69 ---
 configs/3.x-cfgs/QuadroFX5800/gpgpusim.config      |  88 ----
 .../3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt   |  70 ---
 configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config       | 150 ------
 .../3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml   | 538 --------------------
 configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt  |  70 ---
 configs/3.x-cfgs/SM6_P100/gpgpusim.config          | 156 ------
 configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml     | 538 --------------------
 .../3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt    |  70 ---
 configs/3.x-cfgs/SM6_TITANX/gpgpusim.config        | 157 ------
 configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml   | 538 --------------------
 .../3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt    |  70 ---
 configs/3.x-cfgs/SM7_TITANV/gpgpusim.config        | 165 -------
 .../3.x-cfgs/TeslaC2050/config_fermi_islip.icnt    |  70 ---
 configs/3.x-cfgs/TeslaC2050/gpgpusim.config        | 133 -----
 .../4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt    |  70 ---
 configs/4.x-cfgs/SM2_GTX480/gpgpusim.config        | 153 ------
 configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml   | 538 --------------------
 .../4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt    |  73 ---
 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config        | 185 -------
 .../4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt    |  74 ---
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config        | 191 --------
 .../deprecated-cfgs/GTX480/config_fermi_islip.icnt |  70 +++
 configs/deprecated-cfgs/GTX480/gpgpusim.config     | 134 +++++
 .../deprecated-cfgs/GTX480/gpuwattch_gtx480.xml    | 538 ++++++++++++++++++++
 .../GeForceGTX750Ti/config_fermi_islip.icnt        |  70 +++
 .../GeForceGTX750Ti/gpgpusim.config                | 131 +++++
 .../GeForceGTX750Ti/gpuwattch_gtx750Ti.xml         | 539 +++++++++++++++++++++
 .../deprecated-cfgs/QuadroFX5600/gpgpusim.config   |  99 ++++
 .../QuadroFX5600/gpuwattch_quadrofx5600.xml        | 538 ++++++++++++++++++++
 .../QuadroFX5600/icnt_config_islip.icnt            |  70 +++
 .../QuadroFX5800/config_quadro_islip.icnt          |  69 +++
 .../deprecated-cfgs/QuadroFX5800/gpgpusim.config   |  88 ++++
 .../SM6_GTX1080/config_fermi_islip.icnt            |  70 +++
 .../deprecated-cfgs/SM6_GTX1080/gpgpusim.config    | 150 ++++++
 .../SM6_GTX1080/gpuwattch_gtx1080Ti.xml            | 538 ++++++++++++++++++++
 .../SM6_P100/config_fermi_islip.icnt               |  70 +++
 configs/deprecated-cfgs/SM6_P100/gpgpusim.config   | 156 ++++++
 .../deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml  | 538 ++++++++++++++++++++
 .../SM6_TITANX/config_fermi_islip.icnt             |  70 +++
 configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config | 157 ++++++
 .../SM6_TITANX/gpuwattch_gtx480.xml                | 538 ++++++++++++++++++++
 .../SM7_TITANV/config_fermi_islip.icnt             |  70 +++
 configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config | 165 +++++++
 .../TeslaC2050/config_fermi_islip.icnt             |  70 +++
 configs/deprecated-cfgs/TeslaC2050/gpgpusim.config | 133 +++++
 .../tested-cfgs/SM2_GTX480/config_fermi_islip.icnt |  70 +++
 configs/tested-cfgs/SM2_GTX480/gpgpusim.config     | 153 ++++++
 .../tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml    | 538 ++++++++++++++++++++
 .../tested-cfgs/SM6_TITANX/config_fermi_islip.icnt |  73 +++
 configs/tested-cfgs/SM6_TITANX/gpgpusim.config     | 185 +++++++
 .../tested-cfgs/SM7_TITANV/config_fermi_islip.icnt |  74 +++
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config     | 191 ++++++++
 62 files changed, 6355 insertions(+), 6355 deletions(-)
 delete mode 100644 configs/3.x-cfgs/GTX480/config_fermi_islip.icnt
 delete mode 100644 configs/3.x-cfgs/GTX480/gpgpusim.config
 delete mode 100755 configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml
 delete mode 100644 configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
 delete mode 100644 configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
 delete mode 100755 configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
 delete mode 100644 configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
 delete mode 100644 configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
 delete mode 100644 configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt
 delete mode 100644 configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt
 delete mode 100644 configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
 delete mode 100644 configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
 delete mode 100644 configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
 delete mode 100755 configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
 delete mode 100644 configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt
 delete mode 100644 configs/3.x-cfgs/SM6_P100/gpgpusim.config
 delete mode 100755 configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml
 delete mode 100644 configs/3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt
 delete mode 100644 configs/3.x-cfgs/SM6_TITANX/gpgpusim.config
 delete mode 100755 configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
 delete mode 100644 configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
 delete mode 100644 configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
 delete mode 100644 configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt
 delete mode 100644 configs/3.x-cfgs/TeslaC2050/gpgpusim.config
 delete mode 100644 configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
 delete mode 100755 configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
 delete mode 100644 configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
 delete mode 100644 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
 create mode 100644 configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/GTX480/gpgpusim.config
 create mode 100755 configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml
 create mode 100644 configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config
 create mode 100755 configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
 create mode 100644 configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config
 create mode 100644 configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
 create mode 100644 configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt
 create mode 100644 configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt
 create mode 100644 configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config
 create mode 100644 configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
 create mode 100755 configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
 create mode 100644 configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/SM6_P100/gpgpusim.config
 create mode 100755 configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml
 create mode 100644 configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config
 create mode 100755 configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
 create mode 100644 configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config
 create mode 100644 configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/TeslaC2050/gpgpusim.config
 create mode 100644 configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt
 create mode 100644 configs/tested-cfgs/SM2_GTX480/gpgpusim.config
 create mode 100755 configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
 create mode 100644 configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
 create mode 100644 configs/tested-cfgs/SM6_TITANX/gpgpusim.config
 create mode 100644 configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
 create mode 100644 configs/tested-cfgs/SM7_TITANV/gpgpusim.config

(limited to 'configs')

diff --git a/configs/3.x-cfgs/GTX480/config_fermi_islip.icnt b/configs/3.x-cfgs/GTX480/config_fermi_islip.icnt
deleted file mode 100644
index 7820e4e..0000000
--- a/configs/3.x-cfgs/GTX480/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 27;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/3.x-cfgs/GTX480/gpgpusim.config b/configs/3.x-cfgs/GTX480/gpgpusim.config
deleted file mode 100644
index ee90c12..0000000
--- a/configs/3.x-cfgs/GTX480/gpgpusim.config
+++ /dev/null
@@ -1,134 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 20 
-
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 15
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 6
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Fermi clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
-# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
--gpgpu_clock_domains 700.0:700.0:700.0:924.0
-
-# shader core pipeline config
--gpgpu_shader_registers 32768
--gpgpu_occupancy_sm_number 20
-
-# This implies a maximum of 48 warps/SM
--gpgpu_shader_core_pipeline 1536:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,1,1,2,1,1,2
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,1,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,16,8,8,130
-
-
-# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
--gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
--gpgpu_shmem_size 49152
-
-# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
-#-gpgpu_shmem_size 16384
-
-# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
--gpgpu_cache:dl2_texture_only 0 
-
--gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_num_reg_banks 16
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
--gpgpu_max_insn_issue_per_warp 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 116
-
-# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5 is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
-
-# GDDR5 timing from hynix H5GQ1H24AFR
-# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml b/configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml
deleted file mode 100755
index 304e0fd..0000000
--- a/configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="16"/>
-		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="1"/>
-		<param name="core_tech_node" value="40"/><!-- nm -->
-		<param name="target_core_clockrate" value="700"/><!--MHz -->
-		<param name="temperature" value="380"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
-		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
-		<param name="TOT_INST" value="2.00" />
-		<param name="FP_INT" value="4.57" />
-		<param name="IC_H" value="2.14" />
-		<param name="IC_M" value="22.47" />
-		<param name="DC_RH" value="22.14" />
-		<param name="DC_RM" value="24.66" />
-		<param name="DC_WH" value="1.53" />
-		<param name="DC_WM" value="39.79" />
-		<param name="TC_H" value="10.21" />
-		<param name="TC_M" value="24.66" />
-		<param name="CC_H" value="11.07" />
-		<param name="CC_M" value="12.33" />
-		<param name="SHRD_ACC" value="7.04" />
-		<param name="REG_RD" value="0.14" />
-		<param name="REG_WR" value="0.21" />
-		<param name="NON_REG_OPs" value="2.11" />
-		<param name="SP_ACC" value="2.38" />
-		<param name="SFU_ACC" value="0.51" />
-		<param name="FPU_ACC" value="0.64" />
-		<param name="MEM_RD" value="0.33" />
-		<param name="MEM_WR" value="0.40" />
-		<param name="MEM_PRE" value="0.11" />
-		<param name="L2_RH" value="13.79" />
-		<param name="L2_RM" value="35.18" />
-		<param name="L2_WH" value="43.07" />
-		<param name="L2_WM" value="28.72" />
-		<param name="NOC_A" value="305.48" />
-		<param name="PIPE_A" value="2.57" />
-		<param name="IDLE_CORE_N" value="1"/>
-		<param name="CONST_DYNAMICN" value="11" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="700"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="2"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="2"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="32"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="4"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="32"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="32"/>
-			<param name="simd_width" value="32"/>
-			<param name="collector_units" value="32"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="32768"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="2"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="15"/>	
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="0"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="700"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="2"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="6"/>
-			<param name="output_ports" value="6"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="0"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="40"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="6"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="3.8475e-8f"/>
-			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
-			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
deleted file mode 100644
index 069ca02..0000000
--- a/configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 7;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config b/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
deleted file mode 100644
index c675aab..0000000
--- a/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
+++ /dev/null
@@ -1,131 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 52 
-
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 5
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 2
--gpgpu_n_sub_partition_per_mchannel 1
-
-# Maxwell clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number.
--gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 52
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,1,1,2,1,1,2
--gpgpu_num_sp_units 8
--gpgpu_num_sfu_units 32
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 6,12,13,13,210
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 6,12,6,6,374
--ptx_opcode_initiation_fp 1,1,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,16,8,8,130
-
--gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
--gmem_skip_L1D 1
--gpgpu_shmem_size 65536
-
-# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
-#-gpgpu_shmem_size 16384
-
-# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache
--gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32
--gpgpu_cache:dl2_texture_only 0 
-
--gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_num_reg_banks 16
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 150
--dram_latency 130
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 300
-
-# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 32
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5 is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
-
-# GDDR5 timing from hynix H5GQ1H24AFR
-# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
-
-# Maxwell has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
-# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy.
-# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present.
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx750Ti.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
deleted file mode 100755
index e2b2324..0000000
--- a/configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
+++ /dev/null
@@ -1,539 +0,0 @@
-<!-- THIS CONFIG IS CURRENTLY PRESENT ONLY AS A PLACEHOLDER. IT HAS NOT BEEN TESTED FOR ACCURACY VERSUS GTX750TI HARDWARE. ANY USE OF THIS CONFIG WILL LIKELY GIVE HIGHLY INACCURATE RESULTS. -->
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="16"/>
-		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="1"/>
-		<param name="core_tech_node" value="40"/><!-- nm -->
-		<param name="target_core_clockrate" value="700"/><!--MHz -->
-		<param name="temperature" value="380"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
-		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
-		<param name="TOT_INST" value="2.00" />
-		<param name="FP_INT" value="4.57" />
-		<param name="IC_H" value="2.14" />
-		<param name="IC_M" value="22.47" />
-		<param name="DC_RH" value="22.14" />
-		<param name="DC_RM" value="24.66" />
-		<param name="DC_WH" value="1.53" />
-		<param name="DC_WM" value="39.79" />
-		<param name="TC_H" value="10.21" />
-		<param name="TC_M" value="24.66" />
-		<param name="CC_H" value="11.07" />
-		<param name="CC_M" value="12.33" />
-		<param name="SHRD_ACC" value="7.04" />
-		<param name="REG_RD" value="0.14" />
-		<param name="REG_WR" value="0.21" />
-		<param name="NON_REG_OPs" value="2.11" />
-		<param name="SP_ACC" value="2.38" />
-		<param name="SFU_ACC" value="0.51" />
-		<param name="FPU_ACC" value="0.64" />
-		<param name="MEM_RD" value="0.33" />
-		<param name="MEM_WR" value="0.40" />
-		<param name="MEM_PRE" value="0.11" />
-		<param name="L2_RH" value="13.79" />
-		<param name="L2_RM" value="35.18" />
-		<param name="L2_WH" value="43.07" />
-		<param name="L2_WM" value="28.72" />
-		<param name="NOC_A" value="305.48" />
-		<param name="PIPE_A" value="2.57" />
-		<param name="IDLE_CORE_N" value="1"/>
-		<param name="CONST_DYNAMICN" value="11" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="700"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="2"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="2"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="32"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="4"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="32"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="32"/>
-			<param name="simd_width" value="32"/>
-			<param name="collector_units" value="32"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="32768"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="2"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="15"/>	
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="0"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="700"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="2"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="6"/>
-			<param name="output_ports" value="6"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="0"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="40"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="6"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="3.8475e-8f"/>
-			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
-			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config b/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
deleted file mode 100644
index 6f836ee..0000000
--- a/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
+++ /dev/null
@@ -1,99 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 12
-
-# high level architecture configuration
--gpgpu_n_clusters 8 
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 6 
--gpgpu_clock_domains 337.5:600.0:600.0:800.0 
-
-# shader core pipeline config
--gpgpu_shader_registers 16384
--gpgpu_occupancy_sm_number 12
-
--gpgpu_occupancy_sm_number 12
-#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though)
--gpgpu_shader_core_pipeline 768:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 1,1,1,1,1,1,1
--gpgpu_num_sp_units 1
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 1,1,19,25,145
--ptx_opcode_initiation_int 1,1,4,4,32
--ptx_opcode_latency_fp 1,1,1,1,30
--ptx_opcode_initiation_fp 1,1,1,1,5
--ptx_opcode_latency_dp 8,8,8,8,335
--ptx_opcode_initiation_dp 8,8,8,8,130
-
-# memory stage behaviour
--gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
--gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
--gpgpu_cache:dl2_texture_only 1
-
-# TLB parameters
-#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8
-#-gpgpu_tlbl2_latency 45
-
-
--gpgpu_shmem_warp_parts 2
-
-# interconnection
--network_mode 1 
--inter_config_file icnt_config_islip.icnt 
-
-# dram scheduler config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (30 core cycles).  I.e. 
-#   Total buffer space required = 30 x 800MHz / 337.5MHz = 71
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 55
-
-# dram model config
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4 
--gpgpu_dram_burst_length 4
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
-# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
-# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
--gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
-
-
-
-# Using cuobjdump to extract ptx/SASS
--gpgpu_ptx_use_cuobjdump 1
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
-
--visualizer_enabled 0
--power_trace_enabled 0
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_quadrofx5600.xml 
-
--steady_power_levels_enabled 1
--steady_state_definition 8,4
diff --git a/configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
deleted file mode 100644
index 2c5a6fc..0000000
--- a/configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="0"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="16"/>
-		<param name="architecture" value="2"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="0"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="0"/>
-		<param name="core_tech_node" value="65"/><!-- nm -->
-		<param name="target_core_clockrate" value="650"/><!--MHz -->
-		<param name="temperature" value="400"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.54"/><!-- idle core power for GTX479 -->
-		<param name="TOT_INST" value="2" />
-		<param name="FP_INT" value="5" />
-		<param name="IC_H" value="10" />
-		<param name="IC_M" value="10" />
-		<param name="DC_RH" value="10" />
-		<param name="DC_RM" value="10" />
-		<param name="DC_WH" value="10" />
-		<param name="DC_WM" value="10" />
-		<param name="TC_H" value="20" />
-		<param name="TC_M" value="20" />
-		<param name="CC_H" value="10" />
-		<param name="CC_M" value="10" />
-		<param name="SHRD_ACC" value="20" />
-		<param name="REG_RD" value="0.25" />
-		<param name="REG_WR" value="0.4" />
-		<param name="NON_REG_OPs" value="0.4" />
-		<param name="SP_ACC" value="0.6" />
-		<param name="SFU_ACC" value="0.7" />
-		<param name="FPU_ACC" value="0.25" />
-		<param name="MEM_RD" value="0.3" />
-		<param name="MEM_WR" value="0.4" />
-		<param name="MEM_PRE" value="0.7" />
-		<param name="L2_RH" value="1" />
-		<param name="L2_RM" value="1" />
-		<param name="L2_WH" value="1" />
-		<param name="L2_WM" value="1" />
-		<param name="NOC_A" value="80" />
-		<param name="PIPE_A" value="0.8" />
-		<param name="IDLE_CORE_N" value="1"/>
-		<param name="CONST_DYNAMICN" value="9" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="650"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="1"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="1"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="1"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="1"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="8"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="16"/>
-			<param name="simd_width" value="8"/>
-			<param name="collector_units" value="16"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="8192"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="1"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="0.4"/>
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="1"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="1"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="65536,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="16384,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1300"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1300"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="100"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="786432,64,16,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="1300"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="650"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="4"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="7"/>
-			<param name="output_ports" value="7"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="360000"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="65"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="8"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="800"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="9600"/><!--MB/S  Syed: Quadro FX 5800 has 76.8GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="8"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="1.53846154e-8f"/>
-			<param name="dram_rd_coeff" value="3.07692308e-8f"/>
-			<param name="dram_wr_coeff" value="1.30769231e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt b/configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt
deleted file mode 100644
index de3bcc8..0000000
--- a/configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//14*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we donot use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 14;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt b/configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt
deleted file mode 100644
index cfe9cac..0000000
--- a/configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt
+++ /dev/null
@@ -1,69 +0,0 @@
-//18*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we donot use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 18;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config b/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
deleted file mode 100644
index fef1110..0000000
--- a/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
+++ /dev/null
@@ -1,88 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 13
-
-# high level architecture configuration
--gpgpu_n_clusters 10 
--gpgpu_n_cores_per_cluster 3
--gpgpu_n_mem 8 
--gpgpu_clock_domains 325.0:650.0:650.0:800.0 
-
-# shader core pipeline config
--gpgpu_shader_registers 16384
--gpgpu_occupancy_sm_number 13
-
--gpgpu_shader_core_pipeline 1024:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 1,1,1,1,1,1,1
--gpgpu_num_sp_units 1
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 1,1,19,25,145
--ptx_opcode_initiation_int 1,1,4,4,32
--ptx_opcode_latency_fp 1,1,1,1,30
--ptx_opcode_initiation_fp 1,1,1,1,5
--ptx_opcode_latency_dp 8,8,8,8,335
--ptx_opcode_initiation_dp 8,8,8,8,130
-
-# memory stage behaviour
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
--gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
--gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
--gpgpu_cache:dl2_texture_only 1
-
--gpgpu_shmem_warp_parts 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_quadro_islip.icnt
-
-# dram scheduler config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (30 core cycles).  I.e. 
-#   Total buffer space required = 30 x 800MHz / 325MHz = 74
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 58
-
-# dram model config
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4 
--gpgpu_dram_burst_length 4
--dram_data_command_freq_ratio 2  # GDDR3 is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
-# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
--gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
-
--visualizer_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt b/configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
deleted file mode 100644
index 2a69ddd..0000000
--- a/configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 50;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config b/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
deleted file mode 100644
index fb044c6..0000000
--- a/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
+++ /dev/null
@@ -1,150 +0,0 @@
-# This config models the Pascal GP102 (GeForceGTX 1080Ti)
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 60
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 11
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 60
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,4,1,1,6
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# SFU is 32-width in pascal, then dp units initiation is 1 cycle
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 1,2,1,1,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory
-# Pascal GP102 has 64KB L1 cache
-# The default is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,8
--gpgpu_shmem_size 98304
--gmem_skip_L1D 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
--gpgpu_cache:dl2_texture_only 0 
-
-# 4 KB Inst.
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
-
-# enable operand collector 
-## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
--gpgpu_operand_collector_num_units_sp 20
--gpgpu_operand_collector_num_units_sfu 4
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
-# gpgpu_num_reg_banks should be increased to 32, but it gives an error!
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits)
-# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes 
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing from hynix H5GQ1H24AFR
-# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
-
-# Pascal has four schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml b/configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
deleted file mode 100755
index 02619ff..0000000
--- a/configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="28"/>
-		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="1"/>
-		<param name="core_tech_node" value="23"/><!-- nm -->
-		<param name="target_core_clockrate" value="1481"/><!--MHz -->
-		<param name="temperature" value="380"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
-		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
-		<param name="TOT_INST" value="10" />
-		<param name="FP_INT" value="10" />
-		<param name="IC_H" value="0.001" />
-		<param name="IC_M" value="10" />
-		<param name="DC_RH" value="1" />
-		<param name="DC_RM" value="1" />
-		<param name="DC_WH" value="1" />
-		<param name="DC_WM" value="1" />
-		<param name="TC_H" value="0.001" />
-		<param name="TC_M" value="10" />
-		<param name="CC_H" value="4.5071" />
-		<param name="CC_M" value="10" />
-		<param name="SHRD_ACC" value="10" />
-		<param name="REG_RD" value="1.6294" />
-		<param name="REG_WR" value="0.5031" />
-		<param name="NON_REG_OPs" value="0.01" />
-		<param name="SP_ACC" value="10" />
-		<param name="SFU_ACC" value="0.0082" />
-		<param name="FPU_ACC" value="0.4126" />
-		<param name="MEM_RD" value="0.1234" />
-		<param name="MEM_WR" value="0.001" />
-		<param name="MEM_PRE" value="0.001" />
-		<param name="L2_RH" value="100" />
-		<param name="L2_RM" value="100" />
-		<param name="L2_WH" value="100" />
-		<param name="L2_WM" value="42.6966" />
-		<param name="NOC_A" value="100" />
-		<param name="PIPE_A" value="44.8085" />
-		<param name="IDLE_CORE_N" value="2.0382"/>
-		<param name="CONST_DYNAMICN" value="5.0005" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="1481"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="2"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="2"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="32"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="4"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="32"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="32"/>
-			<param name="simd_width" value="32"/>
-			<param name="collector_units" value="32"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="65536"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="2"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="15"/>	
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="0"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="2962"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="700"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="2"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="6"/>
-			<param name="output_ports" value="6"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="0"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="23"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="6"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="3.8475e-8f"/>
-			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
-			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt b/configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt
deleted file mode 100644
index d26c8d9..0000000
--- a/configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 60;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/3.x-cfgs/SM6_P100/gpgpusim.config b/configs/3.x-cfgs/SM6_P100/gpgpusim.config
deleted file mode 100644
index a5e6736..0000000
--- a/configs/3.x-cfgs/SM6_P100/gpgpusim.config
+++ /dev/null
@@ -1,156 +0,0 @@
-# This config models the Pascal GP100
-# For more info about this card, see Nvidia White paper
-# https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 60
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 32
--gpgpu_n_sub_partition_per_mchannel 1
-
-# Pscal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA GP100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Nvidia_Tesla
--gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,2,1,2,2,1,4
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# SFU is 32-width in pascal, then dp units initiation is 1 cycle
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 2,2,2,2,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP100 has 64KB Shared memory
-# Pascal GP100 has 48KB L1 cache
--gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 65536
--gpgpu_shmem_size_PrefShared 65536
--gmem_skip_L1D 0
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 32:32:32:32
-
-# 4 KB Inst.
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
-
-# enable operand collector
--gpgpu_operand_collector_num_units_sp 14
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_units_mem 10
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml b/configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml
deleted file mode 100755
index 304e0fd..0000000
--- a/configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="16"/>
-		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="1"/>
-		<param name="core_tech_node" value="40"/><!-- nm -->
-		<param name="target_core_clockrate" value="700"/><!--MHz -->
-		<param name="temperature" value="380"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
-		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
-		<param name="TOT_INST" value="2.00" />
-		<param name="FP_INT" value="4.57" />
-		<param name="IC_H" value="2.14" />
-		<param name="IC_M" value="22.47" />
-		<param name="DC_RH" value="22.14" />
-		<param name="DC_RM" value="24.66" />
-		<param name="DC_WH" value="1.53" />
-		<param name="DC_WM" value="39.79" />
-		<param name="TC_H" value="10.21" />
-		<param name="TC_M" value="24.66" />
-		<param name="CC_H" value="11.07" />
-		<param name="CC_M" value="12.33" />
-		<param name="SHRD_ACC" value="7.04" />
-		<param name="REG_RD" value="0.14" />
-		<param name="REG_WR" value="0.21" />
-		<param name="NON_REG_OPs" value="2.11" />
-		<param name="SP_ACC" value="2.38" />
-		<param name="SFU_ACC" value="0.51" />
-		<param name="FPU_ACC" value="0.64" />
-		<param name="MEM_RD" value="0.33" />
-		<param name="MEM_WR" value="0.40" />
-		<param name="MEM_PRE" value="0.11" />
-		<param name="L2_RH" value="13.79" />
-		<param name="L2_RM" value="35.18" />
-		<param name="L2_WH" value="43.07" />
-		<param name="L2_WM" value="28.72" />
-		<param name="NOC_A" value="305.48" />
-		<param name="PIPE_A" value="2.57" />
-		<param name="IDLE_CORE_N" value="1"/>
-		<param name="CONST_DYNAMICN" value="11" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="700"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="2"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="2"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="32"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="4"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="32"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="32"/>
-			<param name="simd_width" value="32"/>
-			<param name="collector_units" value="32"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="32768"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="2"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="15"/>	
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="0"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="700"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="2"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="6"/>
-			<param name="output_ports" value="6"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="0"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="40"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="6"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="3.8475e-8f"/>
-			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
-			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt
deleted file mode 100644
index 602daee..0000000
--- a/configs/3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 52;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config
deleted file mode 100644
index 28912a3..0000000
--- a/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config
+++ /dev/null
@@ -1,157 +0,0 @@
-# This config models the Pascal GP102 (NVIDIA TITAN X)
-# For more info about this card, see Nvidia White paper
-# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 61
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 12
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 61
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,4,1,1,6
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# SFU is 32-width in pascal, then dp units initiation is 1 cycle
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,8,4,4,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory
-# Pascal GP102 has 64KB L1 cache
-# The defulat is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_shmem_size 98304
--gpgpu_shmem_size_PrefL1 98304
--gpgpu_shmem_size_PrefShared 98304
--gmem_skip_L1D 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 32:32:32:32
-
-# 4 KB Inst.
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
-
-# enable operand collector 
-## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
--gpgpu_operand_collector_num_units_sp 20
--gpgpu_operand_collector_num_units_sfu 4
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
-# gpgpu_num_reg_banks should be increased to 32
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
-# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes 
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing from hynix H5GQ1H24AFR
-# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml b/configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
deleted file mode 100755
index 304e0fd..0000000
--- a/configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="16"/>
-		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="1"/>
-		<param name="core_tech_node" value="40"/><!-- nm -->
-		<param name="target_core_clockrate" value="700"/><!--MHz -->
-		<param name="temperature" value="380"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
-		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
-		<param name="TOT_INST" value="2.00" />
-		<param name="FP_INT" value="4.57" />
-		<param name="IC_H" value="2.14" />
-		<param name="IC_M" value="22.47" />
-		<param name="DC_RH" value="22.14" />
-		<param name="DC_RM" value="24.66" />
-		<param name="DC_WH" value="1.53" />
-		<param name="DC_WM" value="39.79" />
-		<param name="TC_H" value="10.21" />
-		<param name="TC_M" value="24.66" />
-		<param name="CC_H" value="11.07" />
-		<param name="CC_M" value="12.33" />
-		<param name="SHRD_ACC" value="7.04" />
-		<param name="REG_RD" value="0.14" />
-		<param name="REG_WR" value="0.21" />
-		<param name="NON_REG_OPs" value="2.11" />
-		<param name="SP_ACC" value="2.38" />
-		<param name="SFU_ACC" value="0.51" />
-		<param name="FPU_ACC" value="0.64" />
-		<param name="MEM_RD" value="0.33" />
-		<param name="MEM_WR" value="0.40" />
-		<param name="MEM_PRE" value="0.11" />
-		<param name="L2_RH" value="13.79" />
-		<param name="L2_RM" value="35.18" />
-		<param name="L2_WH" value="43.07" />
-		<param name="L2_WM" value="28.72" />
-		<param name="NOC_A" value="305.48" />
-		<param name="PIPE_A" value="2.57" />
-		<param name="IDLE_CORE_N" value="1"/>
-		<param name="CONST_DYNAMICN" value="11" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="700"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="2"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="2"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="32"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="4"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="32"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="32"/>
-			<param name="simd_width" value="32"/>
-			<param name="collector_units" value="32"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="32768"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="2"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="15"/>	
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="0"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="700"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="2"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="6"/>
-			<param name="output_ports" value="6"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="0"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="40"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="6"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="3.8475e-8f"/>
-			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
-			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
deleted file mode 100644
index fac792a..0000000
--- a/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
deleted file mode 100644
index aefb04a..0000000
--- a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
+++ /dev/null
@@ -1,165 +0,0 @@
-# This config models the Volta Titan X
-# For more info about this card:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 1
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA GP100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,1,4,4,1,9
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Volta GV100 has 64KB Shared memory
--gpgpu_cache:dl1  64:128:8,L:L:m:N:H,A:256:8,16:0
--gpgpu_cache:dl1PrefL1  64:128:16,L:L:m:N:H,A:256:8,16:0
--gpgpu_cache:dl1PrefShared  32:128:6,L:L:m:N:H,A:256:8,16:0
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 1
--gpgpu_shmem_size_PrefShared 98304
--gmem_skip_L1D 0
-
-# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
--gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
-
-# 128 KB Inst.
--gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4
-
-# enable operand collector
--gpgpu_operand_collector_num_units_sp 14
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_units_mem 10
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt b/configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt
deleted file mode 100644
index a11bd8e..0000000
--- a/configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//20*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we donot use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 26;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
diff --git a/configs/3.x-cfgs/TeslaC2050/gpgpusim.config b/configs/3.x-cfgs/TeslaC2050/gpgpusim.config
deleted file mode 100644
index 6ac2c12..0000000
--- a/configs/3.x-cfgs/TeslaC2050/gpgpusim.config
+++ /dev/null
@@ -1,133 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 20 
-
-# Using cuobjdump to extract ptx/SASS
-#-gpgpu_ptx_use_cuobjdump 1 # use default
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-
-# high level architecture configuration
--gpgpu_n_clusters 14
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 6
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Fermi clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
-# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
--gpgpu_clock_domains 575.0:575.0:575.0:750.0
-
-# shader core pipeline config
--gpgpu_shader_registers 32768
--gpgpu_occupancy_sm_number 20
-
-# This implies a maximum of 48 warps/SM
--gpgpu_shader_core_pipeline 1536:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,1,1,2,1,1,2
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,1,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,16,8,8,130
-
-
-# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
--gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
--gpgpu_shmem_size 49152
-
-# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
-#-gpgpu_shmem_size 16384
-
-# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
--gpgpu_cache:dl2_texture_only 0 
-
--gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_num_reg_banks 16
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
--gpgpu_max_insn_issue_per_warp 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 750MHz / 575MHz = 130
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 114  
-
-# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5 is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
-
-# GDDR5 timing from hynix H5GQ1H24AFR
-# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
deleted file mode 100644
index c399db9..0000000
--- a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 27;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 64;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 2.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
deleted file mode 100644
index 4096b09..0000000
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ /dev/null
@@ -1,153 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 20 
-
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 15
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 6
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Fermi clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
-# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
--gpgpu_clock_domains 700.0:700.0:700.0:924.0
-
-# shader core pipeline config
--gpgpu_shader_registers 32768
--gpgpu_occupancy_sm_number 20
-
-# This implies a maximum of 48 warps/SM
--gpgpu_shader_core_pipeline 1536:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-#For Fermi, DP unit =0, DP inst is executed on SFU
--gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 1
--gpgpu_num_dp_units 0
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,1,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,16,8,8,130
-
-
-# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
--gpgpu_cache:dl1  N:32:128:4,L:L:m:N:H,S:64:8,8
--gpgpu_shmem_size 49152
--icnt_flit_size 40
--gmem_skip_L1D 0
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 35
--smem_latency 26
--gpgpu_flush_l1_cache 1
-
-# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,S:64:8,8
-#-gpgpu_shmem_size 16384
-
-# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 S:64:128:8,L:B:m:L:L,A:256:4,4:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 1
--memory_partition_indexing 0
-
--gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4
--gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,T:128:4,128:2
--gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,S:2:32,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_num_reg_banks 16
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 20
-
--gpgpu_max_insn_issue_per_warp 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5 is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
-
-# GDDR5 timing from hynix H5GQ1H24AFR
-# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
-
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml b/configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
deleted file mode 100755
index 304e0fd..0000000
--- a/configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="16"/>
-		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="1"/>
-		<param name="core_tech_node" value="40"/><!-- nm -->
-		<param name="target_core_clockrate" value="700"/><!--MHz -->
-		<param name="temperature" value="380"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
-		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
-		<param name="TOT_INST" value="2.00" />
-		<param name="FP_INT" value="4.57" />
-		<param name="IC_H" value="2.14" />
-		<param name="IC_M" value="22.47" />
-		<param name="DC_RH" value="22.14" />
-		<param name="DC_RM" value="24.66" />
-		<param name="DC_WH" value="1.53" />
-		<param name="DC_WM" value="39.79" />
-		<param name="TC_H" value="10.21" />
-		<param name="TC_M" value="24.66" />
-		<param name="CC_H" value="11.07" />
-		<param name="CC_M" value="12.33" />
-		<param name="SHRD_ACC" value="7.04" />
-		<param name="REG_RD" value="0.14" />
-		<param name="REG_WR" value="0.21" />
-		<param name="NON_REG_OPs" value="2.11" />
-		<param name="SP_ACC" value="2.38" />
-		<param name="SFU_ACC" value="0.51" />
-		<param name="FPU_ACC" value="0.64" />
-		<param name="MEM_RD" value="0.33" />
-		<param name="MEM_WR" value="0.40" />
-		<param name="MEM_PRE" value="0.11" />
-		<param name="L2_RH" value="13.79" />
-		<param name="L2_RM" value="35.18" />
-		<param name="L2_WH" value="43.07" />
-		<param name="L2_WM" value="28.72" />
-		<param name="NOC_A" value="305.48" />
-		<param name="PIPE_A" value="2.57" />
-		<param name="IDLE_CORE_N" value="1"/>
-		<param name="CONST_DYNAMICN" value="11" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="700"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="2"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="2"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="32"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="4"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="32"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="32"/>
-			<param name="simd_width" value="32"/>
-			<param name="collector_units" value="32"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="32768"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="2"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="15"/>	
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="0"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="700"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="2"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="6"/>
-			<param name="output_ports" value="6"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="0"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="40"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="6"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="3.8475e-8f"/>
-			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
-			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt
deleted file mode 100644
index dec4789..0000000
--- a/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt
+++ /dev/null
@@ -1,73 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 52;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 64;
-input_buffer_size = 256;
-ejection_buffer_size = 64;
-boundary_buffer_size = 64;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 2.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
deleted file mode 100644
index 3842508..0000000
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ /dev/null
@@ -1,185 +0,0 @@
-# This config models the Pascal GP102 (NVIDIA TITAN X)
-# For more info about this card, see Nvidia White paper
-# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 61 
--gpgpu_ignore_resources_limitation 1
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
-# P102 has two semi-indp scheds per core, and two cores per cluster 
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 12
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
-
-# shader core pipeline config
--gpgpu_shader_registers 32768
--gpgpu_occupancy_sm_number 62
-
-# This implies a maximum of 32 warps/SM
--gpgpu_shader_core_pipeline 1024:32 
--gpgpu_shader_cta 16
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 4 SFU units
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 2
--gpgpu_num_dp_units 1
-
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,8,8,8,130
--ptx_opcode_initiation_sfu 4
--ptx_opcode_latency_sfu 8
-
-
-# latencies and cache configs are adopted from:
-# https://arxiv.org/pdf/1804.06826.pdf
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
-# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
-# The defulat is to disable the L1 cache, unless cache modifieres are used
--gpgpu_cache:dl1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 49152
--gpgpu_shmem_size_PrefL1 49152
--gpgpu_shmem_size_PrefShared 49152
-# By default, L1 cache is disabled in Pascal P102.
-# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
--gmem_skip_L1D 1
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 82
--smem_latency 24
--gpgpu_flush_l1_cache 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 32:32:32:32
--perf_sim_memcpy 1
-
-# 4 KB Inst.
--gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
-# 48 KB Tex 
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_operand_collector_num_in_ports_sfu 2
--gpgpu_operand_collector_num_out_ports_sfu 2
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-# Use Pascal Coalsce arhitetecture
--gpgpu_coalesce_arch 61
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 240
-
-# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
-# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes 
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
-                        CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
-
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal 102 has four schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 102
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
deleted file mode 100644
index 2f25889..0000000
--- a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ /dev/null
@@ -1,74 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 256;
-input_buffer_size = 256;
-ejection_buffer_size = 256;
-boundary_buffer_size = 256;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 2.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
deleted file mode 100644
index c8351da..0000000
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ /dev/null
@@ -1,191 +0,0 @@
-# This config models the Volta Titan X
-# For more info about this card:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 1 
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA GV100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:2000.0:1200.0:850.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 70
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
-
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 32KB DL1 and 96KB shared memory
-# In Volta, we assign the remaining shared memory to L1 cache 
-# if the assigned shd mem = 0, then L1 cache = 128KB
-# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
-# disable this mode in case of multi kernels/apps execution
--adpative_volta_cache_config 1
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 98304
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 28
--smem_latency 19
--gpgpu_flush_l1_cache 1
-
-# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
--gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 1
-
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal has two schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 100
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt b/configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt
new file mode 100644
index 0000000..7820e4e
--- /dev/null
+++ b/configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 27;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/GTX480/gpgpusim.config b/configs/deprecated-cfgs/GTX480/gpgpusim.config
new file mode 100644
index 0000000..ee90c12
--- /dev/null
+++ b/configs/deprecated-cfgs/GTX480/gpgpusim.config
@@ -0,0 +1,134 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 20 
+
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 15
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 6
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Fermi clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
+# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
+-gpgpu_clock_domains 700.0:700.0:700.0:924.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
+
+# This implies a maximum of 48 warps/SM
+-gpgpu_shader_core_pipeline 1536:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,1,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+
+# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+-gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_shmem_size 49152
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_shmem_size 16384
+
+# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
+-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 116
+
+# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml
new file mode 100755
index 0000000..304e0fd
--- /dev/null
+++ b/configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
new file mode 100644
index 0000000..069ca02
--- /dev/null
+++ b/configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 7;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config b/configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config
new file mode 100644
index 0000000..c675aab
--- /dev/null
+++ b/configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config
@@ -0,0 +1,131 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 52 
+
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 5
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 2
+-gpgpu_n_sub_partition_per_mchannel 1
+
+# Maxwell clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number.
+-gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 52
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
+-gpgpu_num_sp_units 8
+-gpgpu_num_sfu_units 32
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 6,12,13,13,210
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 6,12,6,6,374
+-ptx_opcode_initiation_fp 1,1,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
+-gmem_skip_L1D 1
+-gpgpu_shmem_size 65536
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_shmem_size 16384
+
+# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache
+-gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 150
+-dram_latency 130
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 300
+
+# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 32
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# Maxwell has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy.
+# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present.
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx750Ti.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
new file mode 100755
index 0000000..e2b2324
--- /dev/null
+++ b/configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
@@ -0,0 +1,539 @@
+<!-- THIS CONFIG IS CURRENTLY PRESENT ONLY AS A PLACEHOLDER. IT HAS NOT BEEN TESTED FOR ACCURACY VERSUS GTX750TI HARDWARE. ANY USE OF THIS CONFIG WILL LIKELY GIVE HIGHLY INACCURATE RESULTS. -->
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config b/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config
new file mode 100644
index 0000000..6f836ee
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config
@@ -0,0 +1,99 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 12
+
+# high level architecture configuration
+-gpgpu_n_clusters 8 
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 6 
+-gpgpu_clock_domains 337.5:600.0:600.0:800.0 
+
+# shader core pipeline config
+-gpgpu_shader_registers 16384
+-gpgpu_occupancy_sm_number 12
+
+-gpgpu_occupancy_sm_number 12
+#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though)
+-gpgpu_shader_core_pipeline 768:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 1,1,1,1,1,1,1
+-gpgpu_num_sp_units 1
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 1,1,19,25,145
+-ptx_opcode_initiation_int 1,1,4,4,32
+-ptx_opcode_latency_fp 1,1,1,1,30
+-ptx_opcode_initiation_fp 1,1,1,1,5
+-ptx_opcode_latency_dp 8,8,8,8,335
+-ptx_opcode_initiation_dp 8,8,8,8,130
+
+# memory stage behaviour
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
+-gpgpu_cache:dl2_texture_only 1
+
+# TLB parameters
+#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8
+#-gpgpu_tlbl2_latency 45
+
+
+-gpgpu_shmem_warp_parts 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file icnt_config_islip.icnt 
+
+# dram scheduler config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (30 core cycles).  I.e. 
+#   Total buffer space required = 30 x 800MHz / 337.5MHz = 71
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 55
+
+# dram model config
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4 
+-gpgpu_dram_burst_length 4
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
+# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
+# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
+-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+
+
+
+# Using cuobjdump to extract ptx/SASS
+-gpgpu_ptx_use_cuobjdump 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+
+-visualizer_enabled 0
+-power_trace_enabled 0
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_quadrofx5600.xml 
+
+-steady_power_levels_enabled 1
+-steady_state_definition 8,4
diff --git a/configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
new file mode 100644
index 0000000..2c5a6fc
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="0"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="2"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="0"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="0"/>
+		<param name="core_tech_node" value="65"/><!-- nm -->
+		<param name="target_core_clockrate" value="650"/><!--MHz -->
+		<param name="temperature" value="400"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.54"/><!-- idle core power for GTX479 -->
+		<param name="TOT_INST" value="2" />
+		<param name="FP_INT" value="5" />
+		<param name="IC_H" value="10" />
+		<param name="IC_M" value="10" />
+		<param name="DC_RH" value="10" />
+		<param name="DC_RM" value="10" />
+		<param name="DC_WH" value="10" />
+		<param name="DC_WM" value="10" />
+		<param name="TC_H" value="20" />
+		<param name="TC_M" value="20" />
+		<param name="CC_H" value="10" />
+		<param name="CC_M" value="10" />
+		<param name="SHRD_ACC" value="20" />
+		<param name="REG_RD" value="0.25" />
+		<param name="REG_WR" value="0.4" />
+		<param name="NON_REG_OPs" value="0.4" />
+		<param name="SP_ACC" value="0.6" />
+		<param name="SFU_ACC" value="0.7" />
+		<param name="FPU_ACC" value="0.25" />
+		<param name="MEM_RD" value="0.3" />
+		<param name="MEM_WR" value="0.4" />
+		<param name="MEM_PRE" value="0.7" />
+		<param name="L2_RH" value="1" />
+		<param name="L2_RM" value="1" />
+		<param name="L2_WH" value="1" />
+		<param name="L2_WM" value="1" />
+		<param name="NOC_A" value="80" />
+		<param name="PIPE_A" value="0.8" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="9" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="650"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="1"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="1"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="1"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="1"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="8"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="16"/>
+			<param name="simd_width" value="8"/>
+			<param name="collector_units" value="16"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="8192"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="1"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="0.4"/>
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="1"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="1"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="65536,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="16384,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1300"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1300"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="100"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="786432,64,16,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1300"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="650"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="4"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="7"/>
+			<param name="output_ports" value="7"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="360000"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="65"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="8"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="800"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="9600"/><!--MB/S  Syed: Quadro FX 5800 has 76.8GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="8"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="1.53846154e-8f"/>
+			<param name="dram_rd_coeff" value="3.07692308e-8f"/>
+			<param name="dram_wr_coeff" value="1.30769231e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt b/configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt
new file mode 100644
index 0000000..de3bcc8
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt
@@ -0,0 +1,70 @@
+//14*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we donot use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 14;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt b/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt
new file mode 100644
index 0000000..cfe9cac
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt
@@ -0,0 +1,69 @@
+//18*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we donot use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 18;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config b/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config
new file mode 100644
index 0000000..fef1110
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config
@@ -0,0 +1,88 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 13
+
+# high level architecture configuration
+-gpgpu_n_clusters 10 
+-gpgpu_n_cores_per_cluster 3
+-gpgpu_n_mem 8 
+-gpgpu_clock_domains 325.0:650.0:650.0:800.0 
+
+# shader core pipeline config
+-gpgpu_shader_registers 16384
+-gpgpu_occupancy_sm_number 13
+
+-gpgpu_shader_core_pipeline 1024:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 1,1,1,1,1,1,1
+-gpgpu_num_sp_units 1
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 1,1,19,25,145
+-ptx_opcode_initiation_int 1,1,4,4,32
+-ptx_opcode_latency_fp 1,1,1,1,30
+-ptx_opcode_initiation_fp 1,1,1,1,5
+-ptx_opcode_latency_dp 8,8,8,8,335
+-ptx_opcode_initiation_dp 8,8,8,8,130
+
+# memory stage behaviour
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
+-gpgpu_cache:dl2_texture_only 1
+
+-gpgpu_shmem_warp_parts 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_quadro_islip.icnt
+
+# dram scheduler config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (30 core cycles).  I.e. 
+#   Total buffer space required = 30 x 800MHz / 325MHz = 74
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 58
+
+# dram model config
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4 
+-gpgpu_dram_burst_length 4
+-dram_data_command_freq_ratio 2  # GDDR3 is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
+# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
+-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+
+-visualizer_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt
new file mode 100644
index 0000000..2a69ddd
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 50;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
new file mode 100644
index 0000000..fb044c6
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
@@ -0,0 +1,150 @@
+# This config models the Pascal GP102 (GeForceGTX 1080Ti)
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 60
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 11
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 60
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# SFU is 32-width in pascal, then dp units initiation is 1 cycle
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 1,2,1,1,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory
+# Pascal GP102 has 64KB L1 cache
+# The default is to disable the L1 cache, unless cache modifieres is used
+-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,8
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
+-gpgpu_cache:dl2_texture_only 0 
+
+# 4 KB Inst.
+-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+
+# enable operand collector 
+## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
+-gpgpu_operand_collector_num_units_sp 20
+-gpgpu_operand_collector_num_units_sfu 4
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+# gpgpu_num_reg_banks should be increased to 32, but it gives an error!
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits)
+# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing from hynix H5GQ1H24AFR
+# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
+
+# Pascal has four schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml b/configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
new file mode 100755
index 0000000..02619ff
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="28"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="23"/><!-- nm -->
+		<param name="target_core_clockrate" value="1481"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="10" />
+		<param name="FP_INT" value="10" />
+		<param name="IC_H" value="0.001" />
+		<param name="IC_M" value="10" />
+		<param name="DC_RH" value="1" />
+		<param name="DC_RM" value="1" />
+		<param name="DC_WH" value="1" />
+		<param name="DC_WM" value="1" />
+		<param name="TC_H" value="0.001" />
+		<param name="TC_M" value="10" />
+		<param name="CC_H" value="4.5071" />
+		<param name="CC_M" value="10" />
+		<param name="SHRD_ACC" value="10" />
+		<param name="REG_RD" value="1.6294" />
+		<param name="REG_WR" value="0.5031" />
+		<param name="NON_REG_OPs" value="0.01" />
+		<param name="SP_ACC" value="10" />
+		<param name="SFU_ACC" value="0.0082" />
+		<param name="FPU_ACC" value="0.4126" />
+		<param name="MEM_RD" value="0.1234" />
+		<param name="MEM_WR" value="0.001" />
+		<param name="MEM_PRE" value="0.001" />
+		<param name="L2_RH" value="100" />
+		<param name="L2_RM" value="100" />
+		<param name="L2_WH" value="100" />
+		<param name="L2_WM" value="42.6966" />
+		<param name="NOC_A" value="100" />
+		<param name="PIPE_A" value="44.8085" />
+		<param name="IDLE_CORE_N" value="2.0382"/>
+		<param name="CONST_DYNAMICN" value="5.0005" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="1481"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="65536"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="2962"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="23"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt
new file mode 100644
index 0000000..d26c8d9
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 60;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/SM6_P100/gpgpusim.config b/configs/deprecated-cfgs/SM6_P100/gpgpusim.config
new file mode 100644
index 0000000..a5e6736
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_P100/gpgpusim.config
@@ -0,0 +1,156 @@
+# This config models the Pascal GP100
+# For more info about this card, see Nvidia White paper
+# https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 60
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 32
+-gpgpu_n_sub_partition_per_mchannel 1
+
+# Pscal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA GP100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Nvidia_Tesla
+-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 2,2,1,2,2,1,4
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# SFU is 32-width in pascal, then dp units initiation is 1 cycle
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 2,2,2,2,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP100 has 64KB Shared memory
+# Pascal GP100 has 48KB L1 cache
+-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_shmem_size 65536
+-gpgpu_shmem_size_PrefL1 65536
+-gpgpu_shmem_size_PrefShared 65536
+-gmem_skip_L1D 0
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
+
+# 4 KB Inst.
+-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+
+# enable operand collector
+-gpgpu_operand_collector_num_units_sp 14
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_units_mem 10
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml
new file mode 100755
index 0000000..304e0fd
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt
new file mode 100644
index 0000000..602daee
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config b/configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config
new file mode 100644
index 0000000..28912a3
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config
@@ -0,0 +1,157 @@
+# This config models the Pascal GP102 (NVIDIA TITAN X)
+# For more info about this card, see Nvidia White paper
+# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 61
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 61
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# SFU is 32-width in pascal, then dp units initiation is 1 cycle
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,8,4,4,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory
+# Pascal GP102 has 64KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres is used
+-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_shmem_size 98304
+-gpgpu_shmem_size_PrefL1 98304
+-gpgpu_shmem_size_PrefShared 98304
+-gmem_skip_L1D 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
+
+# 4 KB Inst.
+-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+
+# enable operand collector 
+## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
+-gpgpu_operand_collector_num_units_sp 20
+-gpgpu_operand_collector_num_units_sfu 4
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+# gpgpu_num_reg_banks should be increased to 32
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
+# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing from hynix H5GQ1H24AFR
+# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
new file mode 100755
index 0000000..304e0fd
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt
new file mode 100644
index 0000000..fac792a
--- /dev/null
+++ b/configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config b/configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config
new file mode 100644
index 0000000..aefb04a
--- /dev/null
+++ b/configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config
@@ -0,0 +1,165 @@
+# This config models the Volta Titan X
+# For more info about this card:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 24
+-gpgpu_n_sub_partition_per_mchannel 1
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA GP100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,1,4,4,1,9
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Volta GV100 has 64KB Shared memory
+-gpgpu_cache:dl1  64:128:8,L:L:m:N:H,A:256:8,16:0
+-gpgpu_cache:dl1PrefL1  64:128:16,L:L:m:N:H,A:256:8,16:0
+-gpgpu_cache:dl1PrefShared  32:128:6,L:L:m:N:H,A:256:8,16:0
+-gpgpu_shmem_size 65536
+-gpgpu_shmem_size_PrefL1 1
+-gpgpu_shmem_size_PrefShared 98304
+-gmem_skip_L1D 0
+
+# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
+-gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+
+# 128 KB Inst.
+-gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4
+
+# enable operand collector
+-gpgpu_operand_collector_num_units_sp 14
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_units_mem 10
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt b/configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt
new file mode 100644
index 0000000..a11bd8e
--- /dev/null
+++ b/configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//20*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we donot use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 26;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
diff --git a/configs/deprecated-cfgs/TeslaC2050/gpgpusim.config b/configs/deprecated-cfgs/TeslaC2050/gpgpusim.config
new file mode 100644
index 0000000..6ac2c12
--- /dev/null
+++ b/configs/deprecated-cfgs/TeslaC2050/gpgpusim.config
@@ -0,0 +1,133 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 20 
+
+# Using cuobjdump to extract ptx/SASS
+#-gpgpu_ptx_use_cuobjdump 1 # use default
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+
+# high level architecture configuration
+-gpgpu_n_clusters 14
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 6
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Fermi clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
+# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
+-gpgpu_clock_domains 575.0:575.0:575.0:750.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
+
+# This implies a maximum of 48 warps/SM
+-gpgpu_shader_core_pipeline 1536:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,1,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+
+# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
+-gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_shmem_size 49152
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_shmem_size 16384
+
+# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
+-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 750MHz / 575MHz = 130
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 114  
+
+# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt b/configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt
new file mode 100644
index 0000000..c399db9
--- /dev/null
+++ b/configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 27;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
new file mode 100644
index 0000000..4096b09
--- /dev/null
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -0,0 +1,153 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 20 
+
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 15
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 6
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Fermi clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
+# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
+-gpgpu_clock_domains 700.0:700.0:700.0:924.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
+
+# This implies a maximum of 48 warps/SM
+-gpgpu_shader_core_pipeline 1536:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+#For Fermi, DP unit =0, DP inst is executed on SFU
+-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+-gpgpu_num_dp_units 0
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,1,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+
+# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+-gpgpu_cache:dl1  N:32:128:4,L:L:m:N:H,S:64:8,8
+-gpgpu_shmem_size 49152
+-icnt_flit_size 40
+-gmem_skip_L1D 0
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 35
+-smem_latency 26
+-gpgpu_flush_l1_cache 1
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,S:64:8,8
+#-gpgpu_shmem_size 16384
+
+# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
+-gpgpu_cache:dl2 S:64:128:8,L:B:m:L:L,A:256:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 1
+-memory_partition_indexing 0
+
+-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4
+-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,T:128:4,128:2
+-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,S:2:32,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 20
+
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml b/configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
new file mode 100755
index 0000000..304e0fd
--- /dev/null
+++ b/configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
new file mode 100644
index 0000000..dec4789
--- /dev/null
+++ b/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 64;
+input_buffer_size = 256;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
new file mode 100644
index 0000000..3842508
--- /dev/null
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -0,0 +1,185 @@
+# This config models the Pascal GP102 (NVIDIA TITAN X)
+# For more info about this card, see Nvidia White paper
+# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 61 
+-gpgpu_ignore_resources_limitation 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+# P102 has two semi-indp scheds per core, and two cores per cluster 
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 62
+
+# This implies a maximum of 32 warps/SM
+-gpgpu_shader_core_pipeline 1024:32 
+-gpgpu_shader_cta 16
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 2
+-gpgpu_num_dp_units 1
+
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,8,8,8,130
+-ptx_opcode_initiation_sfu 4
+-ptx_opcode_latency_sfu 8
+
+
+# latencies and cache configs are adopted from:
+# https://arxiv.org/pdf/1804.06826.pdf
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
+# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres are used
+-gpgpu_cache:dl1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 49152
+-gpgpu_shmem_size_PrefL1 49152
+-gpgpu_shmem_size_PrefShared 49152
+# By default, L1 cache is disabled in Pascal P102.
+# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
+-gmem_skip_L1D 1
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 82
+-smem_latency 24
+-gpgpu_flush_l1_cache 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
+-perf_sim_memcpy 1
+
+# 4 KB Inst.
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+# 48 KB Tex 
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_operand_collector_num_in_ports_sfu 2
+-gpgpu_operand_collector_num_out_ports_sfu 2
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+# Use Pascal Coalsce arhitetecture
+-gpgpu_coalesce_arch 61
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 240
+
+# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
+# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
+                        CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
+
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal 102 has four schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 102
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
new file mode 100644
index 0000000..2f25889
--- /dev/null
+++ b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
new file mode 100644
index 0000000..c8351da
--- /dev/null
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -0,0 +1,191 @@
+# This config models the Volta Titan X
+# For more info about this card:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 24
+-gpgpu_n_sub_partition_per_mchannel 1 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA GV100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1200.0:2000.0:1200.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 70
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+-gpgpu_flush_l1_cache 1
+
+# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
+-gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 1
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 100
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
-- 
cgit v1.3


From f06a527258b4a6634f8f148536bb86635b058d55 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Tue, 30 Oct 2018 13:03:50 -0400
Subject: updating the TITANV config

---
 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config        | 11 ++-----
 .../4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt    |  2 +-
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config        | 38 ++++++++++------------
 src/gpgpu-sim/gpu-sim.cc                           | 16 ++++-----
 4 files changed, 29 insertions(+), 38 deletions(-)

(limited to 'configs')

diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 3842508..ed35531 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -86,6 +86,7 @@
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 32:32:32:32
 -perf_sim_memcpy 1
+-memory_partition_indexing 0
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
@@ -131,13 +132,8 @@
 
 # dram model config
 -gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
 -gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 240
+-gpgpu_dram_return_queue_size 64
 
 # for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
 # 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
@@ -149,7 +145,7 @@
 -gpgpu_mem_address_mask 1
 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
 
-# Use the same GDDR5 timing
+# Use the same GDDR5 timing, scaled to 2500MHZ
 -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
                         CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
 
@@ -176,7 +172,6 @@
 
 # power model configs, disable it untill we create a real energy model for Pascal 102
 -power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
 
 # tracing functionality
 #-trace_enabled 1
diff --git a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
index 2f25889..615d0a9 100644
--- a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
@@ -7,7 +7,7 @@ network_count = 2;
 
 // Topology
 topology = fly;
-k = 64;
+k = 88;
 n = 1;
 
 // Routing
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index c8351da..03ef5b9 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -1,5 +1,5 @@
 # This config models the Volta Titan X
-# For more info about this card:
+# For more info about volta architecture:
 # http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
 # https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
 # http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
@@ -21,15 +21,15 @@
 -gpgpu_n_clusters 40
 -gpgpu_n_cores_per_cluster 2
 -gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 1 
+-gpgpu_n_sub_partition_per_mchannel 2 
 
 # volta clock domains
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA GV100  clock domains are adopted from 
+# Volta NVIDIA V100  clock domains are adopted from 
 # https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:2000.0:1200.0:850.0
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
 # boost mode
-# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
+# -gpgpu_clock_domains 1455.0:1455.0:1455.0:850.0
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
@@ -44,7 +44,7 @@
 # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
 ## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,12
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 4
 -gpgpu_num_dp_units 4
@@ -81,11 +81,12 @@
 -smem_latency 19
 -gpgpu_flush_l1_cache 1
 
-# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
--gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
+# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
+-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0
 -gpgpu_dram_partition_queues 64:64:64:64
 -perf_sim_memcpy 1
+-memory_partition_indexing 0
 
 # 128 KB Inst.
 -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
@@ -108,7 +109,8 @@
 -gpgpu_operand_collector_num_out_ports_mem 1
 -gpgpu_operand_collector_num_in_ports_dp 1
 -gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
+# two banks per scheduler
+-gpgpu_num_reg_banks 8
 
 # shared memory bankconflict detection 
 -gpgpu_shmem_num_banks 32
@@ -130,21 +132,16 @@
 
 # dram model config
 -gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
 -gpgpu_frfcfs_dram_sched_queue_size 64
 -gpgpu_dram_return_queue_size 192
 
-# for HBM, 32 channles, each (128 bits) 16 bytes width
+# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
 -gpgpu_n_mem_per_ctrlr 1
 -gpgpu_dram_buswidth 16
 -gpgpu_dram_burst_length 2
 -dram_data_command_freq_ratio 2  # HBM is DDR
 -gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
 
 # HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
 # Timing for 1 GHZ
@@ -152,9 +149,9 @@
 #-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
 #                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
 
-# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
 
 # HBM has dual bus interface, in which it can issue two col and row commands at a time
 -dual_bus_interface 1
@@ -182,7 +179,6 @@
 
 # power model configs, disable it untill we create a real energy model for Pascal 100
 -power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
 
 # tracing functionality
 #-trace_enabled 1
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index d02e8e1..8bbadf5 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -1043,18 +1043,18 @@ void gpgpu_sim::gpu_print_stat()
    printf("gpu_stall_dramfull = %d\n", gpu_stall_dramfull);
    printf("gpu_stall_icnt2sh    = %d\n", gpu_stall_icnt2sh );
 
-   printf("partiton_reqs_in_parallel = %lld\n", partiton_reqs_in_parallel);
-   printf("partiton_reqs_in_parallel_total    = %lld\n", partiton_reqs_in_parallel_total );
+   //printf("partiton_reqs_in_parallel = %lld\n", partiton_reqs_in_parallel);
+   //printf("partiton_reqs_in_parallel_total    = %lld\n", partiton_reqs_in_parallel_total );
    printf("partiton_level_parallism = %12.4f\n", (float)partiton_reqs_in_parallel / gpu_sim_cycle);
    printf("partiton_level_parallism_total  = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) );
-   printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util);
-   printf("partiton_reqs_in_parallel_util_total    = %lld\n", partiton_reqs_in_parallel_util_total );
-   printf("gpu_sim_cycle_parition_util = %lld\n", gpu_sim_cycle_parition_util);
-   printf("gpu_tot_sim_cycle_parition_util    = %lld\n", gpu_tot_sim_cycle_parition_util );
+   //printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util);
+   //printf("partiton_reqs_in_parallel_util_total    = %lld\n", partiton_reqs_in_parallel_util_total );
+   //printf("gpu_sim_cycle_parition_util = %lld\n", gpu_sim_cycle_parition_util);
+   // printf("gpu_tot_sim_cycle_parition_util    = %lld\n", gpu_tot_sim_cycle_parition_util );
    printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle_parition_util);
    printf("partiton_level_parallism_util_total  = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_sim_cycle_parition_util+gpu_tot_sim_cycle_parition_util) );
-   printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel);
-   printf("partiton_replys_in_parallel_total    = %lld\n", partiton_replys_in_parallel_total );
+   //printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel);
+   //printf("partiton_replys_in_parallel_total    = %lld\n", partiton_replys_in_parallel_total );
    printf("L2_BW  = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000);
    printf("L2_BW_total  = %12.4f GB/Sec\n", ((float)((partiton_replys_in_parallel+partiton_replys_in_parallel_total) * 32) / ((gpu_tot_sim_cycle+gpu_sim_cycle) * m_config.icnt_period)) / 1000000000 );
 
-- 
cgit v1.3


From eae030c9d1d607d1c14e4ade99cb5caea6403efd Mon Sep 17 00:00:00 2001
From: aamir <araihan@ece.ubc.ca>
Date: Sat, 3 Nov 2018 17:03:58 -0700
Subject: merged with memory subsytem. Regression is passing but tensorcore
 kernel is stuck in deadlock

---
 .gitignore                                         |   1 +
 .travis.yml                                        |  31 +-
 CHANGES                                            |  30 +
 Jenkinsfile                                        | 126 ++++
 README                                             |  10 +-
 aerialvision/organizedata.py                       |   2 +-
 configs/GTX480/config_fermi_islip.icnt             |  70 --
 configs/GTX480/gpgpusim.config                     | 134 ----
 configs/GTX480/gpuwattch_gtx480.xml                | 538 --------------
 configs/GeForceGTX1080Ti/config_fermi_islip.icnt   |  70 --
 configs/GeForceGTX1080Ti/gpgpusim.config           | 150 ----
 configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml   | 538 --------------
 configs/GeForceGTX750Ti/config_fermi_islip.icnt    |  70 --
 configs/GeForceGTX750Ti/gpgpusim.config            | 131 ----
 configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml     | 539 --------------
 configs/Pascal_TITANX/config_fermi_islip.icnt      |  70 --
 configs/Pascal_TITANX/gpgpusim.config              | 156 ----
 configs/QuadroFX5600/gpgpusim.config               |  99 ---
 configs/QuadroFX5600/gpuwattch_quadrofx5600.xml    | 538 --------------
 configs/QuadroFX5600/icnt_config_islip.icnt        |  70 --
 configs/QuadroFX5800/config_quadro_islip.icnt      |  69 --
 configs/QuadroFX5800/gpgpusim.config               |  88 ---
 configs/TeslaC2050/config_fermi_islip.icnt         |  70 --
 configs/TeslaC2050/gpgpusim.config                 | 133 ----
 .../deprecated-cfgs/GTX480/config_fermi_islip.icnt |  70 ++
 configs/deprecated-cfgs/GTX480/gpgpusim.config     | 134 ++++
 .../deprecated-cfgs/GTX480/gpuwattch_gtx480.xml    | 538 ++++++++++++++
 .../GeForceGTX750Ti/config_fermi_islip.icnt        |  70 ++
 .../GeForceGTX750Ti/gpgpusim.config                | 131 ++++
 .../GeForceGTX750Ti/gpuwattch_gtx750Ti.xml         | 539 ++++++++++++++
 .../deprecated-cfgs/QuadroFX5600/gpgpusim.config   |  99 +++
 .../QuadroFX5600/gpuwattch_quadrofx5600.xml        | 538 ++++++++++++++
 .../QuadroFX5600/icnt_config_islip.icnt            |  70 ++
 .../QuadroFX5800/config_quadro_islip.icnt          |  69 ++
 .../deprecated-cfgs/QuadroFX5800/gpgpusim.config   |  88 +++
 .../SM6_GTX1080/config_fermi_islip.icnt            |  70 ++
 .../deprecated-cfgs/SM6_GTX1080/gpgpusim.config    | 150 ++++
 .../SM6_GTX1080/gpuwattch_gtx1080Ti.xml            | 538 ++++++++++++++
 .../SM6_P100/config_fermi_islip.icnt               |  70 ++
 configs/deprecated-cfgs/SM6_P100/gpgpusim.config   | 156 ++++
 .../deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml  | 538 ++++++++++++++
 .../SM6_TITANX/config_fermi_islip.icnt             |  70 ++
 configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config | 157 +++++
 .../SM6_TITANX/gpuwattch_gtx480.xml                | 538 ++++++++++++++
 .../SM7_TITANV/config_fermi_islip.icnt             |  70 ++
 configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config | 165 +++++
 .../TeslaC2050/config_fermi_islip.icnt             |  70 ++
 configs/deprecated-cfgs/TeslaC2050/gpgpusim.config | 133 ++++
 .../tested-cfgs/SM2_GTX480/config_fermi_islip.icnt |  70 ++
 configs/tested-cfgs/SM2_GTX480/gpgpusim.config     | 153 ++++
 .../tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml    | 538 ++++++++++++++
 .../tested-cfgs/SM6_TITANX/config_fermi_islip.icnt |  73 ++
 configs/tested-cfgs/SM6_TITANX/gpgpusim.config     | 185 +++++
 .../tested-cfgs/SM7_TITANV/config_fermi_islip.icnt |  74 ++
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config     | 191 +++++
 cuobjdump_to_ptxplus/ptx_parser.h                  |   4 +
 libcuda/cuda_runtime_api.cc                        |  49 +-
 nightly.jenkinsfile                                |  75 ++
 setup_environment                                  |   2 +-
 src/abstract_hardware_model.cc                     |  49 +-
 src/abstract_hardware_model.h                      |  33 +-
 src/cuda-sim/cuda-sim.cc                           |  47 +-
 src/cuda-sim/instructions.cc                       |   1 +
 src/cuda-sim/ptx.y                                 |   3 +-
 src/cuda-sim/ptx_ir.cc                             |   7 +-
 src/cuda-sim/ptx_ir.h                              |   7 +
 src/cuda-sim/ptx_parser.cc                         |   4 +
 src/cuda-sim/ptx_parser.h                          |   1 +
 src/gpgpu-sim/addrdec.cc                           |  71 ++
 src/gpgpu-sim/addrdec.h                            |   9 +
 src/gpgpu-sim/delayqueue.h                         |   1 +
 src/gpgpu-sim/dram.cc                              | 637 +++++++++++++----
 src/gpgpu-sim/dram.h                               |  77 +-
 src/gpgpu-sim/dram_sched.cc                        | 121 +++-
 src/gpgpu-sim/dram_sched.h                         |  12 +
 src/gpgpu-sim/gpu-cache.cc                         | 782 +++++++++++++++++----
 src/gpgpu-sim/gpu-cache.h                          | 644 +++++++++++++++--
 src/gpgpu-sim/gpu-sim.cc                           | 125 +++-
 src/gpgpu-sim/gpu-sim.h                            |  57 +-
 src/gpgpu-sim/l2cache.cc                           | 166 ++++-
 src/gpgpu-sim/l2cache.h                            |  18 +
 src/gpgpu-sim/l2cache_trace.h                      |  16 +
 src/gpgpu-sim/mem_fetch.cc                         |   7 +-
 src/gpgpu-sim/mem_fetch.h                          |  13 +-
 src/gpgpu-sim/mem_latency_stat.cc                  |  19 +-
 src/gpgpu-sim/mem_latency_stat.h                   |   4 +
 src/gpgpu-sim/shader.cc                            | 431 ++++++++++--
 src/gpgpu-sim/shader.h                             |  93 ++-
 src/gpgpusim_entrypoint.cc                         |   1 +
 src/gpuwattch/makefile                             |   4 +-
 src/intersim2/Makefile                             |   2 +-
 src/intersim2/interconnect_interface.cpp           |   9 +-
 src/trace_streams.tup                              |   2 +
 version                                            |   2 +-
 94 files changed, 9589 insertions(+), 4104 deletions(-)
 create mode 100644 Jenkinsfile
 delete mode 100644 configs/GTX480/config_fermi_islip.icnt
 delete mode 100644 configs/GTX480/gpgpusim.config
 delete mode 100755 configs/GTX480/gpuwattch_gtx480.xml
 delete mode 100644 configs/GeForceGTX1080Ti/config_fermi_islip.icnt
 delete mode 100644 configs/GeForceGTX1080Ti/gpgpusim.config
 delete mode 100755 configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml
 delete mode 100644 configs/GeForceGTX750Ti/config_fermi_islip.icnt
 delete mode 100644 configs/GeForceGTX750Ti/gpgpusim.config
 delete mode 100755 configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
 delete mode 100644 configs/Pascal_TITANX/config_fermi_islip.icnt
 delete mode 100644 configs/Pascal_TITANX/gpgpusim.config
 delete mode 100644 configs/QuadroFX5600/gpgpusim.config
 delete mode 100644 configs/QuadroFX5600/gpuwattch_quadrofx5600.xml
 delete mode 100644 configs/QuadroFX5600/icnt_config_islip.icnt
 delete mode 100644 configs/QuadroFX5800/config_quadro_islip.icnt
 delete mode 100644 configs/QuadroFX5800/gpgpusim.config
 delete mode 100644 configs/TeslaC2050/config_fermi_islip.icnt
 delete mode 100644 configs/TeslaC2050/gpgpusim.config
 create mode 100644 configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/GTX480/gpgpusim.config
 create mode 100755 configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml
 create mode 100644 configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config
 create mode 100755 configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
 create mode 100644 configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config
 create mode 100644 configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
 create mode 100644 configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt
 create mode 100644 configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt
 create mode 100644 configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config
 create mode 100644 configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
 create mode 100755 configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
 create mode 100644 configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/SM6_P100/gpgpusim.config
 create mode 100755 configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml
 create mode 100644 configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config
 create mode 100755 configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
 create mode 100644 configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config
 create mode 100644 configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt
 create mode 100644 configs/deprecated-cfgs/TeslaC2050/gpgpusim.config
 create mode 100644 configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt
 create mode 100644 configs/tested-cfgs/SM2_GTX480/gpgpusim.config
 create mode 100755 configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
 create mode 100644 configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
 create mode 100644 configs/tested-cfgs/SM6_TITANX/gpgpusim.config
 create mode 100644 configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
 create mode 100644 configs/tested-cfgs/SM7_TITANV/gpgpusim.config
 create mode 100644 nightly.jenkinsfile

(limited to 'configs')

diff --git a/.gitignore b/.gitignore
index d21cc8f..6c6ed5f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -32,4 +32,5 @@ cuobjdump_to_ptxplus/sass_parser.hh
 cuobjdump_to_ptxplus/sass_parser.output
 
 build/*
+tags
 *.swp
diff --git a/.travis.yml b/.travis.yml
index 7a12a1c..b38f468 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -1,7 +1,7 @@
 sudo: required
 
 before_install:
-    - docker pull tgrogers/gpgpu-sim_regress:latest
+    - docker pull tgrogers/gpgpu-sim_regress:volta_update
 
 language: cpp
 
@@ -10,34 +10,13 @@ matrix:
   include:
     - services: docker
       env:
-        - CONFIG=configs.gtx480.yml
+        - CONFIG=GTX480
         - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/
         - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/
-# This config is just taking far too long...
-#    - services: docker
-#      env:
-#       - CONFIG=configs.gtx750ti.yml
-#       - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/
-#        - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/
     - services: docker
       env:
-        - CONFIG=configs.quadro5600.yml
-        - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/
-        - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/
-    - services: docker
-      env:
-        - CONFIG=configs.quadro5800.yml
-        - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/
-        - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/
-    - services: docker
-      env:
-        - CONFIG=configs.teslac2050.yml
-        - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/
-        - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/
-    - services: docker
-      env:
-        - CONFIG=configs.gtx1080ti.yml
-        - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/
+        - CONFIG=TITANV
+        - CUDA_INSTALL_PATH=/usr/local/cuda-9.1/
         - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-9.1/
 
-script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'export CUDA_INSTALL_PATH=$CUDA_INSTALL_PATH && export PTXAS_CUDA_INSTALL_PATH=$PTXAS_CUDA_INSTALL_PATH && source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'"
+script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:volta_update /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'export CUDA_INSTALL_PATH=$CUDA_INSTALL_PATH && export PTXAS_CUDA_INSTALL_PATH=$PTXAS_CUDA_INSTALL_PATH && source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -C $CONFIG -B rodinia_2.0-ft -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'"
diff --git a/CHANGES b/CHANGES
index dbf5b39..60be885 100644
--- a/CHANGES
+++ b/CHANGES
@@ -1,4 +1,34 @@
 LOG:
+Version 4.0.0 (development branch) versus 3.2.3
+-Front-End:
+1- Support .nc cache modifier and __ldg function to access the read-only L1D cache
+2- Partially-support some SASS_60 in the PTXP_PLUS (not completed yet)
+-GPU Core:
+1- Fermi/Pascal coalescer: coalescing on 32-bytes sectors.
+2- Adding separate dp unit pipeline.
+3- diff dual issue: allow scheduler to issue diff insts at a time
+4- Fair memory issue from multiple schedulers.
+-Cache System:
+1- Sector L1/L2 cache
+2- Fetch-on-write and lazy-fetch-on-read write allocation policy.
+3- Improving the L1 cache throughput (streaming L1 cache)
+4- Performance model for CUDA memory copy.
+5- Support memory partition indexing to reduce partition camping (POLY, XOR and PAE (ISCA’18)  Indexing)
+6- Adaptive cache configuration
+-Memory:
+1- Performance Model for HBM (mainly the dual-bus interface)
+2- Separate Read/Write buffers.
+3- Advanced bank indexing function.
+-Statistics:
+1- Adding more detailed cache statistics to define and analyze cache bottlenecks.
+2- Adding more detailed memory statistics (BLP, RBL, etc) to define and analyze memory bottlenecks.
+3- Addig new system stats: gpu occupancy, L2BW, etc
+-Configs:
+Adding the Pascal and Volta config files that has been correlated against real hardware.
+See the correlation website here: 
+https://engineering.purdue.edu/tgrogers/group/correlator.html
+
+
 Version 3.2.3+edits (development branch) versus 3.2.3
 - Support for running regression tests using Travis
 - Support added for CUDA dynamic parallelism (courtesy of Jin Wang from Georgia Tech)
diff --git a/Jenkinsfile b/Jenkinsfile
new file mode 100644
index 0000000..1969aea
--- /dev/null
+++ b/Jenkinsfile
@@ -0,0 +1,126 @@
+pipeline {
+    agent {
+        label "purdue-cluster"
+    }
+
+    options {
+        disableConcurrentBuilds()
+    }
+
+    stages {
+        stage('simulator-build') {
+            steps {
+                parallel "4.2": {
+                    sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\
+                    source `pwd`/setup_environment &&\
+                    make -j'
+                }, "9.1" : {
+                    sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\
+                    source `pwd`/setup_environment &&\
+                    make -j'
+                }
+            }
+        }
+        stage('simulations-build'){
+            steps{
+                sh 'rm -rf gpgpu-sim_simulations'
+                sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \
+                    cd gpgpu-sim_simulations && \
+                    git checkout purdue-cluster && \
+                    git pull && \
+                    ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/'
+                sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\
+                    source `pwd`/setup_environment &&\
+                    cd gpgpu-sim_simulations && \
+                    source ./benchmarks/src/setup_environment && \
+                    make -j -C ./benchmarks/src rodinia_2.0-ft sdk-4.2 && \
+                    make -C ./benchmarks/src data'
+                sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\
+                    source `pwd`/setup_environment &&\
+                    cd gpgpu-sim_simulations && \
+                    source ./benchmarks/src/setup_environment && \
+                    make -j -C ./benchmarks/src/ rodinia_2.0-ft sdk-4.2 && \
+                    make -C ./benchmarks/src data'
+            }
+        }
+        stage('regress'){
+            steps {
+                parallel "4.2-rodinia": {
+                    sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\
+                    source `pwd`/setup_environment &&\
+                    ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS -N regress-$$ && \
+                    PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \
+                    ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-per-app-4.2.csv && \
+                    ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-per-app-4.2.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR '
+                }, "9.1-functest": {
+                    sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\
+                    source `pwd`/setup_environment &&\
+                    ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft,sdk-4.2 -C TITANX,TITANX-L1ON -N regress-$$ && \
+                    PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \
+                    ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v  -s stats-per-app-9.1.csv -N regress-$$ && \
+                    ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-per-app-9.1.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR'
+                }
+            }
+        }
+        stage('4.2-correlate'){
+            steps {
+                sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\
+                    source `pwd`/setup_environment &&\
+                    PLOTDIR="jenkins/${JOB_NAME}" &&\
+                    ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS > stats-per-kernel-4.2.csv &&\
+                    ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh stats-per-kernel-4.2.csv $PLOTDIR ${BUILD_NUMBER}'
+            }
+        }
+        stage('9.1-correlate'){
+            steps {
+                sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\
+                    source `pwd`/setup_environment &&\
+                    PLOTDIR="jenkins/${JOB_NAME}" &&\
+                    ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft,sdk-4.2 -C TITANX,TITANX-L1ON > stats-per-kernel-9.1.csv &&\
+                    ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh stats-per-kernel-9.1.csv $PLOTDIR ${BUILD_NUMBER}'
+            }
+        }
+        stage('archive-and-delta') {
+            steps {
+                    sh 'rm -rf gpgpu-sim-results-repo'
+                    sh 'git clone git@github.com:purdue-aalp/gpgpu-sim-results-repo.git'
+                    sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\
+                    ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480-PTXPLUS > stats-per-kernel-4.2-ptxplus.csv &&\
+                    ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480 > stats-per-kernel-4.2-ptx.csv'
+                    sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\
+                    ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft,sdk-4.2 -C TITANX > stats-per-kernel-9.1-titanx.csv'
+                    sh './gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/jenkins/quick-regress/AALP/gpgpu-sim_distribution/dev-purdue-integration/stats-per-app-4.2.csv,./stats-per-app-4.2.csv -R > per-app-merge-4.2.csv'
+                    sh './gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/jenkins/quick-regress/AALP/gpgpu-sim_distribution/dev-purdue-integration/stats-per-app-9.1.csv,./stats-per-app-9.1.csv -R > per-app-merge-9.1.csv'
+                    sh 'PLOTDIR="jenkins/${JOB_NAME}" &&\
+                        ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c per-app-merge-4.2.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR/deltas -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR/deltas &&\
+                        ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c per-app-merge-9.1.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR/deltas -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR/deltas -n $PLOTDIR/deltas &&\
+                        ./gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/jenkins/quick-regress/AALP/gpgpu-sim_distribution/dev-purdue-integration/stats-per-kernel-4.2-ptx.csv,./stats-per-kernel-4.2-ptx.csv -R > per-kernel-merge-4.2-ptx.csv &&\
+                        ./gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/jenkins/quick-regress/AALP/gpgpu-sim_distribution/dev-purdue-integration/stats-per-kernel-4.2-ptxplus.csv,./stats-per-kernel-4.2-ptxplus.csv -R > per-kernel-merge-4.2-ptxplus.csv &&\
+                        ./gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/jenkins/quick-regress/AALP/gpgpu-sim_distribution/dev-purdue-integration/stats-per-kernel-9.1-titanx.csv,./stats-per-kernel-9.1-titanx.csv -R > per-kernel-merge-9.1-titanx.csv &&\
+                        ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh per-kernel-merge-4.2-ptx.csv $PLOTDIR ${BUILD_NUMBER} &&\
+                        ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh per-kernel-merge-4.2-ptxplus.csv $PLOTDIR ${BUILD_NUMBER} &&\
+                        ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh per-kernel-merge-9.1-titanx.csv $PLOTDIR ${BUILD_NUMBER} &&\
+                        mkdir -p ./jenkins/quick-regress/${JOB_NAME}/ && cp stats-per-*.csv ./jenkins/quick-regress/${JOB_NAME}/ &&\
+                        cd ./gpgpu-sim-results-repo &&\
+                        git diff --quiet && git diff --staged --quiet || git commit -am "Jenkins automated checkin ${BUILD_NUMBER}" &&\
+                        git push'
+            }
+        }
+    }
+    post {
+        success {
+            emailext body: "See ${BUILD_URL}",
+                recipientProviders: [[$class: 'CulpritsRecipientProvider'],
+                    [$class: 'RequesterRecipientProvider']],
+                subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!",
+                to: 'tgrogers@purdue.edu'
+        }
+        failure {
+            emailext body: "See ${BUILD_URL}",
+                recipientProviders: [[$class: 'CulpritsRecipientProvider'],
+                    [$class: 'RequesterRecipientProvider']],
+                subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}",
+                to: 'tgrogers@purdue.edu'
+        }
+    }
+}
diff --git a/README b/README
index 6e2d734..7eaae5d 100644
--- a/README
+++ b/README
@@ -5,8 +5,8 @@ AerialVision and a configurable and extensible energy model called GPUWattch.
 GPGPU-Sim and GPUWattch have been rigorously validated with performance and
 power measurements of real hardware GPUs. 
 
-This version of GPGPU-Sim has been tested with CUDA version 2.3, 3.1, 4.0, 
-5.0, 5.5, 6.0 and 7.5.
+This version of GPGPU-Sim has been tested with CUDA version 4.2,
+5.0, 5.5, 6.0 and 7.5, 8.0, 9.0, 9.1
 
 Please see the copyright notice in the file COPYRIGHT distributed with this
 release in the same directory as this file.
@@ -18,6 +18,12 @@ Analyzing CUDA Workloads Using a Detailed GPU Simulator, in IEEE International
 Symposium on Performance Analysis of Systems and Software (ISPASS), Boston, MA,
 April 19-21, 2009.
 
+If you use the memory system in GPGPU-Sim, or the Volta/Pascal models,
+please cite:
+Mahmoud Khairy, Jain Akshay, Tor Aamodt, Timothy G Rogers,
+Exploring Modern GPU Memory System Design Challenges through Accurate Modeling, arXiv:1810.07269, 
+https://arxiv.org/abs/1810.07269
+
 If you use the GPUWattch energy model in your research, please cite:
 
 Jingwen Leng, Tayler Hetherington, Ahmed ElTantawy, Syed Gilani, Nam Sung Kim,
diff --git a/aerialvision/organizedata.py b/aerialvision/organizedata.py
index 090b90f..ea947cd 100644
--- a/aerialvision/organizedata.py
+++ b/aerialvision/organizedata.py
@@ -97,7 +97,7 @@ def organizedata(fileVars):
         'sparse':OrganizeSparse,        # Vector data with 2D index  (used by DRAM access stats)
         'custom':0
     }
-    data_type_char = {int:'I', float:'f'}
+    data_type_char = {int:'L', float:'d'}
 
     print "Organizing data into internal format..."
 
diff --git a/configs/GTX480/config_fermi_islip.icnt b/configs/GTX480/config_fermi_islip.icnt
deleted file mode 100644
index 7820e4e..0000000
--- a/configs/GTX480/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 27;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config
deleted file mode 100644
index ee90c12..0000000
--- a/configs/GTX480/gpgpusim.config
+++ /dev/null
@@ -1,134 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 20 
-
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 15
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 6
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Fermi clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
-# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
--gpgpu_clock_domains 700.0:700.0:700.0:924.0
-
-# shader core pipeline config
--gpgpu_shader_registers 32768
--gpgpu_occupancy_sm_number 20
-
-# This implies a maximum of 48 warps/SM
--gpgpu_shader_core_pipeline 1536:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,1,1,2,1,1,2
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,1,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,16,8,8,130
-
-
-# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
--gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
--gpgpu_shmem_size 49152
-
-# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
-#-gpgpu_shmem_size 16384
-
-# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
--gpgpu_cache:dl2_texture_only 0 
-
--gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_num_reg_banks 16
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
--gpgpu_max_insn_issue_per_warp 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 116
-
-# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5 is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
-
-# GDDR5 timing from hynix H5GQ1H24AFR
-# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/GTX480/gpuwattch_gtx480.xml b/configs/GTX480/gpuwattch_gtx480.xml
deleted file mode 100755
index 304e0fd..0000000
--- a/configs/GTX480/gpuwattch_gtx480.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="16"/>
-		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="1"/>
-		<param name="core_tech_node" value="40"/><!-- nm -->
-		<param name="target_core_clockrate" value="700"/><!--MHz -->
-		<param name="temperature" value="380"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
-		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
-		<param name="TOT_INST" value="2.00" />
-		<param name="FP_INT" value="4.57" />
-		<param name="IC_H" value="2.14" />
-		<param name="IC_M" value="22.47" />
-		<param name="DC_RH" value="22.14" />
-		<param name="DC_RM" value="24.66" />
-		<param name="DC_WH" value="1.53" />
-		<param name="DC_WM" value="39.79" />
-		<param name="TC_H" value="10.21" />
-		<param name="TC_M" value="24.66" />
-		<param name="CC_H" value="11.07" />
-		<param name="CC_M" value="12.33" />
-		<param name="SHRD_ACC" value="7.04" />
-		<param name="REG_RD" value="0.14" />
-		<param name="REG_WR" value="0.21" />
-		<param name="NON_REG_OPs" value="2.11" />
-		<param name="SP_ACC" value="2.38" />
-		<param name="SFU_ACC" value="0.51" />
-		<param name="FPU_ACC" value="0.64" />
-		<param name="MEM_RD" value="0.33" />
-		<param name="MEM_WR" value="0.40" />
-		<param name="MEM_PRE" value="0.11" />
-		<param name="L2_RH" value="13.79" />
-		<param name="L2_RM" value="35.18" />
-		<param name="L2_WH" value="43.07" />
-		<param name="L2_WM" value="28.72" />
-		<param name="NOC_A" value="305.48" />
-		<param name="PIPE_A" value="2.57" />
-		<param name="IDLE_CORE_N" value="1"/>
-		<param name="CONST_DYNAMICN" value="11" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="700"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="2"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="2"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="32"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="4"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="32"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="32"/>
-			<param name="simd_width" value="32"/>
-			<param name="collector_units" value="32"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="32768"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="2"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="15"/>	
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="0"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="700"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="2"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="6"/>
-			<param name="output_ports" value="6"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="0"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="40"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="6"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="3.8475e-8f"/>
-			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
-			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/GeForceGTX1080Ti/config_fermi_islip.icnt b/configs/GeForceGTX1080Ti/config_fermi_islip.icnt
deleted file mode 100644
index 2a69ddd..0000000
--- a/configs/GeForceGTX1080Ti/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 50;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config
deleted file mode 100644
index fb044c6..0000000
--- a/configs/GeForceGTX1080Ti/gpgpusim.config
+++ /dev/null
@@ -1,150 +0,0 @@
-# This config models the Pascal GP102 (GeForceGTX 1080Ti)
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 60
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 11
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 60
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,4,1,1,6
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# SFU is 32-width in pascal, then dp units initiation is 1 cycle
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 1,2,1,1,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory
-# Pascal GP102 has 64KB L1 cache
-# The default is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,8
--gpgpu_shmem_size 98304
--gmem_skip_L1D 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
--gpgpu_cache:dl2_texture_only 0 
-
-# 4 KB Inst.
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
-
-# enable operand collector 
-## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
--gpgpu_operand_collector_num_units_sp 20
--gpgpu_operand_collector_num_units_sfu 4
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
-# gpgpu_num_reg_banks should be increased to 32, but it gives an error!
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits)
-# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes 
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing from hynix H5GQ1H24AFR
-# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
-
-# Pascal has four schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml b/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml
deleted file mode 100755
index 02619ff..0000000
--- a/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="28"/>
-		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="1"/>
-		<param name="core_tech_node" value="23"/><!-- nm -->
-		<param name="target_core_clockrate" value="1481"/><!--MHz -->
-		<param name="temperature" value="380"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
-		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
-		<param name="TOT_INST" value="10" />
-		<param name="FP_INT" value="10" />
-		<param name="IC_H" value="0.001" />
-		<param name="IC_M" value="10" />
-		<param name="DC_RH" value="1" />
-		<param name="DC_RM" value="1" />
-		<param name="DC_WH" value="1" />
-		<param name="DC_WM" value="1" />
-		<param name="TC_H" value="0.001" />
-		<param name="TC_M" value="10" />
-		<param name="CC_H" value="4.5071" />
-		<param name="CC_M" value="10" />
-		<param name="SHRD_ACC" value="10" />
-		<param name="REG_RD" value="1.6294" />
-		<param name="REG_WR" value="0.5031" />
-		<param name="NON_REG_OPs" value="0.01" />
-		<param name="SP_ACC" value="10" />
-		<param name="SFU_ACC" value="0.0082" />
-		<param name="FPU_ACC" value="0.4126" />
-		<param name="MEM_RD" value="0.1234" />
-		<param name="MEM_WR" value="0.001" />
-		<param name="MEM_PRE" value="0.001" />
-		<param name="L2_RH" value="100" />
-		<param name="L2_RM" value="100" />
-		<param name="L2_WH" value="100" />
-		<param name="L2_WM" value="42.6966" />
-		<param name="NOC_A" value="100" />
-		<param name="PIPE_A" value="44.8085" />
-		<param name="IDLE_CORE_N" value="2.0382"/>
-		<param name="CONST_DYNAMICN" value="5.0005" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="1481"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="2"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="2"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="32"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="4"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="32"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="32"/>
-			<param name="simd_width" value="32"/>
-			<param name="collector_units" value="32"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="65536"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="2"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="15"/>	
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="0"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="2962"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="700"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="2"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="6"/>
-			<param name="output_ports" value="6"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="0"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="23"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="6"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="3.8475e-8f"/>
-			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
-			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/GeForceGTX750Ti/config_fermi_islip.icnt
deleted file mode 100644
index 069ca02..0000000
--- a/configs/GeForceGTX750Ti/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 7;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config
deleted file mode 100644
index c675aab..0000000
--- a/configs/GeForceGTX750Ti/gpgpusim.config
+++ /dev/null
@@ -1,131 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 52 
-
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 5
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 2
--gpgpu_n_sub_partition_per_mchannel 1
-
-# Maxwell clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number.
--gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 52
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,1,1,2,1,1,2
--gpgpu_num_sp_units 8
--gpgpu_num_sfu_units 32
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 6,12,13,13,210
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 6,12,6,6,374
--ptx_opcode_initiation_fp 1,1,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,16,8,8,130
-
--gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
--gmem_skip_L1D 1
--gpgpu_shmem_size 65536
-
-# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
-#-gpgpu_shmem_size 16384
-
-# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache
--gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32
--gpgpu_cache:dl2_texture_only 0 
-
--gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_num_reg_banks 16
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 150
--dram_latency 130
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 300
-
-# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 32
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5 is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
-
-# GDDR5 timing from hynix H5GQ1H24AFR
-# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
-
-# Maxwell has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
-# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy.
-# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present.
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx750Ti.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
deleted file mode 100755
index e2b2324..0000000
--- a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
+++ /dev/null
@@ -1,539 +0,0 @@
-<!-- THIS CONFIG IS CURRENTLY PRESENT ONLY AS A PLACEHOLDER. IT HAS NOT BEEN TESTED FOR ACCURACY VERSUS GTX750TI HARDWARE. ANY USE OF THIS CONFIG WILL LIKELY GIVE HIGHLY INACCURATE RESULTS. -->
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="16"/>
-		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="1"/>
-		<param name="core_tech_node" value="40"/><!-- nm -->
-		<param name="target_core_clockrate" value="700"/><!--MHz -->
-		<param name="temperature" value="380"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
-		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
-		<param name="TOT_INST" value="2.00" />
-		<param name="FP_INT" value="4.57" />
-		<param name="IC_H" value="2.14" />
-		<param name="IC_M" value="22.47" />
-		<param name="DC_RH" value="22.14" />
-		<param name="DC_RM" value="24.66" />
-		<param name="DC_WH" value="1.53" />
-		<param name="DC_WM" value="39.79" />
-		<param name="TC_H" value="10.21" />
-		<param name="TC_M" value="24.66" />
-		<param name="CC_H" value="11.07" />
-		<param name="CC_M" value="12.33" />
-		<param name="SHRD_ACC" value="7.04" />
-		<param name="REG_RD" value="0.14" />
-		<param name="REG_WR" value="0.21" />
-		<param name="NON_REG_OPs" value="2.11" />
-		<param name="SP_ACC" value="2.38" />
-		<param name="SFU_ACC" value="0.51" />
-		<param name="FPU_ACC" value="0.64" />
-		<param name="MEM_RD" value="0.33" />
-		<param name="MEM_WR" value="0.40" />
-		<param name="MEM_PRE" value="0.11" />
-		<param name="L2_RH" value="13.79" />
-		<param name="L2_RM" value="35.18" />
-		<param name="L2_WH" value="43.07" />
-		<param name="L2_WM" value="28.72" />
-		<param name="NOC_A" value="305.48" />
-		<param name="PIPE_A" value="2.57" />
-		<param name="IDLE_CORE_N" value="1"/>
-		<param name="CONST_DYNAMICN" value="11" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="700"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="2"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="2"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="32"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="4"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="32"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="32"/>
-			<param name="simd_width" value="32"/>
-			<param name="collector_units" value="32"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="32768"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="2"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="15"/>	
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="0"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="0"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="1400"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="700"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="2"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="6"/>
-			<param name="output_ports" value="6"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="0"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="40"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="6"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="3.8475e-8f"/>
-			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
-			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/Pascal_TITANX/config_fermi_islip.icnt b/configs/Pascal_TITANX/config_fermi_islip.icnt
deleted file mode 100644
index 602daee..0000000
--- a/configs/Pascal_TITANX/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 52;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/Pascal_TITANX/gpgpusim.config b/configs/Pascal_TITANX/gpgpusim.config
deleted file mode 100644
index f78bd02..0000000
--- a/configs/Pascal_TITANX/gpgpusim.config
+++ /dev/null
@@ -1,156 +0,0 @@
-# This config models the Pascal GP102 (NVIDIA TITAN X)
-# For more info about this card, see Nvidia White paper
-# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 61
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 12
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,4,1,1,6
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# SFU is 32-width in pascal, then dp units initiation is 1 cycle
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,8,4,4,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory
-# Pascal GP102 has 64KB L1 cache
-# The defulat is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
--gpgpu_shmem_size 98304
--gpgpu_shmem_size_PrefL1 98304
--gpgpu_shmem_size_PrefShared 98304
--gmem_skip_L1D 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 32:32:32:32
-
-# 4 KB Inst.
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
-
-# enable operand collector 
-## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
--gpgpu_operand_collector_num_units_sp 20
--gpgpu_operand_collector_num_units_sfu 4
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
-# gpgpu_num_reg_banks should be increased to 32
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
-# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes 
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing from hynix H5GQ1H24AFR
-# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config
deleted file mode 100644
index 6f836ee..0000000
--- a/configs/QuadroFX5600/gpgpusim.config
+++ /dev/null
@@ -1,99 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 12
-
-# high level architecture configuration
--gpgpu_n_clusters 8 
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 6 
--gpgpu_clock_domains 337.5:600.0:600.0:800.0 
-
-# shader core pipeline config
--gpgpu_shader_registers 16384
--gpgpu_occupancy_sm_number 12
-
--gpgpu_occupancy_sm_number 12
-#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though)
--gpgpu_shader_core_pipeline 768:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 1,1,1,1,1,1,1
--gpgpu_num_sp_units 1
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 1,1,19,25,145
--ptx_opcode_initiation_int 1,1,4,4,32
--ptx_opcode_latency_fp 1,1,1,1,30
--ptx_opcode_initiation_fp 1,1,1,1,5
--ptx_opcode_latency_dp 8,8,8,8,335
--ptx_opcode_initiation_dp 8,8,8,8,130
-
-# memory stage behaviour
--gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
--gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
--gpgpu_cache:dl2_texture_only 1
-
-# TLB parameters
-#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8
-#-gpgpu_tlbl2_latency 45
-
-
--gpgpu_shmem_warp_parts 2
-
-# interconnection
--network_mode 1 
--inter_config_file icnt_config_islip.icnt 
-
-# dram scheduler config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (30 core cycles).  I.e. 
-#   Total buffer space required = 30 x 800MHz / 337.5MHz = 71
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 55
-
-# dram model config
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4 
--gpgpu_dram_burst_length 4
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
-# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
-# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
--gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
-
-
-
-# Using cuobjdump to extract ptx/SASS
--gpgpu_ptx_use_cuobjdump 1
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
-
--visualizer_enabled 0
--power_trace_enabled 0
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_quadrofx5600.xml 
-
--steady_power_levels_enabled 1
--steady_state_definition 8,4
diff --git a/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml
deleted file mode 100644
index 2c5a6fc..0000000
--- a/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
-	<component id="system" name="system">
-		<!--McPAT will skip the components if number is set to 0 -->
-		<param name="GPU_Architecture" value="0"/><!-- 0-G80; 1-Fermi; others not supported -->
-		<param name="number_of_cores" value="16"/>
-		<param name="architecture" value="2"/> <!-- fermi:1 quadro:2 other: undefined-->
-		<param name="number_of_L1Directories" value="0"/>
-		<param name="number_of_L2Directories" value="0"/>
-		<param name="number_of_L2s" value="0"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
-		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
-		<param name="number_of_NoCs" value="1"/> 
-		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
-		<param name="homogeneous_L2s" value="1"/>
-		<param name="homogeneous_L1Directorys" value="1"/>
-		<param name="homogeneous_L2Directorys" value="1"/>
-		<param name="homogeneous_L3s" value="1"/>
-		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
-		<param name="homogeneous_NoCs" value="0"/>
-		<param name="core_tech_node" value="65"/><!-- nm -->
-		<param name="target_core_clockrate" value="650"/><!--MHz -->
-		<param name="temperature" value="400"/> <!-- Kelvin -->
-		<param name="number_cache_levels" value="2"/>
-		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
-		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
-		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
-		<param name="machine_bits" value="32"/>
-		<param name="virtual_address_width" value="32"/>
-		<param name="physical_address_width" value="32"/>
-		<param name="virtual_memory_page_size" value="4096"/>
-		<param name="idle_core_power" value="1.54"/><!-- idle core power for GTX479 -->
-		<param name="TOT_INST" value="2" />
-		<param name="FP_INT" value="5" />
-		<param name="IC_H" value="10" />
-		<param name="IC_M" value="10" />
-		<param name="DC_RH" value="10" />
-		<param name="DC_RM" value="10" />
-		<param name="DC_WH" value="10" />
-		<param name="DC_WM" value="10" />
-		<param name="TC_H" value="20" />
-		<param name="TC_M" value="20" />
-		<param name="CC_H" value="10" />
-		<param name="CC_M" value="10" />
-		<param name="SHRD_ACC" value="20" />
-		<param name="REG_RD" value="0.25" />
-		<param name="REG_WR" value="0.4" />
-		<param name="NON_REG_OPs" value="0.4" />
-		<param name="SP_ACC" value="0.6" />
-		<param name="SFU_ACC" value="0.7" />
-		<param name="FPU_ACC" value="0.25" />
-		<param name="MEM_RD" value="0.3" />
-		<param name="MEM_WR" value="0.4" />
-		<param name="MEM_PRE" value="0.7" />
-		<param name="L2_RH" value="1" />
-		<param name="L2_RM" value="1" />
-		<param name="L2_WH" value="1" />
-		<param name="L2_WM" value="1" />
-		<param name="NOC_A" value="80" />
-		<param name="PIPE_A" value="0.8" />
-		<param name="IDLE_CORE_N" value="1"/>
-		<param name="CONST_DYNAMICN" value="9" />
-		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
-		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
-			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
-		<!-- *********************** cores ******************* -->
-		<component id="system.core0" name="core0">
-			<!-- Core property -->
-			<param name="clock_rate" value="650"/>
-			<param name="instruction_length" value="32"/>
-			<param name="opcode_width" value="9"/>
-			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
-			default value is machine_bits, if not set --> 
-			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
-			<!-- inorder/OoO -->
-			<param name="number_hardware_threads" value="32"/>
-			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
-			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
-			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
-			<param name="fetch_width" value="1"/>
-			<!-- fetch_width determins the size of cachelines of L1 cache block -->
-			<param name="number_instruction_fetch_ports" value="1"/>
-			<param name="decode_width" value="1"/>
-			<!-- decode_width determins the number of ports of the 
-			renaming table (both RAM and CAM) scheme -->
-			<param name="issue_width" value="1"/>
-			<!-- issue_width determins the number of ports of Issue window and other logic 
-			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
-			<param name="commit_width" value="1"/>
-			<!-- commit_width determins the number of ports of register files -->
-			<param name="fp_issue_width" value="1"/>
-			<param name="prediction_width" value="0"/> 
-			<!-- number of branch instructions can be predicted simultannouesl-->
-			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
-			Theses parameters are reserved for future use.--> 
-			<param name="pipelines_per_core" value="1,1"/>
-			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
-			<param name="pipeline_depth" value="8,8"/>
-			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
-			<!-- issue and exe unit-->
-			<param name="ALU_per_core" value="1"/>
-			<!-- contains an adder, a shifter, and a logical unit -->
-			<param name="MUL_per_core" value="1"/>
-			<!-- For MUL and Div -->
-			<param name="FPU_per_core" value="8"/>		
-			<!-- buffer between IF and ID stage -->
-			<param name="instruction_buffer_size" value="1"/>
-			<!-- buffer between ID and sche/exe stage -->
-			<param name="decoded_stream_buffer_size" value="1"/>
-			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
-			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
-			<param name="instruction_window_size" value="1"/>
-			<param name="fp_instruction_window_size" value="1"/>
-			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
-			<param name="ROB_size" value="0"/>
-			<!-- each in-flight instruction has an entry in ROB -->
-			<!-- registers -->
-
-			<!-- SM parameters  Added by Syed Gilani -->
-			<param name="rf_banks" value="16"/>
-			<param name="simd_width" value="8"/>
-			<param name="collector_units" value="16"/>
-			<param name="core_clock_ratio" value="2"/>
-			<param name="warp_size" value="32"/>
-
-			<param name="archi_Regs_IRF_size" value="8192"/>			
-			<param name="archi_Regs_FRF_size" value="32"/>
-			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
-			renaming logic is for both integer and floating point insts.  -->
-			<param name="phy_Regs_IRF_size" value="32"/>
-			<param name="phy_Regs_FRF_size" value="32"/>
-			<!-- rename logic -->
-			<param name="rename_scheme" value="0"/>
-			<!-- can be RAM based(0) or CAM based(1) rename scheme 
-			RAM-based scheme will have free list, status table;
-			CAM-based scheme have the valid bit in the data field of the CAM 
-			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
-			Detailed RAT Implementation see TR -->
-			<param name="register_windows_size" value="0"/>
-			<!-- how many windows in the windowed register file, sun processors;
-			no register windowing is used when this number is 0 -->
-			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
-			They will always try to exeute out-of-order though. -->
-			<param name="LSU_order" value="inorder"/>
-			<param name="store_buffer_size" value="32"/>
-			<!-- By default, in-order cores do not have load buffers -->
-			<param name="load_buffer_size" value="32"/>	
-			<!-- number of ports refer to sustainable concurrent memory accesses --> 
-			<param name="memory_ports" value="1"/>	
-			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
-			as well as the ports of Dcache which is connected to LSU -->	
-			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
-			<param name="RAS_size" value="1"/>						
-			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
-			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
-			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
-			<stat name="branch_mispredictions" value="0"/>
-			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
-			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
-			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
-			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
-			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
-			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
-			<!-- the following cycle stats are used for heterogeneouse cores only, 
-				please ignore them if homogeneouse cores -->
-			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
-		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
-		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
-			<!-- instruction buffer stats -->
-			<!-- ROB stats, both RS and Phy based OoOs have ROB
-			performance simulator should capture the difference on accesses,
-			otherwise, McPAT has to guess based on number of commited instructions. -->
-			<stat name="ROB_reads" value="263886"/>
-			<stat name="ROB_writes" value="263886"/>
-			<!-- RAT accesses -->
-			<stat name="rename_accesses" value="263886"/>
-			<stat name="fp_rename_accesses" value="263886"/>
-			<!-- decode and rename stage use this, should be total ic - nop -->
-			<!-- Inst window stats -->
-			<stat name="inst_window_reads" value="263886"/>
-			<stat name="inst_window_writes" value="263886"/>
-			<stat name="inst_window_wakeup_accesses" value="263886"/>
-			<stat name="fp_inst_window_reads" value="263886"/>
-			<stat name="fp_inst_window_writes" value="263886"/>
-			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
-			<!--  RF accesses -->
-			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
-			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
-			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-			
-			<!-- The following stat is for operand collector power - Added by Syed -->
-			<stat name="non_rf_operands" value="0"/>
-
-			<!-- accesses to the working reg -->
-			<stat name="function_calls" value="0"/>
-			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
-			<!-- Number of Windowes switches (number of function calls and returns)-->
-			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
-			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
-			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
-			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
-			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
-			<stat name="cdb_alu_accesses" value="0"/>
-			<stat name="cdb_mul_accesses" value="0"/>
-			<stat name="cdb_fpu_accesses" value="0"/>
-			<!-- multiple cycle accesses should be counted multiple times, 
-			otherwise, McPAT can use internal counter for different floating point instructions 
-			to get final accesses. But that needs detailed info for floating point inst mix -->
-			<!--  currently the performance simulator should 
-			make sure all the numbers are final numbers, 
-			including the explicit read/write accesses, 
-			and the implicite accesses such as replacements and etc.
-			Future versions of McPAT may be able to reason the implicite access
-			based on param and stats of last level cache
-			The same rule applies to all cache access stats too!  -->
-			<!-- following is AF for max power computation. 
-				Do not change them, unless you understand them-->
-			<stat name="IFU_duty_cycle" value="0.25"/>			
-			<stat name="LSU_duty_cycle" value="0.25"/>
-			<stat name="MemManU_I_duty_cycle" value="1"/>
-			<stat name="MemManU_D_duty_cycle" value="0.25"/>
-			<stat name="ALU_duty_cycle" value="0.9"/>
-			<stat name="MUL_duty_cycle" value="0.5"/>
-			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
-			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
-			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
-			<stat name="FPU_cdb_duty_cycle" value="0.4"/>
-			<component id="system.core0.predictor" name="PBT">
-				<!-- branch predictor; tournament predictor see Alpha implementation -->
-				<param name="local_predictor_size" value="10,3"/>
-				<param name="local_predictor_entries" value="1024"/>
-				<param name="global_predictor_entries" value="4096"/>
-				<param name="global_predictor_bits" value="2"/>
-				<param name="chooser_predictor_entries" value="4096"/>
-				<param name="chooser_predictor_bits" value="2"/>
-				<!-- These parameters can be combined like below in next version
-				<param name="load_predictor" value="10,3,1024"/>
-				<param name="global_predictor" value="4096,2"/>
-				<param name="predictor_chooser" value="4096,2"/>
-				-->
-			</component>
-			<component id="system.core0.itlb" name="itlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="1"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
-				which is actually a replacement -->
-			</component>
-			<component id="system.core0.icache" name="icache">
-				<!-- there is no write requests to itlb although writes happen to it after miss, 
-				which is actually a replacement -->
-				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
-				<param name="buffer_sizes" value="16, 16, 16,0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
-				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="conflicts" value="0"/>				
-			</component>
-			<component id="system.core0.dtlb" name="dtlb">
-				<param name="number_entries" value="1"/>
-				<stat name="total_accesses" value="1"/>
-				<stat name="total_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.ccache" name="ccache">
-			        <!-- all the buffer related are optional -->
-				<param name="ccache_config" value="65536,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.tcache" name="tcache">
-			        <!-- all the buffer related are optional -->
-				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-      <!--model the shared memory by mimicing dcache-->
-			<component id="system.core0.sharedmemory" name="sharedmemory">
-			        <!-- all the buffer related are optional -->
-				<param name="sharedmemory_config" value="16384,16,1,16,1,3,16,0"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.dcache" name="dcache">
-			        <!-- all the buffer related are optional -->
-				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 0"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
-				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
-				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
-				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
-				<stat name="conflicts" value="0"/>	
-			</component>
-			<component id="system.core0.BTB" name="BTB">
-			        <!-- all the buffer related are optional -->
-				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
-				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			</component>
-	</component>
-		<component id="system.L1Directory0" name="L1Directory0">
-				<param name="Directory_type" value="0"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1300"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="800000"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="20"/>	
-				<stat name="duty_cycle" value="0.45"/>	
-		</component>
-		<component id="system.L2Directory0" name="L2Directory0">
-				<param name="Directory_type" value="1"/>
-			    <!--0 cam based shadowed tag. 1 directory cache -->	
-				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
-				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
-			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
-				<!-- all the buffer related are optional -->
-			    <param name="clockrate" value="1300"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw search ports -->
-				<param name="device_type" value="0"/>
-				<!-- altough there are multiple access types, 
-				Performance simulator needs to cast them into reads or writes
-				e.g. the invalidates can be considered as writes -->
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="100"/>
-			    <stat name="duty_cycle" value="0.45"/>		
-		</component>
-		<component id="system.L20" name="L20">
-			<!-- all the buffer related are optional -->
-				<param name="L2_config" value="786432,64,16,1, 4,23, 64, 1"/>
-			    <!-- consider 4-way bank interleaving for Niagara 1 -->
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<param name="clockrate" value="1300"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<stat name="read_accesses" value="200000"/>
-				<stat name="write_accesses" value="0"/>
-				<stat name="read_misses" value="0"/>
-				<stat name="write_misses" value="0"/>
-				<stat name="conflicts" value="0"/>	
-			    <stat name="duty_cycle" value="0.5"/>	
-		</component>
-		
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
-				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
-				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
-				<param name="clockrate" value="3500"/>
-				<param name="ports" value="1,1,1"/>
-				<!-- number of r, w, and rw ports -->
-				<param name="device_type" value="0"/>
-				<param name="buffer_sizes" value="16, 16, 16, 16"/>
-				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
-				<stat name="read_accesses" value="58824"/>
-				<stat name="write_accesses" value="27276"/>
-				<stat name="read_misses" value="1632"/>
-				<stat name="write_misses" value="183"/>
-				<stat name="conflicts" value="0"/>	
-	            <stat name="duty_cycle" value="0.35"/>	
-		</component>
-
-
-<!--**********************************************************************-->
-		<component id="system.NoC0" name="noc0">
-			<param name="clockrate" value="650"/>
-			<param name="type" value="1"/>
-			<!-- 1 NoC, O bus -->
-			<param name="horizontal_nodes" value="4"/>
-			<param name="vertical_nodes" value="1"/>
-			<param name="has_global_link" value="0"/>
-			<!-- 1 has global link, 0 does not have global link -->
-			<param name="link_throughput" value="1"/><!--w.r.t clock -->
-			<param name="link_latency" value="1"/><!--w.r.t clock -->
-			<!-- througput >= latency -->
-			<!-- Router architecture -->
-			<param name="input_ports" value="7"/>
-			<param name="output_ports" value="7"/>
-			<param name="virtual_channel_per_port" value="1"/>
-			<!-- input buffer; in classic routers only input ports need buffers -->
-			<param name="flit_bits" value="32"/>
-			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
-			<param name="chip_coverage" value="1"/>
-			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
-			<stat name="total_accesses" value="360000"/>
-			<!-- This is the number of total accesses within the whole network not for each router -->
-			<stat name="duty_cycle" value="0.6"/>
-		</component>	
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
-		<component id="system.mem" name="mem">
-			<!-- Main memory property -->
-			<param name="mem_tech_node" value="65"/>
-			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
-			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
-			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
-			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
-			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
-			<!-- above numbers can be easily found from Wikipedia -->
-			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
-			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
-			Current McPAT assumes single DIMMs are used.--> 		
-			<param name="number_ranks" value="2"/>
-			<param name="num_banks_of_DRAM_chip" value="8"/>			
-			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
-			<param name="output_width_of_DRAM_chip" value="8"/>
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
-			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
-			<param name="burstlength_of_DRAM_chip" value="8"/>
-			<stat name="memory_accesses" value="1052"/>
-			<stat name="memory_reads" value="1052"/>
-			<stat name="memory_writes" value="1052"/>									
-		</component>
-		<component id="system.mc" name="mc">
-			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
-			<!-- current version of McPAT uses published values for base parameters of memory controller
-			improvments on MC will be added in later versions. -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="mc_clock" value="800"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
-			<param name="peak_transfer_rate" value="9600"/><!--MB/S  Syed: Quadro FX 5800 has 76.8GB/s mem transfer rate with 6 MCs -->
-			<param name="block_size" value="64"/><!--B-->
-			<param name="number_mcs" value="8"/><!-- 6 GDDR5 memory controllers  -->
-			<!-- current McPAT only supports homogeneous memory controllers -->
-			<param name="memory_channels_per_mc" value="2"/>
-			<param name="number_ranks" value="1"/>
-			<param name="withPHY" value="0"/>
-			<!-- # of ranks of each channel-->
-			<param name="req_window_size_per_channel" value="16"/>
-			<param name="IO_buffer_size_per_channel" value="16"/>
-			<param name="databus_width" value="32"/>
-			<param name="addressbus_width" value="32"/>
-			<param name="PRT_entries" value="32"/>
-			<!-- # of empirical DRAM model parameter -->
-			<param name="dram_cmd_coeff" value="0"/>
-			<param name="dram_act_coeff" value="0"/>
-			<param name="dram_nop_coeff" value="0"/>
-			<param name="dram_activity_coeff" value="0"/>
-			<param name="dram_pre_coeff" value="1.53846154e-8f"/>
-			<param name="dram_rd_coeff" value="3.07692308e-8f"/>
-			<param name="dram_wr_coeff" value="1.30769231e-8f"/>
-			<param name="dram_req_coeff" value="0"/>
-			<param name="dram_const_coeff" value="0"/>
-
-			<!-- McPAT will add the control bus width to the addressbus width automatically -->
-			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
-			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
-			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
-			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
-			the average power per MC or per channel. This is sufficent for most application. 
-			Further trackdown can be easily added in later versions. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.niu" name="niu">
-			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
-			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
-				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
-			the average power per nic or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.pcie" name="pcie">
-			<!-- On chip PCIe controller, including Phy-->
-			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
-				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
-			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
-			<param name="withPHY" value="1"/>
-			<param name="clockrate" value="350"/>
-			<param name="number_units" value="0"/>
-			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
-			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
-		</component>
-<!--**********************************************************************-->
-		<component id="system.flashc" name="flashc">
-		    <param name="number_flashcs" value="0"/>
-			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
-            <param name="withPHY" value="1"/>
-			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
-			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
-			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
-			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
-			the average power per fc or per channel. This is sufficent for most application -->  			
-		</component>
-<!--**********************************************************************-->
-
-		</component>
-</component>
diff --git a/configs/QuadroFX5600/icnt_config_islip.icnt b/configs/QuadroFX5600/icnt_config_islip.icnt
deleted file mode 100644
index de3bcc8..0000000
--- a/configs/QuadroFX5600/icnt_config_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//14*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we donot use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 14;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/QuadroFX5800/config_quadro_islip.icnt b/configs/QuadroFX5800/config_quadro_islip.icnt
deleted file mode 100644
index cfe9cac..0000000
--- a/configs/QuadroFX5800/config_quadro_islip.icnt
+++ /dev/null
@@ -1,69 +0,0 @@
-//18*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we donot use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 18;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config
deleted file mode 100644
index fef1110..0000000
--- a/configs/QuadroFX5800/gpgpusim.config
+++ /dev/null
@@ -1,88 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 13
-
-# high level architecture configuration
--gpgpu_n_clusters 10 
--gpgpu_n_cores_per_cluster 3
--gpgpu_n_mem 8 
--gpgpu_clock_domains 325.0:650.0:650.0:800.0 
-
-# shader core pipeline config
--gpgpu_shader_registers 16384
--gpgpu_occupancy_sm_number 13
-
--gpgpu_shader_core_pipeline 1024:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 1,1,1,1,1,1,1
--gpgpu_num_sp_units 1
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 1,1,19,25,145
--ptx_opcode_initiation_int 1,1,4,4,32
--ptx_opcode_latency_fp 1,1,1,1,30
--ptx_opcode_initiation_fp 1,1,1,1,5
--ptx_opcode_latency_dp 8,8,8,8,335
--ptx_opcode_initiation_dp 8,8,8,8,130
-
-# memory stage behaviour
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
--gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
--gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
--gpgpu_cache:dl2_texture_only 1
-
--gpgpu_shmem_warp_parts 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_quadro_islip.icnt
-
-# dram scheduler config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (30 core cycles).  I.e. 
-#   Total buffer space required = 30 x 800MHz / 325MHz = 74
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 58
-
-# dram model config
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4 
--gpgpu_dram_burst_length 4
--dram_data_command_freq_ratio 2  # GDDR3 is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
-# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
--gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
-
--visualizer_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/TeslaC2050/config_fermi_islip.icnt b/configs/TeslaC2050/config_fermi_islip.icnt
deleted file mode 100644
index a11bd8e..0000000
--- a/configs/TeslaC2050/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//20*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32; 
-
-// currently we donot use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 26;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config
deleted file mode 100644
index 6ac2c12..0000000
--- a/configs/TeslaC2050/gpgpusim.config
+++ /dev/null
@@ -1,133 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 20 
-
-# Using cuobjdump to extract ptx/SASS
-#-gpgpu_ptx_use_cuobjdump 1 # use default
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-
-# high level architecture configuration
--gpgpu_n_clusters 14
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 6
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Fermi clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
-# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
--gpgpu_clock_domains 575.0:575.0:575.0:750.0
-
-# shader core pipeline config
--gpgpu_shader_registers 32768
--gpgpu_occupancy_sm_number 20
-
-# This implies a maximum of 48 warps/SM
--gpgpu_shader_core_pipeline 1536:32 
--gpgpu_shader_cta 8
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,1,1,2,1,1,2
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,1,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,16,8,8,130
-
-
-# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
--gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
--gpgpu_shmem_size 49152
-
-# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
-#-gpgpu_shmem_size 16384
-
-# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
--gpgpu_cache:dl2_texture_only 0 
-
--gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 6
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_num_reg_banks 16
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
--gpgpu_max_insn_issue_per_warp 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 750MHz / 575MHz = 130
--gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 114  
-
-# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
--gpgpu_n_mem_per_ctrlr 2
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5 is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
-
-# GDDR5 timing from hynix H5GQ1H24AFR
-# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
diff --git a/configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt b/configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt
new file mode 100644
index 0000000..7820e4e
--- /dev/null
+++ b/configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 27;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/GTX480/gpgpusim.config b/configs/deprecated-cfgs/GTX480/gpgpusim.config
new file mode 100644
index 0000000..ee90c12
--- /dev/null
+++ b/configs/deprecated-cfgs/GTX480/gpgpusim.config
@@ -0,0 +1,134 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 20 
+
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 15
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 6
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Fermi clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
+# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
+-gpgpu_clock_domains 700.0:700.0:700.0:924.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
+
+# This implies a maximum of 48 warps/SM
+-gpgpu_shader_core_pipeline 1536:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,1,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+
+# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+-gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_shmem_size 49152
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_shmem_size 16384
+
+# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
+-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 116
+
+# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml
new file mode 100755
index 0000000..304e0fd
--- /dev/null
+++ b/configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
new file mode 100644
index 0000000..069ca02
--- /dev/null
+++ b/configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 7;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config b/configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config
new file mode 100644
index 0000000..c675aab
--- /dev/null
+++ b/configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config
@@ -0,0 +1,131 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 52 
+
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 5
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 2
+-gpgpu_n_sub_partition_per_mchannel 1
+
+# Maxwell clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number.
+-gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 52
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
+-gpgpu_num_sp_units 8
+-gpgpu_num_sfu_units 32
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 6,12,13,13,210
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 6,12,6,6,374
+-ptx_opcode_initiation_fp 1,1,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
+-gmem_skip_L1D 1
+-gpgpu_shmem_size 65536
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_shmem_size 16384
+
+# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache
+-gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 150
+-dram_latency 130
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 300
+
+# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 32
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# Maxwell has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy.
+# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present.
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx750Ti.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
new file mode 100755
index 0000000..e2b2324
--- /dev/null
+++ b/configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
@@ -0,0 +1,539 @@
+<!-- THIS CONFIG IS CURRENTLY PRESENT ONLY AS A PLACEHOLDER. IT HAS NOT BEEN TESTED FOR ACCURACY VERSUS GTX750TI HARDWARE. ANY USE OF THIS CONFIG WILL LIKELY GIVE HIGHLY INACCURATE RESULTS. -->
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config b/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config
new file mode 100644
index 0000000..6f836ee
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config
@@ -0,0 +1,99 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 12
+
+# high level architecture configuration
+-gpgpu_n_clusters 8 
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 6 
+-gpgpu_clock_domains 337.5:600.0:600.0:800.0 
+
+# shader core pipeline config
+-gpgpu_shader_registers 16384
+-gpgpu_occupancy_sm_number 12
+
+-gpgpu_occupancy_sm_number 12
+#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though)
+-gpgpu_shader_core_pipeline 768:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 1,1,1,1,1,1,1
+-gpgpu_num_sp_units 1
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 1,1,19,25,145
+-ptx_opcode_initiation_int 1,1,4,4,32
+-ptx_opcode_latency_fp 1,1,1,1,30
+-ptx_opcode_initiation_fp 1,1,1,1,5
+-ptx_opcode_latency_dp 8,8,8,8,335
+-ptx_opcode_initiation_dp 8,8,8,8,130
+
+# memory stage behaviour
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
+-gpgpu_cache:dl2_texture_only 1
+
+# TLB parameters
+#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8
+#-gpgpu_tlbl2_latency 45
+
+
+-gpgpu_shmem_warp_parts 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file icnt_config_islip.icnt 
+
+# dram scheduler config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (30 core cycles).  I.e. 
+#   Total buffer space required = 30 x 800MHz / 337.5MHz = 71
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 55
+
+# dram model config
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4 
+-gpgpu_dram_burst_length 4
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
+# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
+# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
+-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+
+
+
+# Using cuobjdump to extract ptx/SASS
+-gpgpu_ptx_use_cuobjdump 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+
+-visualizer_enabled 0
+-power_trace_enabled 0
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_quadrofx5600.xml 
+
+-steady_power_levels_enabled 1
+-steady_state_definition 8,4
diff --git a/configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
new file mode 100644
index 0000000..2c5a6fc
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="0"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="2"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="0"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="0"/>
+		<param name="core_tech_node" value="65"/><!-- nm -->
+		<param name="target_core_clockrate" value="650"/><!--MHz -->
+		<param name="temperature" value="400"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.54"/><!-- idle core power for GTX479 -->
+		<param name="TOT_INST" value="2" />
+		<param name="FP_INT" value="5" />
+		<param name="IC_H" value="10" />
+		<param name="IC_M" value="10" />
+		<param name="DC_RH" value="10" />
+		<param name="DC_RM" value="10" />
+		<param name="DC_WH" value="10" />
+		<param name="DC_WM" value="10" />
+		<param name="TC_H" value="20" />
+		<param name="TC_M" value="20" />
+		<param name="CC_H" value="10" />
+		<param name="CC_M" value="10" />
+		<param name="SHRD_ACC" value="20" />
+		<param name="REG_RD" value="0.25" />
+		<param name="REG_WR" value="0.4" />
+		<param name="NON_REG_OPs" value="0.4" />
+		<param name="SP_ACC" value="0.6" />
+		<param name="SFU_ACC" value="0.7" />
+		<param name="FPU_ACC" value="0.25" />
+		<param name="MEM_RD" value="0.3" />
+		<param name="MEM_WR" value="0.4" />
+		<param name="MEM_PRE" value="0.7" />
+		<param name="L2_RH" value="1" />
+		<param name="L2_RM" value="1" />
+		<param name="L2_WH" value="1" />
+		<param name="L2_WM" value="1" />
+		<param name="NOC_A" value="80" />
+		<param name="PIPE_A" value="0.8" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="9" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="650"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="1"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="1"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="1"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="1"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="8"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="16"/>
+			<param name="simd_width" value="8"/>
+			<param name="collector_units" value="16"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="8192"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="1"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="0.4"/>
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="1"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="1"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="65536,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="16384,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1300"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1300"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="100"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="786432,64,16,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1300"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="650"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="4"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="7"/>
+			<param name="output_ports" value="7"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="360000"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="65"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="8"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="800"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="9600"/><!--MB/S  Syed: Quadro FX 5800 has 76.8GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="8"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="1.53846154e-8f"/>
+			<param name="dram_rd_coeff" value="3.07692308e-8f"/>
+			<param name="dram_wr_coeff" value="1.30769231e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt b/configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt
new file mode 100644
index 0000000..de3bcc8
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt
@@ -0,0 +1,70 @@
+//14*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we donot use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 14;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt b/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt
new file mode 100644
index 0000000..cfe9cac
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt
@@ -0,0 +1,69 @@
+//18*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we donot use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 18;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config b/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config
new file mode 100644
index 0000000..fef1110
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config
@@ -0,0 +1,88 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 13
+
+# high level architecture configuration
+-gpgpu_n_clusters 10 
+-gpgpu_n_cores_per_cluster 3
+-gpgpu_n_mem 8 
+-gpgpu_clock_domains 325.0:650.0:650.0:800.0 
+
+# shader core pipeline config
+-gpgpu_shader_registers 16384
+-gpgpu_occupancy_sm_number 13
+
+-gpgpu_shader_core_pipeline 1024:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 1,1,1,1,1,1,1
+-gpgpu_num_sp_units 1
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 1,1,19,25,145
+-ptx_opcode_initiation_int 1,1,4,4,32
+-ptx_opcode_latency_fp 1,1,1,1,30
+-ptx_opcode_initiation_fp 1,1,1,1,5
+-ptx_opcode_latency_dp 8,8,8,8,335
+-ptx_opcode_initiation_dp 8,8,8,8,130
+
+# memory stage behaviour
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
+-gpgpu_cache:dl2_texture_only 1
+
+-gpgpu_shmem_warp_parts 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_quadro_islip.icnt
+
+# dram scheduler config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (30 core cycles).  I.e. 
+#   Total buffer space required = 30 x 800MHz / 325MHz = 74
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 58
+
+# dram model config
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4 
+-gpgpu_dram_burst_length 4
+-dram_data_command_freq_ratio 2  # GDDR3 is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
+# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
+-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+
+-visualizer_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt
new file mode 100644
index 0000000..2a69ddd
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 50;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
new file mode 100644
index 0000000..fb044c6
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
@@ -0,0 +1,150 @@
+# This config models the Pascal GP102 (GeForceGTX 1080Ti)
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 60
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 11
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 60
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# SFU is 32-width in pascal, then dp units initiation is 1 cycle
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 1,2,1,1,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory
+# Pascal GP102 has 64KB L1 cache
+# The default is to disable the L1 cache, unless cache modifieres is used
+-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,8
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
+-gpgpu_cache:dl2_texture_only 0 
+
+# 4 KB Inst.
+-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+
+# enable operand collector 
+## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
+-gpgpu_operand_collector_num_units_sp 20
+-gpgpu_operand_collector_num_units_sfu 4
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+# gpgpu_num_reg_banks should be increased to 32, but it gives an error!
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits)
+# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing from hynix H5GQ1H24AFR
+# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
+
+# Pascal has four schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml b/configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
new file mode 100755
index 0000000..02619ff
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="28"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="23"/><!-- nm -->
+		<param name="target_core_clockrate" value="1481"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="10" />
+		<param name="FP_INT" value="10" />
+		<param name="IC_H" value="0.001" />
+		<param name="IC_M" value="10" />
+		<param name="DC_RH" value="1" />
+		<param name="DC_RM" value="1" />
+		<param name="DC_WH" value="1" />
+		<param name="DC_WM" value="1" />
+		<param name="TC_H" value="0.001" />
+		<param name="TC_M" value="10" />
+		<param name="CC_H" value="4.5071" />
+		<param name="CC_M" value="10" />
+		<param name="SHRD_ACC" value="10" />
+		<param name="REG_RD" value="1.6294" />
+		<param name="REG_WR" value="0.5031" />
+		<param name="NON_REG_OPs" value="0.01" />
+		<param name="SP_ACC" value="10" />
+		<param name="SFU_ACC" value="0.0082" />
+		<param name="FPU_ACC" value="0.4126" />
+		<param name="MEM_RD" value="0.1234" />
+		<param name="MEM_WR" value="0.001" />
+		<param name="MEM_PRE" value="0.001" />
+		<param name="L2_RH" value="100" />
+		<param name="L2_RM" value="100" />
+		<param name="L2_WH" value="100" />
+		<param name="L2_WM" value="42.6966" />
+		<param name="NOC_A" value="100" />
+		<param name="PIPE_A" value="44.8085" />
+		<param name="IDLE_CORE_N" value="2.0382"/>
+		<param name="CONST_DYNAMICN" value="5.0005" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="1481"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="65536"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="2962"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="23"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt
new file mode 100644
index 0000000..d26c8d9
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 60;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/SM6_P100/gpgpusim.config b/configs/deprecated-cfgs/SM6_P100/gpgpusim.config
new file mode 100644
index 0000000..a5e6736
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_P100/gpgpusim.config
@@ -0,0 +1,156 @@
+# This config models the Pascal GP100
+# For more info about this card, see Nvidia White paper
+# https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 60
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 32
+-gpgpu_n_sub_partition_per_mchannel 1
+
+# Pscal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA GP100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Nvidia_Tesla
+-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 2,2,1,2,2,1,4
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# SFU is 32-width in pascal, then dp units initiation is 1 cycle
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 2,2,2,2,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP100 has 64KB Shared memory
+# Pascal GP100 has 48KB L1 cache
+-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_shmem_size 65536
+-gpgpu_shmem_size_PrefL1 65536
+-gpgpu_shmem_size_PrefShared 65536
+-gmem_skip_L1D 0
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
+
+# 4 KB Inst.
+-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+
+# enable operand collector
+-gpgpu_operand_collector_num_units_sp 14
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_units_mem 10
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml
new file mode 100755
index 0000000..304e0fd
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt
new file mode 100644
index 0000000..602daee
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config b/configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config
new file mode 100644
index 0000000..28912a3
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config
@@ -0,0 +1,157 @@
+# This config models the Pascal GP102 (NVIDIA TITAN X)
+# For more info about this card, see Nvidia White paper
+# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 61
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 61
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# SFU is 32-width in pascal, then dp units initiation is 1 cycle
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,8,4,4,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory
+# Pascal GP102 has 64KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres is used
+-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_shmem_size 98304
+-gpgpu_shmem_size_PrefL1 98304
+-gpgpu_shmem_size_PrefShared 98304
+-gmem_skip_L1D 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
+
+# 4 KB Inst.
+-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+
+# enable operand collector 
+## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
+-gpgpu_operand_collector_num_units_sp 20
+-gpgpu_operand_collector_num_units_sfu 4
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+# gpgpu_num_reg_banks should be increased to 32
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
+# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing from hynix H5GQ1H24AFR
+# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
new file mode 100755
index 0000000..304e0fd
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt
new file mode 100644
index 0000000..fac792a
--- /dev/null
+++ b/configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config b/configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config
new file mode 100644
index 0000000..aefb04a
--- /dev/null
+++ b/configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config
@@ -0,0 +1,165 @@
+# This config models the Volta Titan X
+# For more info about this card:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 24
+-gpgpu_n_sub_partition_per_mchannel 1
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA GP100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,1,4,4,1,9
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Volta GV100 has 64KB Shared memory
+-gpgpu_cache:dl1  64:128:8,L:L:m:N:H,A:256:8,16:0
+-gpgpu_cache:dl1PrefL1  64:128:16,L:L:m:N:H,A:256:8,16:0
+-gpgpu_cache:dl1PrefShared  32:128:6,L:L:m:N:H,A:256:8,16:0
+-gpgpu_shmem_size 65536
+-gpgpu_shmem_size_PrefL1 1
+-gpgpu_shmem_size_PrefShared 98304
+-gmem_skip_L1D 0
+
+# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
+-gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+
+# 128 KB Inst.
+-gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4
+
+# enable operand collector
+-gpgpu_operand_collector_num_units_sp 14
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_units_mem 10
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt b/configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt
new file mode 100644
index 0000000..a11bd8e
--- /dev/null
+++ b/configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//20*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we donot use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 26;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
diff --git a/configs/deprecated-cfgs/TeslaC2050/gpgpusim.config b/configs/deprecated-cfgs/TeslaC2050/gpgpusim.config
new file mode 100644
index 0000000..6ac2c12
--- /dev/null
+++ b/configs/deprecated-cfgs/TeslaC2050/gpgpusim.config
@@ -0,0 +1,133 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 20 
+
+# Using cuobjdump to extract ptx/SASS
+#-gpgpu_ptx_use_cuobjdump 1 # use default
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+
+# high level architecture configuration
+-gpgpu_n_clusters 14
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 6
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Fermi clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
+# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
+-gpgpu_clock_domains 575.0:575.0:575.0:750.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
+
+# This implies a maximum of 48 warps/SM
+-gpgpu_shader_core_pipeline 1536:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,1,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+
+# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
+-gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_shmem_size 49152
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_shmem_size 16384
+
+# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
+-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 750MHz / 575MHz = 130
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 114  
+
+# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt b/configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt
new file mode 100644
index 0000000..c399db9
--- /dev/null
+++ b/configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 27;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
new file mode 100644
index 0000000..4096b09
--- /dev/null
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -0,0 +1,153 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 20 
+
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 15
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 6
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Fermi clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
+# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
+-gpgpu_clock_domains 700.0:700.0:700.0:924.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
+
+# This implies a maximum of 48 warps/SM
+-gpgpu_shader_core_pipeline 1536:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+#For Fermi, DP unit =0, DP inst is executed on SFU
+-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+-gpgpu_num_dp_units 0
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,1,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+
+# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+-gpgpu_cache:dl1  N:32:128:4,L:L:m:N:H,S:64:8,8
+-gpgpu_shmem_size 49152
+-icnt_flit_size 40
+-gmem_skip_L1D 0
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 35
+-smem_latency 26
+-gpgpu_flush_l1_cache 1
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,S:64:8,8
+#-gpgpu_shmem_size 16384
+
+# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
+-gpgpu_cache:dl2 S:64:128:8,L:B:m:L:L,A:256:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 1
+-memory_partition_indexing 0
+
+-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4
+-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,T:128:4,128:2
+-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,S:2:32,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 20
+
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml b/configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
new file mode 100755
index 0000000..304e0fd
--- /dev/null
+++ b/configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="16"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="40"/><!-- nm -->
+		<param name="target_core_clockrate" value="700"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="2.00" />
+		<param name="FP_INT" value="4.57" />
+		<param name="IC_H" value="2.14" />
+		<param name="IC_M" value="22.47" />
+		<param name="DC_RH" value="22.14" />
+		<param name="DC_RM" value="24.66" />
+		<param name="DC_WH" value="1.53" />
+		<param name="DC_WM" value="39.79" />
+		<param name="TC_H" value="10.21" />
+		<param name="TC_M" value="24.66" />
+		<param name="CC_H" value="11.07" />
+		<param name="CC_M" value="12.33" />
+		<param name="SHRD_ACC" value="7.04" />
+		<param name="REG_RD" value="0.14" />
+		<param name="REG_WR" value="0.21" />
+		<param name="NON_REG_OPs" value="2.11" />
+		<param name="SP_ACC" value="2.38" />
+		<param name="SFU_ACC" value="0.51" />
+		<param name="FPU_ACC" value="0.64" />
+		<param name="MEM_RD" value="0.33" />
+		<param name="MEM_WR" value="0.40" />
+		<param name="MEM_PRE" value="0.11" />
+		<param name="L2_RH" value="13.79" />
+		<param name="L2_RM" value="35.18" />
+		<param name="L2_WH" value="43.07" />
+		<param name="L2_WM" value="28.72" />
+		<param name="NOC_A" value="305.48" />
+		<param name="PIPE_A" value="2.57" />
+		<param name="IDLE_CORE_N" value="1"/>
+		<param name="CONST_DYNAMICN" value="11" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="700"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="32768"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="40"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
new file mode 100644
index 0000000..dec4789
--- /dev/null
+++ b/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 64;
+input_buffer_size = 256;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
new file mode 100644
index 0000000..3842508
--- /dev/null
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -0,0 +1,185 @@
+# This config models the Pascal GP102 (NVIDIA TITAN X)
+# For more info about this card, see Nvidia White paper
+# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 61 
+-gpgpu_ignore_resources_limitation 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+# P102 has two semi-indp scheds per core, and two cores per cluster 
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 62
+
+# This implies a maximum of 32 warps/SM
+-gpgpu_shader_core_pipeline 1024:32 
+-gpgpu_shader_cta 16
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 2
+-gpgpu_num_dp_units 1
+
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,8,8,8,130
+-ptx_opcode_initiation_sfu 4
+-ptx_opcode_latency_sfu 8
+
+
+# latencies and cache configs are adopted from:
+# https://arxiv.org/pdf/1804.06826.pdf
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
+# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres are used
+-gpgpu_cache:dl1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 49152
+-gpgpu_shmem_size_PrefL1 49152
+-gpgpu_shmem_size_PrefShared 49152
+# By default, L1 cache is disabled in Pascal P102.
+# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
+-gmem_skip_L1D 1
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 82
+-smem_latency 24
+-gpgpu_flush_l1_cache 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
+-perf_sim_memcpy 1
+
+# 4 KB Inst.
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+# 48 KB Tex 
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_operand_collector_num_in_ports_sfu 2
+-gpgpu_operand_collector_num_out_ports_sfu 2
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+# Use Pascal Coalsce arhitetecture
+-gpgpu_coalesce_arch 61
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 240
+
+# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
+# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
+                        CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
+
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal 102 has four schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 102
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
new file mode 100644
index 0000000..2f25889
--- /dev/null
+++ b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
new file mode 100644
index 0000000..c8351da
--- /dev/null
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -0,0 +1,191 @@
+# This config models the Volta Titan X
+# For more info about this card:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 24
+-gpgpu_n_sub_partition_per_mchannel 1 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA GV100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1200.0:2000.0:1200.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 70
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+-gpgpu_flush_l1_cache 1
+
+# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
+-gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 1
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 100
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/cuobjdump_to_ptxplus/ptx_parser.h b/cuobjdump_to_ptxplus/ptx_parser.h
index a534e92..ee7a942 100644
--- a/cuobjdump_to_ptxplus/ptx_parser.h
+++ b/cuobjdump_to_ptxplus/ptx_parser.h
@@ -376,4 +376,8 @@ void func_header_info_int(const char* s, int i)
 		g_headerList->getListEnd().addOperand(buff);
 	}
 }
+
+void maxnt_id(int x, int y, int z) {
+
+}
 #endif //_PTX_PARSER_H_
diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc
index d67fd85..61af0ee 100644
--- a/libcuda/cuda_runtime_api.cc
+++ b/libcuda/cuda_runtime_api.cc
@@ -338,10 +338,19 @@ struct _cuda_device_id *GPGPUSim_Init()
 		prop->minor = 2;
 		prop->totalGlobalMem = 0x80000000 /* 2 GB */;
 		prop->memPitch = 0;
-		prop->maxThreadsPerBlock = 512;
-		prop->maxThreadsDim[0] = 512;
-		prop->maxThreadsDim[1] = 512;
-		prop->maxThreadsDim[2] = 512;
+		if(prop->major >= 2) {
+			prop->maxThreadsPerBlock = 1024;
+			prop->maxThreadsDim[0] = 1024;
+			prop->maxThreadsDim[1] = 1024;
+		}
+		else
+		{
+			prop->maxThreadsPerBlock = 512;
+			prop->maxThreadsDim[0] = 512;
+			prop->maxThreadsDim[1] = 512;
+		}
+
+		prop->maxThreadsDim[2] = 64;
 		prop->maxGridSize[0] = 0x40000000;
 		prop->maxGridSize[1] = 0x40000000;
 		prop->maxGridSize[2] = 0x40000000;
@@ -353,6 +362,9 @@ struct _cuda_device_id *GPGPUSim_Init()
 		prop->clockRate = the_gpu->shader_clock();
 #if (CUDART_VERSION >= 2010)
 		prop->multiProcessorCount = the_gpu->get_config().num_shader();
+#endif
+#if (CUDART_VERSION >= 4000)
+		prop->maxThreadsPerMultiProcessor = the_gpu->threads_per_core();
 #endif
 		the_gpu->set_prop(prop);
 		the_device = new _cuda_device_id(the_gpu);
@@ -2167,8 +2179,28 @@ cudaError_t CUDARTAPI cudaSetValidDevices(int *device_arr, int len)
 
 cudaError_t CUDARTAPI cudaSetDeviceFlags( int flags )
 {
-	cuda_not_implemented(__my_func__,__LINE__);
-	return g_last_cudaError = cudaErrorUnknown;
+    // This flag is implicitly always on (unless you are using the driver API). It is safe for GPGPU-Sim to
+    // just ignore it.
+    if ( cudaDeviceMapHost == flags ) {
+		return g_last_cudaError = cudaSuccess;
+    } else {
+	    cuda_not_implemented(__my_func__,__LINE__);
+	    return g_last_cudaError = cudaErrorUnknown;
+    }
+}
+
+size_t getMaxThreadsPerBlock(struct cudaFuncAttributes *attr) {
+  _cuda_device_id *dev = GPGPUSim_Init();
+  struct cudaDeviceProp prop;
+
+  prop = *dev->get_prop();
+
+  size_t max = prop.maxThreadsPerBlock;
+
+  if ((prop.regsPerBlock / attr->numRegs) < max)
+    max = prop.regsPerBlock / attr->numRegs;
+
+  return max;
 }
 
 cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, const char *hostFun )
@@ -2181,7 +2213,10 @@ cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, con
 		attr->constSizeBytes  = kinfo->cmem;
 		attr->localSizeBytes  = kinfo->lmem;
 		attr->numRegs         = kinfo->regs;
-		attr->maxThreadsPerBlock = 0; // from pragmas?
+		if(kinfo->maxthreads > 0)
+		  attr->maxThreadsPerBlock = kinfo->maxthreads;
+		else
+		  attr->maxThreadsPerBlock = getMaxThreadsPerBlock(attr);
 #if CUDART_VERSION >= 3000
 		attr->ptxVersion      = kinfo->ptx_version;
 		attr->binaryVersion   = kinfo->sm_target;
diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile
new file mode 100644
index 0000000..5221b3b
--- /dev/null
+++ b/nightly.jenkinsfile
@@ -0,0 +1,75 @@
+pipeline {
+    agent {
+        label "purdue-cluster"
+    }
+
+    options {
+        disableConcurrentBuilds()
+        overrideIndexTriggers(true)
+    }
+
+    triggers {
+        pollSCM('0 1 * * *')
+    }
+
+    stages {
+        stage('nightly-simulator-build') {
+            steps {
+                sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\
+                source `pwd`/setup_environment &&\
+                make -j'
+            }
+        }
+        stage('nightly-simulations-build'){
+            steps{
+                sh 'rm -rf gpgpu-sim_simulations'
+                sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \
+                    cd gpgpu-sim_simulations && \
+                    git checkout purdue-cluster && \
+                    git pull && \
+                    ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/'
+                sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\
+                    source `pwd`/setup_environment &&\
+                    cd gpgpu-sim_simulations && \
+                    source ./benchmarks/src/setup_environment && \
+                    make -i -j -C ./benchmarks/src/ all && \
+                    make -C ./benchmarks/src data'
+            }
+        }
+        stage('nightly-2B-insn-run'){
+            steps {
+                    sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\
+                    source `pwd`/setup_environment &&\
+                    ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C TITANX-2B,TITANX-L1ON-2B,P100-2B,TITANV-2B -N nightly-$$ && \
+                    PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/getstats" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \
+                    ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -I -S 1800 -v  -s stats-$$.csv -N nightly-$$ && \
+                    ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR'
+            }
+        }
+        stage('nightly-correlate'){
+            steps {
+                sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\
+                    source `pwd`/setup_environment &&\
+                    PLOTDIR="jenkins/${JOB_NAME}" &&\
+                    ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C TITANX-2B,TITANX-L1ON-2B,P100-2B,TITANV-2B > nightly-stats-per-kernel-9.1.csv &&\
+                    ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh nightly-stats-per-kernel-9.1.csv $PLOTDIR ${BUILD_NUMBER}'
+            }
+        }
+    }
+    post {
+        success {
+            emailext body: "See ${BUILD_URL}",
+                recipientProviders: [[$class: 'CulpritsRecipientProvider'],
+                    [$class: 'RequesterRecipientProvider']],
+                subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!",
+                to: 'tgrogers@purdue.edu'
+        }
+        failure {
+            emailext body: "See ${BUILD_URL}",
+                recipientProviders: [[$class: 'CulpritsRecipientProvider'],
+                    [$class: 'RequesterRecipientProvider']],
+                subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}",
+                to: 'tgrogers@purdue.edu'
+        }
+    }
+}
diff --git a/setup_environment b/setup_environment
index f1af978..9578942 100644
--- a/setup_environment
+++ b/setup_environment
@@ -1,6 +1,6 @@
 # see README before running this
 
-ps -p $$ | awk '/bash/ || / sh/ || /zsh/ {exit 1;}' && echo "ERROR ** source setup_environment must be run in a bash, zsh or sh shell; see README" && exit
+ps -p $$ | awk '/bash/ || / sh/ || /zsh/ {exit 1;}' && echo "WARNING ** source setup_environment must be run in a bash, zsh or sh shell; see README"
 
 export GPGPUSIM_SETUP_ENVIRONMENT_WAS_RUN=
 export GPGPUSIM_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )"
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index f7f1016..acb376a 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -316,12 +316,12 @@ void warp_inst_t::generate_mem_accesses()
         break;
 
     case global_space: case local_space: case param_space_local:
-        if( m_config->gpgpu_coalesce_arch == 13 ) {
-           if(isatomic())
-               memory_coalescing_arch_13_atomic(is_write, access_type);
-           else
-               memory_coalescing_arch_13(is_write, access_type);
-        } else abort();
+    	 if( m_config->gpgpu_coalesce_arch >= 13 && m_config->gpgpu_coalesce_arch <= 62) {
+            if(isatomic())
+                memory_coalescing_arch_atomic(is_write, access_type);
+            else
+                memory_coalescing_arch(is_write, access_type);
+         } else abort();
 
         break;
 
@@ -345,7 +345,7 @@ void warp_inst_t::generate_mem_accesses()
                 byte_mask.set(idx+i);
         }
         for( a=accesses.begin(); a != accesses.end(); ++a ) 
-            m_accessq.push_back( mem_access_t(access_type,a->first,cache_block_size,is_write,a->second,byte_mask) );
+            m_accessq.push_back( mem_access_t(access_type,a->first,cache_block_size,is_write,a->second, byte_mask, mem_access_sector_mask_t()));
     }
 
     if ( space.get_type() == global_space ) {
@@ -354,15 +354,32 @@ void warp_inst_t::generate_mem_accesses()
     m_mem_accesses_created=true;
 }
 
-void warp_inst_t::memory_coalescing_arch_13( bool is_write, mem_access_type access_type )
+void warp_inst_t::memory_coalescing_arch( bool is_write, mem_access_type access_type )
 {
     // see the CUDA manual where it discusses coalescing rules before reading this
     unsigned segment_size = 0;
     unsigned warp_parts = m_config->mem_warp_parts;
+    bool sector_segment_size = false;
+
+    if(m_config->gpgpu_coalesce_arch >= 20 && m_config->gpgpu_coalesce_arch < 39)
+    {
+    	//Fermi and Kepler, L1 is normal and L2 is sector
+    	if(m_config->gmem_skip_L1D || cache_op == CACHE_GLOBAL)
+    		sector_segment_size = true;
+    	else
+    		sector_segment_size = false;
+    }
+    else if(m_config->gpgpu_coalesce_arch >= 40)
+    {
+    	//Maxwell and Pascal, L1 and L2 are sectors
+    	//all requests should be 32 bytes
+    	sector_segment_size = true;
+    }
+
     switch( data_size ) {
     case 1: segment_size = 32; break;
-    case 2: segment_size = 64; break;
-    case 4: case 8: case 16: segment_size = 128; break;
+    case 2: segment_size = sector_segment_size? 32 : 64; break;
+    case 4: case 8: case 16: segment_size = sector_segment_size? 32 : 128; break;
     }
     unsigned subwarp_size = m_config->warp_size / warp_parts;
 
@@ -413,13 +430,13 @@ void warp_inst_t::memory_coalescing_arch_13( bool is_write, mem_access_type acce
             new_addr_type addr = t->first;
             const transaction_info &info = t->second;
 
-            memory_coalescing_arch_13_reduce_and_send(is_write, access_type, info, addr, segment_size);
+            memory_coalescing_arch_reduce_and_send(is_write, access_type, info, addr, segment_size);
 
         }
     }
 }
 
-void warp_inst_t::memory_coalescing_arch_13_atomic( bool is_write, mem_access_type access_type )
+void warp_inst_t::memory_coalescing_arch_atomic( bool is_write, mem_access_type access_type )
 {
 
    assert(space.get_type() == global_space); // Atomics allowed only for global memory
@@ -488,13 +505,13 @@ void warp_inst_t::memory_coalescing_arch_13_atomic( bool is_write, mem_access_ty
            for(t=transaction_list.begin(); t!=transaction_list.end(); t++) {
                // For each transaction
                const transaction_info &info = *t;
-               memory_coalescing_arch_13_reduce_and_send(is_write, access_type, info, addr, segment_size);
+               memory_coalescing_arch_reduce_and_send(is_write, access_type, info, addr, segment_size);
            }
        }
    }
 }
 
-void warp_inst_t::memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size )
+void warp_inst_t::memory_coalescing_arch_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size )
 {
    assert( (addr & (segment_size-1)) == 0 );
 
@@ -543,7 +560,7 @@ void warp_inst_t::memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_
            assert(lower_half_used && upper_half_used);
        }
    }
-   m_accessq.push_back( mem_access_t(access_type,addr,size,is_write,info.active,info.bytes) );
+   m_accessq.push_back( mem_access_t(access_type,addr,size,is_write,info.active,info.bytes, info.chunks) );
 }
 
 void warp_inst_t::completed( unsigned long long cycle ) const 
@@ -577,6 +594,8 @@ kernel_info_t::kernel_info_t( dim3 gridDim, dim3 blockDim, class function_info *
    
     //Jin: launch latency management
     m_launch_latency = g_kernel_launch_latency;
+
+    volta_cache_config_set=false;
 }
 
 kernel_info_t::~kernel_info_t()
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 71d3d89..a612bac 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -82,6 +82,7 @@ enum uarch_op_t {
    ALU_OP=1,
    SFU_OP,
    TENSOR_CORE_OP,
+   DP_OP,
    ALU_SFU_OP,
    LOAD_OP,
    TENSOR_CORE_LOAD_OP,
@@ -139,6 +140,7 @@ typedef enum special_operations_t special_ops; // Required to identify for the p
 enum operation_pipeline_t {
     UNKOWN_OP,
     SP__OP,
+	DP__OP,
     SFU__OP,
     TENSOR_CORE__OP,
     MEM__OP
@@ -308,6 +310,8 @@ public:
    unsigned long long start_cycle;
    unsigned long long end_cycle;
    unsigned m_launch_latency;
+
+   mutable bool volta_cache_config_set;
 };
 
 struct core_config {
@@ -347,6 +351,7 @@ struct core_config {
     unsigned gpgpu_cache_constl1_linesize;
 
 	unsigned gpgpu_max_insn_issue_per_warp;
+	bool gmem_skip_L1D; // on = global memory access always skip the L1 cache
 };
 
 // bounded stack that implements simt reconvergence using pdom mechanism from MICRO'07 paper
@@ -398,6 +403,7 @@ protected:
 #define LOCAL_MEM_SIZE_MAX (8*1024)
 #define MAX_STREAMING_MULTIPROCESSORS 64
 #define MAX_THREAD_PER_SM 2048
+#define MAX_WARP_PER_SM 64
 #define TOTAL_LOCAL_MEM_PER_SM (MAX_THREAD_PER_SM*LOCAL_MEM_SIZE_MAX)
 #define TOTAL_SHARED_MEM (MAX_STREAMING_MULTIPROCESSORS*SHARED_MEM_SIZE_MAX)
 #define TOTAL_LOCAL_MEM (MAX_STREAMING_MULTIPROCESSORS*MAX_THREAD_PER_SM*LOCAL_MEM_SIZE_MAX)
@@ -523,7 +529,14 @@ public:
     const struct textureReference* get_texref(const std::string &texname) const
     {
         std::map<std::string, const struct textureReference*>::const_iterator t=m_NameToTextureRef.find(texname);
-        assert( t != m_NameToTextureRef.end() );
+        if( t == m_NameToTextureRef.end() ) {
+	  // search for :: prefixed names
+	  std::string temp("::" + texname);
+	  t=m_NameToTextureRef.find(temp);
+	}
+
+	assert(t != m_NameToTextureRef.end());
+
         return t->second;
     }
     const struct cudaArray* get_texarray( const struct textureReference *texref ) const
@@ -574,6 +587,7 @@ struct gpgpu_ptx_sim_info
    int cmem;
    int gmem;
    int regs;
+   unsigned maxthreads;
    unsigned ptx_version;
    unsigned sm_target;
 };
@@ -625,6 +639,9 @@ private:
 
 const unsigned MAX_MEMORY_ACCESS_SIZE = 128;
 typedef std::bitset<MAX_MEMORY_ACCESS_SIZE> mem_access_byte_mask_t;
+const unsigned SECTOR_CHUNCK_SIZE = 4;   //four sectors
+const unsigned SECTOR_SIZE = 32 ;        //sector is 32 bytes width
+typedef std::bitset<SECTOR_CHUNCK_SIZE> mem_access_sector_mask_t;
 #define NO_PARTIAL_WRITE (mem_access_byte_mask_t())
 
 #define MEM_ACCESS_TYPE_TUP_DEF \
@@ -660,6 +677,7 @@ enum cache_operator_type {
     CACHE_ALL,          // .ca
     CACHE_LAST_USE,     // .lu
     CACHE_VOLATILE,     // .cv
+    CACHE_L1,     // .nc
                        
     // loads and stores 
     CACHE_STREAMING,    // .cs
@@ -689,8 +707,9 @@ public:
                  unsigned size, 
                  bool wr, 
                  const active_mask_t &active_mask,
-                 const mem_access_byte_mask_t &byte_mask )
-    : m_warp_mask(active_mask), m_byte_mask(byte_mask)
+                 const mem_access_byte_mask_t &byte_mask,
+		 const mem_access_sector_mask_t &sector_mask)
+    : m_warp_mask(active_mask), m_byte_mask(byte_mask), m_sector_mask(sector_mask)
    {
       init();
       m_type = type;
@@ -706,6 +725,7 @@ public:
    bool is_write() const { return m_write; }
    enum mem_access_type get_type() const { return m_type; }
    mem_access_byte_mask_t get_byte_mask() const { return m_byte_mask; }
+   mem_access_sector_mask_t get_sector_mask() const { return m_sector_mask; }
 
    void print(FILE *fp) const
    {
@@ -739,6 +759,7 @@ private:
    mem_access_type m_type;
    active_mask_t m_warp_mask;
    mem_access_byte_mask_t m_byte_mask;
+   mem_access_sector_mask_t m_sector_mask;
 
    static unsigned sm_next_access_uid;
 };
@@ -961,9 +982,9 @@ public:
     };
 
     void generate_mem_accesses();
-    void memory_coalescing_arch_13( bool is_write, mem_access_type access_type );
-    void memory_coalescing_arch_13_atomic( bool is_write, mem_access_type access_type );
-    void memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size );
+    void memory_coalescing_arch( bool is_write, mem_access_type access_type );
+    void memory_coalescing_arch_atomic( bool is_write, mem_access_type access_type );
+    void memory_coalescing_arch_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size );
 
     void add_callback( unsigned lane_id, 
                        void (*function)(const class inst_t*, class ptx_thread_info*),
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index d5c5c3d..87a0b9c 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -62,8 +62,8 @@ addr_t g_debug_pc = 0xBEEF1518;
 unsigned g_ptx_sim_num_insn = 0;
 unsigned gpgpu_param_num_shaders = 0;
 
-char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp;
-char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp;
+char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp,*opcode_latency_sfu;
+char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp,*opcode_initiation_sfu;
 char *cdp_latency_str;
 unsigned cdp_latency[5];
 
@@ -80,6 +80,10 @@ void ptx_opcocde_latency_options (option_parser_t opp) {
 			"Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>"
 			"Default 8,8,8,8,335",
 			"8,8,8,8,335");
+	option_parser_register(opp, "-ptx_opcode_latency_sfu", OPT_CSTR, &opcode_latency_sfu,
+			"Opcode latencies for SFU instructions"
+			"Default 8",
+			"8");
 	option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int,
 			"Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV>"
 			"Default 1,1,4,4,32",
@@ -92,6 +96,10 @@ void ptx_opcocde_latency_options (option_parser_t opp) {
 			"Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>"
 			"Default 8,8,8,8,130",
 			"8,8,8,8,130");
+	option_parser_register(opp, "-ptx_opcode_initiation_sfu", OPT_CSTR, &opcode_initiation_sfu,
+			"Opcode initiation intervals for sfu instructions"
+			"Default 8",
+			"8");
 	option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str,
 			"CDP API latency <cudaStreamCreateWithFlags, \
 cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, \
@@ -393,6 +401,10 @@ void gpgpu_t::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t coun
    char *src_data = (char*)src;
    for (unsigned n=0; n < count; n ++ ) 
       m_global_mem->write(dst_start_addr+n,1, src_data+n,NULL,NULL);
+
+   // Copy into the performance model.
+   extern gpgpu_sim* g_the_gpu; 
+   g_the_gpu->perf_memcpy_to_gpu(dst_start_addr, count);
    if(g_debug_execution >= 3) {
       printf( " done.\n");
       fflush(stdout);
@@ -408,6 +420,10 @@ void gpgpu_t::memcpy_from_gpu( void *dst, size_t src_start_addr, size_t count )
    unsigned char *dst_data = (unsigned char*)dst;
    for (unsigned n=0; n < count; n ++ ) 
       m_global_mem->read(src_start_addr+n,1,dst_data+n);
+
+   // Copy into the performance model.
+   extern gpgpu_sim* g_the_gpu; 
+   g_the_gpu->perf_memcpy_to_gpu(src_start_addr, count);
    if(g_debug_execution >= 3) {
       printf( " done.\n");
       fflush(stdout);
@@ -592,9 +608,11 @@ void ptx_instruction::set_opcode_and_latency()
 	unsigned int_latency[5];
 	unsigned fp_latency[5];
 	unsigned dp_latency[5];
+	unsigned sfu_latency;
 	unsigned int_init[5];
 	unsigned fp_init[5];
 	unsigned dp_init[5];
+	unsigned sfu_init;
 	/*
 	 * [0] ADD,SUB
 	 * [1] MAX,Min
@@ -611,7 +629,9 @@ void ptx_instruction::set_opcode_and_latency()
 	sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u",
 			&dp_latency[0],&dp_latency[1],&dp_latency[2],
 			&dp_latency[3],&dp_latency[4]);
-	sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u, %u",
+	sscanf(opcode_latency_sfu, "%u",
+			&sfu_latency);
+	sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u",
 			&int_init[0],&int_init[1],&int_init[2],
 			&int_init[3],&int_init[4]);
 	sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u",
@@ -620,8 +640,10 @@ void ptx_instruction::set_opcode_and_latency()
 	sscanf(opcode_initiation_dp, "%u,%u,%u,%u,%u",
 			&dp_init[0],&dp_init[1],&dp_init[2],
 			&dp_init[3],&dp_init[4]);
+	sscanf(opcode_initiation_sfu, "%u",
+			&sfu_init);
 	sscanf(cdp_latency_str, "%u,%u,%u,%u,%u",
-			&cdp_latency[0],&cdp_latency[1],&cdp_latency[2], 
+			&cdp_latency[0],&cdp_latency[1],&cdp_latency[2],
             &cdp_latency[3],&cdp_latency[4]);
 
 	if(!m_operands.empty()){
@@ -684,6 +706,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   case FF64_TYPE:
 		   latency = dp_latency[0];
 		   initiation_interval = dp_init[0];
+		   op = DP_OP;
 		   break;
 	   case B32_TYPE:
 	   case U32_TYPE:
@@ -705,6 +728,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   case FF64_TYPE:
 		   latency = dp_latency[1];
 		   initiation_interval = dp_init[1];
+		   op = DP_OP;
 		   break;
 	   case B32_TYPE:
 	   case U32_TYPE:
@@ -721,13 +745,12 @@ void ptx_instruction::set_opcode_and_latency()
 	   case F32_TYPE:
 		   latency = fp_latency[2];
 		   initiation_interval = fp_init[2];
-		   op = ALU_SFU_OP;
 		   break;
 	   case F64_TYPE:
 	   case FF64_TYPE:
 		   latency = dp_latency[2];
 		   initiation_interval = dp_init[2];
-		   op = ALU_SFU_OP;
+		   op = DP_OP;
 		   break;
 	   case B32_TYPE:
 	   case U32_TYPE:
@@ -750,6 +773,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   case FF64_TYPE:
 		   latency = dp_latency[3];
 		   initiation_interval = dp_init[3];
+		   op = DP_OP;
 		   break;
 	   case B32_TYPE:
 	   case U32_TYPE:
@@ -785,8 +809,8 @@ void ptx_instruction::set_opcode_and_latency()
 	   break;
    case SQRT_OP: case SIN_OP: case COS_OP: case EX2_OP: case LG2_OP: case RSQRT_OP: case RCP_OP:
 	   //Using double to approximate those
-	  latency = dp_latency[2];
-	  initiation_interval = dp_init[2];
+	  latency = sfu_latency;
+	  initiation_interval = sfu_init;
       op = SFU_OP;
       break;
    case MMA_OP:
@@ -796,7 +820,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   break;
    case SHFL_OP:
 	   latency = 32;
-	   initiation_interval = 15;
+	   initiation_interval = 4;
 	   break;
    default: 
        break;
@@ -889,6 +913,7 @@ void ptx_instruction::pre_decode()
 
    switch( m_cache_option ) {
    case CA_OPTION: cache_op = CACHE_ALL; break;
+   case NC_OPTION: cache_op = CACHE_L1; break;
    case CG_OPTION: cache_op = CACHE_GLOBAL; break;
    case CS_OPTION: cache_op = CACHE_STREAMING; break;
    case LU_OPTION: cache_op = CACHE_LAST_USE; break;
@@ -1169,13 +1194,13 @@ void function_info::finalize( memory_space *param_mem )
       // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over
       //Jin: copy parameter using aligned rules
       const size_t word_size = 4; 
-      param_address = (param_address + size - 1) / size * size; //aligned with size 
+      //param_address = (param_address + size - 1) / size * size; //aligned with size TODO: align not correct
       for (size_t idx = 0; idx < size; idx += word_size) {
          const char *pdata = reinterpret_cast<const char*>(param_value.pdata) + idx; // cast to char * for ptr arithmetic
          param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); 
       }
       unsigned offset = p.get_offset();
-      assert(offset == param_address);
+      //assert(offset == param_address);
       param->set_address(param_address);
       param_address += size;
    }
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 4614f25..973eeab 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -33,6 +33,7 @@
 #include "ptx.tab.h"
 #include <stdlib.h>
 #include <math.h>
+#include <cmath>
 #include <fenv.h>
 #include "cuda-math.h"
 #include "../abstract_hardware_model.h"
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index 8b901a3..45392fb 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -237,7 +237,8 @@ function_defn: function_decl { set_symtab($1); func_header(".skip"); } statement
 
 block_spec: MAXNTID_DIRECTIVE INT_OPERAND COMMA INT_OPERAND COMMA INT_OPERAND {func_header_info_int(".maxntid", $2);
 										func_header_info_int(",", $4);
-										func_header_info_int(",", $6); }
+										func_header_info_int(",", $6); 
+                                                                                maxnt_id($2, $4, $6);}
 	| MINNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".minnctapersm", $2); printf("GPGPU-Sim: Warning: .minnctapersm ignored. \n"); }
 	| MAXNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".maxnctapersm", $2); printf("GPGPU-Sim: Warning: .maxnctapersm ignored. \n"); }
 	;
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index d12c741..1813f8c 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -222,6 +222,7 @@ bool symbol_table::add_function_decl( const char *name, int entry_point, functio
    } else {
       *func_info = new function_info(entry_point);
       (*func_info)->set_name(name);
+      (*func_info)->set_maxnt_id(0);
       m_function_info_lookup[key] = *func_info;
    }
 
@@ -1234,16 +1235,16 @@ ptx_instruction::ptx_instruction( int opcode,
          m_inst_size = 4; // bytes
          break;
       case EXTP_OPTION:
-	 break;
+             break;
       case NC_OPTION:
-	 break;
+             m_cache_option = last_ptx_inst_option;
+             break;
       case UP_OPTION:
       case DOWN_OPTION:
       case BFLY_OPTION:
       case IDX_OPTION:
 		  m_shfl_op = last_ptx_inst_option;
 		  break;
-
       case PRMT_F4E_MODE:
       case PRMT_B4E_MODE:
       case PRMT_RC8_MODE:
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 0767379..4c36cfc 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -1333,6 +1333,7 @@ public:
 
    const struct gpgpu_ptx_sim_info* get_kernel_info () const
    {
+      assert (m_kernel_info.maxthreads == maxnt_id);
       return &m_kernel_info;
    }
 
@@ -1340,6 +1341,8 @@ public:
       m_kernel_info = info;
       m_kernel_info.ptx_version = 10*get_ptx_version().ver();
       m_kernel_info.sm_target = get_ptx_version().target();
+      // THIS DEPENDS ON ptxas being called after the PTX is parsed.
+      m_kernel_info.maxthreads = maxnt_id;
    }
    symbol_table *get_symtab()
    {
@@ -1363,7 +1366,11 @@ public:
    }
    bool is_entry_point() const { return m_entry_point; }
 
+   void set_maxnt_id(unsigned maxthreads) { maxnt_id = maxthreads;}
+   unsigned get_maxnt_id() { return maxnt_id;}
+
 private:
+   unsigned maxnt_id;
    unsigned m_uid;
    unsigned m_local_mem_framesize;
    bool m_entry_point;
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index 9671ab7..cf40365 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -1012,6 +1012,10 @@ void target_header3(char* a, char* b, char* c)
    g_global_symbol_table->set_sm_target(a,b,c);
 }
 
+void maxnt_id(int x, int y, int z) {
+  g_func_info->set_maxnt_id(x * y * z);
+}
+
 void func_header(const char* a) {} //intentional dummy function
 void func_header_info(const char* a) {} //intentional dummy function
 void func_header_info_int(const char* a, int b) {} //intentional dummy function
diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h
index 8094b43..7b6e3a2 100644
--- a/src/cuda-sim/ptx_parser.h
+++ b/src/cuda-sim/ptx_parser.h
@@ -95,6 +95,7 @@ void change_double_operand_type( int addr_type );
 void change_operand_neg( );
 void set_immediate_operand_type( );
 void version_header(double a);
+void maxnt_id(int x, int y, int z);
 
 //Jin: handle instructino group for cdp
 void start_inst_group();
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index 422576d..8651869 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -62,6 +62,9 @@ void linear_to_raw_address_translation::addrdec_setoption(option_parser_t opp)
    option_parser_register(opp, "-gpgpu_mem_address_mask", OPT_INT32, &gpgpu_mem_address_mask, 
                "0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits",
                "0");
+   option_parser_register(opp, "-memory_partition_indexing", OPT_UINT32, &memory_partition_indexing,
+                  "0 = no indexing, 1 = bitwise xoring, 2 = IPoly, 3 = custom indexing",
+                  "0");
 }
 
 new_addr_type linear_to_raw_address_translation::partition_address( new_addr_type addr ) const 
@@ -103,6 +106,74 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_
       tlx->burst= addrdec_packbits(addrdec_mask[BURST], rest_of_addr, addrdec_mkhigh[BURST], addrdec_mklow[BURST]);
    }
 
+    switch(memory_partition_indexing){
+		case CONSECUTIVE:
+			//Do nothing
+			break;
+		case BITWISE_PERMUTATION:
+		{
+			assert(!gap);
+			tlx->chip = (tlx->chip) ^ (tlx->row & (m_n_channel-1));
+			assert(tlx->chip < m_n_channel);
+			break;
+		}
+		case IPOLY:
+		{
+		    /*
+			* Set Indexing function from "Pseudo-randomly interleaved memory."
+			* Rau, B. R et al.
+			* ISCA 1991
+			*
+			* equations are adopted from:
+			* "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu cache management scheme."
+			* Khairy et al.
+			* IEEE TPDS 2017.
+			*/
+			if(m_n_channel == 32) {
+				std::bitset<64> a(tlx->row);
+				std::bitset<5> chip(tlx->chip);
+				chip[0] = a[13]^a[12]^a[11]^a[10]^a[9]^a[6]^a[5]^a[3]^a[0]^chip[0];
+				chip[1] = a[14]^a[13]^a[12]^a[11]^a[10]^a[7]^a[6]^a[4]^a[1]^chip[1];
+				chip[2] = a[14]^a[10]^a[9]^a[8]^a[7]^a[6]^a[3]^a[2]^a[0]^chip[2];
+				chip[3] = a[11]^a[10]^a[9]^a[8]^a[7]^a[4]^a[3]^a[1]^chip[3];
+				chip[4] = a[12]^a[11]^a[10]^a[9]^a[8]^a[5]^a[4]^a[2]^chip[4];
+				tlx->chip = chip.to_ulong();
+				
+			}
+			else{ /* Else incorrect number of channels for the hashing function */
+            assert("\nGPGPU-Sim memory_partition_indexing error: The number of channels should be "
+                    "32 for the hashing IPOLY index function.\n" && 0);
+			}
+			assert(tlx->chip < m_n_channel);
+			break;
+		}
+		case PAE:
+		{
+			//Page Address Entropy
+			//random selected bits from the page and bank bits
+			//similar to
+			//Liu, Yuxi, et al. "Get Out of the Valley: Power-Efficient Address Mapping for GPUs." ISCA 2018
+			std::bitset<64> a(tlx->row);
+			std::bitset<5> chip(tlx->chip);
+			std::bitset<4> b(tlx->bk);
+			chip[0] = a[13]^a[10]^a[9]^a[5]^a[0]^b[3]^b[0]^chip[0];
+			chip[1] = a[12]^a[11]^a[6]^a[1]^b[3]^b[2]^b[1]^chip[1];
+			chip[2] = a[14]^a[9]^a[8]^a[7]^a[2]^b[1]^chip[2];
+			chip[3] = a[11]^a[10]^a[8]^a[3]^b[2]^b[3]^chip[3];
+			chip[4] = a[12]^a[9]^a[8]^a[5]^a[4]^b[1]^b[0]^chip[4];
+			tlx->chip = chip.to_ulong();
+			assert(tlx->chip < m_n_channel);
+			break;
+		}
+		case CUSTOM:
+			/* No custom set function implemented */
+			//Do you custom index here
+			break;
+		default:
+			 assert("\nUndefined set index function.\n" && 0);
+			 break;
+	}
+
    // combine the chip address and the lower bits of DRAM bank address to form the subpartition ID
    unsigned sub_partition_addr_mask = m_n_sub_partition_in_channel - 1; 
    tlx->sub_partition = tlx->chip * m_n_sub_partition_in_channel
diff --git a/src/gpgpu-sim/addrdec.h b/src/gpgpu-sim/addrdec.h
index fd9af8d..bdc5fec 100644
--- a/src/gpgpu-sim/addrdec.h
+++ b/src/gpgpu-sim/addrdec.h
@@ -35,6 +35,14 @@
 
 #include "../abstract_hardware_model.h"
 
+enum partition_index_function{
+	CONSECUTIVE = 0,
+	BITWISE_PERMUTATION,
+	IPOLY,
+	PAE,
+    CUSTOM
+};
+
 struct addrdec_t {
    void print( FILE *fp ) const;
     
@@ -72,6 +80,7 @@ private:
 
    const char *addrdec_option;
    int gpgpu_mem_address_mask;
+   partition_index_function memory_partition_indexing;
    bool run_test; 
 
    int ADDR_CHIP_S;
diff --git a/src/gpgpu-sim/delayqueue.h b/src/gpgpu-sim/delayqueue.h
index b25f143..0caa5d4 100644
--- a/src/gpgpu-sim/delayqueue.h
+++ b/src/gpgpu-sim/delayqueue.h
@@ -161,6 +161,7 @@ public:
    }
 
    bool full() const { return (m_max_len && m_length >= m_max_len); }
+   bool is_avilable_size(unsigned size) const { return (m_max_len && m_length+size-1 >= m_max_len); }
    bool empty() const { return m_head == NULL; }
    unsigned get_n_element() const { return m_n_element; }
    unsigned get_length() const { return m_length; }
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index a0e024b..6c11b43 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -49,11 +49,45 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m
    m_stats = stats;
    m_config = config;
 
+   //rowblp
+   access_num=0;
+   hits_num=0;
+   read_num=0;
+   write_num=0;
+   hits_read_num=0;
+   hits_write_num=0;
+   banks_1time=0;
+   banks_acess_total=0;
+   banks_acess_total_after=0;
+   banks_time_ready=0;
+   banks_access_ready_total=0;
+   issued_two=0;
+   issued_total=0;
+   issued_total_row=0;
+   issued_total_col=0;
+
    CCDc = 0;
    RRDc = 0;
    RTWc = 0;
    WTRc = 0;
 
+   wasted_bw_row=0;
+   wasted_bw_col=0;
+   util_bw=0;
+   idle_bw=0;
+   RCDc_limit=0;
+   CCDLc_limit=0;
+   CCDLc_limit_alone=0;
+   CCDc_limit=0;
+   WTRc_limit=0;
+   WTRc_limit_alone=0;
+   RCDWRc_limit=0;
+   RTWc_limit=0;
+   RTWc_limit_alone=0;
+   rwq_limit=0;
+   write_to_read_ratio_blp_rw_average=0;
+   bkgrp_parallsim_rw=0;
+
    rw = READ; //read mode is default
 
 	bkgrp = (bankgrp_t**) calloc(sizeof(bankgrp_t*), m_config->nbkgrp);
@@ -74,12 +108,13 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m
       bk[i]->state = BANK_IDLE;
       bk[i]->bkgrpindex = i/(m_config->nbk/m_config->nbkgrp);
    }
-   prio = 0;  
+   prio = 0;
+
    rwq = new fifo_pipeline<dram_req_t>("rwq",m_config->CL,m_config->CL+1);
    mrqq = new fifo_pipeline<dram_req_t>("mrqq",0,2);
    returnq = new fifo_pipeline<mem_fetch>("dramreturnq",0,m_config->gpgpu_dram_return_queue_size==0?1024:m_config->gpgpu_dram_return_queue_size); 
    m_frfcfs_scheduler = NULL;
-   if ( m_config->scheduler_type == DRAM_FRFCFS )
+   if ( m_config->scheduler_type == DRAM_FRFCFS)
       m_frfcfs_scheduler = new frfcfs_scheduler(m_config,this,stats);
    n_cmd = 0;
    n_activity = 0;
@@ -88,6 +123,8 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m
    n_pre = 0; 
    n_rd = 0;
    n_wr = 0;
+   n_wr_WB=0;
+   n_rd_L2_A=0;
    n_req = 0;
    max_mrqs_temp = 0;
    bwutil = 0;
@@ -113,13 +150,21 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m
       mrqq_Dist = StatCreate("mrqq_length",1, queue_limit());
    else //queue length is unlimited; 
       mrqq_Dist = StatCreate("mrqq_length",1,64); //track up to 64 entries
+
 }
 
-bool dram_t::full() const 
+bool dram_t::full(bool is_write) const
 {
-    if(m_config->scheduler_type == DRAM_FRFCFS ){
+    if(m_config->scheduler_type == DRAM_FRFCFS){
         if(m_config->gpgpu_frfcfs_dram_sched_queue_size == 0 ) return false;
-        return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_frfcfs_dram_sched_queue_size;
+        if(m_config->seperate_write_queue_enabled){
+        	if(is_write)
+        		return m_frfcfs_scheduler->num_write_pending() >= m_config->gpgpu_frfcfs_dram_write_queue_size;
+        	else
+        		return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_frfcfs_dram_sched_queue_size;
+        }
+        else
+        	return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_frfcfs_dram_sched_queue_size;
     }
    else return mrqq->full();
 }
@@ -127,7 +172,7 @@ bool dram_t::full() const
 unsigned dram_t::que_length() const
 {
    unsigned nreqs = 0;
-   if (m_config->scheduler_type == DRAM_FRFCFS ) {
+   if (m_config->scheduler_type == DRAM_FRFCFS) {
       nreqs = m_frfcfs_scheduler->num_pending();
    } else {
       nreqs = mrqq->get_length();
@@ -146,7 +191,7 @@ unsigned int dram_t::queue_limit() const
 }
 
 
-dram_req_t::dram_req_t( class mem_fetch *mf )
+dram_req_t::dram_req_t( class mem_fetch *mf, unsigned banks, unsigned dram_bnk_indexing_policy)
 {
    txbytes = 0;
    dqbytes = 0;
@@ -154,7 +199,29 @@ dram_req_t::dram_req_t( class mem_fetch *mf )
 
    const addrdec_t &tlx = mf->get_tlx_addr();
 
-   bk  = tlx.bk; 
+    switch(dram_bnk_indexing_policy){
+		case LINEAR_BK_INDEX:
+		{
+			bk = tlx.bk;
+			break;
+		}
+		case BITWISE_XORING_BK_INDEX:
+		{
+			//xoring bank bits with lower bits of the page
+			int lbank = log2(banks);
+			bk  = tlx.bk ^ (tlx.row & ((1<<lbank)-1));
+			break;
+		}
+		case CUSTOM_BK_INDEX:
+	        /* No custom set function implemented */
+			//Do you custom index here
+			break;
+		default:
+			 assert("\nUndefined bank index function.\n" && 0);
+			 break;
+	}
+
+
    row = tlx.row; 
    col = tlx.col; 
    nbytes = mf->get_data_size();
@@ -169,14 +236,15 @@ void dram_t::push( class mem_fetch *data )
 {
    assert(id == data->get_tlx_addr().chip); // Ensure request is in correct memory partition
 
-   dram_req_t *mrq = new dram_req_t(data);
+   dram_req_t *mrq = new dram_req_t(data,m_config->nbk,m_config->dram_bnk_indexing_policy);
+
    data->set_status(IN_PARTITION_MC_INTERFACE_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
-   mrqq->push(mrq);
+	   mrqq->push(mrq);
 
    // stats...
    n_req += 1;
    n_req_partial += 1;
-   if ( m_config->scheduler_type == DRAM_FRFCFS ) {
+   if ( m_config->scheduler_type == DRAM_FRFCFS) {
       unsigned nreqs = m_frfcfs_scheduler->num_pending();
       if ( nreqs > max_mrqs_temp)
          max_mrqs_temp = nreqs;
@@ -212,6 +280,7 @@ void dram_t::cycle()
            printf("\tDQ: BK%d Row:%03x Col:%03x", cmd->bk, cmd->row, cmd->col + cmd->dqbytes);
 #endif
            cmd->dqbytes += m_config->dram_atom_size; 
+
            if (cmd->dqbytes >= cmd->nbytes) {
               mem_fetch *data = cmd->data; 
               data->set_status(IN_PARTITION_MC_RETURNQ,gpu_sim_cycle+gpu_tot_sim_cycle); 
@@ -240,7 +309,7 @@ void dram_t::cycle()
 		printf("Error: Unknown DRAM scheduler type\n");
 		assert(0);
    }
-   if ( m_config->scheduler_type == DRAM_FRFCFS ) {
+   if ( m_config->scheduler_type == DRAM_FRFCFS) {
       unsigned nreqs = m_frfcfs_scheduler->num_pending();
       if ( nreqs > max_mrqs) {
          max_mrqs = nreqs;
@@ -258,130 +327,123 @@ void dram_t::cycle()
    unsigned k=m_config->nbk;
    bool issued = false;
 
-   // check if any bank is ready to issue a new read
+   //collect row buffer locality, BLP and other statistics
+   /////////////////////////////////////////////////////////////////////////
+   unsigned int memory_pending=0;
    for (unsigned i=0;i<m_config->nbk;i++) {
-      unsigned j = (i + prio) % m_config->nbk;
-	  unsigned grp = j>>m_config->bk_tag_length;
-      if (bk[j]->mrq) { //if currently servicing a memory request
-          bk[j]->mrq->data->set_status(IN_PARTITION_DRAM,gpu_sim_cycle+gpu_tot_sim_cycle);
-         // correct row activated for a READ
-         if ( !issued && !CCDc && !bk[j]->RCDc &&
-              !(bkgrp[grp]->CCDLc) &&
-              (bk[j]->curr_row == bk[j]->mrq->row) && 
-              (bk[j]->mrq->rw == READ) && (WTRc == 0 )  &&
-              (bk[j]->state == BANK_ACTIVE) &&
-              !rwq->full() ) {
-            if (rw==WRITE) {
-               rw=READ;
-               rwq->set_min_length(m_config->CL);
-            }
-            rwq->push(bk[j]->mrq);
-            bk[j]->mrq->txbytes += m_config->dram_atom_size; 
-            CCDc = m_config->tCCD;
-            bkgrp[grp]->CCDLc = m_config->tCCDL;
-            RTWc = m_config->tRTW;
-            bk[j]->RTPc = m_config->BL/m_config->data_command_freq_ratio;
-            bkgrp[grp]->RTPLc = m_config->tRTPL;
-            issued = true;
-            n_rd++;
-            bwutil += m_config->BL/m_config->data_command_freq_ratio;
-            bwutil_partial += m_config->BL/m_config->data_command_freq_ratio;
-            bk[j]->n_access++;
-#ifdef DRAM_VERIFY
-            PRINT_CYCLE=1;
-            printf("\tRD  Bk:%d Row:%03x Col:%03x \n",
-                   j, bk[j]->curr_row,
-                   bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size);
-#endif            
-            // transfer done
-            if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) {
-               bk[j]->mrq = NULL;
-            }
-         } else
-            // correct row activated for a WRITE
-            if ( !issued && !CCDc && !bk[j]->RCDWRc &&
-                 !(bkgrp[grp]->CCDLc) &&
-                 (bk[j]->curr_row == bk[j]->mrq->row)  && 
-                 (bk[j]->mrq->rw == WRITE) && (RTWc == 0 )  &&
-                 (bk[j]->state == BANK_ACTIVE) &&
-                 !rwq->full() ) {
-            if (rw==READ) {
-               rw=WRITE;
-               rwq->set_min_length(m_config->WL);
-            }
-            rwq->push(bk[j]->mrq);
-
-            bk[j]->mrq->txbytes += m_config->dram_atom_size; 
-            CCDc = m_config->tCCD;
-            bkgrp[grp]->CCDLc = m_config->tCCDL;
-            WTRc = m_config->tWTR; 
-            bk[j]->WTPc = m_config->tWTP; 
-            issued = true;
-            n_wr++;
-            bwutil += m_config->BL/m_config->data_command_freq_ratio;
-            bwutil_partial += m_config->BL/m_config->data_command_freq_ratio;
-#ifdef DRAM_VERIFY
-            PRINT_CYCLE=1;
-            printf("\tWR  Bk:%d Row:%03x Col:%03x \n",
-                   j, bk[j]->curr_row, 
-                   bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size);
-#endif  
-            // transfer done 
-            if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) {
-               bk[j]->mrq = NULL;
-            }
-         }
-
-         else
-            // bank is idle
-            if ( !issued && !RRDc && 
-                 (bk[j]->state == BANK_IDLE) &&
-                 !bk[j]->RPc && !bk[j]->RCc ) {
-#ifdef DRAM_VERIFY
-            PRINT_CYCLE=1;
-            printf("\tACT BK:%d NewRow:%03x From:%03x \n",
-                   j,bk[j]->mrq->row,bk[j]->curr_row);
-#endif
-            // activate the row with current memory request 
-            bk[j]->curr_row = bk[j]->mrq->row;
-            bk[j]->state = BANK_ACTIVE;
-            RRDc = m_config->tRRD;
-            bk[j]->RCDc = m_config->tRCD;
-            bk[j]->RCDWRc = m_config->tRCDWR;
-            bk[j]->RASc = m_config->tRAS;
-            bk[j]->RCc = m_config->tRC;
-            prio = (j + 1) % m_config->nbk;
-            issued = true;
-            n_act_partial++;
-            n_act++;
-         }
-
-         else
-            // different row activated
-            if ( (!issued) && 
-                 (bk[j]->curr_row != bk[j]->mrq->row) &&
-                 (bk[j]->state == BANK_ACTIVE) && 
-                 (!bk[j]->RASc && !bk[j]->WTPc && 
-				  !bk[j]->RTPc &&
-				  !bkgrp[grp]->RTPLc) ) {
-            // make the bank idle again
-            bk[j]->state = BANK_IDLE;
-            bk[j]->RPc = m_config->tRP;
-            prio = (j + 1) % m_config->nbk;
-            issued = true;
-            n_pre++;
-            n_pre_partial++;
-#ifdef DRAM_VERIFY
-            PRINT_CYCLE=1;
-            printf("\tPRE BK:%d Row:%03x \n", j,bk[j]->curr_row);
-#endif
-         }
-      } else {
-         if (!CCDc && !RRDc && !RTWc && !WTRc && !bk[j]->RCDc && !bk[j]->RASc
-             && !bk[j]->RCc && !bk[j]->RPc  && !bk[j]->RCDWRc) k--;
-         bk[j]->n_idle++;
-      }
+	   if (bk[i]->mrq)
+		   memory_pending++;
    }
+   banks_1time += memory_pending;
+   if(memory_pending >0)
+	   banks_acess_total++;
+
+   unsigned int memory_pending_rw=0;
+   unsigned read_blp_rw=0;
+   unsigned write_blp_rw=0;
+   std::bitset<8> bnkgrp_rw_found;  //assume max we have 8 bank groups
+
+   for (unsigned j=0;j<m_config->nbk;j++) {
+  	   unsigned grp = get_bankgrp_number(j);
+  	   if (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) &&
+  		  (bk[j]->mrq->rw == READ)  &&
+  		  (bk[j]->state == BANK_ACTIVE))))
+  	   {
+  		    memory_pending_rw++;
+  		    read_blp_rw++;
+  		    bnkgrp_rw_found.set(grp);
+  	   }
+  	   else if
+  	        (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row)  &&
+  			 (bk[j]->mrq->rw == WRITE) &&
+  			 (bk[j]->state == BANK_ACTIVE))))
+  	   {
+  		     memory_pending_rw++;
+  		     write_blp_rw++;
+  		     bnkgrp_rw_found.set(grp);
+  	   }
+     }
+     banks_time_rw += memory_pending_rw;
+     bkgrp_parallsim_rw += bnkgrp_rw_found.count();
+     if(memory_pending_rw >0)
+     {
+    	 write_to_read_ratio_blp_rw_average += (double)write_blp_rw/(write_blp_rw+read_blp_rw);
+  	     banks_access_rw_total++;
+     }
+
+   unsigned int memory_Pending_ready=0;
+   for (unsigned j=0;j<m_config->nbk;j++) {
+	   unsigned grp = get_bankgrp_number(j);
+	   if (bk[j]->mrq && ((!CCDc && !bk[j]->RCDc &&
+		  !(bkgrp[grp]->CCDLc) &&
+		  (bk[j]->curr_row == bk[j]->mrq->row) &&
+		  (bk[j]->mrq->rw == READ) && (WTRc == 0 )  &&
+		  (bk[j]->state == BANK_ACTIVE) &&
+		  !rwq->full())
+		   ||
+		   (!CCDc && !bk[j]->RCDWRc &&
+			 !(bkgrp[grp]->CCDLc) &&
+			 (bk[j]->curr_row == bk[j]->mrq->row)  &&
+			 (bk[j]->mrq->rw == WRITE) && (RTWc == 0 )  &&
+			 (bk[j]->state == BANK_ACTIVE) &&
+			 !rwq->full())))
+	   {
+		   memory_Pending_ready++;
+	   }
+   }
+   banks_time_ready += memory_Pending_ready;
+   if(memory_Pending_ready >0)
+	   banks_access_ready_total++;
+   ///////////////////////////////////////////////////////////////////////////////////
+
+   bool issued_col_cmd = false;
+   bool issued_row_cmd = false;
+
+   if(m_config->dual_bus_interface)
+   {
+	   //dual bus interface
+	   //issue one row command and one column command
+	     for (unsigned i=0;i<m_config->nbk;i++) {
+	       unsigned j = (i + prio) % m_config->nbk;
+	  	   issued_col_cmd  = issue_col_command(j);
+	  	   if(issued_col_cmd) break;
+	     }
+	     for (unsigned i=0;i<m_config->nbk;i++) {
+	    	unsigned j = (i + prio) % m_config->nbk;
+	  	    issued_row_cmd = issue_row_command(j);
+	  	    if(issued_row_cmd) break;
+	     }
+	     for (unsigned i=0;i<m_config->nbk;i++) {
+	    	 unsigned j = (i + prio) % m_config->nbk;
+	    	 if(!bk[j]->mrq) {
+				  if (!CCDc && !RRDc && !RTWc && !WTRc && !bk[j]->RCDc && !bk[j]->RASc
+					  && !bk[j]->RCc && !bk[j]->RPc  && !bk[j]->RCDWRc) k--;
+				  bk[j]->n_idle++;
+			}
+	     }
+   }
+   else
+   {
+	   //single bus interface
+	   //issue only one row/column command
+	   for (unsigned i=0;i<m_config->nbk;i++) {
+		   unsigned j = (i + prio) % m_config->nbk;
+		   if(!issued_col_cmd)
+		       issued_col_cmd  = issue_col_command(j);
+
+		   if(!issued_col_cmd && !issued_row_cmd)
+		       issued_row_cmd = issue_row_command(j);
+
+		   if(!bk[j]->mrq) {
+		          if (!CCDc && !RRDc && !RTWc && !WTRc && !bk[j]->RCDc && !bk[j]->RASc
+		              && !bk[j]->RCc && !bk[j]->RPc  && !bk[j]->RCDWRc) k--;
+		          bk[j]->n_idle++;
+		    }
+
+	   }
+   }
+
+   issued = issued_row_cmd || issued_col_cmd;
    if (!issued) {
       n_nop++;
       n_nop_partial++;
@@ -395,6 +457,85 @@ void dram_t::cycle()
    }
    n_cmd++;
    n_cmd_partial++;
+   if(issued)
+   {
+	   issued_total++;
+	   if(issued_col_cmd && issued_row_cmd)
+		   issued_two++;
+   }
+   if(issued_col_cmd)  issued_total_col++;
+   if(issued_row_cmd)  issued_total_row++;
+
+
+   //Collect some statistics
+   //check the limitation, see where BW is wasted?
+   /////////////////////////////////////////////////////////
+   unsigned int memory_pending_found=0;
+      for (unsigned i=0;i<m_config->nbk;i++) {
+   	   if (bk[i]->mrq)
+   		memory_pending_found++;
+      }
+      if(memory_pending_found>0)
+    	  banks_acess_total_after++;
+
+        bool memory_pending_rw_found=false;
+        for (unsigned j=0;j<m_config->nbk;j++) {
+     	   unsigned grp = get_bankgrp_number(j);
+     	   if (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) &&
+     		  (bk[j]->mrq->rw == READ)  &&
+     		  (bk[j]->state == BANK_ACTIVE))
+     		   ||
+     		   (
+     			 (bk[j]->curr_row == bk[j]->mrq->row)  &&
+     			 (bk[j]->mrq->rw == WRITE) &&
+     			 (bk[j]->state == BANK_ACTIVE))))
+     		  memory_pending_rw_found=true;
+        }
+
+
+   if(issued_col_cmd  || CCDc)
+	   util_bw++;
+   else if (memory_pending_rw_found)
+   {
+	   wasted_bw_col++;
+	   for (unsigned j=0;j<m_config->nbk;j++) {
+		   unsigned grp = get_bankgrp_number(j);
+		   //read
+		   if (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) &&
+			  (bk[j]->mrq->rw == READ)  &&
+			  (bk[j]->state == BANK_ACTIVE))))
+		   {
+			   if(bk[j]->RCDc) RCDc_limit++;
+			   if(bkgrp[grp]->CCDLc) CCDLc_limit++;
+			   if(WTRc) WTRc_limit++;
+			   if(CCDc) CCDc_limit++;
+			   if(rwq->full()) rwq_limit++;
+			   if(bkgrp[grp]->CCDLc && !WTRc) CCDLc_limit_alone++;
+			   if(!bkgrp[grp]->CCDLc && WTRc) WTRc_limit_alone++;
+		   }
+		   //write
+		   else if (bk[j]->mrq && ((bk[j]->curr_row == bk[j]->mrq->row)  &&
+				 (bk[j]->mrq->rw == WRITE) &&
+				 (bk[j]->state == BANK_ACTIVE)))
+		   {
+			   if(bk[j]->RCDWRc) RCDWRc_limit++;
+			   if(bkgrp[grp]->CCDLc) CCDLc_limit++;
+			   if(RTWc) RTWc_limit++;
+			   if(CCDc) CCDc_limit++;
+			   if(rwq->full()) rwq_limit++;
+			   if(bkgrp[grp]->CCDLc && !RTWc) CCDLc_limit_alone++;
+			   if(!bkgrp[grp]->CCDLc && RTWc) RTWc_limit_alone++;
+		   }
+	     }
+   }
+   else if (memory_pending_found)
+	   wasted_bw_row++;
+   else if (!memory_pending_found)
+  	   idle_bw++;
+   else
+	   assert(1);
+
+   /////////////////////////////////////////////////////////
 
    // decrements counters once for each time dram_issueCMD is called
    DEC2ZERO(RRDc);
@@ -420,39 +561,237 @@ void dram_t::cycle()
 #endif
 }
 
+bool dram_t::issue_col_command(int j)
+{
+	bool issued = false;
+	unsigned grp = get_bankgrp_number(j);
+    if (bk[j]->mrq) { //if currently servicing a memory request
+        bk[j]->mrq->data->set_status(IN_PARTITION_DRAM,gpu_sim_cycle+gpu_tot_sim_cycle);
+       // correct row activated for a READ
+       if ( !issued && !CCDc && !bk[j]->RCDc &&
+            !(bkgrp[grp]->CCDLc) &&
+            (bk[j]->curr_row == bk[j]->mrq->row) &&
+            (bk[j]->mrq->rw == READ) && (WTRc == 0 )  &&
+            (bk[j]->state == BANK_ACTIVE) &&
+            !rwq->full() ) {
+          if (rw==WRITE) {
+             rw=READ;
+             rwq->set_min_length(m_config->CL);
+          }
+          rwq->push(bk[j]->mrq);
+          bk[j]->mrq->txbytes += m_config->dram_atom_size;
+          CCDc = m_config->tCCD;
+          bkgrp[grp]->CCDLc = m_config->tCCDL;
+          RTWc = m_config->tRTW;
+          bk[j]->RTPc = m_config->BL/m_config->data_command_freq_ratio;
+          bkgrp[grp]->RTPLc = m_config->tRTPL;
+          issued = true;
+          if(bk[j]->mrq->data->get_access_type() == L2_WR_ALLOC_R)
+        	  n_rd_L2_A++;
+          else
+                n_rd++;
+
+          bwutil += m_config->BL/m_config->data_command_freq_ratio;
+          bwutil_partial += m_config->BL/m_config->data_command_freq_ratio;
+          bk[j]->n_access++;
+
+#ifdef DRAM_VERIFY
+          PRINT_CYCLE=1;
+          printf("\tRD  Bk:%d Row:%03x Col:%03x \n",
+                 j, bk[j]->curr_row,
+                 bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size);
+#endif
+          // transfer done
+          if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) {
+             bk[j]->mrq = NULL;
+          }
+       } else
+          // correct row activated for a WRITE
+          if ( !issued && !CCDc && !bk[j]->RCDWRc &&
+               !(bkgrp[grp]->CCDLc) &&
+               (bk[j]->curr_row == bk[j]->mrq->row)  &&
+               (bk[j]->mrq->rw == WRITE) && (RTWc == 0 )  &&
+               (bk[j]->state == BANK_ACTIVE) &&
+               !rwq->full() ) {
+          if (rw==READ) {
+             rw=WRITE;
+             rwq->set_min_length(m_config->WL);
+          }
+          rwq->push(bk[j]->mrq);
+
+          bk[j]->mrq->txbytes += m_config->dram_atom_size;
+          CCDc = m_config->tCCD;
+          bkgrp[grp]->CCDLc = m_config->tCCDL;
+          WTRc = m_config->tWTR;
+          bk[j]->WTPc = m_config->tWTP;
+          issued = true;
+
+          if(bk[j]->mrq->data->get_access_type() == L2_WRBK_ACC)
+          	n_wr_WB++;
+          else
+          	 n_wr++;
+          bwutil += m_config->BL/m_config->data_command_freq_ratio;
+          bwutil_partial += m_config->BL/m_config->data_command_freq_ratio;
+#ifdef DRAM_VERIFY
+          PRINT_CYCLE=1;
+          printf("\tWR  Bk:%d Row:%03x Col:%03x \n",
+                 j, bk[j]->curr_row,
+                 bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size);
+#endif
+          // transfer done
+          if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) {
+             bk[j]->mrq = NULL;
+          }
+       }
+
+    }
+
+    return issued;
+}
+
+bool dram_t::issue_row_command(int j)
+{
+	bool issued = false;
+	unsigned grp = get_bankgrp_number(j);
+    if (bk[j]->mrq) { //if currently servicing a memory request
+        bk[j]->mrq->data->set_status(IN_PARTITION_DRAM,gpu_sim_cycle+gpu_tot_sim_cycle);
+      //     bank is idle
+    //else
+  	  if ( !issued && !RRDc &&
+               (bk[j]->state == BANK_IDLE) &&
+               !bk[j]->RPc && !bk[j]->RCc) { //
+#ifdef DRAM_VERIFY
+          PRINT_CYCLE=1;
+          printf("\tACT BK:%d NewRow:%03x From:%03x \n",
+                 j,bk[j]->mrq->row,bk[j]->curr_row);
+#endif
+          // activate the row with current memory request
+          bk[j]->curr_row = bk[j]->mrq->row;
+          bk[j]->state = BANK_ACTIVE;
+          RRDc = m_config->tRRD;
+          bk[j]->RCDc = m_config->tRCD;
+          bk[j]->RCDWRc = m_config->tRCDWR;
+          bk[j]->RASc = m_config->tRAS;
+          bk[j]->RCc = m_config->tRC;
+          prio = (j + 1) % m_config->nbk;
+          issued = true;
+          n_act_partial++;
+          n_act++;
+       }
+
+       else
+          // different row activated
+          if ( (!issued) &&
+               (bk[j]->curr_row != bk[j]->mrq->row) &&
+               (bk[j]->state == BANK_ACTIVE) &&
+               (!bk[j]->RASc && !bk[j]->WTPc &&
+				  !bk[j]->RTPc &&
+				  !bkgrp[grp]->RTPLc) ) {
+          // make the bank idle again
+          bk[j]->state = BANK_IDLE;
+          bk[j]->RPc = m_config->tRP;
+          prio = (j + 1) % m_config->nbk;
+          issued = true;
+          n_pre++;
+          n_pre_partial++;
+#ifdef DRAM_VERIFY
+          PRINT_CYCLE=1;
+          printf("\tPRE BK:%d Row:%03x \n", j,bk[j]->curr_row);
+#endif
+       }
+    }
+    return issued;
+}
+
+
 //if mrq is being serviced by dram, gets popped after CL latency fulfilled
-class mem_fetch* dram_t::return_queue_pop() 
+class mem_fetch* dram_t::return_queue_pop()
 {
     return returnq->pop();
 }
 
-class mem_fetch* dram_t::return_queue_top() 
+class mem_fetch* dram_t::return_queue_top()
 {
     return returnq->top();
 }
 
+
 void dram_t::print( FILE* simFile) const
 {
    unsigned i;
    fprintf(simFile,"DRAM[%d]: %d bks, busW=%d BL=%d CL=%d, ", 
            id, m_config->nbk, m_config->busW, m_config->BL, m_config->CL );
    fprintf(simFile,"tRRD=%d tCCD=%d, tRCD=%d tRAS=%d tRP=%d tRC=%d\n",
-           m_config->tCCD, m_config->tRRD, m_config->tRCD, m_config->tRAS, m_config->tRP, m_config->tRC );
-   fprintf(simFile,"n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_req=%d n_rd=%d n_write=%d bw_util=%.4g\n",
-           n_cmd, n_nop, n_act, n_pre, n_req, n_rd, n_wr,
+           m_config->tRRD, m_config->tCCD, m_config->tRCD, m_config->tRAS, m_config->tRP, m_config->tRC );
+   fprintf(simFile,"n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_ref_event=%d n_req=%d n_rd=%d n_rd_L2_A=%d n_write=%d n_wr_bk=%d bw_util=%.4g\n",
+           n_cmd, n_nop, n_act, n_pre, n_ref, n_req, n_rd, n_rd_L2_A, n_wr, n_wr_WB,
            (float)bwutil/n_cmd);
    fprintf(simFile,"n_activity=%d dram_eff=%.4g\n",
            n_activity, (float)bwutil/n_activity);
    for (i=0;i<m_config->nbk;i++) {
       fprintf(simFile, "bk%d: %da %di ",i,bk[i]->n_access,bk[i]->n_idle);
    }
+   fprintf(simFile, "\n");
+   fprintf(simFile, "\n------------------------------------------------------------------------\n");
+
+   printf("\nRow_Buffer_Locality = %.6f", (float)hits_num / access_num);
+   printf("\nRow_Buffer_Locality_read = %.6f", (float)hits_read_num / read_num);
+   printf("\nRow_Buffer_Locality_write = %.6f", (float)hits_write_num / write_num);
+   printf("\nBank_Level_Parallism = %.6f", (float)banks_1time / banks_acess_total);
+   printf("\nBank_Level_Parallism_Col = %.6f", (float)banks_time_rw / banks_access_rw_total);
+   printf("\nBank_Level_Parallism_Ready = %.6f", (float)banks_time_ready /banks_access_ready_total);
+   printf("\nwrite_to_read_ratio_blp_rw_average = %.6f", write_to_read_ratio_blp_rw_average /banks_access_rw_total);
+   printf("\nGrpLevelPara = %.6f \n", (float)bkgrp_parallsim_rw /banks_access_rw_total);
+
+   printf("\nBW Util details:\n");
+   printf("bwutil = %.6f \n", (float)bwutil/n_cmd);
+   printf("total_CMD = %d \n", n_cmd);
+   printf("util_bw = %d \n", util_bw);
+   printf("Wasted_Col = %d \n", wasted_bw_col);
+   printf("Wasted_Row = %d \n", wasted_bw_row);
+   printf("Idle = %d \n", idle_bw);
+
+   printf("\nBW Util Bottlenecks: \n");
+   printf("RCDc_limit = %d \n", RCDc_limit);
+   printf("RCDWRc_limit = %d \n", RCDWRc_limit);
+   printf("WTRc_limit = %d \n", WTRc_limit);
+   printf("RTWc_limit = %d \n", RTWc_limit);
+   printf("CCDLc_limit = %d \n", CCDLc_limit);
+   printf("rwq = %d \n", rwq_limit);
+   printf("CCDLc_limit_alone = %d \n", CCDLc_limit_alone);
+   printf("WTRc_limit_alone = %d \n", WTRc_limit_alone);
+   printf("RTWc_limit_alone = %d \n", RTWc_limit_alone);
+
+   printf("\nCommands details: \n");
+   printf("total_CMD = %d \n", n_cmd);
+   printf("n_nop = %d \n", n_nop);
+   printf("Read = %d \n", n_rd);
+   printf("Write = %d \n",n_wr);
+   printf("L2_Alloc = %d \n", n_rd_L2_A);
+   printf("L2_WB = %d \n", n_wr_WB);
+   printf("n_act = %d \n", n_act);
+   printf("n_pre = %d \n", n_pre);
+   printf("n_ref = %d \n", n_ref);
+   printf("n_req = %d \n", n_req );
+   printf("total_req = %d \n", n_rd+n_wr+n_rd_L2_A+n_wr_WB);
+
+   printf("\nDual Bus Interface Util: \n");
+   printf("issued_total_row = %lu \n", issued_total_row);
+   printf("issued_total_col = %lu \n", issued_total_col);
+   printf("Row_Bus_Util =  %.6f \n", (float)issued_total_row / n_cmd);
+   printf("CoL_Bus_Util = %.6f \n", (float)issued_total_col / n_cmd);
+   printf("Either_Row_CoL_Bus_Util = %.6f \n",  (float)issued_total / n_cmd);
+   printf("Issued_on_Two_Bus_Simul_Util = %.6f \n",  (float)issued_two /n_cmd);
+   printf("issued_two_Eff = %.6f \n",  (float)issued_two /issued_total);
+   printf("queue_avg = %.6f \n\n", (float)ave_mrqs/n_cmd );
+
    fprintf(simFile, "\n");
    fprintf(simFile, "dram_util_bins:");
    for (i=0;i<10;i++) fprintf(simFile, " %d", dram_util_bins[i]);
    fprintf(simFile, "\ndram_eff_bins:");
    for (i=0;i<10;i++) fprintf(simFile, " %d", dram_eff_bins[i]);
    fprintf(simFile, "\n");
-   if(m_config->scheduler_type== DRAM_FRFCFS) 
+   if(m_config->scheduler_type== DRAM_FRFCFS)
        fprintf(simFile, "mrqq: max=%d avg=%g\n", max_mrqs, (float)ave_mrqs/n_cmd);
 }
 
@@ -476,8 +815,8 @@ void dram_t::visualize() const
 
 void dram_t::print_stat( FILE* simFile ) 
 {
-   fprintf(simFile,"DRAM (%d): n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_req=%d n_rd=%d n_write=%d bw_util=%.4g ",
-           id, n_cmd, n_nop, n_act, n_pre, n_req, n_rd, n_wr,
+   fprintf(simFile,"DRAM (%d): n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_ref=%d n_req=%d n_rd=%d n_write=%d bw_util=%.4g ",
+           id, n_cmd, n_nop, n_act, n_pre, n_ref, n_req, n_rd, n_wr,
            (float)bwutil/n_cmd);
    fprintf(simFile, "mrqq: %d %.4g mrqsmax=%d ", max_mrqs, (float)ave_mrqs/n_cmd, max_mrqs_temp);
    fprintf(simFile, "\n");
@@ -516,6 +855,7 @@ void dram_t::visualizer_print( gzFile visualizer_file )
    n_pre_partial = 0;
    n_req_partial = 0;
 
+
    // dram access type classification
    for (unsigned j = 0; j < m_config->nbk; j++) {
       gzprintf(visualizer_file,"dramglobal_acc_r: %u %u %u\n", id, j, 
@@ -553,3 +893,16 @@ void dram_t::set_dram_power_stats(	unsigned &cmd,
 	wr = n_wr;
 	req = n_req;
 }
+
+unsigned dram_t::get_bankgrp_number(unsigned i)
+{
+	if(m_config->dram_bnkgrp_indexing_policy == HIGHER_BITS) { //higher bits
+		return i>>m_config->bk_tag_length;
+	}
+	else if (m_config->dram_bnkgrp_indexing_policy == LOWER_BITS) { //lower bits
+		return i&((m_config->nbkgrp-1));
+	}
+	else {
+		assert(1);
+	}
+}
diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h
index 15c63e7..bee5b7b 100644
--- a/src/gpgpu-sim/dram.h
+++ b/src/gpgpu-sim/dram.h
@@ -31,9 +31,15 @@
 
 #include "delayqueue.h"
 #include <set>
+#include <vector>
+#include <bitset>
+#include <sstream>
+#include <string>
+#include <fstream>
 #include <zlib.h>
 #include <stdio.h>
 #include <stdlib.h>
+#include<iomanip>
 
 #define READ 'R'  //define read and write states
 #define WRITE 'W'
@@ -42,7 +48,7 @@
 
 class dram_req_t {
 public:
-   dram_req_t( class mem_fetch *data );
+   dram_req_t( class mem_fetch *data , unsigned banks, unsigned dram_bnk_indexing_policy);
 
    unsigned int row;
    unsigned int col;
@@ -87,6 +93,17 @@ struct bank_t
    unsigned int bkgrpindex;
 };
 
+enum bank_index_function{
+	LINEAR_BK_INDEX = 0,
+	BITWISE_XORING_BK_INDEX,
+    CUSTOM_BK_INDEX
+};
+
+enum bank_grp_bits_position{
+	HIGHER_BITS = 0,
+	LOWER_BITS
+};
+
 class mem_fetch;
 
 class dram_t 
@@ -95,7 +112,7 @@ public:
    dram_t( unsigned int parition_id, const struct memory_config *config, class memory_stats_t *stats, 
            class memory_partition_unit *mp );
 
-   bool full() const;
+   bool full(bool is_write) const;
    void print( FILE* simFile ) const;
    void visualize() const;
    void print_stat( FILE* simFile );
@@ -106,6 +123,7 @@ public:
 
    class mem_fetch* return_queue_pop();
    class mem_fetch* return_queue_top();
+
    void push( class mem_fetch *data );
    void cycle();
    void dram_log (int task);
@@ -123,17 +141,24 @@ public:
 								unsigned &wr,
 								unsigned &req) const;
 
-private:
-   void scheduler_fifo();
-   void scheduler_frfcfs();
+
 
    const struct memory_config *m_config;
 
+private:
    bankgrp_t **bkgrp;
 
    bank_t **bk;
    unsigned int prio;
 
+   unsigned get_bankgrp_number(unsigned i);
+
+   void scheduler_fifo();
+   void scheduler_frfcfs();
+
+   bool issue_col_command(int j);
+   bool issue_row_command(int j);
+
    unsigned int RRDc;
    unsigned int CCDc;
    unsigned int RTWc;   //read to write penalty applies across banks
@@ -146,7 +171,7 @@ private:
    fifo_pipeline<dram_req_t> *rwq;
    fifo_pipeline<dram_req_t> *mrqq;
    //buffer to hold packets when DRAM processing is over
-   //should be filled with dram clock and popped with l2or icnt clock 
+   //should be filled with dram clock and popped with l2or icnt clock
    fifo_pipeline<mem_fetch> *returnq;
 
    unsigned int dram_util_bins[10];
@@ -158,11 +183,51 @@ private:
    unsigned int n_nop;
    unsigned int n_act;
    unsigned int n_pre;
+   unsigned int n_ref;
    unsigned int n_rd;
+   unsigned int n_rd_L2_A;
    unsigned int n_wr;
+   unsigned int n_wr_WB;
    unsigned int n_req;
    unsigned int max_mrqs_temp;
 
+   //some statistics to collect to see where BW is wasted?
+   unsigned wasted_bw_row;
+   unsigned wasted_bw_col;
+   unsigned util_bw;
+   unsigned idle_bw;
+   unsigned RCDc_limit;
+   unsigned CCDLc_limit;
+   unsigned CCDLc_limit_alone;
+   unsigned CCDc_limit;
+   unsigned WTRc_limit;
+   unsigned WTRc_limit_alone;
+   unsigned RCDWRc_limit;
+   unsigned RTWc_limit;
+   unsigned RTWc_limit_alone;
+   unsigned rwq_limit;
+
+   //row locality, BLP and other statistics
+   unsigned long  access_num;
+   unsigned long  read_num;
+   unsigned long  write_num;
+   unsigned long long hits_num;
+   unsigned long long hits_read_num;
+   unsigned long long hits_write_num;
+   unsigned long long banks_1time;
+   unsigned long long banks_acess_total;
+   unsigned long long banks_acess_total_after;
+   unsigned long long banks_time_rw;
+   unsigned long long banks_access_rw_total;
+   unsigned long long banks_time_ready;
+   unsigned long long banks_access_ready_total;
+   unsigned long long issued_two;
+   unsigned long long issued_total;
+   unsigned long long issued_total_row;
+   unsigned long long issued_total_col;
+   double write_to_read_ratio_blp_rw_average;
+   unsigned long long bkgrp_parallsim_rw;
+
    unsigned int bwutil;
    unsigned int max_mrqs;
    unsigned int ave_mrqs;
diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc
index 8303e86..ff50050 100644
--- a/src/gpgpu-sim/dram_sched.cc
+++ b/src/gpgpu-sim/dram_sched.cc
@@ -36,6 +36,7 @@ frfcfs_scheduler::frfcfs_scheduler( const memory_config *config, dram_t *dm, mem
    m_config = config;
    m_stats = stats;
    m_num_pending = 0;
+   m_num_write_pending = 0;
    m_dram = dm;
    m_queue = new std::list<dram_req_t*>[m_config->nbk];
    m_bins = new std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> >[ m_config->nbk ];
@@ -49,15 +50,36 @@ frfcfs_scheduler::frfcfs_scheduler( const memory_config *config, dram_t *dm, mem
       curr_row_service_time[i] = 0;
       row_service_timestamp[i] = 0;
    }
+   if(m_config->seperate_write_queue_enabled) {
+	   m_write_queue = new std::list<dram_req_t*>[m_config->nbk];
+	   m_write_bins = new std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> >[ m_config->nbk ];
+	   m_last_write_row = new std::list<std::list<dram_req_t*>::iterator>*[ m_config->nbk ];
+
+	   for ( unsigned i=0; i < m_config->nbk; i++ ) {
+	         m_write_queue[i].clear();
+	         m_write_bins[i].clear();
+	         m_last_write_row[i] = NULL;
+	      }
+   }
+   m_mode = READ_MODE;
 
 }
 
 void frfcfs_scheduler::add_req( dram_req_t *req )
 {
-   m_num_pending++;
-   m_queue[req->bk].push_front(req);
-   std::list<dram_req_t*>::iterator ptr = m_queue[req->bk].begin();
-   m_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front
+  if(m_config->seperate_write_queue_enabled && req->data->is_write()) {
+	  assert(m_num_write_pending < m_config->gpgpu_frfcfs_dram_write_queue_size);
+	  m_num_write_pending++;
+	  m_write_queue[req->bk].push_front(req);
+	  std::list<dram_req_t*>::iterator ptr = m_write_queue[req->bk].begin();
+	  m_write_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front
+  } else {
+	   assert(m_num_pending < m_config->gpgpu_frfcfs_dram_sched_queue_size);
+	   m_num_pending++;
+	   m_queue[req->bk].push_front(req);
+	   std::list<dram_req_t*>::iterator ptr = m_queue[req->bk].begin();
+	   m_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front
+  }
 }
 
 void frfcfs_scheduler::data_collection(unsigned int bank)
@@ -78,41 +100,92 @@ void frfcfs_scheduler::data_collection(unsigned int bank)
 
 dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row )
 {
-   if ( m_last_row[bank] == NULL ) {
-      if ( m_queue[bank].empty() )
+   //row
+   bool rowhit = true;
+   std::list<dram_req_t*> *m_current_queue = m_queue;
+   std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> > *m_current_bins = m_bins ;
+   std::list<std::list<dram_req_t*>::iterator> **m_current_last_row = m_last_row;
+
+   if(m_config->seperate_write_queue_enabled) {
+	   if(m_mode == READ_MODE &&
+			  ((m_num_write_pending >= m_config->write_high_watermark )
+			  // || (m_queue[bank].empty() && !m_write_queue[bank].empty())
+			   )) {
+		   m_mode = WRITE_MODE;
+	   }
+	   else if(m_mode == WRITE_MODE &&
+				  (( m_num_write_pending < m_config->write_low_watermark )
+				 //  || (!m_queue[bank].empty() && m_write_queue[bank].empty())
+				   )){
+		   m_mode = READ_MODE;
+	   }
+   }
+
+   if(m_mode == WRITE_MODE) {
+	   m_current_queue = m_write_queue;
+	   m_current_bins = m_write_bins ;
+	   m_current_last_row = m_last_write_row;
+   }
+
+   if ( m_current_last_row[bank] == NULL ) {
+      if ( m_current_queue[bank].empty() )
          return NULL;
 
-      std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> >::iterator bin_ptr = m_bins[bank].find( curr_row );
-      if ( bin_ptr == m_bins[bank].end()) {
-         dram_req_t *req = m_queue[bank].back();
-         bin_ptr = m_bins[bank].find( req->row );
-         assert( bin_ptr != m_bins[bank].end() ); // where did the request go???
-         m_last_row[bank] = &(bin_ptr->second);
+      std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> >::iterator bin_ptr = m_current_bins[bank].find( curr_row );
+      if ( bin_ptr == m_current_bins[bank].end()) {
+         dram_req_t *req = m_current_queue[bank].back();
+         bin_ptr = m_current_bins[bank].find( req->row );
+         assert( bin_ptr != m_current_bins[bank].end() ); // where did the request go???
+         m_current_last_row[bank] = &(bin_ptr->second);
          data_collection(bank);
+         rowhit = false;
       } else {
-         m_last_row[bank] = &(bin_ptr->second);
-
+    	  m_current_last_row[bank] = &(bin_ptr->second);
+         rowhit = true;
       }
    }
-   std::list<dram_req_t*>::iterator next = m_last_row[bank]->back();
+   std::list<dram_req_t*>::iterator next = m_current_last_row[bank]->back();
    dram_req_t *req = (*next);
 
+   //rowblp stats
+    m_dram->access_num++;
+    bool is_write = req->data->is_write();
+    if(is_write)
+  	  m_dram->write_num++;
+    else
+  	  m_dram->read_num++;
+
+    if(rowhit) {
+     m_dram->hits_num++;
+     if(is_write)
+    	  m_dram->hits_write_num++;
+      else
+    	  m_dram->hits_read_num++;
+    }
+
    m_stats->concurrent_row_access[m_dram->id][bank]++;
    m_stats->row_access[m_dram->id][bank]++;
-   m_last_row[bank]->pop_back();
+   m_current_last_row[bank]->pop_back();
 
-   m_queue[bank].erase(next);
-   if ( m_last_row[bank]->empty() ) {
-      m_bins[bank].erase( req->row );
-      m_last_row[bank] = NULL;
+   m_current_queue[bank].erase(next);
+   if ( m_current_last_row[bank]->empty() ) {
+	   m_current_bins[bank].erase( req->row );
+	   m_current_last_row[bank] = NULL;
    }
 #ifdef DEBUG_FAST_IDEAL_SCHED
    if ( req )
       printf("%08u : DRAM(%u) scheduling memory request to bank=%u, row=%u\n", 
              (unsigned)gpu_sim_cycle, m_dram->id, req->bk, req->row );
 #endif
-   assert( req != NULL && m_num_pending != 0 ); 
-   m_num_pending--;
+
+   if(m_config->seperate_write_queue_enabled && req->data->is_write()) {
+	   assert( req != NULL && m_num_write_pending != 0 );
+	   m_num_write_pending--;
+   }
+   else {
+	   assert( req != NULL && m_num_pending != 0 );
+	   m_num_pending--;
+   }
 
    return req;
 }
@@ -129,7 +202,7 @@ void dram_t::scheduler_frfcfs()
 {
    unsigned mrq_latency;
    frfcfs_scheduler *sched = m_frfcfs_scheduler;
-   while ( !mrqq->empty() && (!m_config->gpgpu_frfcfs_dram_sched_queue_size || sched->num_pending() < m_config->gpgpu_frfcfs_dram_sched_queue_size)) {
+   while ( !mrqq->empty() ) {
       dram_req_t *req = mrqq->pop();
 
       // Power stats
@@ -160,6 +233,8 @@ void dram_t::scheduler_frfcfs()
             bk[b]->mrq = req;
             if (m_config->gpgpu_memlatency_stat) {
                mrq_latency = gpu_sim_cycle + gpu_tot_sim_cycle - bk[b]->mrq->timestamp;
+               m_stats->tot_mrq_latency += mrq_latency;
+               m_stats->tot_mrq_num++;
                bk[b]->mrq->timestamp = gpu_tot_sim_cycle + gpu_sim_cycle;
                m_stats->mrq_lat_table[LOGB2(mrq_latency)]++;
                if (mrq_latency > m_stats->max_mrq_latency) {
diff --git a/src/gpgpu-sim/dram_sched.h b/src/gpgpu-sim/dram_sched.h
index 3860f5b..63f5831 100644
--- a/src/gpgpu-sim/dram_sched.h
+++ b/src/gpgpu-sim/dram_sched.h
@@ -35,6 +35,11 @@
 #include <list>
 #include <map>
 
+enum memory_mode {
+   READ_MODE = 0,
+   WRITE_MODE
+};
+
 class frfcfs_scheduler {
 public:
    frfcfs_scheduler( const memory_config *config, dram_t *dm, memory_stats_t *stats );
@@ -43,17 +48,24 @@ public:
    dram_req_t *schedule( unsigned bank, unsigned curr_row );
    void print( FILE *fp );
    unsigned num_pending() const { return m_num_pending;}
+   unsigned num_write_pending() const { return m_num_write_pending;}
 
 private:
    const memory_config *m_config;
    dram_t *m_dram;
    unsigned m_num_pending;
+   unsigned m_num_write_pending;
    std::list<dram_req_t*>                                    *m_queue;
    std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> >    *m_bins;
    std::list<std::list<dram_req_t*>::iterator>                 **m_last_row;
    unsigned *curr_row_service_time; //one set of variables for each bank.
    unsigned *row_service_timestamp; //tracks when scheduler began servicing current row
 
+   std::list<dram_req_t*>                                    *m_write_queue;
+   std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> >    *m_write_bins;
+   std::list<std::list<dram_req_t*>::iterator>                 **m_last_write_row;
+
+   enum memory_mode m_mode;
    memory_stats_t *m_stats;
 };
 
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index 8886398..ba81440 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -29,7 +29,6 @@
 #include "stat-tool.h"
 #include <assert.h>
 
-#define MAX_DEFAULT_CACHE_SIZE_MULTIBLIER 4
 // used to allocate memory that is large enough to adapt the changes in cache size across kernels
 
 const char * cache_request_status_str(enum cache_request_status status) 
@@ -38,7 +37,8 @@ const char * cache_request_status_str(enum cache_request_status status)
       "HIT",
       "HIT_RESERVED",
       "MISS",
-      "RESERVATION_FAIL"
+      "RESERVATION_FAIL",
+	  "SECTOR_MISS"
    }; 
 
    assert(sizeof(static_cache_request_status_str) / sizeof(const char*) == NUM_CACHE_REQUEST_STATUS); 
@@ -47,6 +47,22 @@ const char * cache_request_status_str(enum cache_request_status status)
    return static_cache_request_status_str[status]; 
 }
 
+const char * cache_fail_status_str(enum cache_reservation_fail_reason status)
+{
+   static const char * static_cache_reservation_fail_reason_str[] = {
+	  "LINE_ALLOC_FAIL",
+	  "MISS_QUEUE_FULL",
+	  "MSHR_ENRTY_FAIL",
+      "MSHR_MERGE_ENRTY_FAIL",
+      "MSHR_RW_PENDING"
+   };
+
+   assert(sizeof(static_cache_reservation_fail_reason_str) / sizeof(const char*) == NUM_CACHE_RESERVATION_FAIL_STATUS);
+   assert(status < NUM_CACHE_RESERVATION_FAIL_STATUS);
+
+   return static_cache_reservation_fail_reason_str[status];
+}
+
 unsigned l1d_cache_config::set_index(new_addr_type addr) const{
     unsigned set_index = m_nset; // Default to linear set index function
     unsigned lower_xor = 0;
@@ -54,10 +70,11 @@ unsigned l1d_cache_config::set_index(new_addr_type addr) const{
 
     switch(m_set_index_function){
     case FERMI_HASH_SET_FUNCTION:
+    case BITWISE_XORING_FUNCTION:
         /*
         * Set Indexing function from "A Detailed GPU Cache Model Based on Reuse Distance Theory"
         * Cedric Nugteren et al.
-        * ISCA 2014
+        * HPCA 2014
         */
         if(m_nset == 32 || m_nset == 64){
             // Lower xor value is bits 7-11
@@ -80,6 +97,36 @@ unsigned l1d_cache_config::set_index(new_addr_type addr) const{
         }
         break;
 
+    case HASH_IPOLY_FUNCTION:
+    	/*
+		* Set Indexing function from "Pseudo-randomly interleaved memory."
+		* Rau, B. R et al.
+		* ISCA 1991
+		*
+		* "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu cache management scheme."
+		* Khairy et al.
+		* IEEE TPDS 2017.
+    	*/
+    	if(m_nset == 32 || m_nset == 64){
+		std::bitset<64> a(addr);
+		std::bitset<6> index;
+		index[0] = a[25]^a[24]^a[23]^a[22]^a[21]^a[18]^a[17]^a[15]^a[12]^a[7]; //10
+		index[1] = a[26]^a[25]^a[24]^a[23]^a[22]^a[19]^a[18]^a[16]^a[13]^a[8]; //10
+		index[2] = a[26]^a[22]^a[21]^a[20]^a[19]^a[18]^a[15]^a[14]^a[12]^a[9]; //10
+		index[3] = a[23]^a[22]^a[21]^a[20]^a[19]^a[16]^a[15]^a[13]^a[10]; //9
+		index[4] = a[24]^a[23]^a[22]^a[21]^a[20]^a[17]^a[16]^a[14]^a[11]; //9
+
+		 if(m_nset == 64)
+			 index[5] = a[12];
+
+		set_index = index.to_ulong();
+
+    	}else{ /* Else incorrect number of sets for the hashing function */
+    	            assert("\nGPGPU-Sim cache configuration error: The number of sets should be "
+    	                    "32 or 64 for the hashing set index function.\n" && 0);
+    	 }
+        break;
+
     case CUSTOM_SET_FUNCTION:
         /* No custom set function implemented */
         break;
@@ -87,6 +134,10 @@ unsigned l1d_cache_config::set_index(new_addr_type addr) const{
     case LINEAR_SET_FUNCTION:
         set_index = (addr >> m_line_sz_log2) & (m_nset-1);
         break;
+
+    default:
+    	 assert("\nUndefined set index function.\n" && 0);
+    	 break;
     }
 
     // Linear function selected or custom set index function not implemented
@@ -113,13 +164,16 @@ unsigned l2_cache_config::set_index(new_addr_type addr) const{
 
 tag_array::~tag_array() 
 {
+	unsigned cache_lines_num = m_config.get_max_num_lines();
+	for(unsigned i=0; i<cache_lines_num; ++i)
+		delete m_lines[i];
     delete[] m_lines;
 }
 
 tag_array::tag_array( cache_config &config,
                       int core_id,
                       int type_id,
-                      cache_block_t* new_lines)
+                      cache_block_t** new_lines)
     : m_config( config ),
       m_lines( new_lines )
 {
@@ -137,7 +191,21 @@ tag_array::tag_array( cache_config &config,
     : m_config( config )
 {
     //assert( m_config.m_write_policy == READ_ONLY ); Old assert
-    m_lines = new cache_block_t[MAX_DEFAULT_CACHE_SIZE_MULTIBLIER*config.get_num_lines()];
+	unsigned cache_lines_num = config.get_max_num_lines();
+	m_lines = new cache_block_t*[cache_lines_num];
+	if(config.m_cache_type == NORMAL)
+	{
+		for(unsigned i=0; i<cache_lines_num; ++i)
+			m_lines[i] = new line_cache_block();
+	}
+	else if(config.m_cache_type == SECTOR)
+	{
+		for(unsigned i=0; i<cache_lines_num; ++i)
+			m_lines[i] = new sector_cache_block();
+	}
+	else
+		assert(0);
+
     init( core_id, type_id );
 }
 
@@ -147,15 +215,41 @@ void tag_array::init( int core_id, int type_id )
     m_miss = 0;
     m_pending_hit = 0;
     m_res_fail = 0;
+    m_sector_miss = 0;
     // initialize snapshot counters for visualizer
     m_prev_snapshot_access = 0;
     m_prev_snapshot_miss = 0;
     m_prev_snapshot_pending_hit = 0;
     m_core_id = core_id; 
     m_type_id = type_id;
+    is_used = false;
+}
+
+void tag_array::add_pending_line(mem_fetch *mf){
+	assert(mf);
+	new_addr_type addr = m_config.block_addr(mf->get_addr());
+	line_table::const_iterator i = pending_lines.find(addr);
+	if ( i == pending_lines.end() ) {
+		pending_lines[addr] = mf->get_inst().get_uid();
+	}
+}
+
+void tag_array::remove_pending_line(mem_fetch *mf){
+	assert(mf);
+	new_addr_type addr = m_config.block_addr(mf->get_addr());
+	line_table::const_iterator i = pending_lines.find(addr);
+	if ( i != pending_lines.end() ) {
+		pending_lines.erase(addr);
+	}
 }
 
-enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx ) const {
+enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx, mem_fetch* mf, bool probe_mode) const {
+    mem_access_sector_mask_t mask = mf->get_access_sector_mask();
+    return probe(addr, idx, mask, probe_mode, mf);
+}
+
+
+enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx, mem_access_sector_mask_t mask, bool probe_mode, mem_fetch* mf) const {
     //assert( m_config.m_write_policy == READ_ONLY );
     unsigned set_index = m_config.set_index(addr);
     new_addr_type tag = m_config.tag(addr);
@@ -169,35 +263,45 @@ enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx )
     // check for hit or pending hit
     for (unsigned way=0; way<m_config.m_assoc; way++) {
         unsigned index = set_index*m_config.m_assoc+way;
-        cache_block_t *line = &m_lines[index];
+        cache_block_t *line = m_lines[index];
         if (line->m_tag == tag) {
-            if ( line->m_status == RESERVED ) {
+            if ( line->get_status(mask) == RESERVED ) {
                 idx = index;
                 return HIT_RESERVED;
-            } else if ( line->m_status == VALID ) {
+            } else if ( line->get_status(mask) == VALID ) {
                 idx = index;
                 return HIT;
-            } else if ( line->m_status == MODIFIED ) {
+            } else if ( line->get_status(mask) == MODIFIED) {
+            	if(line->is_readable(mask)) {
+					idx = index;
+					return HIT;
+            	}
+            	else {
+            		idx = index;
+            		return SECTOR_MISS;
+            	}
+
+            } else if ( line->is_valid_line() && line->get_status(mask) == INVALID ) {
                 idx = index;
-                return HIT;
-            } else {
-                assert( line->m_status == INVALID );
+                return SECTOR_MISS;
+            }else {
+                assert( line->get_status(mask) == INVALID );
             }
         }
-        if (line->m_status != RESERVED) {
+        if (!line->is_reserved_line()) {
             all_reserved = false;
-            if (line->m_status == INVALID) {
+            if (line->is_invalid_line()) {
                 invalid_line = index;
             } else {
                 // valid line : keep track of most appropriate replacement candidate
                 if ( m_config.m_replacement_policy == LRU ) {
-                    if ( line->m_last_access_time < valid_timestamp ) {
-                        valid_timestamp = line->m_last_access_time;
+                    if ( line->get_last_access_time() < valid_timestamp ) {
+                        valid_timestamp = line->get_last_access_time();
                         valid_line = index;
                     }
                 } else if ( m_config.m_replacement_policy == FIFO ) {
-                    if ( line->m_alloc_time < valid_timestamp ) {
-                        valid_timestamp = line->m_alloc_time;
+                    if ( line->get_alloc_time() < valid_timestamp ) {
+                        valid_timestamp = line->get_alloc_time();
                         valid_line = index;
                     }
                 }
@@ -215,40 +319,59 @@ enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx )
         idx = valid_line;
     } else abort(); // if an unreserved block exists, it is either invalid or replaceable 
 
+
+    if(probe_mode && m_config.is_streaming()){
+		line_table::const_iterator i = pending_lines.find(m_config.block_addr(addr));
+		assert(mf);
+		if ( !mf->is_write() && i != pending_lines.end() ) {
+			 if(i->second != mf->get_inst().get_uid())
+				 return SECTOR_MISS;
+		}
+    }
+
     return MISS;
 }
 
-enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, unsigned &idx )
+enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, unsigned &idx, mem_fetch* mf)
 {
     bool wb=false;
-    cache_block_t evicted;
-    enum cache_request_status result = access(addr,time,idx,wb,evicted);
+    evicted_block_info evicted;
+    enum cache_request_status result = access(addr,time,idx,wb,evicted,mf);
     assert(!wb);
     return result;
 }
 
-enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, unsigned &idx, bool &wb, cache_block_t &evicted ) 
+enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, unsigned &idx, bool &wb, evicted_block_info &evicted, mem_fetch* mf )
 {
     m_access++;
+    is_used = true;
     shader_cache_access_log(m_core_id, m_type_id, 0); // log accesses to cache
-    enum cache_request_status status = probe(addr,idx);
+    enum cache_request_status status = probe(addr,idx,mf);
     switch (status) {
     case HIT_RESERVED: 
         m_pending_hit++;
     case HIT: 
-        m_lines[idx].m_last_access_time=time; 
+        m_lines[idx]->set_last_access_time(time, mf->get_access_sector_mask());
         break;
     case MISS:
         m_miss++;
         shader_cache_access_log(m_core_id, m_type_id, 1); // log cache misses
         if ( m_config.m_alloc_policy == ON_MISS ) {
-            if( m_lines[idx].m_status == MODIFIED ) {
+            if( m_lines[idx]->is_modified_line()) {
                 wb = true;
-                evicted = m_lines[idx];
+                evicted.set_info(m_lines[idx]->m_block_addr, m_lines[idx]->get_modified_size());
             }
-            m_lines[idx].allocate( m_config.tag(addr), m_config.block_addr(addr), time );
+            m_lines[idx]->allocate( m_config.tag(addr), m_config.block_addr(addr), time, mf->get_access_sector_mask());
         }
         break;
+    case SECTOR_MISS:
+    	assert(m_config.m_cache_type == SECTOR);
+    	m_sector_miss++;
+		shader_cache_access_log(m_core_id, m_type_id, 1); // log cache misses
+		if ( m_config.m_alloc_policy == ON_MISS ) {
+			((sector_cache_block*)m_lines[idx])->allocate_sector( time, mf->get_access_sector_mask() );
+		}
+		break;
     case RESERVATION_FAIL:
         m_res_fail++;
         shader_cache_access_log(m_core_id, m_type_id, 1); // log cache misses
@@ -261,37 +384,70 @@ enum cache_request_status tag_array::access( new_addr_type addr, unsigned time,
     return status;
 }
 
-void tag_array::fill( new_addr_type addr, unsigned time )
+void tag_array::fill( new_addr_type addr, unsigned time, mem_fetch* mf)
+{
+    fill(addr, time, mf->get_access_sector_mask());
+}
+
+void tag_array::fill( new_addr_type addr, unsigned time, mem_access_sector_mask_t mask )
 {
-    assert( m_config.m_alloc_policy == ON_FILL );
+    //assert( m_config.m_alloc_policy == ON_FILL );
     unsigned idx;
-    enum cache_request_status status = probe(addr,idx);
-    assert(status==MISS); // MSHR should have prevented redundant memory request
-    m_lines[idx].allocate( m_config.tag(addr), m_config.block_addr(addr), time );
-    m_lines[idx].fill(time);
+    enum cache_request_status status = probe(addr,idx,mask);
+    //assert(status==MISS||status==SECTOR_MISS); // MSHR should have prevented redundant memory request
+    if(status==MISS)
+    	m_lines[idx]->allocate( m_config.tag(addr), m_config.block_addr(addr), time, mask );
+    else if (status==SECTOR_MISS) {
+    	assert(m_config.m_cache_type == SECTOR);
+    	((sector_cache_block*)m_lines[idx])->allocate_sector( time, mask );
+    }
+
+    m_lines[idx]->fill(time, mask);
 }
 
-void tag_array::fill( unsigned index, unsigned time ) 
+void tag_array::fill( unsigned index, unsigned time, mem_fetch* mf)
 {
     assert( m_config.m_alloc_policy == ON_MISS );
-    m_lines[index].fill(time);
+    m_lines[index]->fill(time, mf->get_access_sector_mask());
 }
 
+
+//TODO: we need write back the flushed data to the upper level
 void tag_array::flush() 
 {
+	if(!is_used)
+		return;
+
     for (unsigned i=0; i < m_config.get_num_lines(); i++)
-        m_lines[i].m_status = INVALID;
+    	if(m_lines[i]->is_modified_line()) {
+    	for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++)
+    		m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ;
+    	}
+
+    is_used = false;
+}
+
+void tag_array::invalidate()
+{
+	if(!is_used)
+		return;
+
+    for (unsigned i=0; i < m_config.get_num_lines(); i++)
+    	for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++)
+    		m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ;
+
+    is_used = false;
 }
 
 float tag_array::windowed_miss_rate( ) const
 {
     unsigned n_access    = m_access - m_prev_snapshot_access;
-    unsigned n_miss      = m_miss - m_prev_snapshot_miss;
+    unsigned n_miss      = (m_miss+m_sector_miss) - m_prev_snapshot_miss;
     // unsigned n_pending_hit = m_pending_hit - m_prev_snapshot_pending_hit;
 
     float missrate = 0.0f;
     if (n_access != 0)
-        missrate = (float) n_miss / n_access;
+        missrate = (float) (n_miss+m_sector_miss) / n_access;
     return missrate;
 }
 
@@ -299,23 +455,24 @@ void tag_array::new_window()
 {
     m_prev_snapshot_access = m_access;
     m_prev_snapshot_miss = m_miss;
+    m_prev_snapshot_miss = m_miss + m_sector_miss;
     m_prev_snapshot_pending_hit = m_pending_hit;
 }
 
 void tag_array::print( FILE *stream, unsigned &total_access, unsigned &total_misses ) const
 {
     m_config.print(stream);
-    fprintf( stream, "\t\tAccess = %d, Miss = %d (%.3g), PendingHit = %d (%.3g)\n", 
-             m_access, m_miss, (float) m_miss / m_access, 
+    fprintf( stream, "\t\tAccess = %d, Miss = %d, Sector_Miss = %d, Total_Miss = %d (%.3g), PendingHit = %d (%.3g)\n",
+             m_access, m_miss, m_sector_miss, (m_miss+m_sector_miss), (float) (m_miss+m_sector_miss) / m_access,
              m_pending_hit, (float) m_pending_hit / m_access);
-    total_misses+=m_miss;
+    total_misses+=(m_miss+m_sector_miss);
     total_access+=m_access;
 }
 
 void tag_array::get_stats(unsigned &total_access, unsigned &total_misses, unsigned &total_hit_res, unsigned &total_res_fail) const{
     // Update statistics from the tag array
     total_access    = m_access;
-    total_misses    = m_miss;
+    total_misses    = (m_miss+m_sector_miss);
     total_hit_res   = m_pending_hit;
     total_res_fail  = m_res_fail;
 }
@@ -324,16 +481,17 @@ void tag_array::get_stats(unsigned &total_access, unsigned &total_misses, unsign
 bool was_write_sent( const std::list<cache_event> &events )
 {
     for( std::list<cache_event>::const_iterator e=events.begin(); e!=events.end(); e++ ) {
-        if( *e == WRITE_REQUEST_SENT ) 
+        if( (*e).m_cache_event_type == WRITE_REQUEST_SENT )
             return true;
     }
     return false;
 }
 
-bool was_writeback_sent( const std::list<cache_event> &events )
+bool was_writeback_sent( const std::list<cache_event> &events, cache_event& wb_event)
 {
     for( std::list<cache_event>::const_iterator e=events.begin(); e!=events.end(); e++ ) {
-        if( *e == WRITE_BACK_REQUEST_SENT ) 
+        if( (*e).m_cache_event_type == WRITE_BACK_REQUEST_SENT )
+        	wb_event = *e;
             return true;
     }
     return false;
@@ -342,7 +500,16 @@ bool was_writeback_sent( const std::list<cache_event> &events )
 bool was_read_sent( const std::list<cache_event> &events )
 {
     for( std::list<cache_event>::const_iterator e=events.begin(); e!=events.end(); e++ ) {
-        if( *e == READ_REQUEST_SENT ) 
+        if( (*e).m_cache_event_type == READ_REQUEST_SENT )
+            return true;
+    }
+    return false;
+}
+
+bool was_writeallocate_sent( const std::list<cache_event> &events )
+{
+    for( std::list<cache_event>::const_iterator e=events.begin(); e!=events.end(); e++ ) {
+        if( (*e).m_cache_event_type == WRITE_ALLOCATE_SENT )
             return true;
     }
     return false;
@@ -375,11 +542,27 @@ void mshr_table::add( new_addr_type block_addr, mem_fetch *mf ){
 	}
 }
 
+/// check is_read_after_write_pending
+bool mshr_table::is_read_after_write_pending( new_addr_type block_addr){
+	std::list<mem_fetch*> my_list = m_data[block_addr].m_list;
+	bool write_found = false;
+	for (std::list<mem_fetch*>::iterator it=my_list.begin(); it != my_list.end(); ++it)
+	{
+		if((*it)->is_write()) //Pending Write Request
+			write_found = true;
+		else if(write_found)   //Pending Read Request and we found previous Write
+				return true;
+	}
+
+	return false;
+
+}
+
 /// Accept a new cache fill response: mark entry ready for processing
 void mshr_table::mark_ready( new_addr_type block_addr, bool &has_atomic ){
     assert( !busy() );
     table::iterator a = m_data.find(block_addr);
-    assert( a != m_data.end() ); // don't remove same request twice
+    assert( a != m_data.end() );
     m_current_response.push_back( block_addr );
     has_atomic = a->second.m_has_atomic;
     assert( m_current_response.size() <= m_data.size() );
@@ -417,9 +600,11 @@ void mshr_table::display( FILE *fp ) const{
 /***************************************************************** Caches *****************************************************************/
 cache_stats::cache_stats(){
     m_stats.resize(NUM_MEM_ACCESS_TYPE);
+    m_fail_stats.resize(NUM_MEM_ACCESS_TYPE);
     for(unsigned i=0; i<NUM_MEM_ACCESS_TYPE; ++i){
         m_stats[i].resize(NUM_CACHE_REQUEST_STATUS, 0);
-    }
+		m_fail_stats[i].resize(NUM_CACHE_RESERVATION_FAIL_STATUS, 0);
+	}
     m_cache_port_available_cycles = 0; 
     m_cache_data_port_busy_cycles = 0; 
     m_cache_fill_port_busy_cycles = 0; 
@@ -431,7 +616,8 @@ void cache_stats::clear(){
     ///
     for(unsigned i=0; i<NUM_MEM_ACCESS_TYPE; ++i){
         std::fill(m_stats[i].begin(), m_stats[i].end(), 0);
-    }
+		std::fill(m_fail_stats[i].begin(), m_fail_stats[i].end(), 0);
+	}
     m_cache_port_available_cycles = 0; 
     m_cache_data_port_busy_cycles = 0; 
     m_cache_fill_port_busy_cycles = 0; 
@@ -446,6 +632,14 @@ void cache_stats::inc_stats(int access_type, int access_outcome){
 
     m_stats[access_type][access_outcome]++;
 }
+void cache_stats::inc_fail_stats(int access_type, int fail_outcome){
+
+	if(!check_fail_valid(access_type, fail_outcome))
+		 assert(0 && "Unknown cache access type or access fail");
+
+	m_fail_stats[access_type][fail_outcome]++;
+}
+
 
 enum cache_request_status cache_stats::select_stats_status(enum cache_request_status probe, enum cache_request_status access) const {
 	///
@@ -454,29 +648,47 @@ enum cache_request_status cache_stats::select_stats_status(enum cache_request_st
 	///
 	if(probe == HIT_RESERVED && access != RESERVATION_FAIL)
 		return probe;
+	else if(probe == SECTOR_MISS && access == MISS)
+		return probe;
 	else
 		return access;
 }
 
-unsigned &cache_stats::operator()(int access_type, int access_outcome){
+unsigned &cache_stats::operator()(int access_type, int access_outcome, bool fail_outcome){
     ///
     /// Simple method to read/modify the stat corresponding to (access_type, access_outcome)
     /// Used overloaded () to avoid the need for separate read/write member functions
     ///
-    if(!check_valid(access_type, access_outcome))
-        assert(0 && "Unknown cache access type or access outcome");
+	if(fail_outcome) {
+		if(!check_fail_valid(access_type, access_outcome))
+			assert(0 && "Unknown cache access type or fail outcome");
+
+		return m_fail_stats[access_type][access_outcome];
+	}
+	else {
+		if(!check_valid(access_type, access_outcome))
+			assert(0 && "Unknown cache access type or access outcome");
 
-    return m_stats[access_type][access_outcome];
+		return m_stats[access_type][access_outcome];
+	}
 }
 
-unsigned cache_stats::operator()(int access_type, int access_outcome) const{
+unsigned cache_stats::operator()(int access_type, int access_outcome, bool fail_outcome) const{
     ///
     /// Const accessor into m_stats.
     ///
-    if(!check_valid(access_type, access_outcome))
-        assert(0 && "Unknown cache access type or access outcome");
+	if(fail_outcome) {
+		if(!check_fail_valid(access_type, access_outcome))
+			assert(0 && "Unknown cache access type or fail outcome");
 
-    return m_stats[access_type][access_outcome];
+		return m_fail_stats[access_type][access_outcome];
+	}
+	else {
+		if(!check_valid(access_type, access_outcome))
+			assert(0 && "Unknown cache access type or access outcome");
+
+		return m_stats[access_type][access_outcome];
+	}
 }
 
 cache_stats cache_stats::operator+(const cache_stats &cs){
@@ -486,9 +698,12 @@ cache_stats cache_stats::operator+(const cache_stats &cs){
     cache_stats ret;
     for(unsigned type=0; type<NUM_MEM_ACCESS_TYPE; ++type){
         for(unsigned status=0; status<NUM_CACHE_REQUEST_STATUS; ++status){
-            ret(type, status) = m_stats[type][status] + cs(type, status);
+            ret(type, status, false) = m_stats[type][status] + cs(type, status, false);
+        }
+		for(unsigned status=0; status<NUM_CACHE_RESERVATION_FAIL_STATUS; ++status){
+			   ret(type, status, true) = m_fail_stats[type][status] + cs(type, status, true);
+		   }
         }
-    }
     ret.m_cache_port_available_cycles = m_cache_port_available_cycles + cs.m_cache_port_available_cycles; 
     ret.m_cache_data_port_busy_cycles = m_cache_data_port_busy_cycles + cs.m_cache_data_port_busy_cycles; 
     ret.m_cache_fill_port_busy_cycles = m_cache_fill_port_busy_cycles + cs.m_cache_fill_port_busy_cycles; 
@@ -501,8 +716,11 @@ cache_stats &cache_stats::operator+=(const cache_stats &cs){
     ///
     for(unsigned type=0; type<NUM_MEM_ACCESS_TYPE; ++type){
         for(unsigned status=0; status<NUM_CACHE_REQUEST_STATUS; ++status){
-            m_stats[type][status] += cs(type, status);
+            m_stats[type][status] += cs(type, status, false);
         }
+        for(unsigned status=0; status<NUM_CACHE_RESERVATION_FAIL_STATUS; ++status){
+            m_fail_stats[type][status] += cs(type, status, true);
+	   }
     }
     m_cache_port_available_cycles += cs.m_cache_port_available_cycles; 
     m_cache_data_port_busy_cycles += cs.m_cache_data_port_busy_cycles; 
@@ -528,19 +746,34 @@ void cache_stats::print_stats(FILE *fout, const char *cache_name) const{
                 cache_request_status_str((enum cache_request_status)status),
                 m_stats[type][status]);
             if(status != RESERVATION_FAIL)
-                 total_access[type]+= m_stats[type][status];
+            	 total_access[type]+= m_stats[type][status];
         }
     }
     for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) {
-         if(total_access[type] > 0)
-          fprintf(fout, "\t%s[%s][%s] = %u\n",
-                m_cache_name.c_str(),
-                mem_access_type_str((enum mem_access_type)type),
-                "TOTAL_ACCESS",
-                total_access[type]);
+    	 if(total_access[type] > 0)
+    	  fprintf(fout, "\t%s[%s][%s] = %u\n",
+				m_cache_name.c_str(),
+				mem_access_type_str((enum mem_access_type)type),
+				"TOTAL_ACCESS",
+				total_access[type]);
     }
 }
 
+void cache_stats::print_fail_stats(FILE *fout, const char *cache_name) const{
+	std::string m_cache_name = cache_name;
+	    for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) {
+	        for (unsigned fail = 0; fail < NUM_CACHE_RESERVATION_FAIL_STATUS; ++fail) {
+	            if(m_fail_stats[type][fail] > 0){
+	                fprintf(fout, "\t%s[%s][%s] = %u\n",
+	                    m_cache_name.c_str(),
+	                    mem_access_type_str((enum mem_access_type)type),
+						cache_fail_status_str((enum cache_reservation_fail_reason)fail),
+						m_fail_stats[type][fail]);
+	            }
+	        }
+	    }
+}
+
 void cache_sub_stats::print_port_stats(FILE *fout, const char *cache_name) const
 {
     float data_port_util = 0.0f; 
@@ -580,10 +813,10 @@ void cache_stats::get_sub_stats(struct cache_sub_stats &css) const{
 
     for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) {
         for (unsigned status = 0; status < NUM_CACHE_REQUEST_STATUS; ++status) {
-            if(status == HIT || status == MISS || status == HIT_RESERVED)
+            if(status == HIT || status == MISS || status == SECTOR_MISS || status == HIT_RESERVED)
                 t_css.accesses += m_stats[type][status];
 
-            if(status == MISS)
+            if(status == MISS || status == SECTOR_MISS)
                 t_css.misses += m_stats[type][status];
 
             if(status == HIT_RESERVED)
@@ -611,6 +844,16 @@ bool cache_stats::check_valid(int type, int status) const{
         return false;
 }
 
+bool cache_stats::check_fail_valid(int type, int fail) const{
+    ///
+    /// Verify a valid access_type/access_status
+    ///
+    if((type >= 0) && (type < NUM_MEM_ACCESS_TYPE) && (fail >= 0) && (fail < NUM_CACHE_RESERVATION_FAIL_STATUS))
+        return true;
+    else
+        return false;
+}
+
 void cache_stats::sample_cache_port_utility(bool data_port_busy, bool fill_port_busy) 
 {
     m_cache_port_available_cycles += 1; 
@@ -639,15 +882,18 @@ void baseline_cache::bandwidth_management::use_data_port(mem_fetch *mf, enum cac
         unsigned data_cycles = data_size / port_width + ((data_size % port_width > 0)? 1 : 0); 
         m_data_port_occupied_cycles += data_cycles; 
         } break; 
-    case HIT_RESERVED: 
+    case HIT_RESERVED:
     case MISS: {
         // the data array is accessed to read out the entire line for write-back 
-        if (was_writeback_sent(events)) {
-            unsigned data_cycles = m_config.m_line_sz / port_width; 
+    	// in case of sector cache we need to write bank only the modified sectors
+    	cache_event ev(WRITE_BACK_REQUEST_SENT);
+        if (was_writeback_sent(events, ev)) {
+            unsigned data_cycles = ev.m_evicted_block.m_modified_size / port_width;
             m_data_port_occupied_cycles += data_cycles; 
         }
         } break; 
-    case RESERVATION_FAIL: 
+    case SECTOR_MISS:
+    case RESERVATION_FAIL:
         // Does not consume any port bandwidth 
         break; 
     default: 
@@ -660,7 +906,7 @@ void baseline_cache::bandwidth_management::use_data_port(mem_fetch *mf, enum cac
 void baseline_cache::bandwidth_management::use_fill_port(mem_fetch *mf)
 {
     // assume filling the entire line with the returned request 
-    unsigned fill_cycles = m_config.m_line_sz / m_config.m_data_port_width; 
+    unsigned fill_cycles = m_config.get_atom_sz() / m_config.m_data_port_width;
     m_fill_port_occupied_cycles += fill_cycles; 
 }
 
@@ -707,21 +953,43 @@ void baseline_cache::cycle(){
 
 /// Interface for response from lower memory level (model bandwidth restictions in caller)
 void baseline_cache::fill(mem_fetch *mf, unsigned time){
+
+	if(m_config.m_mshr_type == SECTOR_ASSOC) {
+	assert(mf->get_original_mf());
+	extra_mf_fields_lookup::iterator e = m_extra_mf_fields.find(mf->get_original_mf());
+    assert( e != m_extra_mf_fields.end() );
+    e->second.pending_read--;
+
+    if(e->second.pending_read > 0) {
+    	//wait for the other requests to come back
+    	delete mf;
+    	return;
+      } else {
+    	mem_fetch *temp = mf;
+    	mf = mf->get_original_mf();
+    	delete temp;
+      }
+	}
+
     extra_mf_fields_lookup::iterator e = m_extra_mf_fields.find(mf);
     assert( e != m_extra_mf_fields.end() );
     assert( e->second.m_valid );
     mf->set_data_size( e->second.m_data_size );
+    mf->set_addr( e->second.m_addr );
     if ( m_config.m_alloc_policy == ON_MISS )
-        m_tag_array->fill(e->second.m_cache_index,time);
-    else if ( m_config.m_alloc_policy == ON_FILL )
-        m_tag_array->fill(e->second.m_block_addr,time);
+        m_tag_array->fill(e->second.m_cache_index,time,mf);
+    else if ( m_config.m_alloc_policy == ON_FILL ) {
+        m_tag_array->fill(e->second.m_block_addr,time,mf);
+        if(m_config.is_streaming())
+        	m_tag_array->remove_pending_line(mf);
+    }
     else abort();
     bool has_atomic = false;
     m_mshrs.mark_ready(e->second.m_block_addr, has_atomic);
     if (has_atomic) {
         assert(m_config.m_alloc_policy == ON_MISS);
-        cache_block_t &block = m_tag_array->get_block(e->second.m_cache_index);
-        block.m_status = MODIFIED; // mark line as dirty for atomic operation
+        cache_block_t* block = m_tag_array->get_block(e->second.m_cache_index);
+        block->set_status(MODIFIED, mf->get_access_sector_mask()); // mark line as dirty for atomic operation
     }
     m_extra_mf_fields.erase(mf);
     m_bandwidth_management.use_fill_port(mf); 
@@ -749,45 +1017,59 @@ void baseline_cache::send_read_request(new_addr_type addr, new_addr_type block_a
 		unsigned time, bool &do_miss, std::list<cache_event> &events, bool read_only, bool wa){
 
 	bool wb=false;
-	cache_block_t e;
+	evicted_block_info e;
 	send_read_request(addr, block_addr, cache_index, mf, time, do_miss, wb, e, events, read_only, wa);
 }
 
 /// Read miss handler. Check MSHR hit or MSHR available
 void baseline_cache::send_read_request(new_addr_type addr, new_addr_type block_addr, unsigned cache_index, mem_fetch *mf,
-		unsigned time, bool &do_miss, bool &wb, cache_block_t &evicted, std::list<cache_event> &events, bool read_only, bool wa){
+		unsigned time, bool &do_miss, bool &wb, evicted_block_info &evicted, std::list<cache_event> &events, bool read_only, bool wa){
 
-    bool mshr_hit = m_mshrs.probe(block_addr);
-    bool mshr_avail = !m_mshrs.full(block_addr);
+	new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr());
+    bool mshr_hit = m_mshrs.probe(mshr_addr);
+    bool mshr_avail = !m_mshrs.full(mshr_addr);
     if ( mshr_hit && mshr_avail ) {
     	if(read_only)
-    		m_tag_array->access(block_addr,time,cache_index);
+    		m_tag_array->access(block_addr,time,cache_index,mf);
     	else
-    		m_tag_array->access(block_addr,time,cache_index,wb,evicted);
+    		m_tag_array->access(block_addr,time,cache_index,wb,evicted,mf);
 
-        m_mshrs.add(block_addr,mf);
+        m_mshrs.add(mshr_addr,mf);
         do_miss = true;
+
     } else if ( !mshr_hit && mshr_avail && (m_miss_queue.size() < m_config.m_miss_queue_size) ) {
     	if(read_only)
-    		m_tag_array->access(block_addr,time,cache_index);
+    		m_tag_array->access(block_addr,time,cache_index,mf);
     	else
-    		m_tag_array->access(block_addr,time,cache_index,wb,evicted);
-
-        m_mshrs.add(block_addr,mf);
-        m_extra_mf_fields[mf] = extra_mf_fields(block_addr,cache_index, mf->get_data_size());
-        mf->set_data_size( m_config.get_line_sz() );
+    		m_tag_array->access(block_addr,time,cache_index,wb,evicted,mf);
+
+        m_mshrs.add(mshr_addr,mf);
+        if(m_config.is_streaming() && m_config.m_cache_type == SECTOR){
+			m_tag_array->add_pending_line(mf);
+		}
+        m_extra_mf_fields[mf] = extra_mf_fields(mshr_addr,mf->get_addr(),cache_index, mf->get_data_size(), m_config);
+        mf->set_data_size( m_config.get_atom_sz() );
+        mf->set_addr( mshr_addr );
         m_miss_queue.push_back(mf);
         mf->set_status(m_miss_queue_status,time);
         if(!wa)
-        	events.push_back(READ_REQUEST_SENT);
+        	events.push_back(cache_event(READ_REQUEST_SENT));
+
         do_miss = true;
     }
+    else if(mshr_hit && !mshr_avail)
+        m_stats.inc_fail_stats(mf->get_access_type(), MSHR_MERGE_ENRTY_FAIL);
+    else if (!mshr_hit && !mshr_avail)
+    	 m_stats.inc_fail_stats(mf->get_access_type(), MSHR_ENRTY_FAIL);
+    else
+    	assert(0);
 }
 
 
 /// Sends write request to lower level memory (write or writeback)
 void data_cache::send_write_request(mem_fetch *mf, cache_event request, unsigned time, std::list<cache_event> &events){
-    events.push_back(request);
+
+	events.push_back(request);
     m_miss_queue.push_back(mf);
     mf->set_status(m_miss_queue_status,time);
 }
@@ -798,40 +1080,44 @@ void data_cache::send_write_request(mem_fetch *mf, cache_event request, unsigned
 /// Write-back hit: Mark block as modified
 cache_request_status data_cache::wr_hit_wb(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events, enum cache_request_status status ){
 	new_addr_type block_addr = m_config.block_addr(addr);
-	m_tag_array->access(block_addr,time,cache_index); // update LRU state
-	cache_block_t &block = m_tag_array->get_block(cache_index);
-	block.m_status = MODIFIED;
+	m_tag_array->access(block_addr,time,cache_index,mf); // update LRU state
+	cache_block_t* block = m_tag_array->get_block(cache_index);
+	block->set_status(MODIFIED, mf->get_access_sector_mask());
 
 	return HIT;
 }
 
 /// Write-through hit: Directly send request to lower level memory
 cache_request_status data_cache::wr_hit_wt(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events, enum cache_request_status status ){
-	if(miss_queue_full(0))
+	if(miss_queue_full(0)) {
+		m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL);
 		return RESERVATION_FAIL; // cannot handle request this cycle
+	}
 
 	new_addr_type block_addr = m_config.block_addr(addr);
-	m_tag_array->access(block_addr,time,cache_index); // update LRU state
-	cache_block_t &block = m_tag_array->get_block(cache_index);
-	block.m_status = MODIFIED;
+	m_tag_array->access(block_addr,time,cache_index,mf); // update LRU state
+	cache_block_t* block = m_tag_array->get_block(cache_index);
+	block->set_status(MODIFIED, mf->get_access_sector_mask());
 
 	// generate a write-through
-	send_write_request(mf, WRITE_REQUEST_SENT, time, events);
+	send_write_request(mf, cache_event(WRITE_REQUEST_SENT), time, events);
 
 	return HIT;
 }
 
 /// Write-evict hit: Send request to lower level memory and invalidate corresponding block
 cache_request_status data_cache::wr_hit_we(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events, enum cache_request_status status ){
-	if(miss_queue_full(0))
+	if(miss_queue_full(0)) {
+		m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL);
 		return RESERVATION_FAIL; // cannot handle request this cycle
+	}
 
 	// generate a write-through/evict
-	cache_block_t &block = m_tag_array->get_block(cache_index);
-	send_write_request(mf, WRITE_REQUEST_SENT, time, events);
+	cache_block_t* block = m_tag_array->get_block(cache_index);
+	send_write_request(mf, cache_event(WRITE_REQUEST_SENT), time, events);
 
 	// Invalidate block
-	block.m_status = INVALID;
+	block->set_status(INVALID, mf->get_access_sector_mask());
 
 	return HIT;
 }
@@ -850,34 +1136,46 @@ enum cache_request_status data_cache::wr_hit_global_we_local_wb(new_addr_type ad
 /// Write-allocate miss: Send write request to lower level memory
 // and send a read request for the same block
 enum cache_request_status
-data_cache::wr_miss_wa( new_addr_type addr,
+data_cache::wr_miss_wa_naive( new_addr_type addr,
                         unsigned cache_index, mem_fetch *mf,
                         unsigned time, std::list<cache_event> &events,
                         enum cache_request_status status )
 {
     new_addr_type block_addr = m_config.block_addr(addr);
+    new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr());
 
     // Write allocate, maximum 3 requests (write miss, read request, write back request)
     // Conservatively ensure the worst-case request can be handled this cycle
-    bool mshr_hit = m_mshrs.probe(block_addr);
-    bool mshr_avail = !m_mshrs.full(block_addr);
+    bool mshr_hit = m_mshrs.probe(mshr_addr);
+    bool mshr_avail = !m_mshrs.full(mshr_addr);
     if(miss_queue_full(2) 
         || (!(mshr_hit && mshr_avail) 
-        && !(!mshr_hit && mshr_avail 
-        && (m_miss_queue.size() < m_config.m_miss_queue_size))))
+        && !(!mshr_hit && mshr_avail && (m_miss_queue.size() < m_config.m_miss_queue_size)))) {
+    	//check what is the exactly the failure reason
+    	 if(miss_queue_full(2) )
+    		 m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL);
+         else if(mshr_hit && !mshr_avail)
+    	      m_stats.inc_fail_stats(mf->get_access_type(), MSHR_MERGE_ENRTY_FAIL);
+    	 else if (!mshr_hit && !mshr_avail)
+    	    m_stats.inc_fail_stats(mf->get_access_type(), MSHR_ENRTY_FAIL);
+    	 else
+    		 assert(0);
+
         return RESERVATION_FAIL;
+    }
 
-    send_write_request(mf, WRITE_REQUEST_SENT, time, events);
+    send_write_request(mf, cache_event(WRITE_REQUEST_SENT), time, events);
     // Tries to send write allocate request, returns true on success and false on failure
     //if(!send_write_allocate(mf, addr, block_addr, cache_index, time, events))
     //    return RESERVATION_FAIL;
 
     const mem_access_t *ma = new  mem_access_t( m_wr_alloc_type,
                         mf->get_addr(),
-                        mf->get_data_size(),
+						m_config.get_atom_sz(),
                         false, // Now performing a read
                         mf->get_access_warp_mask(),
-                        mf->get_access_byte_mask() );
+                        mf->get_access_byte_mask(),
+		                mf->get_access_sector_mask());
 
     mem_fetch *n_mf = new mem_fetch( *ma,
                     NULL,
@@ -889,20 +1187,22 @@ data_cache::wr_miss_wa( new_addr_type addr,
 
     bool do_miss = false;
     bool wb = false;
-    cache_block_t evicted;
+    evicted_block_info evicted;
 
     // Send read request resulting from write miss
     send_read_request(addr, block_addr, cache_index, n_mf, time, do_miss, wb,
         evicted, events, false, true);
 
+    events.push_back(cache_event(WRITE_ALLOCATE_SENT));
+
     if( do_miss ){
         // If evicted block is modified and not a write-through
         // (already modified lower level)
         if( wb && (m_config.m_write_policy != WRITE_THROUGH) ) { 
+        	assert(status == MISS);   //SECTOR_MISS and HIT_RESERVED should not send write back
             mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr,
-                m_wrbk_type,m_config.get_line_sz(),true);
-            m_miss_queue.push_back(wb);
-            wb->set_status(m_miss_queue_status,time);
+                m_wrbk_type,evicted.m_modified_size,true);
+            send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events);
         }
         return MISS;
     }
@@ -910,6 +1210,177 @@ data_cache::wr_miss_wa( new_addr_type addr,
     return RESERVATION_FAIL;
 }
 
+
+enum cache_request_status
+data_cache::wr_miss_wa_fetch_on_write( new_addr_type addr,
+                        unsigned cache_index, mem_fetch *mf,
+                        unsigned time, std::list<cache_event> &events,
+                        enum cache_request_status status )
+{
+    new_addr_type block_addr = m_config.block_addr(addr);
+    new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr());
+
+	if(mf->get_access_byte_mask().count() == m_config.get_atom_sz())
+	{
+		//if the request writes to the whole cache line/sector, then, write and set cache line Modified.
+		//and no need to send read request to memory or reserve mshr
+
+		if(miss_queue_full(0)) {
+			m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL);
+			return RESERVATION_FAIL; // cannot handle request this cycle
+		}
+
+		bool wb = false;
+		evicted_block_info evicted;
+
+		cache_request_status status =  m_tag_array->access(block_addr,time,cache_index,wb,evicted,mf);
+		assert(status != HIT);
+		cache_block_t* block = m_tag_array->get_block(cache_index);
+		block->set_status(MODIFIED, mf->get_access_sector_mask());
+		if(status == HIT_RESERVED)
+			block->set_ignore_on_fill(true, mf->get_access_sector_mask());
+
+		if( status != RESERVATION_FAIL ){
+			   // If evicted block is modified and not a write-through
+			   // (already modified lower level)
+			   if( wb && (m_config.m_write_policy != WRITE_THROUGH) ) {
+				   mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr,
+					   m_wrbk_type,evicted.m_modified_size,true);
+				   send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events);
+			   }
+			   return MISS;
+		   }
+		return RESERVATION_FAIL;
+	}
+	else
+	{
+		bool mshr_hit = m_mshrs.probe(mshr_addr);
+		bool mshr_avail = !m_mshrs.full(mshr_addr);
+		if(miss_queue_full(1)
+			|| (!(mshr_hit && mshr_avail)
+			&& !(!mshr_hit && mshr_avail && (m_miss_queue.size() < m_config.m_miss_queue_size)))) {
+			//check what is the exactly the failure reason
+			 if(miss_queue_full(1) )
+				 m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL);
+			 else if(mshr_hit && !mshr_avail)
+				  m_stats.inc_fail_stats(mf->get_access_type(), MSHR_MERGE_ENRTY_FAIL);
+			 else if (!mshr_hit && !mshr_avail)
+				m_stats.inc_fail_stats(mf->get_access_type(), MSHR_ENRTY_FAIL);
+			 else
+				 assert(0);
+
+			return RESERVATION_FAIL;
+		}
+
+
+		  //prevent Write - Read - Write in pending mshr
+		  //allowing another write will override the value of the first write, and the pending read request will read incorrect result from the second write
+		  if(m_mshrs.probe(mshr_addr) && m_mshrs.is_read_after_write_pending(mshr_addr) && mf->is_write())
+		  {
+			  //assert(0);
+			  m_stats.inc_fail_stats(mf->get_access_type(), MSHR_RW_PENDING);
+			  return RESERVATION_FAIL;
+		  }
+
+		  const mem_access_t *ma = new  mem_access_t( m_wr_alloc_type,
+									mf->get_addr(),
+									m_config.get_atom_sz(),
+									false, // Now performing a read
+									mf->get_access_warp_mask(),
+									mf->get_access_byte_mask(),
+									mf->get_access_sector_mask());
+
+		  mem_fetch *n_mf = new mem_fetch( *ma,
+								NULL,
+								mf->get_ctrl_size(),
+								mf->get_wid(),
+								mf->get_sid(),
+								mf->get_tpc(),
+								mf->get_mem_config(),
+								NULL,
+								mf);
+
+
+			new_addr_type block_addr = m_config.block_addr(addr);
+			bool do_miss = false;
+			bool wb = false;
+			evicted_block_info evicted;
+			send_read_request( addr,
+							   block_addr,
+							   cache_index,
+							   n_mf, time, do_miss, wb, evicted, events, false, true);
+
+			cache_block_t* block = m_tag_array->get_block(cache_index);
+			block->set_modified_on_fill(true, mf->get_access_sector_mask());
+
+			events.push_back(cache_event(WRITE_ALLOCATE_SENT));
+
+			if( do_miss ){
+				// If evicted block is modified and not a write-through
+				// (already modified lower level)
+				if(wb && (m_config.m_write_policy != WRITE_THROUGH) ){
+					mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr,
+						m_wrbk_type,evicted.m_modified_size,true);
+					send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events);
+			}
+				return MISS;
+			}
+	   return RESERVATION_FAIL;
+	}
+}
+
+enum cache_request_status
+data_cache::wr_miss_wa_lazy_fetch_on_read( new_addr_type addr,
+                        unsigned cache_index, mem_fetch *mf,
+                        unsigned time, std::list<cache_event> &events,
+                        enum cache_request_status status )
+{
+
+	    new_addr_type block_addr = m_config.block_addr(addr);
+	    new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr());
+
+
+		//if the request writes to the whole cache line/sector, then, write and set cache line Modified.
+		//and no need to send read request to memory or reserve mshr
+
+		if(miss_queue_full(0)) {
+			m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL);
+			return RESERVATION_FAIL; // cannot handle request this cycle
+		}
+
+		bool wb = false;
+		evicted_block_info evicted;
+
+		cache_request_status m_status =  m_tag_array->access(block_addr,time,cache_index,wb,evicted,mf);
+		assert(m_status != HIT);
+		cache_block_t* block = m_tag_array->get_block(cache_index);
+		block->set_status(MODIFIED, mf->get_access_sector_mask());
+		if(m_status == HIT_RESERVED) {
+			block->set_ignore_on_fill(true, mf->get_access_sector_mask());
+			block->set_modified_on_fill(true, mf->get_access_sector_mask());
+		}
+
+		if(mf->get_access_byte_mask().count() == m_config.get_atom_sz())
+		{
+			block->set_m_readable(true, mf->get_access_sector_mask());
+		} else
+		{
+			block->set_m_readable(false, mf->get_access_sector_mask());
+		}
+
+		if( m_status != RESERVATION_FAIL ){
+			   // If evicted block is modified and not a write-through
+			   // (already modified lower level)
+			   if( wb && (m_config.m_write_policy != WRITE_THROUGH) ) {
+				   mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr,
+					   m_wrbk_type,evicted.m_modified_size,true);
+				   send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events);
+			   }
+			   return MISS;
+		   }
+		return RESERVATION_FAIL;
+}
+
 /// No write-allocate miss: Simply send write request to lower level memory
 enum cache_request_status
 data_cache::wr_miss_no_wa( new_addr_type addr,
@@ -919,11 +1390,14 @@ data_cache::wr_miss_no_wa( new_addr_type addr,
                            std::list<cache_event> &events,
                            enum cache_request_status status )
 {
-    if(miss_queue_full(0))
-        return RESERVATION_FAIL; // cannot handle request this cycle
+    if(miss_queue_full(0)) {
+    	m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL);
+    	return RESERVATION_FAIL; // cannot handle request this cycle
+    }
+
 
     // on miss, generate write through (no write buffering -- too many threads for that)
-    send_write_request(mf, WRITE_REQUEST_SENT, time, events);
+    send_write_request(mf, cache_event(WRITE_REQUEST_SENT), time, events);
 
     return MISS;
 }
@@ -941,13 +1415,13 @@ data_cache::rd_hit_base( new_addr_type addr,
                          enum cache_request_status status )
 {
     new_addr_type block_addr = m_config.block_addr(addr);
-    m_tag_array->access(block_addr,time,cache_index);
+    m_tag_array->access(block_addr,time,cache_index,mf);
     // Atomics treated as global read/write requests - Perform read, mark line as
     // MODIFIED
     if(mf->isatomic()){ 
         assert(mf->get_access_type() == GLOBAL_ACC_R);
-        cache_block_t &block = m_tag_array->get_block(cache_index);
-        block.m_status = MODIFIED;  // mark line as dirty
+        cache_block_t* block = m_tag_array->get_block(cache_index);
+        block->set_status(MODIFIED, mf->get_access_sector_mask()) ;  // mark line as dirty
     }
     return HIT;
 }
@@ -963,15 +1437,17 @@ data_cache::rd_miss_base( new_addr_type addr,
                           unsigned time,
                           std::list<cache_event> &events,
                           enum cache_request_status status ){
-    if(miss_queue_full(1))
+    if(miss_queue_full(1)) {
         // cannot handle request this cycle
         // (might need to generate two requests)
+    	m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL);
         return RESERVATION_FAIL; 
+    }
 
     new_addr_type block_addr = m_config.block_addr(addr);
     bool do_miss = false;
     bool wb = false;
-    cache_block_t evicted;
+    evicted_block_info evicted;
     send_read_request( addr,
                        block_addr,
                        cache_index,
@@ -982,12 +1458,12 @@ data_cache::rd_miss_base( new_addr_type addr,
         // (already modified lower level)
         if(wb && (m_config.m_write_policy != WRITE_THROUGH) ){ 
             mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr,
-                m_wrbk_type,m_config.get_line_sz(),true);
+                m_wrbk_type,evicted.m_modified_size,true);
         send_write_request(wb, WRITE_BACK_REQUEST_SENT, time, events);
     }
         return MISS;
     }
-    return RESERVATION_FAIL;
+        return RESERVATION_FAIL;
 }
 
 /// Access cache for read_only_cache: returns RESERVATION_FAIL if
@@ -998,16 +1474,16 @@ read_only_cache::access( new_addr_type addr,
                          unsigned time,
                          std::list<cache_event> &events )
 {
-    assert( mf->get_data_size() <= m_config.get_line_sz());
+    assert( mf->get_data_size() <= m_config.get_atom_sz());
     assert(m_config.m_write_policy == READ_ONLY);
     assert(!mf->get_is_write());
     new_addr_type block_addr = m_config.block_addr(addr);
     unsigned cache_index = (unsigned)-1;
-    enum cache_request_status status = m_tag_array->probe(block_addr,cache_index);
+    enum cache_request_status status = m_tag_array->probe(block_addr,cache_index,mf);
     enum cache_request_status cache_status = RESERVATION_FAIL;
 
     if ( status == HIT ) {
-        cache_status = m_tag_array->access(block_addr,time,cache_index); // update LRU state
+        cache_status = m_tag_array->access(block_addr,time,cache_index,mf); // update LRU state
     }else if ( status != RESERVATION_FAIL ) {
         if(!miss_queue_full(0)){
             bool do_miss=false;
@@ -1018,7 +1494,10 @@ read_only_cache::access( new_addr_type addr,
                 cache_status = RESERVATION_FAIL;
         }else{
             cache_status = RESERVATION_FAIL;
+            m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL);
         }
+    }else {
+    	m_stats.inc_fail_stats(mf->get_access_type(), LINE_ALLOC_FAIL);
     }
 
     m_stats.inc_stats(mf->get_access_type(), m_stats.select_stats_status(status, cache_status));
@@ -1047,10 +1526,13 @@ data_cache::process_tag_probe( bool wr,
             access_status = (this->*m_wr_hit)( addr,
                                       cache_index,
                                       mf, time, events, probe_status );
-        }else if ( probe_status != RESERVATION_FAIL ) {
+        }else if ( (probe_status != RESERVATION_FAIL) || (probe_status == RESERVATION_FAIL && m_config.m_write_alloc_policy == NO_WRITE_ALLOCATE) ) {
             access_status = (this->*m_wr_miss)( addr,
                                        cache_index,
                                        mf, time, events, probe_status );
+        }else {
+        	//the only reason for reservation fail here is LINE_ALLOC_FAIL (i.e all lines are reserved)
+        	m_stats.inc_fail_stats(mf->get_access_type(), LINE_ALLOC_FAIL);
         }
     }else{ // Read
         if(probe_status == HIT){
@@ -1061,6 +1543,9 @@ data_cache::process_tag_probe( bool wr,
             access_status = (this->*m_rd_miss)( addr,
                                        cache_index,
                                        mf, time, events, probe_status );
+        }else {
+        	//the only reason for reservation fail here is LINE_ALLOC_FAIL (i.e all lines are reserved)
+        	m_stats.inc_fail_stats(mf->get_access_type(), LINE_ALLOC_FAIL);
         }
     }
 
@@ -1080,12 +1565,12 @@ data_cache::access( new_addr_type addr,
                     std::list<cache_event> &events )
 {
 
-    assert( mf->get_data_size() <= m_config.get_line_sz());
+    assert( mf->get_data_size() <= m_config.get_atom_sz());
     bool wr = mf->get_is_write();
     new_addr_type block_addr = m_config.block_addr(addr);
     unsigned cache_index = (unsigned)-1;
     enum cache_request_status probe_status
-        = m_tag_array->probe( block_addr, cache_index );
+        = m_tag_array->probe( block_addr, cache_index, mf, true);
     enum cache_request_status access_status
         = process_tag_probe( wr, probe_status, addr, cache_index, mf, time, events );
     m_stats.inc_stats(mf->get_access_type(),
@@ -1134,7 +1619,7 @@ enum cache_request_status tex_cache::access( new_addr_type addr, mem_fetch *mf,
     // at this point, we will accept the request : access tags and immediately allocate line
     new_addr_type block_addr = m_config.block_addr(addr);
     unsigned cache_index = (unsigned)-1;
-    enum cache_request_status status = m_tags.access(block_addr,time,cache_index);
+    enum cache_request_status status = m_tags.access(block_addr,time,cache_index,mf);
     enum cache_request_status cache_status = RESERVATION_FAIL;
     assert( status != RESERVATION_FAIL );
     assert( status != HIT_RESERVED ); // as far as tags are concerned: HIT or MISS
@@ -1142,12 +1627,12 @@ enum cache_request_status tex_cache::access( new_addr_type addr, mem_fetch *mf,
     if ( status == MISS ) {
         // we need to send a memory request...
         unsigned rob_index = m_rob.push( rob_entry(cache_index, mf, block_addr) );
-        m_extra_mf_fields[mf] = extra_mf_fields(rob_index);
+        m_extra_mf_fields[mf] = extra_mf_fields(rob_index, m_config);
         mf->set_data_size(m_config.get_line_sz());
-        m_tags.fill(cache_index,time); // mark block as valid
+        m_tags.fill(cache_index,time,mf); // mark block as valid
         m_request_fifo.push(mf);
         mf->set_status(m_request_queue_status,time);
-        events.push_back(READ_REQUEST_SENT);
+        events.push_back(cache_event(READ_REQUEST_SENT));
         cache_status = MISS;
     } else {
         // the value *will* *be* in the cache already
@@ -1174,7 +1659,7 @@ void tex_cache::cycle(){
             unsigned rob_index = m_rob.next_pop_index();
             const rob_entry &r = m_rob.peek(rob_index);
             assert( r.m_request == e.m_request );
-            assert( r.m_block_addr == m_config.block_addr(e.m_request->get_addr()) );
+            //assert( r.m_block_addr == m_config.block_addr(e.m_request->get_addr()) );
             if ( r.m_ready ) {
                 assert( r.m_index == e.m_cache_index );
                 m_cache[r.m_index].m_valid = true;
@@ -1197,6 +1682,23 @@ void tex_cache::cycle(){
 /// Place returning cache block into reorder buffer
 void tex_cache::fill( mem_fetch *mf, unsigned time )
 {
+	if(m_config.m_mshr_type == SECTOR_TEX_FIFO) {
+	assert(mf->get_original_mf());
+	extra_mf_fields_lookup::iterator e = m_extra_mf_fields.find(mf->get_original_mf());
+    assert( e != m_extra_mf_fields.end() );
+    e->second.pending_read--;
+
+    if(e->second.pending_read > 0) {
+    	//wait for the other requests to come back
+    	delete mf;
+    	return;
+      } else {
+    	mem_fetch *temp = mf;
+    	mf = mf->get_original_mf();
+    	delete temp;
+      }
+	}
+
     extra_mf_fields_lookup::iterator e = m_extra_mf_fields.find(mf);
     assert( e != m_extra_mf_fields.end() );
     assert( e->second.m_valid );
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 7535a1d..e663cf6 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -36,9 +36,12 @@
 #include "../tr1_hash_map.h"
 
 #include "addrdec.h"
+#include <iostream>
+
+#define MAX_DEFAULT_CACHE_SIZE_MULTIBLIER 4
 
 enum cache_block_state {
-    INVALID,
+    INVALID=0,
     RESERVED,
     VALID,
     MODIFIED
@@ -49,13 +52,51 @@ enum cache_request_status {
     HIT_RESERVED,
     MISS,
     RESERVATION_FAIL, 
+	SECTOR_MISS,
     NUM_CACHE_REQUEST_STATUS
 };
 
-enum cache_event {
+enum cache_reservation_fail_reason {
+	LINE_ALLOC_FAIL= 0,// all line are reserved
+	MISS_QUEUE_FULL,   // MISS queue (i.e. interconnect or DRAM) is full
+	MSHR_ENRTY_FAIL,
+	MSHR_MERGE_ENRTY_FAIL,
+	MSHR_RW_PENDING,
+    NUM_CACHE_RESERVATION_FAIL_STATUS
+};
+
+enum cache_event_type {
     WRITE_BACK_REQUEST_SENT,
     READ_REQUEST_SENT,
-    WRITE_REQUEST_SENT
+    WRITE_REQUEST_SENT,
+	WRITE_ALLOCATE_SENT
+};
+
+struct evicted_block_info {
+	new_addr_type m_block_addr;
+	unsigned m_modified_size;
+	evicted_block_info() {
+		m_block_addr = 0;
+		m_modified_size = 0;
+	}
+	void set_info(new_addr_type block_addr, unsigned modified_size){
+		m_block_addr = block_addr;
+		m_modified_size = modified_size;
+	}
+};
+
+struct cache_event {
+	enum cache_event_type m_cache_event_type;
+	evicted_block_info m_evicted_block; //if it was write_back event, fill the the evicted block info
+
+	cache_event(enum cache_event_type m_cache_event){
+		m_cache_event_type = m_cache_event;
+	}
+
+	cache_event(enum cache_event_type cache_event, evicted_block_info evicted_block){
+	m_cache_event_type = cache_event;
+	m_evicted_block = evicted_block;
+	}
 };
 
 const char * cache_request_status_str(enum cache_request_status status); 
@@ -65,33 +106,340 @@ struct cache_block_t {
     {
         m_tag=0;
         m_block_addr=0;
-        m_alloc_time=0;
-        m_fill_time=0;
-        m_last_access_time=0;
-        m_status=INVALID;
     }
-    void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time )
+
+    virtual void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask) = 0;
+    virtual void fill( unsigned time, mem_access_sector_mask_t sector_mask) = 0;
+
+    virtual bool is_invalid_line() = 0;
+    virtual bool is_valid_line() = 0;
+    virtual bool is_reserved_line() = 0;
+    virtual bool is_modified_line() = 0;
+
+    virtual enum cache_block_state get_status( mem_access_sector_mask_t sector_mask) = 0;
+    virtual void set_status(enum cache_block_state m_status, mem_access_sector_mask_t sector_mask) = 0;
+
+    virtual unsigned get_last_access_time() = 0;
+    virtual void set_last_access_time(unsigned time, mem_access_sector_mask_t sector_mask) = 0;
+    virtual unsigned get_alloc_time() = 0;
+    virtual void set_ignore_on_fill(bool m_ignore, mem_access_sector_mask_t sector_mask) = 0;
+    virtual void set_modified_on_fill(bool m_modified, mem_access_sector_mask_t sector_mask) = 0;
+    virtual unsigned get_modified_size() = 0;
+    virtual void set_m_readable(bool readable, mem_access_sector_mask_t sector_mask)=0;
+    virtual bool is_readable(mem_access_sector_mask_t sector_mask)=0;
+    virtual void print_status()=0;
+    virtual ~cache_block_t() {}
+
+
+    new_addr_type    m_tag;
+    new_addr_type    m_block_addr;
+
+};
+
+struct line_cache_block: public cache_block_t  {
+	line_cache_block()
+	    {
+	        m_alloc_time=0;
+	        m_fill_time=0;
+	        m_last_access_time=0;
+	        m_status=INVALID;
+	        m_ignore_on_fill_status = false;
+	        m_set_modified_on_fill = false;
+	        m_readable = true;
+	    }
+	    void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask)
+	    {
+	        m_tag=tag;
+	        m_block_addr=block_addr;
+	        m_alloc_time=time;
+	        m_last_access_time=time;
+	        m_fill_time=0;
+	        m_status=RESERVED;
+	        m_ignore_on_fill_status = false;
+	        m_set_modified_on_fill = false;
+	    }
+		void fill( unsigned time, mem_access_sector_mask_t sector_mask )
+	    {
+	    	//if(!m_ignore_on_fill_status)
+	    	//	assert( m_status == RESERVED );
+
+	    	m_status = m_set_modified_on_fill? MODIFIED : VALID;
+
+	        m_fill_time=time;
+	    }
+		virtual bool is_invalid_line()
+	    {
+	    	return m_status == INVALID;
+	    }
+		virtual bool is_valid_line()
+	    {
+	    	 return m_status == VALID;
+	    }
+		virtual bool is_reserved_line()
+	    {
+	    	 return m_status == RESERVED;
+	    }
+		virtual bool is_modified_line()
+	    {
+	    	return m_status == MODIFIED;
+	    }
+
+		virtual enum cache_block_state get_status(mem_access_sector_mask_t sector_mask)
+	    {
+	    	return m_status;
+	    }
+		virtual void set_status(enum cache_block_state status, mem_access_sector_mask_t sector_mask)
+	    {
+	    	m_status = status;
+	    }
+		virtual unsigned get_last_access_time()
+		{
+			return m_last_access_time;
+		}
+		virtual void set_last_access_time(unsigned time, mem_access_sector_mask_t sector_mask)
+	    {
+	    	m_last_access_time = time;
+	    }
+		virtual unsigned get_alloc_time()
+	    {
+	    	return m_alloc_time;
+	    }
+		virtual void set_ignore_on_fill(bool m_ignore, mem_access_sector_mask_t sector_mask)
+		{
+			m_ignore_on_fill_status = m_ignore;
+		}
+		virtual void set_modified_on_fill(bool m_modified, mem_access_sector_mask_t sector_mask)
+		{
+	    	m_set_modified_on_fill = m_modified;
+		}
+		virtual unsigned  get_modified_size()
+		{
+			return SECTOR_CHUNCK_SIZE * SECTOR_SIZE;   //i.e. cache line size
+		}
+		virtual void set_m_readable(bool readable, mem_access_sector_mask_t sector_mask)
+		{
+			m_readable = readable;
+		}
+		virtual bool is_readable(mem_access_sector_mask_t sector_mask) {
+			return m_readable;
+		}
+		virtual void print_status() {
+			 printf("m_block_addr is %llu, status = %u\n", m_block_addr, m_status);
+		}
+
+
+private:
+	    unsigned         m_alloc_time;
+	    unsigned         m_last_access_time;
+	    unsigned         m_fill_time;
+	    cache_block_state    m_status;
+	    bool m_ignore_on_fill_status;
+	    bool m_set_modified_on_fill;
+	    bool m_readable;
+};
+
+struct sector_cache_block : public cache_block_t {
+	sector_cache_block()
     {
-        m_tag=tag;
-        m_block_addr=block_addr;
-        m_alloc_time=time;
-        m_last_access_time=time;
-        m_fill_time=0;
-        m_status=RESERVED;
+		init();
     }
-    void fill( unsigned time )
+
+	void init() {
+		for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) {
+			m_sector_alloc_time[i]= 0;
+			m_sector_fill_time[i]= 0;
+			m_last_sector_access_time[i]= 0;
+			m_status[i]= INVALID;
+			m_ignore_on_fill_status[i] = false;
+			m_set_modified_on_fill[i] = false;
+			m_readable[i] = true;
+			}
+			m_line_alloc_time=0;
+			m_line_last_access_time=0;
+			m_line_fill_time=0;
+	}
+
+	virtual void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask )
     {
-        assert( m_status == RESERVED );
-        m_status=VALID;
-        m_fill_time=time;
+    	allocate_line( tag,  block_addr,  time, sector_mask );
     }
 
-    new_addr_type    m_tag;
-    new_addr_type    m_block_addr;
-    unsigned         m_alloc_time;
-    unsigned         m_last_access_time;
-    unsigned         m_fill_time;
-    cache_block_state    m_status;
+    void allocate_line( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask )
+	{
+		//allocate a new line
+		//assert(m_block_addr != 0 && m_block_addr != block_addr);
+		init();
+		m_tag=tag;
+		m_block_addr=block_addr;
+
+		unsigned sidx = get_sector_index(sector_mask);
+
+		//set sector stats
+		m_sector_alloc_time[sidx]=time;
+		m_last_sector_access_time[sidx]=time;
+		m_sector_fill_time[sidx]=0;
+		m_status[sidx]=RESERVED;
+		m_ignore_on_fill_status[sidx] = false;
+		m_set_modified_on_fill[sidx] = false;
+
+		//set line stats
+		m_line_alloc_time=time;   //only set this for the first allocated sector
+		m_line_last_access_time=time;
+		m_line_fill_time=0;
+	}
+
+    void allocate_sector(unsigned time, mem_access_sector_mask_t sector_mask )
+	{
+    	//allocate invalid sector of this allocated valid line
+    	assert(is_valid_line());
+		unsigned sidx = get_sector_index(sector_mask);
+
+		//set sector stats
+		m_sector_alloc_time[sidx]=time;
+		m_last_sector_access_time[sidx]=time;
+		m_sector_fill_time[sidx]=0;
+		if(m_status[sidx]==MODIFIED)    //this should be the case only for fetch-on-write policy //TO DO
+			m_set_modified_on_fill[sidx] = true;
+		else
+			m_set_modified_on_fill[sidx] = false;
+
+		m_status[sidx]=RESERVED;
+		m_ignore_on_fill_status[sidx] = false;
+		//m_set_modified_on_fill[sidx] = false;
+		m_readable[sidx] = true;
+
+		//set line stats
+		m_line_last_access_time=time;
+		m_line_fill_time=0;
+	}
+
+    virtual void fill( unsigned time, mem_access_sector_mask_t sector_mask)
+    {
+    	unsigned sidx = get_sector_index(sector_mask);
+
+    //	if(!m_ignore_on_fill_status[sidx])
+    //	         assert( m_status[sidx] == RESERVED );
+
+    	m_status[sidx] = m_set_modified_on_fill[sidx]? MODIFIED : VALID;
+
+        m_sector_fill_time[sidx]=time;
+        m_line_fill_time=time;
+    }
+    virtual bool is_invalid_line() {
+    	//all the sectors should be invalid
+    	for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) {
+    		if (m_status[i] != INVALID)
+    			return false;
+    	}
+    	return true;
+    }
+    virtual bool is_valid_line() { return  !(is_invalid_line()); }
+    virtual bool is_reserved_line() {
+    	//if any of the sector is reserved, then the line is reserved
+		for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) {
+			if (m_status[i] == RESERVED)
+				return true;
+		}
+		return false;
+    }
+    virtual bool is_modified_line() {
+    	//if any of the sector is modified, then the line is modified
+    	for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) {
+			if (m_status[i] == MODIFIED)
+				return true;
+		}
+		return false;
+    }
+
+    virtual enum cache_block_state get_status(mem_access_sector_mask_t sector_mask)
+	{
+    	unsigned sidx = get_sector_index(sector_mask);
+
+		return m_status[sidx];
+	}
+
+    virtual void set_status(enum cache_block_state status, mem_access_sector_mask_t sector_mask)
+	{
+		unsigned sidx = get_sector_index(sector_mask);
+		m_status[sidx] = status;
+	}
+
+    virtual unsigned get_last_access_time()
+	{
+		return m_line_last_access_time;
+	}
+
+    virtual void set_last_access_time(unsigned time, mem_access_sector_mask_t sector_mask)
+	{
+		unsigned sidx = get_sector_index(sector_mask);
+
+		m_last_sector_access_time[sidx] = time;
+		m_line_last_access_time = time;
+	}
+
+    virtual unsigned get_alloc_time()
+	{
+		return m_line_alloc_time;
+	}
+
+    virtual void set_ignore_on_fill(bool m_ignore, mem_access_sector_mask_t sector_mask)
+	{
+		unsigned sidx = get_sector_index(sector_mask);
+		m_ignore_on_fill_status[sidx] = m_ignore;
+	}
+
+    virtual void set_modified_on_fill(bool m_modified, mem_access_sector_mask_t sector_mask)
+	{
+		unsigned sidx = get_sector_index(sector_mask);
+		m_set_modified_on_fill[sidx] = m_modified;
+	}
+
+    virtual void set_m_readable(bool readable, mem_access_sector_mask_t sector_mask)
+    {
+    	unsigned sidx = get_sector_index(sector_mask);
+    	m_readable[sidx] = readable;
+    }
+
+    virtual bool is_readable(mem_access_sector_mask_t sector_mask) {
+    	unsigned sidx = get_sector_index(sector_mask);
+    	return m_readable[sidx];
+	}
+
+    virtual unsigned  get_modified_size()
+	{
+		unsigned modified=0;
+		for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) {
+			if (m_status[i] == MODIFIED)
+				modified++;
+		}
+		return modified * SECTOR_SIZE;
+	}
+
+    virtual void print_status() {
+    	 printf("m_block_addr is %llu, status = %u %u %u %u\n", m_block_addr, m_status[0], m_status[1], m_status[2], m_status[3]);
+    }
+
+
+private:
+    unsigned m_sector_alloc_time[SECTOR_CHUNCK_SIZE];
+    unsigned m_last_sector_access_time[SECTOR_CHUNCK_SIZE];
+    unsigned m_sector_fill_time[SECTOR_CHUNCK_SIZE];
+    unsigned m_line_alloc_time;
+    unsigned m_line_last_access_time;
+    unsigned m_line_fill_time;
+    cache_block_state    m_status[SECTOR_CHUNCK_SIZE];
+    bool m_ignore_on_fill_status[SECTOR_CHUNCK_SIZE];
+    bool m_set_modified_on_fill[SECTOR_CHUNCK_SIZE];
+    bool m_readable[SECTOR_CHUNCK_SIZE];
+
+    unsigned get_sector_index(mem_access_sector_mask_t sector_mask)
+    {
+    	assert(sector_mask.count() == 1);
+    	for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) {
+    		if(sector_mask.to_ulong() & (1<<i))
+    			return i;
+    	}
+    }
 };
 
 enum replacement_policy_t {
@@ -109,26 +457,44 @@ enum write_policy_t {
 
 enum allocation_policy_t {
     ON_MISS,
-    ON_FILL
+    ON_FILL,
+	STREAMING
 };
 
 
 enum write_allocate_policy_t {
 	NO_WRITE_ALLOCATE,
-	WRITE_ALLOCATE
+	WRITE_ALLOCATE,
+	FETCH_ON_WRITE,
+	LAZY_FETCH_ON_READ
 };
 
 enum mshr_config_t {
-    TEX_FIFO,
-    ASSOC // normal cache 
+    TEX_FIFO, // Tex cache
+    ASSOC, // normal cache
+	SECTOR_TEX_FIFO,  //Tex cache sends requests to high-level sector cache
+	SECTOR_ASSOC // normal cache sends requests to high-level sector cache
 };
 
 enum set_index_function{
-    FERMI_HASH_SET_FUNCTION = 0,
-    LINEAR_SET_FUNCTION,
+	LINEAR_SET_FUNCTION = 0,
+	BITWISE_XORING_FUNCTION,
+	HASH_IPOLY_FUNCTION,
+	FERMI_HASH_SET_FUNCTION,
     CUSTOM_SET_FUNCTION
 };
 
+enum cache_type{
+    NORMAL = 0,
+    SECTOR
+};
+
+#define MAX_WARP_PER_SHADER 64
+#define INCT_TOTAL_BUFFER 64
+#define L2_TOTAL 64
+#define MAX_WARP_PER_SHADER 64
+#define MAX_WARP_PER_SHADER 64
+
 class cache_config {
 public:
     cache_config() 
@@ -140,27 +506,39 @@ public:
         m_config_stringPrefShared = NULL;
         m_data_port_width = 0;
         m_set_index_function = LINEAR_SET_FUNCTION;
+        m_is_streaming = false;
     }
     void init(char * config, FuncCache status)
     {
     	cache_status= status;
         assert( config );
-        char rp, wp, ap, mshr_type, wap, sif;
+        char ct, rp, wp, ap, mshr_type, wap, sif;
 
 
-        int ntok = sscanf(config,"%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u",
-                          &m_nset, &m_line_sz, &m_assoc, &rp, &wp, &ap, &wap,
+        int ntok = sscanf(config,"%c:%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u",
+                          &ct, &m_nset, &m_line_sz, &m_assoc, &rp, &wp, &ap, &wap,
                           &sif,&mshr_type,&m_mshr_entries,&m_mshr_max_merge,
                           &m_miss_queue_size, &m_result_fifo_entries,
                           &m_data_port_width);
 
-        if ( ntok < 11 ) {
+        if ( ntok < 12 ) {
             if ( !strcmp(config,"none") ) {
                 m_disabled = true;
                 return;
             }
             exit_parse_error();
         }
+
+        switch (ct) {
+			   case 'N': m_cache_type = NORMAL; break;
+			   case 'S': m_cache_type = SECTOR; break;
+			   default: exit_parse_error();
+        }
+        switch (rp) {
+               case 'L': m_replacement_policy = LRU; break;
+               case 'F': m_replacement_policy = FIFO; break;
+               default: exit_parse_error();
+        }
         switch (rp) {
         case 'L': m_replacement_policy = LRU; break;
         case 'F': m_replacement_policy = FIFO; break;
@@ -177,21 +555,46 @@ public:
         switch (ap) {
         case 'm': m_alloc_policy = ON_MISS; break;
         case 'f': m_alloc_policy = ON_FILL; break;
+        case 's': m_alloc_policy = STREAMING; break;
         default: exit_parse_error();
         }
+        if(m_alloc_policy == STREAMING) {
+        	//For streaming cache, we set the alloc policy to be on-fill to remove all line_alloc_fail stalls
+        	//we set the MSHRs to be equal to max allocated cache lines. This is possible by moving TAG to be shared between cache line and MSHR enrty (i.e. for each cache line, there is an MSHR rntey associated with it)
+        	//This is the easiest think we can think about to model (mimic) L1 streaming cache in Pascal and Volta
+        	//Based on our microbenchmakrs, MSHRs entries have been increasing substantially in Pascal and Volta
+        	//For more information about streaming cache, see:
+        	// http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+        	// https://ieeexplore.ieee.org/document/8344474/
+        	m_is_streaming = true;
+			m_alloc_policy = ON_FILL;
+			m_mshr_entries = m_nset*m_assoc*MAX_DEFAULT_CACHE_SIZE_MULTIBLIER;
+			if(m_cache_type == SECTOR)
+				m_mshr_entries *=  SECTOR_CHUNCK_SIZE;
+			m_mshr_max_merge = MAX_WARP_PER_SM;
+        }
         switch (mshr_type) {
-        case 'F': m_mshr_type = TEX_FIFO; assert(ntok==13); break;
+        case 'F': m_mshr_type = TEX_FIFO; assert(ntok==14); break;
+        case 'T': m_mshr_type = SECTOR_TEX_FIFO; assert(ntok==14); break;
         case 'A': m_mshr_type = ASSOC; break;
+        case 'S' : m_mshr_type = SECTOR_ASSOC; break;
         default: exit_parse_error();
         }
         m_line_sz_log2 = LOGB2(m_line_sz);
         m_nset_log2 = LOGB2(m_nset);
         m_valid = true;
+        m_atom_sz = (m_cache_type == SECTOR)? SECTOR_SIZE : m_line_sz;
+        original_m_assoc = m_assoc;
 
+        //For more details about difference between FETCH_ON_WRITE and WRITE VALIDAE policies
+        //Read: Jouppi, Norman P. "Cache write policies and performance". ISCA 93.
+        //WRITE_ALLOCATE is the old write policy in GPGPU-sim 3.x, that send WRITE and READ for every write request
         switch(wap){
-        case 'W': m_write_alloc_policy = WRITE_ALLOCATE; break;
         case 'N': m_write_alloc_policy = NO_WRITE_ALLOCATE; break;
-        default: exit_parse_error();
+        case 'W': m_write_alloc_policy = WRITE_ALLOCATE; break;
+        case 'F': m_write_alloc_policy = FETCH_ON_WRITE; break;
+        case 'L': m_write_alloc_policy = LAZY_FETCH_ON_READ; break;
+		default: exit_parse_error();
         }
 
         // detect invalid configuration 
@@ -208,6 +611,15 @@ public:
             assert(0 && "Invalid cache configuration: Writeback cache cannot allocate new line on fill. "); 
         }
 
+        if((m_write_alloc_policy == FETCH_ON_WRITE || m_write_alloc_policy == LAZY_FETCH_ON_READ )&& m_alloc_policy == ON_FILL)
+		{
+			assert(0 && "Invalid cache configuration: FETCH_ON_WRITE and LAZY_FETCH_ON_READ cannot work properly with ON_FILL policy. Cache must be ON_MISS. ");
+		}
+        if(m_cache_type == SECTOR)
+		{
+			assert(m_line_sz / SECTOR_SIZE == SECTOR_CHUNCK_SIZE && m_line_sz % SECTOR_SIZE == 0);
+		}
+
         // default: port to data array width and granularity = line size 
         if (m_data_port_width == 0) {
             m_data_port_width = m_line_sz; 
@@ -216,6 +628,7 @@ public:
 
         switch(sif){
         case 'H': m_set_index_function = FERMI_HASH_SET_FUNCTION; break;
+        case 'P': m_set_index_function = HASH_IPOLY_FUNCTION; break;
         case 'C': m_set_index_function = CUSTOM_SET_FUNCTION; break;
         case 'L': m_set_index_function = LINEAR_SET_FUNCTION; break;
         default: exit_parse_error();
@@ -227,12 +640,21 @@ public:
         assert( m_valid );
         return m_line_sz;
     }
+    unsigned get_atom_sz() const
+	{
+		assert( m_valid );
+		return m_atom_sz;
+	}
     unsigned get_num_lines() const
     {
         assert( m_valid );
         return m_nset * m_assoc;
     }
-
+    unsigned get_max_num_lines() const
+    {
+        assert( m_valid );
+        return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * m_nset * original_m_assoc;
+    }
     void print( FILE *fp ) const
     {
         fprintf( fp, "Size = %d B (%d Set x %d-way x %d byte line)\n", 
@@ -265,6 +687,32 @@ public:
     {
         return addr & ~(m_line_sz-1);
     }
+    new_addr_type mshr_addr( new_addr_type addr ) const
+	{
+    	return addr & ~(m_atom_sz-1);
+	}
+    enum mshr_config_t get_mshr_type() const
+	{
+    	return m_mshr_type;
+	}
+    void set_assoc(unsigned n)
+	{
+    	//set new assoc. L1 cache dynamically resized in Volta
+    	m_assoc = n;
+	}
+    unsigned get_nset() const
+	{
+		assert( m_valid );
+		return m_nset;
+	}
+    unsigned get_total_size_inKB() const
+	{
+		assert( m_valid );
+		return (m_assoc*m_nset*m_line_sz)/1024;
+	}
+    bool is_streaming() {
+    	return m_is_streaming;
+    }
     FuncCache get_cache_status() {return cache_status;}
     char *m_config_string;
     char *m_config_stringPrefL1;
@@ -285,11 +733,15 @@ protected:
     unsigned m_nset;
     unsigned m_nset_log2;
     unsigned m_assoc;
+    unsigned m_atom_sz;
+    unsigned original_m_assoc;
+    bool m_is_streaming;
 
     enum replacement_policy_t m_replacement_policy; // 'L' = LRU, 'F' = FIFO
     enum write_policy_t m_write_policy;             // 'T' = write through, 'B' = write back, 'R' = read only
     enum allocation_policy_t m_alloc_policy;        // 'm' = allocate on miss, 'f' = allocate on fill
     enum mshr_config_t m_mshr_type;
+    enum cache_type m_cache_type;
 
     write_allocate_policy_t m_write_alloc_policy;	// 'W' = Write allocate, 'N' = No write allocate
 
@@ -316,12 +768,14 @@ protected:
     friend class data_cache;
     friend class l1_cache;
     friend class l2_cache;
+    friend class memory_sub_partition;
 };
 
 class l1d_cache_config : public cache_config{
 public:
 	l1d_cache_config() : cache_config(){}
 	virtual unsigned set_index(new_addr_type addr) const;
+	unsigned l1_latency;
 };
 
 class l2_cache_config : public cache_config {
@@ -340,17 +794,20 @@ public:
     tag_array(cache_config &config, int core_id, int type_id );
     ~tag_array();
 
-    enum cache_request_status probe( new_addr_type addr, unsigned &idx ) const;
-    enum cache_request_status access( new_addr_type addr, unsigned time, unsigned &idx );
-    enum cache_request_status access( new_addr_type addr, unsigned time, unsigned &idx, bool &wb, cache_block_t &evicted );
+    enum cache_request_status probe( new_addr_type addr, unsigned &idx, mem_fetch* mf, bool probe_mode=false ) const;
+    enum cache_request_status probe( new_addr_type addr, unsigned &idx, mem_access_sector_mask_t mask, bool probe_mode=false, mem_fetch* mf = NULL ) const;
+    enum cache_request_status access( new_addr_type addr, unsigned time, unsigned &idx, mem_fetch* mf );
+    enum cache_request_status access( new_addr_type addr, unsigned time, unsigned &idx, bool &wb, evicted_block_info &evicted, mem_fetch* mf );
 
-    void fill( new_addr_type addr, unsigned time );
-    void fill( unsigned idx, unsigned time );
+    void fill( new_addr_type addr, unsigned time, mem_fetch* mf );
+    void fill( unsigned idx, unsigned time, mem_fetch* mf );
+    void fill( new_addr_type addr, unsigned time, mem_access_sector_mask_t mask );
 
     unsigned size() const { return m_config.get_num_lines();}
-    cache_block_t &get_block(unsigned idx) { return m_lines[idx];}
+    cache_block_t* get_block(unsigned idx) { return m_lines[idx];}
 
-    void flush(); // flash invalidate all entries
+    void flush(); // flush all written entries
+    void invalidate(); // invalidate all entries
     void new_window();
 
     void print( FILE *stream, unsigned &total_access, unsigned &total_misses ) const;
@@ -358,6 +815,8 @@ public:
     void get_stats(unsigned &total_access, unsigned &total_misses, unsigned &total_hit_res, unsigned &total_res_fail) const;
 
 	void update_cache_parameters(cache_config &config);
+	void add_pending_line(mem_fetch *mf);
+	void remove_pending_line(mem_fetch *mf);
 protected:
     // This constructor is intended for use only from derived classes that wish to
     // avoid unnecessary memory allocation that takes place in the
@@ -365,19 +824,20 @@ protected:
     tag_array( cache_config &config,
                int core_id,
                int type_id,
-               cache_block_t* new_lines );
+               cache_block_t** new_lines );
     void init( int core_id, int type_id );
 
 protected:
 
     cache_config &m_config;
 
-    cache_block_t *m_lines; /* nbanks x nset x assoc lines in total */
+    cache_block_t **m_lines; /* nbanks x nset x assoc lines in total */
 
     unsigned m_access;
     unsigned m_miss;
     unsigned m_pending_hit; // number of cache miss that hit a line that is allocated but not filled
     unsigned m_res_fail;
+    unsigned m_sector_miss;
 
     // performance counters for calculating the amount of misses within a time window
     unsigned m_prev_snapshot_access;
@@ -386,11 +846,16 @@ protected:
 
     int m_core_id; // which shader core is using this
     int m_type_id; // what kind of cache is this (normal, texture, constant)
+
+    bool is_used;  //a flag if the whole cache has ever been accessed before
+
+    typedef tr1_hash_map<new_addr_type,unsigned> line_table;
+    line_table pending_lines;
 };
 
 class mshr_table {
 public:
-    mshr_table( unsigned num_entries, unsigned max_merged )
+    mshr_table( unsigned num_entries, unsigned max_merged)
     : m_num_entries(num_entries),
     m_max_merged(max_merged)
 #if (tr1_hash_map_ismap == 0)
@@ -414,6 +879,8 @@ public:
     /// Returns next ready access
     mem_fetch *next_access();
     void display( FILE *fp ) const;
+    // Returns true if there is a pending read after write
+    bool is_read_after_write_pending(new_addr_type block_addr);
 
     void check_mshr_parameters( unsigned num_entries, unsigned max_merged )
     {
@@ -433,7 +900,9 @@ private:
         mshr_entry() : m_has_atomic(false) { }
     }; 
     typedef tr1_hash_map<new_addr_type,mshr_entry> table;
+    typedef tr1_hash_map<new_addr_type,mshr_entry> line_table;
     table m_data;
+    line_table pending_lines;
 
     // it may take several cycles to process the merged requests
     bool m_current_response_ready;
@@ -510,12 +979,14 @@ public:
     cache_stats();
     void clear();
     void inc_stats(int access_type, int access_outcome);
+    void inc_fail_stats(int access_type, int fail_outcome);
     enum cache_request_status select_stats_status(enum cache_request_status probe, enum cache_request_status access) const;
-    unsigned &operator()(int access_type, int access_outcome);
-    unsigned operator()(int access_type, int access_outcome) const;
+    unsigned &operator()(int access_type, int access_outcome, bool fail_outcome);
+    unsigned operator()(int access_type, int access_outcome, bool fail_outcome) const;
     cache_stats operator+(const cache_stats &cs);
     cache_stats &operator+=(const cache_stats &cs);
     void print_stats(FILE *fout, const char *cache_name = "Cache_stats") const;
+    void print_fail_stats(FILE *fout, const char *cache_name = "Cache_fail_stats") const;
 
     unsigned get_stats(enum mem_access_type *access_type, unsigned num_access_type, enum cache_request_status *access_status, unsigned num_access_status)  const;
     void get_sub_stats(struct cache_sub_stats &css) const;
@@ -523,8 +994,10 @@ public:
     void sample_cache_port_utility(bool data_port_busy, bool fill_port_busy); 
 private:
     bool check_valid(int type, int status) const;
+    bool check_fail_valid(int type, int fail) const;
 
     std::vector< std::vector<unsigned> > m_stats;
+    std::vector< std::vector<unsigned> > m_fail_stats;
 
     unsigned long long m_cache_port_available_cycles; 
     unsigned long long m_cache_data_port_busy_cycles; 
@@ -543,6 +1016,7 @@ public:
 
 bool was_write_sent( const std::list<cache_event> &events );
 bool was_read_sent( const std::list<cache_event> &events );
+bool was_writeallocate_sent( const std::list<cache_event> &events );
 
 /// Baseline cache
 /// Implements common functions for read_only_cache and data_cache
@@ -552,7 +1026,7 @@ public:
     baseline_cache( const char *name, cache_config &config, int core_id, int type_id, mem_fetch_interface *memport,
                      enum mem_fetch_status status )
     : m_config(config), m_tag_array(new tag_array(config,core_id,type_id)), 
-      m_mshrs(config.m_mshr_entries,config.m_mshr_max_merge), 
+      m_mshrs(config.m_mshr_entries,config.m_mshr_max_merge),
       m_bandwidth_management(config) 
     {
         init( name, config, memport, status );
@@ -564,7 +1038,7 @@ public:
                enum mem_fetch_status status )
     {
         m_name = name;
-        assert(config.m_mshr_type == ASSOC);
+        assert(config.m_mshr_type == ASSOC || config.m_mshr_type == SECTOR_ASSOC);
         m_memport=memport;
         m_miss_queue_status = status;
     }
@@ -594,6 +1068,7 @@ public:
     mem_fetch *next_access(){return m_mshrs.next_access();}
     // flash invalidate all entries in cache
     void flush(){m_tag_array->flush();}
+    void invalidate(){m_tag_array->invalidate();}
     void print(FILE *fp, unsigned &accesses, unsigned &misses) const;
     void display_state( FILE *fp ) const;
 
@@ -612,6 +1087,15 @@ public:
     bool data_port_free() const { return m_bandwidth_management.data_port_free(); } 
     bool fill_port_free() const { return m_bandwidth_management.fill_port_free(); } 
 
+    // This is a gapping hole we are poking in the system to quickly handle
+    // filling the cache on cudamemcopies. We don't care about anything other than
+    // L2 state after the memcopy - so just force the tag array to act as though
+    // something is read or written without doing anything else.
+    void force_tag_access( new_addr_type addr, unsigned time, mem_access_sector_mask_t mask )
+    {
+        m_tag_array->fill( addr, time, mask );
+    }
+
 protected:
     // Constructor that can be used by derived classes with custom tag arrays
     baseline_cache( const char *name,
@@ -633,24 +1117,31 @@ protected:
     std::string m_name;
     cache_config &m_config;
     tag_array*  m_tag_array;
-    mshr_table m_mshrs;
+	mshr_table m_mshrs;
     std::list<mem_fetch*> m_miss_queue;
     enum mem_fetch_status m_miss_queue_status;
     mem_fetch_interface *m_memport;
 
     struct extra_mf_fields {
         extra_mf_fields()  { m_valid = false;}
-        extra_mf_fields( new_addr_type a, unsigned i, unsigned d ) 
+        extra_mf_fields( new_addr_type a, new_addr_type ad, unsigned i, unsigned d, const cache_config& m_config)
         {
             m_valid = true;
             m_block_addr = a;
+            m_addr = ad;
             m_cache_index = i;
             m_data_size = d;
+        	pending_read = m_config.m_mshr_type == SECTOR_ASSOC? m_config.m_line_sz/SECTOR_SIZE : 0;
+
         }
         bool m_valid;
         new_addr_type m_block_addr;
+        new_addr_type m_addr;
         unsigned m_cache_index;
         unsigned m_data_size;
+        //this variable is used when a load request generates multiple load transactions
+        //For example, a read request from non-sector L1 request sends a request to sector L2
+        unsigned pending_read;
     };
 
     typedef std::map<mem_fetch*,extra_mf_fields> extra_mf_fields_lookup;
@@ -668,7 +1159,7 @@ protected:
     		unsigned time, bool &do_miss, std::list<cache_event> &events, bool read_only, bool wa);
     /// Read miss handler. Check MSHR hit or MSHR available
     void send_read_request(new_addr_type addr, new_addr_type block_addr, unsigned cache_index, mem_fetch *mf,
-    		unsigned time, bool &do_miss, bool &wb, cache_block_t &evicted, std::list<cache_event> &events, bool read_only, bool wa);
+    		unsigned time, bool &do_miss, bool &wb, evicted_block_info &evicted, std::list<cache_event> &events, bool read_only, bool wa);
 
     /// Sub-class containing all metadata for port bandwidth management 
     class bandwidth_management 
@@ -760,8 +1251,10 @@ public:
 
         // Set write miss function
         switch(m_config.m_write_alloc_policy){
-        case WRITE_ALLOCATE: m_wr_miss = &data_cache::wr_miss_wa; break;
         case NO_WRITE_ALLOCATE: m_wr_miss = &data_cache::wr_miss_no_wa; break;
+		case WRITE_ALLOCATE: m_wr_miss = &data_cache::wr_miss_wa_naive; break;
+		case FETCH_ON_WRITE: m_wr_miss = &data_cache::wr_miss_wa_fetch_on_write; break;
+		case LAZY_FETCH_ON_READ: m_wr_miss = &data_cache::wr_miss_wa_lazy_fetch_on_read; break;
         default:
             assert(0 && "Error: Must set valid cache write miss policy\n");
             break; // Need to set a write miss function
@@ -870,12 +1363,33 @@ protected:
     /// Sends read request, and possible write-back request,
     //  to lower level memory for a write miss with write-allocate
     enum cache_request_status
-        wr_miss_wa( new_addr_type addr,
-                    unsigned cache_index,
-                    mem_fetch *mf,
-                    unsigned time,
-                    std::list<cache_event> &events,
-                    enum cache_request_status status ); // write-allocate
+    	wr_miss_wa_naive( new_addr_type addr,
+                        unsigned cache_index,
+                        mem_fetch *mf,
+                        unsigned time,
+                        std::list<cache_event> &events,
+                        enum cache_request_status status ); // write-allocate-send-write-and-read-request
+	enum cache_request_status
+			   wr_miss_wa_fetch_on_write( new_addr_type addr,
+							unsigned cache_index,
+							mem_fetch *mf,
+							unsigned time,
+							std::list<cache_event> &events,
+							enum cache_request_status status ); // write-allocate with fetch-on-every-write
+	enum cache_request_status
+				   wr_miss_wa_lazy_fetch_on_read( new_addr_type addr,
+								unsigned cache_index,
+								mem_fetch *mf,
+								unsigned time,
+								std::list<cache_event> &events,
+								enum cache_request_status status ); // write-allocate with read-fetch-only
+	enum cache_request_status
+				wr_miss_wa_write_validate( new_addr_type addr,
+							unsigned cache_index,
+							mem_fetch *mf,
+							unsigned time,
+							std::list<cache_event> &events,
+							enum cache_request_status status ); // write-allocate that writes with no read fetch
     enum cache_request_status
         wr_miss_no_wa( new_addr_type addr,
                        unsigned cache_index,
@@ -991,7 +1505,7 @@ public:
     m_result_fifo(config.m_result_fifo_entries)
     {
         m_name = name;
-        assert(config.m_mshr_type == TEX_FIFO);
+        assert(config.m_mshr_type == TEX_FIFO || config.m_mshr_type == SECTOR_TEX_FIFO );
         assert(config.m_write_policy == READ_ONLY);
         assert(config.m_alloc_policy == ON_MISS);
         m_memport=memport;
@@ -1144,13 +1658,15 @@ private:
 
     struct extra_mf_fields {
         extra_mf_fields()  { m_valid = false;}
-        extra_mf_fields( unsigned i ) 
+        extra_mf_fields( unsigned i, const cache_config &m_config )
         {
             m_valid = true;
             m_rob_index = i;
+            pending_read = m_config.m_mshr_type == SECTOR_TEX_FIFO? m_config.m_line_sz/SECTOR_SIZE : 0;
         }
         bool m_valid;
         unsigned m_rob_index;
+        unsigned pending_read;
     };
 
     cache_stats m_stats;
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 63ba759..a8be4d2 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -150,6 +150,8 @@ void power_config::reg_options(class OptionParser * opp)
 
 void memory_config::reg_options(class OptionParser * opp)
 {
+    option_parser_register(opp, "-perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, 
+                                "Fill the L2 cache on memcpy", "1");
     option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, &scheduler_type, 
                                 "0 = fifo, 1 = FR-FCFS (defaul)", "1");
     option_parser_register(opp, "-gpgpu_dram_partition_queues", OPT_CSTR, &gpgpu_L2_queue_config, 
@@ -202,7 +204,27 @@ void memory_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-dram_latency", OPT_UINT32, &dram_latency,
                      "DRAM latency (default 30)",
                      "30");
-
+    option_parser_register(opp, "-dual_bus_interface", OPT_UINT32, &dual_bus_interface,
+                                        "dual_bus_interface (default = 0) ",
+                                        "0");
+    option_parser_register(opp, "-dram_bnk_indexing_policy", OPT_UINT32, &dram_bnk_indexing_policy,
+                                            "dram_bnk_indexing_policy (0 = normal indexing, 1 = Xoring with the higher bits) (Default = 0)",
+                                            "0");
+    option_parser_register(opp, "-dram_bnkgrp_indexing_policy", OPT_UINT32, &dram_bnkgrp_indexing_policy,
+                                            "dram_bnkgrp_indexing_policy (0 = take higher bits, 1 = take lower bits) (Default = 0)",
+                                            "0");
+    option_parser_register(opp, "-Seperate_Write_Queue_Enable", OPT_BOOL, &seperate_write_queue_enabled,
+                           "Seperate_Write_Queue_Enable",
+                           "0");
+    option_parser_register(opp, "-Write_Queue_Size", OPT_CSTR, &write_queue_size_opt,
+                                  "Write_Queue_Size",
+                                  "32:28:16");
+    option_parser_register(opp, "-Elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround,
+                               "elimnate_rw_turnaround i.e set tWTR and tRTW = 0",
+                               "0");
+    option_parser_register(opp, "-icnt_flit_size", OPT_UINT32, &icnt_flit_size,
+                               "icnt_flit_size",
+                               "32");
     m_address_mapping.addrdec_setoption(opp);
 }
 
@@ -229,6 +251,12 @@ void shader_core_config::reg_options(class OptionParser * opp)
                    "per-shader L1 data cache config "
                    " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
                    "none" );
+    option_parser_register(opp, "-l1_latency", OPT_UINT32, &m_L1D_config.l1_latency,
+                 "L1 Hit Latency",
+                 "0");
+    option_parser_register(opp, "-smem_latency", OPT_UINT32, &smem_latency,
+                 "smem Latency",
+                 "3");
     option_parser_register(opp, "-gpgpu_cache:dl1PrefL1", OPT_CSTR, &m_L1D_config.m_config_stringPrefL1,
                    "per-shader L1 data cache config "
                    " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
@@ -256,6 +284,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_shader_registers", OPT_UINT32, &gpgpu_shader_registers, 
                  "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)",
                  "8192");
+    option_parser_register(opp, "-gpgpu_ignore_resources_limitation", OPT_BOOL, &gpgpu_ignore_resources_limitation,
+                 "gpgpu_ignore_resources_limitation (default 0)",
+                 "0");
     option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, 
                  "Maximum number of concurrent CTAs in shader (default 8)",
                  "8");
@@ -277,6 +308,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size,
                  "Size of shared memory per shader core (default 16kB)",
                  "16384");
+    option_parser_register(opp, "-adpative_volta_cache_config", OPT_BOOL, &adpative_volta_cache_config,
+                 "adpative_volta_cache_config",
+                 "0");
     option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_sizeDefault,
                  "Size of shared memory per shader core (default 16kB)",
                  "16384");
@@ -295,6 +329,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts,  
                  "Number of portions a warp is divided into for shared memory bank conflict check ",
                  "2");
+    option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts,
+				 "Number of portions a warp is divided into for shared memory bank conflict check ",
+				 "2");
     option_parser_register(opp, "-gpgpu_warpdistro_shader", OPT_INT32, &gpgpu_warpdistro_shader, 
                 "Specify which shader core to collect the warp size distribution from", 
                 "-1");
@@ -303,7 +340,7 @@ void shader_core_config::reg_options(class OptionParser * opp)
                 "0");
     option_parser_register(opp, "-gpgpu_local_mem_map", OPT_BOOL, &gpgpu_local_mem_map, 
                 "Mapping from local memory space address to simulated GPU physical address space (default = enabled)", 
-                "1");
+		"1");
     option_parser_register(opp, "-gpgpu_num_reg_banks", OPT_INT32, &gpgpu_num_reg_banks, 
                 "Number of register banks (default = 8)", 
                 "8");
@@ -313,6 +350,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_units_sp", OPT_INT32, &gpgpu_operand_collector_num_units_sp,
                 "number of collector units (default = 4)", 
                 "4");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_units_dp", OPT_INT32, &gpgpu_operand_collector_num_units_dp,
+                   "number of collector units (default = 0)",
+                   "0");
     option_parser_register(opp, "-gpgpu_operand_collector_num_units_sfu", OPT_INT32, &gpgpu_operand_collector_num_units_sfu,
                 "number of collector units (default = 4)", 
                 "4");
@@ -328,6 +368,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_sp", OPT_INT32, &gpgpu_operand_collector_num_in_ports_sp,
                            "number of collector unit in ports (default = 1)", 
                            "1");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_dp", OPT_INT32, &gpgpu_operand_collector_num_in_ports_dp,
+                           "number of collector unit in ports (default = 0)",
+                           "0");
     option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_sfu", OPT_INT32, &gpgpu_operand_collector_num_in_ports_sfu,
                            "number of collector unit in ports (default = 1)", 
                            "1");
@@ -343,6 +386,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_sp", OPT_INT32, &gpgpu_operand_collector_num_out_ports_sp,
                            "number of collector unit in ports (default = 1)", 
                            "1");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_dp", OPT_INT32, &gpgpu_operand_collector_num_out_ports_dp,
+                           "number of collector unit in ports (default = 0)",
+                           "0");
     option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_sfu", OPT_INT32, &gpgpu_operand_collector_num_out_ports_sfu,
                            "number of collector unit in ports (default = 1)", 
                            "1");
@@ -356,27 +402,33 @@ void shader_core_config::reg_options(class OptionParser * opp)
                            "number of collector unit in ports (default = 0)", 
                            "0");
     option_parser_register(opp, "-gpgpu_coalesce_arch", OPT_INT32, &gpgpu_coalesce_arch, 
-                            "Coalescing arch (default = 13, anything else is off for now)", 
+    		            "Coalescing arch (GT200 = 13, Fermi = 20)",
                             "13");
     option_parser_register(opp, "-gpgpu_num_sched_per_core", OPT_INT32, &gpgpu_num_sched_per_core, 
                             "Number of warp schedulers per core", 
                             "1");
     option_parser_register(opp, "-gpgpu_max_insn_issue_per_warp", OPT_INT32, &gpgpu_max_insn_issue_per_warp,
-                            "Max number of instructions that can be issued per warp in one cycle by scheduler",
-                            "2");
+    		            "Max number of instructions that can be issued per warp in one cycle by scheduler (either 1 or 2)",
+			    "2");
+    option_parser_register(opp, "-gpgpu_dual_issue_diff_exec_units", OPT_BOOL, &gpgpu_dual_issue_diff_exec_units,
+			    "should dual issue use two different execution unit resources (Default = 1)",
+			    "1");
     option_parser_register(opp, "-gpgpu_simt_core_sim_order", OPT_INT32, &simt_core_sim_order,
                             "Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)",
                             "1");
     option_parser_register(opp, "-gpgpu_pipeline_widths", OPT_CSTR, &pipeline_widths_string,
                             "Pipeline widths "
-                            "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB",
-                            "1,1,1,1,1,1,1,1,1,1" );
+                            "ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE",
+                            "1,1,1,1,1,1,1,1,1,1,1" );
     option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_INT32, &gpgpu_tensor_core_avail,
                             "Tensor Core Available (default=0)",
                             "0");
     option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32, &gpgpu_num_sp_units,
                             "Number of SP units (default=1)",
                             "1");
+    option_parser_register(opp, "-gpgpu_num_dp_units", OPT_INT32, &gpgpu_num_dp_units,
+                            "Number of DP units (default=0)",
+                            "0");
     option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_INT32, &gpgpu_num_sfu_units,
                             "Number of SF units (default=1)",
                             "1");
@@ -425,7 +477,6 @@ void gpgpu_sim_config::reg_options(option_parser_t opp)
    option_parser_register(opp, "-gpgpu_flush_l2_cache", OPT_BOOL, &gpgpu_flush_l2_cache,
                    "Flush L2 cache at the end of each kernel call",
                    "0");
-
    option_parser_register(opp, "-gpgpu_deadlock_detect", OPT_BOOL, &gpu_deadlock_detect, 
                 "Stop the simulation at deadlock (1=on (default), 0=off)", 
                 "1");
@@ -669,7 +720,7 @@ gpgpu_sim::gpgpu_sim( const gpgpu_sim_config &config )
 
     m_running_kernels.resize( config.max_concurrent_kernel, NULL );
     m_last_issued_kernel = 0;
-    m_last_cluster_issue = 0;
+    m_last_cluster_issue = m_shader_config->n_simt_clusters-1; // this causes first launch to use simt cluster 0
     *average_pipeline_duty_cycle=0;
     *active_sms=0;
 
@@ -813,6 +864,7 @@ void gpgpu_sim::update_stats() {
     partiton_replys_in_parallel_total += partiton_replys_in_parallel;
     partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util;
     gpu_tot_sim_cycle_parition_util += gpu_sim_cycle_parition_util ;
+    gpu_tot_occupancy += gpu_occupancy;
 
     gpu_sim_cycle = 0;
     partiton_reqs_in_parallel = 0;
@@ -821,6 +873,7 @@ void gpgpu_sim::update_stats() {
     gpu_sim_cycle_parition_util = 0;
     gpu_sim_insn = 0;
     m_total_cta_launched = 0;
+    gpu_occupancy = occupancy_stats();
 }
 
 void gpgpu_sim::print_stats()
@@ -994,6 +1047,9 @@ void gpgpu_sim::gpu_print_stat()
    printf("gpu_tot_sim_insn = %lld\n", gpu_tot_sim_insn+gpu_sim_insn);
    printf("gpu_tot_ipc = %12.4f\n", (float)(gpu_tot_sim_insn+gpu_sim_insn) / (gpu_tot_sim_cycle+gpu_sim_cycle));
    printf("gpu_tot_issued_cta = %lld\n", gpu_tot_issued_cta + m_total_cta_launched);
+   printf("gpu_occupancy = %.4f\% \n", gpu_occupancy.get_occ_fraction() * 100);
+   printf("gpu_tot_occupancy = %.4f\% \n", (gpu_occupancy + gpu_tot_occupancy).get_occ_fraction() * 100);
+
 
    extern unsigned long long g_max_total_param_size;
    fprintf(statfout, "max_total_param_size = %llu\n", g_max_total_param_size);
@@ -1032,6 +1088,8 @@ void gpgpu_sim::gpu_print_stat()
    }
    printf("\nTotal_core_cache_stats:\n");
    core_cache_stats.print_stats(stdout, "Total_core_cache_stats_breakdown");
+   printf("\nTotal_core_cache_fail_stats:\n");
+   core_cache_stats.print_fail_stats(stdout, "Total_core_cache_fail_stats_breakdown");
    shader_print_scheduler_stat( stdout, false );
 
    m_shader_stats->print(stdout);
@@ -1076,6 +1134,8 @@ void gpgpu_sim::gpu_print_stat()
           printf("L2_total_cache_reservation_fails = %u\n", total_l2_css.res_fails);
           printf("L2_total_cache_breakdown:\n");
           l2_stats.print_stats(stdout, "L2_cache_stats_breakdown");
+          printf("L2_total_cache_reservation_fail_breakdown:\n");
+          l2_stats.print_fail_stats(stdout, "L2_cache_stats_fail_breakdown");
           total_l2_css.print_port_stats(stdout, "L2_cache");
        }
    }
@@ -1429,7 +1489,7 @@ void gpgpu_sim::cycle()
             if (mf) {
                 unsigned response_size = mf->get_is_write()?mf->get_ctrl_size():mf->size();
                 if ( ::icnt_has_buffer( m_shader_config->mem2device(i), response_size ) ) {
-                    if (!mf->get_is_write()) 
+                    //if (!mf->get_is_write())
                        mf->set_return_timestamp(gpu_sim_cycle+gpu_tot_sim_cycle);
                     mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle);
                     ::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size );
@@ -1462,12 +1522,14 @@ void gpgpu_sim::cycle()
       for (unsigned i=0;i<m_memory_config->m_n_mem_sub_partition;i++) {
           //move memory request from interconnect into memory partition (if not backed up)
           //Note:This needs to be called in DRAM clock domain if there is no L2 cache in the system
-          if ( m_memory_sub_partition[i]->full() ) {
+    	  //In the worst case, we may need to push SECTOR_CHUNCK_SIZE requests, so ensure you have enough buffer for them
+          if ( m_memory_sub_partition[i]->full(SECTOR_CHUNCK_SIZE) ) {
              gpu_stall_dramfull++;
           } else {
               mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) );
               m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle );
-              partiton_reqs_in_parallel_per_cycle++;
+              if(mf)
+            	  partiton_reqs_in_parallel_per_cycle++;
           }
           m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle);
           m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]);
@@ -1494,6 +1556,8 @@ void gpgpu_sim::cycle()
          // Update core icnt/cache stats for GPUWattch
          m_cluster[i]->get_icnt_stats(m_power_stats->pwr_mem_stat->n_simt_to_mem[CURRENT_STAT_IDX][i], m_power_stats->pwr_mem_stat->n_mem_to_simt[CURRENT_STAT_IDX][i]);
          m_cluster[i]->get_cache_stats(m_power_stats->pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX]);
+         m_cluster[i]->get_current_occupancy(gpu_occupancy.aggregate_warp_slot_filled, gpu_occupancy.aggregate_theoretical_warp_slots);
+
       }
       float temp=0;
       for (unsigned i=0;i<m_shader_config->num_shader();i++){
@@ -1521,12 +1585,12 @@ void gpgpu_sim::cycle()
 
       issue_block2core();
       
-      // Depending on configuration, flush the caches once all of threads are completed.
+      // Depending on configuration, invalidate the caches once all of threads are completed.
       int all_threads_complete = 1;
       if (m_config.gpgpu_flush_l1_cache) {
          for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++) {
             if (m_cluster[i]->get_not_completed() == 0)
-                m_cluster[i]->cache_flush();
+                m_cluster[i]->cache_invalidate();
             else
                all_threads_complete = 0 ;
          }
@@ -1548,7 +1612,7 @@ void gpgpu_sim::cycle()
                int dlc = 0;
                for (unsigned i=0;i<m_memory_config->m_n_mem;i++) {
                   dlc = m_memory_sub_partition[i]->flushL2();
-                  assert (dlc == 0); // need to model actual writes to DRAM here
+                  assert (dlc == 0); // TODO: need to model actual writes to DRAM here
                   printf("Dirty lines flushed from L2 %d is %d\n", i, dlc  );
                }
             }
@@ -1560,15 +1624,20 @@ void gpgpu_sim::cycle()
          time_t curr_time;
          time(&curr_time);
          unsigned long long  elapsed_time = MAX(curr_time - g_simulation_starttime, 1);
-         if ( (elapsed_time - last_liveness_message_time) >= m_config.liveness_message_freq ) {
+         if ( (elapsed_time - last_liveness_message_time) >= m_config.liveness_message_freq && DTRACE(LIVENESS) ) {
             days    = elapsed_time/(3600*24);
             hrs     = elapsed_time/3600 - 24*days;
             minutes = elapsed_time/60 - 60*(hrs + 24*days);
             sec = elapsed_time - 60*(minutes + 60*(hrs + 24*days));
-
-            DPRINTF(LIVENESS, "GPGPU-Sim uArch: cycles simulated: %lld  inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", 
-                   gpu_tot_sim_cycle + gpu_sim_cycle, gpu_tot_sim_insn + gpu_sim_insn, 
+            
+            unsigned long long active = 0, total = 0;
+            for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++) {
+                m_cluster[i]->get_current_occupancy(active, total);
+            }
+            DPRINTF(LIVENESS, "uArch: inst.: %lld (ipc=%4.1f, occ=%0.4f\% [%llu / %llu]) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", 
+                   gpu_tot_sim_insn + gpu_sim_insn, 
                    (double)gpu_sim_insn/(double)gpu_sim_cycle,
+                   float(active)/float(total) * 100, active, total,
                    (unsigned)((gpu_tot_sim_insn+gpu_sim_insn) / elapsed_time),
                    (unsigned)days,(unsigned)hrs,(unsigned)minutes,(unsigned)sec,
                    ctime(&curr_time));
@@ -1620,6 +1689,24 @@ void shader_core_ctx::dump_warp_state( FILE *fout ) const
        m_warp[w].print(fout);
 }
 
+
+void gpgpu_sim::perf_memcpy_to_gpu( size_t dst_start_addr, size_t count )
+{
+    if (m_memory_config->m_perf_sim_memcpy) {
+       assert (dst_start_addr % 32 == 0);
+
+       for ( unsigned counter = 0; counter < count; counter += 32 ) {
+           const unsigned wr_addr = dst_start_addr + counter;
+           addrdec_t raw_addr;
+           mem_access_sector_mask_t mask;
+           mask.set(wr_addr % 128 / 32);
+           m_memory_config->m_address_mapping.addrdec_tlx( wr_addr, &raw_addr );
+           const unsigned partition_id = raw_addr.sub_partition / m_memory_config->m_n_sub_partition_per_memory_channel;
+           m_memory_partition_unit[ partition_id ]->handle_memcpy_to_gpu( wr_addr, raw_addr.sub_partition, mask );
+       }
+    }
+}
+
 void gpgpu_sim::dump_pipeline( int mask, int s, int m ) const
 {
 /*
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 7d92c66..1bae1fa 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -198,8 +198,14 @@ struct memory_config {
       bk_tag_length = i-1;
       assert(nbkgrp>0 && "Number of bank groups cannot be zero");
       tRCDWR = tRCD-(WL+1);
+      if(elimnate_rw_turnaround)
+      {
+    	  tRTW = 0;
+    	  tWTR = 0;
+      } else {
       tRTW = (CL+(BL/data_command_freq_ratio)+2-WL);
-      tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR); 
+      tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR);
+      }
       tWTP = (WL+(BL/data_command_freq_ratio)+tWR);
       dram_atom_size = BL * busW * gpu_n_mem_per_ctrlr; // burst length x bus width x # chips per partition 
 
@@ -213,7 +219,9 @@ struct memory_config {
       m_L2_config.init(&m_address_mapping);
 
       m_valid = true;
-      icnt_flit_size = 32; // Default 32
+
+      sscanf(write_queue_size_opt,"%d:%d:%d",
+                     &gpgpu_frfcfs_dram_write_queue_size,&write_high_watermark,&write_low_watermark);
    }
    void reg_options(class OptionParser * opp);
 
@@ -264,12 +272,25 @@ struct memory_config {
 
    unsigned nbk;
 
+   bool elimnate_rw_turnaround;
+
    unsigned data_command_freq_ratio; // frequency ratio between DRAM data bus and command bus (2 for GDDR3, 4 for GDDR5)
    unsigned dram_atom_size; // number of bytes transferred per read or write command 
 
    linear_to_raw_address_translation m_address_mapping;
 
    unsigned icnt_flit_size;
+
+   unsigned dram_bnk_indexing_policy;
+   unsigned dram_bnkgrp_indexing_policy;
+   bool dual_bus_interface;
+
+   bool seperate_write_queue_enabled;
+   char *write_queue_size_opt;
+   unsigned gpgpu_frfcfs_dram_write_queue_size;
+   unsigned write_high_watermark;
+   unsigned write_low_watermark;
+   bool m_perf_sim_memcpy;
 };
 
 // global counters and flags (please try not to add to this list!!!)
@@ -362,6 +383,32 @@ private:
     friend class gpgpu_sim;
 };
 
+struct occupancy_stats {
+    occupancy_stats() : aggregate_warp_slot_filled(0), aggregate_theoretical_warp_slots(0){}
+    occupancy_stats( unsigned long long wsf, unsigned long long tws )
+        : aggregate_warp_slot_filled(wsf), aggregate_theoretical_warp_slots(tws){}
+
+    unsigned long long aggregate_warp_slot_filled;
+    unsigned long long aggregate_theoretical_warp_slots;
+
+    float get_occ_fraction() const {
+        return float(aggregate_warp_slot_filled) / float(aggregate_theoretical_warp_slots);
+    }
+
+    occupancy_stats& operator+=(const occupancy_stats& rhs) {
+        aggregate_warp_slot_filled += rhs.aggregate_warp_slot_filled;
+        aggregate_theoretical_warp_slots += rhs.aggregate_theoretical_warp_slots;
+        return *this;
+    }
+
+    occupancy_stats operator+(const occupancy_stats& rhs) const{
+        return occupancy_stats( aggregate_warp_slot_filled + rhs.aggregate_warp_slot_filled,
+                                aggregate_theoretical_warp_slots + rhs.aggregate_theoretical_warp_slots
+                               );
+    }
+};
+
+
 class gpgpu_sim : public gpgpu_t {
 public:
    gpgpu_sim( const gpgpu_sim_config &config );
@@ -405,6 +452,8 @@ public:
    void gpu_print_stat();
    void dump_pipeline( int mask, int s, int m ) const;
 
+    void perf_memcpy_to_gpu( size_t dst_start_addr, size_t count );
+
    //The next three functions added to be used by the functional simulation function
    
    //! Get shader core configuration
@@ -498,6 +547,9 @@ public:
    unsigned long long  gpu_tot_sim_insn;
    unsigned long long  gpu_sim_insn_last_update;
    unsigned gpu_sim_insn_last_update_sid;
+   occupancy_stats gpu_occupancy;
+   occupancy_stats gpu_tot_occupancy;
+
 
    FuncCache get_cache_config(std::string kernel_name);
    void set_cache_config(std::string kernel_name, FuncCache cacheConfig );
@@ -526,4 +578,5 @@ public:
    }
 };
 
+
 #endif
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index c5fc44e..25da107 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -74,6 +74,15 @@ memory_partition_unit::memory_partition_unit( unsigned partition_id,
     }
 }
 
+void memory_partition_unit::handle_memcpy_to_gpu( size_t addr, unsigned global_subpart_id, mem_access_sector_mask_t mask )
+{
+    unsigned p = global_sub_partition_id_to_local_id(global_subpart_id);
+    std::string mystring =
+        mask.to_string<char,std::string::traits_type,std::string::allocator_type>();
+    MEMPART_DPRINTF("Copy Engine Request Received For Address=%llx, local_subpart=%u, global_subpart=%u, sector_mask=%s \n", addr, p, global_subpart_id, mystring.c_str()); 
+    m_sub_partition[p]->force_l2_tag_update(addr,gpu_sim_cycle+gpu_tot_sim_cycle, mask);
+}
+
 memory_partition_unit::~memory_partition_unit() 
 {
     delete m_dram; 
@@ -93,7 +102,9 @@ memory_partition_unit::arbitration_metadata::arbitration_metadata(const struct m
     m_private_credit_limit = 1; 
     m_shared_credit_limit = config->gpgpu_frfcfs_dram_sched_queue_size 
                             + config->gpgpu_dram_return_queue_size 
-                            - (config->m_n_sub_partition_per_memory_channel - 1); 
+                            - (config->m_n_sub_partition_per_memory_channel - 1);
+    if(config->seperate_write_queue_enabled )
+    	m_shared_credit_limit += config->gpgpu_frfcfs_dram_write_queue_size;
     if (config->gpgpu_frfcfs_dram_sched_queue_size == 0 
         or config->gpgpu_dram_return_queue_size == 0) 
     {
@@ -220,7 +231,8 @@ void memory_partition_unit::dram_cycle()
     m_dram->cycle(); 
     m_dram->dram_log(SAMPLELOG);   
 
-    if( !m_dram->full() ) {
+   // mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top();
+    //if( !m_dram->full(mf->is_write()) ) {
         // L2->DRAM queue to DRAM latency queue
         // Arbitrate among multiple L2 subpartitions 
         int last_issued_partition = m_arbitration_metadata.last_borrower(); 
@@ -228,6 +240,9 @@ void memory_partition_unit::dram_cycle()
             int spid = (p + last_issued_partition + 1) % m_config->m_n_sub_partition_per_memory_channel; 
             if (!m_sub_partition[spid]->L2_dram_queue_empty() && can_issue_to_dram(spid)) {
                 mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top();
+                if(m_dram->full(mf->is_write()) )
+                	break;
+
                 m_sub_partition[spid]->L2_dram_queue_pop();
                 MEMPART_DPRINTF("Issue mem_fetch request %p from sub partition %d to dram\n", mf, spid); 
                 dram_delay_t d;
@@ -239,12 +254,13 @@ void memory_partition_unit::dram_cycle()
                 break;  // the DRAM should only accept one request per cycle 
             }
         }
-    }
+    //}
 
     // DRAM latency queue
-    if( !m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle ) && !m_dram->full() ) {
-        mem_fetch* mf = m_dram_latency_queue.front().req;
-        m_dram_latency_queue.pop_front();
+
+    if( !m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle ) && !m_dram->full(m_dram_latency_queue.front().req->is_write()) ) {
+    	mem_fetch* mf = m_dram_latency_queue.front().req;
+    	m_dram_latency_queue.pop_front();
         m_dram->push(mf);
     }
 }
@@ -299,6 +315,7 @@ memory_sub_partition::memory_sub_partition( unsigned sub_partition_id,
     m_id = sub_partition_id;
     m_config=config;
     m_stats=stats;
+    m_memcpy_cycle_offset = 0;
 
     assert(m_id < m_config->m_n_mem_sub_partition); 
 
@@ -343,6 +360,14 @@ void memory_sub_partition::cache_cycle( unsigned cycle )
 				mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
 				m_L2_icnt_queue->push(mf);
            }else{
+        	    if(m_config->m_L2_config.m_write_alloc_policy == FETCH_ON_WRITE)
+        	    {
+        	    	mem_fetch* original_wr_mf = mf->get_original_wr_mf();
+					assert(original_wr_mf);
+					original_wr_mf->set_reply();
+					original_wr_mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
+					m_L2_icnt_queue->push(original_wr_mf);
+        	    }
 				m_request_tracker.erase(mf);
 				delete mf;
            }
@@ -355,10 +380,11 @@ void memory_sub_partition::cache_cycle( unsigned cycle )
         if ( !m_config->m_L2_config.disabled() && m_L2cache->waiting_for_fill(mf) ) {
             if (m_L2cache->fill_port_free()) {
                 mf->set_status(IN_PARTITION_L2_FILL_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
-                m_L2cache->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle);
+                m_L2cache->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle+m_memcpy_cycle_offset);
                 m_dram_L2_queue->pop();
             }
         } else if ( !m_L2_icnt_queue->full() ) {
+        	if(mf->is_write() && mf->get_type() == WRITE_ACK)
             mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
             m_L2_icnt_queue->push(mf);
             m_dram_L2_queue->pop();
@@ -380,9 +406,10 @@ void memory_sub_partition::cache_cycle( unsigned cycle )
             bool port_free = m_L2cache->data_port_free(); 
             if ( !output_full && port_free ) {
                 std::list<cache_event> events;
-                enum cache_request_status status = m_L2cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle,events);
+                enum cache_request_status status = m_L2cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle+m_memcpy_cycle_offset,events);
                 bool write_sent = was_write_sent(events);
                 bool read_sent = was_read_sent(events);
+                MEM_SUBPART_DPRINTF("Probing L2 cache Address=%llx, status=%u\n", mf->get_addr(), status); 
 
                 if ( status == HIT ) {
                     if( !write_sent ) {
@@ -402,6 +429,11 @@ void memory_sub_partition::cache_cycle( unsigned cycle )
                         m_icnt_L2_queue->pop();
                     }
                 } else if ( status != RESERVATION_FAIL ) {
+                	if(mf->is_write() && (m_config->m_L2_config.m_write_alloc_policy == FETCH_ON_WRITE || m_config->m_L2_config.m_write_alloc_policy == LAZY_FETCH_ON_READ) && !was_writeallocate_sent(events)) {
+                		mf->set_reply();
+                		mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
+                		m_L2_icnt_queue->push(mf);
+                	}
                     // L2 cache accepted request
                     m_icnt_L2_queue->pop();
                 } else {
@@ -432,6 +464,11 @@ bool memory_sub_partition::full() const
     return m_icnt_L2_queue->full();
 }
 
+bool memory_sub_partition::full(unsigned size) const
+{
+    return m_icnt_L2_queue->is_avilable_size(size);
+}
+
 bool memory_sub_partition::L2_dram_queue_empty() const
 {
    return m_L2_dram_queue->empty(); 
@@ -532,7 +569,15 @@ unsigned memory_sub_partition::flushL2()
     if (!m_config->m_L2_config.disabled()) {
         m_L2cache->flush(); 
     }
-    return 0; // L2 is read only in this version
+    return 0;   //TODO: write the flushed data to the main memory
+}
+
+unsigned memory_sub_partition::invalidateL2()
+{
+    if (!m_config->m_L2_config.disabled()) {
+        m_L2cache->invalidate();
+    }
+    return 0;
 }
 
 bool memory_sub_partition::busy() const 
@@ -540,21 +585,94 @@ bool memory_sub_partition::busy() const
     return !m_request_tracker.empty();
 }
 
-void memory_sub_partition::push( mem_fetch* req, unsigned long long cycle ) 
-{
-    if (req) {
-        m_request_tracker.insert(req);
-        m_stats->memlatstat_icnt2mem_pop(req);
-        if( req->istexture() ) {
-            m_icnt_L2_queue->push(req);
-            req->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
-        } else {
-            rop_delay_t r;
-            r.req = req;
-            r.ready_cycle = cycle + m_config->rop_latency;
-            m_rop.push(r);
-            req->set_status(IN_PARTITION_ROP_DELAY,gpu_sim_cycle+gpu_tot_sim_cycle);
-        }
+std::vector<mem_fetch*> memory_sub_partition::breakdown_request_to_sector_requests(mem_fetch* mf)
+{
+	std::vector<mem_fetch*> result;
+
+	if(mf->get_data_size() == SECTOR_SIZE && mf->get_access_sector_mask().count() == 1) {
+		result.push_back(mf);
+	} else if (mf->get_data_size() == 128 || mf->get_data_size() == 64) {
+        //We only accept 32, 64 and 128 bytes reqs
+		unsigned start=0, end=0;
+		if(mf->get_data_size() == 128) {
+			start=0; end=3;
+		} else if (mf->get_data_size() == 64 && mf->get_access_sector_mask().to_string() == "1100") {
+			start=2; end=3;
+		} else if (mf->get_data_size() == 64 && mf->get_access_sector_mask().to_string() == "0011") {
+			start=0; end=1;
+		} else if (mf->get_data_size() == 64 && (mf->get_access_sector_mask().to_string() == "1111" || mf->get_access_sector_mask().to_string() == "0000")) {
+			if(mf->get_addr() % 128 == 0) {
+				start=0; end=1;
+			} else {
+				start=2; end=3;
+			}
+		} else
+			{
+			    printf("Invalid sector received, address = 0x%06x, sector mask = %s, data size = %d",
+			    		mf->get_addr(), mf->get_access_sector_mask(), mf->get_data_size());
+				assert(0 && "Undefined sector mask is received");
+			}
+
+		std::bitset<SECTOR_SIZE*SECTOR_CHUNCK_SIZE> byte_sector_mask;
+		byte_sector_mask.reset();
+		for(unsigned  k=start*SECTOR_SIZE; k< SECTOR_SIZE; ++k)
+			byte_sector_mask.set(k);
+
+		for(unsigned j=start, i=0; j<= end ; ++j, ++i){
+
+			const mem_access_t *ma = new  mem_access_t( mf->get_access_type(),
+									mf->get_addr() + SECTOR_SIZE*i,
+									SECTOR_SIZE,
+									mf->is_write(),
+									mf->get_access_warp_mask(),
+									mf->get_access_byte_mask() & byte_sector_mask,
+									std::bitset<SECTOR_CHUNCK_SIZE>().set(j));
+
+			 mem_fetch *n_mf = new mem_fetch( *ma,
+								NULL,
+								mf->get_ctrl_size(),
+								mf->get_wid(),
+								mf->get_sid(),
+								mf->get_tpc(),
+								mf->get_mem_config(),
+								mf);
+
+			 result.push_back(n_mf);
+			 byte_sector_mask <<= SECTOR_SIZE;
+		}
+	} else {
+		 printf("Invalid sector received, address = 0x%06x, sector mask = %d, byte mask = , data size = %d",
+					    		mf->get_addr(), mf->get_access_sector_mask().count(), mf->get_data_size());
+		 assert(0 && "Undefined data size is received");
+	}
+
+	return result;
+}
+
+void memory_sub_partition::push( mem_fetch* m_req, unsigned long long cycle )
+{
+    if (m_req) {
+    	m_stats->memlatstat_icnt2mem_pop(m_req);
+    	std::vector<mem_fetch*> reqs;
+    	if(m_config->m_L2_config.m_cache_type == SECTOR)
+    		reqs = breakdown_request_to_sector_requests(m_req);
+    	else
+    		reqs.push_back(m_req);
+
+    	for(unsigned i=0; i<reqs.size(); ++i) {
+    		mem_fetch* req = reqs[i];
+			m_request_tracker.insert(req);
+			if( req->istexture() ) {
+				m_icnt_L2_queue->push(req);
+				req->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
+			} else {
+				rop_delay_t r;
+				r.req = req;
+				r.ready_cycle = cycle + m_config->rop_latency;
+				m_rop.push(r);
+				req->set_status(IN_PARTITION_ROP_DELAY,gpu_sim_cycle+gpu_tot_sim_cycle);
+			}
+    	}
     }
 }
 
diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h
index 3df54b1..18c0a8b 100644
--- a/src/gpgpu-sim/l2cache.h
+++ b/src/gpgpu-sim/l2cache.h
@@ -72,6 +72,7 @@ public:
    void print_stat( FILE *fp ) { m_dram->print_stat(fp); }
    void visualize() const { m_dram->visualize(); }
    void print( FILE *fp ) const;
+   void handle_memcpy_to_gpu( size_t dst_start_addr, unsigned subpart_id, mem_access_sector_mask_t mask );
 
    class memory_sub_partition * get_sub_partition(int sub_partition_id) 
    {
@@ -154,12 +155,14 @@ public:
    void cache_cycle( unsigned cycle );
 
    bool full() const;
+   bool full(unsigned size) const;
    void push( class mem_fetch* mf, unsigned long long clock_cycle );
    class mem_fetch* pop(); 
    class mem_fetch* top();
    void set_done( mem_fetch *mf );
 
    unsigned flushL2();
+   unsigned invalidateL2();
 
    // interface to L2_dram_queue
    bool L2_dram_queue_empty() const; 
@@ -177,6 +180,12 @@ public:
    void accumulate_L2cache_stats(class cache_stats &l2_stats) const;
    void get_L2cache_sub_stats(struct cache_sub_stats &css) const;
 
+   void force_l2_tag_update(new_addr_type addr, unsigned time, mem_access_sector_mask_t mask)
+   {
+        m_L2cache->force_tag_access( addr, m_memcpy_cycle_offset + time, mask );
+        m_memcpy_cycle_offset += 1;
+   }
+
 private:
 // data
    unsigned m_id;  //< the global sub partition ID
@@ -207,6 +216,15 @@ private:
    std::set<mem_fetch*> m_request_tracker;
 
    friend class L2interface;
+
+   std::vector<mem_fetch*> breakdown_request_to_sector_requests(mem_fetch* mf);
+
+   // This is a cycle offset that has to be applied to the l2 accesses to account for
+   // the cudamemcpy read/writes. We want GPGPU-Sim to only count cycles for kernel execution
+   // but we want cudamemcpy to go through the L2. Everytime an access is made from cudamemcpy
+   // this counter is incremented, and when the l2 is accessed (in both cudamemcpyies and otherwise)
+   // this value is added to the gpgpu-sim cycle counters.
+   unsigned m_memcpy_cycle_offset;
 };
 
 class L2interface : public mem_fetch_interface {
diff --git a/src/gpgpu-sim/l2cache_trace.h b/src/gpgpu-sim/l2cache_trace.h
index 3dac87d..2235cdc 100644
--- a/src/gpgpu-sim/l2cache_trace.h
+++ b/src/gpgpu-sim/l2cache_trace.h
@@ -34,6 +34,9 @@
 #define MEMPART_PRINT_STR SIM_PRINT_STR " %d - "
 #define MEMPART_DTRACE(x)  ( DTRACE(x) && (Trace::sampling_memory_partition == -1 || Trace::sampling_memory_partition == (int)get_mpid()) )
 
+#define MEM_SUBPART_PRINT_STR SIM_PRINT_STR " %d - "
+#define MEM_SUBPART_DTRACE(x)  ( DTRACE(x) && (Trace::sampling_memory_partition == -1 || Trace::sampling_memory_partition == (int)m_id) )
+
 // Intended to be called from inside components of a memory partition
 // Depends on a get_mpid() function
 #define MEMPART_DPRINTF(...) do {\
@@ -46,10 +49,23 @@
     }\
 } while (0)
 
+#define MEM_SUBPART_DPRINTF(...) do {\
+    if (MEM_SUBPART_DTRACE(MEMORY_PARTITION_UNIT)) {\
+        printf( MEM_SUBPART_PRINT_STR,\
+                gpu_sim_cycle + gpu_tot_sim_cycle,\
+                Trace::trace_streams_str[Trace::MEMORY_SUBPARTITION_UNIT],\
+                m_id );\
+        printf(__VA_ARGS__);\
+    }\
+} while (0)
+
 #else
 
 #define MEMPART_DTRACE(x)  (false)
 #define MEMPART_DPRINTF(x, ...) do {} while (0)
 
+#define MEM_SUBPART_DTRACE(x)  (false)
+#define MEM_SUBPART_DPRINTF(x, ...) do {} while (0)
+
 #endif
 
diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc
index 729636d..a260a35 100644
--- a/src/gpgpu-sim/mem_fetch.cc
+++ b/src/gpgpu-sim/mem_fetch.cc
@@ -39,7 +39,10 @@ mem_fetch::mem_fetch( const mem_access_t &access,
                       unsigned wid,
                       unsigned sid, 
                       unsigned tpc, 
-                      const struct memory_config *config )
+                      const struct memory_config *config,
+					  mem_fetch *m_original_mf,
+					  mem_fetch *m_original_wr_mf)
+
 {
    m_request_uid = sm_next_mf_request_uid++;
    m_access = access;
@@ -61,6 +64,8 @@ mem_fetch::mem_fetch( const mem_access_t &access,
    m_status_change = gpu_sim_cycle + gpu_tot_sim_cycle;
    m_mem_config = config;
    icnt_flit_size = config->icnt_flit_size;
+   original_mf = m_original_mf;
+   original_wr_mf = m_original_wr_mf;
 }
 
 mem_fetch::~mem_fetch()
diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h
index de98748..e5efffd 100644
--- a/src/gpgpu-sim/mem_fetch.h
+++ b/src/gpgpu-sim/mem_fetch.h
@@ -55,7 +55,9 @@ public:
                unsigned wid,
                unsigned sid, 
                unsigned tpc, 
-               const struct memory_config *config );
+               const struct memory_config *config,
+			   mem_fetch *original_mf = NULL,
+			   mem_fetch *original_wr_mf = NULL);
    ~mem_fetch();
 
    void set_status( enum mem_fetch_status status, unsigned long long cycle );
@@ -104,6 +106,7 @@ public:
    enum mem_access_type get_access_type() const { return m_access.get_type(); }
    const active_mask_t& get_access_warp_mask() const { return m_access.get_warp_mask(); }
    mem_access_byte_mask_t get_access_byte_mask() const { return m_access.get_byte_mask(); }
+   mem_access_sector_mask_t get_access_sector_mask() const { return m_access.get_sector_mask(); }
 
    address_type get_pc() const { return m_inst.empty()?-1:m_inst.pc; }
    const warp_inst_t &get_inst() { return m_inst; }
@@ -112,6 +115,10 @@ public:
    const memory_config *get_mem_config(){return m_mem_config;}
 
    unsigned get_num_flits(bool simt_to_mem);
+
+   mem_fetch* get_original_mf() { return original_mf; }
+   mem_fetch* get_original_wr_mf()  { return original_wr_mf; }
+
 private:
    // request source information
    unsigned m_request_uid;
@@ -143,6 +150,10 @@ private:
 
    const struct memory_config *m_mem_config;
    unsigned icnt_flit_size;
+
+   mem_fetch* original_mf;  //this pointer is set up when a request is divided into sector requests at L2 cache (if the req size > L2 sector size), so the pointer refers to the original request
+   mem_fetch* original_wr_mf;  //this pointer refers to the original write req, when fetch-on-write policy is used
+
 };
 
 #endif
diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc
index fde0eff..c5452b9 100644
--- a/src/gpgpu-sim/mem_latency_stat.cc
+++ b/src/gpgpu-sim/mem_latency_stat.cc
@@ -75,6 +75,10 @@ memory_stats_t::memory_stats_t( unsigned n_shader, const struct shader_core_conf
    max_mf_latency = 0;
    max_icnt2mem_latency = 0;
    max_icnt2sh_latency = 0;
+   tot_icnt2mem_latency = 0;
+   tot_icnt2sh_latency = 0;
+   tot_mrq_num = 0;
+   tot_mrq_latency = 0;
    memset(mrq_lat_table, 0, sizeof(unsigned)*32);
    memset(dq_lat_table, 0, sizeof(unsigned)*32);
    memset(mf_lat_table, 0, sizeof(unsigned)*32);
@@ -158,6 +162,7 @@ void memory_stats_t::memlatstat_read_done(mem_fetch *mf)
          mf_max_lat_table[mf->get_tlx_addr().chip][mf->get_tlx_addr().bk] = mf_latency;
       unsigned icnt2sh_latency;
       icnt2sh_latency = (gpu_tot_sim_cycle+gpu_sim_cycle) - mf->get_return_timestamp();
+      tot_icnt2sh_latency += icnt2sh_latency;
       icnt2sh_lat_table[LOGB2(icnt2sh_latency)]++;
       if (icnt2sh_latency > max_icnt2sh_latency)
          max_icnt2sh_latency = icnt2sh_latency;
@@ -191,6 +196,7 @@ void memory_stats_t::memlatstat_icnt2mem_pop(mem_fetch *mf)
    if (m_memory_config->gpgpu_memlatency_stat) {
       unsigned icnt2mem_latency;
       icnt2mem_latency = (gpu_tot_sim_cycle+gpu_sim_cycle) - mf->get_timestamp();
+      tot_icnt2mem_latency += icnt2mem_latency;
       icnt2mem_lat_table[LOGB2(icnt2mem_latency)]++;
       if (icnt2mem_latency > max_icnt2mem_latency)
          max_icnt2mem_latency = icnt2mem_latency;
@@ -216,14 +222,19 @@ void memory_stats_t::memlatstat_print( unsigned n_mem, unsigned gpu_mem_n_bk )
    unsigned max_bank_accesses, min_bank_accesses, max_chip_accesses, min_chip_accesses;
 
    if (m_memory_config->gpgpu_memlatency_stat) {
+	   printf("maxmflatency = %d \n", max_mf_latency);
+	   printf("max_icnt2mem_latency = %d \n", max_icnt2mem_latency);
       printf("maxmrqlatency = %d \n", max_mrq_latency);
-      printf("maxdqlatency = %d \n", max_dq_latency);
-      printf("maxmflatency = %d \n", max_mf_latency);
+      //printf("maxdqlatency = %d \n", max_dq_latency);
+      printf("max_icnt2sh_latency = %d \n", max_icnt2sh_latency);
       if (num_mfs) {
          printf("averagemflatency = %lld \n", mf_total_lat/num_mfs);
+         printf("avg_icnt2mem_latency = %lld \n", tot_icnt2mem_latency/num_mfs);
+         if(tot_mrq_num)
+        	 printf("avg_mrq_latency = %lld \n", tot_mrq_latency/tot_mrq_num);
+
+         printf("avg_icnt2sh_latency = %lld \n", tot_icnt2sh_latency/num_mfs);
       }
-      printf("max_icnt2mem_latency = %d \n", max_icnt2mem_latency);
-      printf("max_icnt2sh_latency = %d \n", max_icnt2sh_latency);
       printf("mrq_lat_table:");
       for (i=0; i< 32; i++) {
          printf("%d \t", mrq_lat_table[i]);
diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h
index 4968a3b..5b89202 100644
--- a/src/gpgpu-sim/mem_latency_stat.h
+++ b/src/gpgpu-sim/mem_latency_stat.h
@@ -56,6 +56,10 @@ public:
    unsigned max_dq_latency;
    unsigned max_mf_latency;
    unsigned max_icnt2mem_latency;
+   unsigned long long int tot_icnt2mem_latency;
+   unsigned long long int tot_icnt2sh_latency;
+   unsigned long long int tot_mrq_latency;
+   unsigned long long int tot_mrq_num;
    unsigned max_icnt2sh_latency;
    unsigned mrq_lat_table[32];
    unsigned dq_lat_table[32];
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index f9cfa58..82f9181 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -74,13 +74,14 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                   shader_core_stats *stats )
    : core_t( gpu, NULL, config->warp_size, config->n_thread_per_shader ),
      m_barriers( this, config->max_warps_per_shader, config->max_cta_per_core, config->max_barriers_per_cta, config->warp_size ),
-     m_dynamic_warp_id(0)
+     m_dynamic_warp_id(0), m_active_warps(0)
 {
     m_cluster = cluster;
     m_config = config;
     m_memory_config = mem_config;
     m_stats = stats;
     unsigned warp_size=config->warp_size;
+    Issue_Prio = 0;
     
     m_sid = shader_id;
     m_tpc = tpc_id;
@@ -131,6 +132,8 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                          CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE :
                                          sched_config.find("gto") != std::string::npos ?
                                          CONCRETE_SCHEDULER_GTO :
+					 sched_config.find("old") != std::string::npos ?
+					 CONCRETE_SCHEDULER_OLDEST_FIRST :
                                          sched_config.find("warp_limiting") != std::string::npos ?
                                          CONCRETE_SCHEDULER_WARP_LIMITING:
                                          NUM_CONCRETE_SCHEDULERS;
@@ -147,6 +150,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        m_simt_stack,
                                        &m_warp,
                                        &m_pipeline_reg[ID_OC_SP],
+									   &m_pipeline_reg[ID_OC_DP],
                                        &m_pipeline_reg[ID_OC_SFU],
                                        &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
@@ -162,6 +166,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                                     m_simt_stack,
                                                     &m_warp,
                                                     &m_pipeline_reg[ID_OC_SP],
+													&m_pipeline_reg[ID_OC_DP],
                                                     &m_pipeline_reg[ID_OC_SFU],
                                                     &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                                     &m_pipeline_reg[ID_OC_MEM],
@@ -178,6 +183,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        m_simt_stack,
                                        &m_warp,
                                        &m_pipeline_reg[ID_OC_SP],
+									   &m_pipeline_reg[ID_OC_DP],
                                        &m_pipeline_reg[ID_OC_SFU],
                                        &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
@@ -185,6 +191,22 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                      )
                 );
                 break;
+            case CONCRETE_SCHEDULER_OLDEST_FIRST:
+				schedulers.push_back(
+		    new oldest_scheduler( m_stats,
+					  this,
+					  m_scoreboard,
+					  m_simt_stack,
+					  &m_warp,
+					  &m_pipeline_reg[ID_OC_SP],
+					  &m_pipeline_reg[ID_OC_DP],
+					  &m_pipeline_reg[ID_OC_SFU],
+                                       	  &m_pipeline_reg[ID_OC_TENSOR_CORE],
+					  &m_pipeline_reg[ID_OC_MEM],
+					  i
+					 )
+				);
+				break;
             case CONCRETE_SCHEDULER_WARP_LIMITING:
                 schedulers.push_back(
                     new swl_scheduler( m_stats,
@@ -193,6 +215,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        m_simt_stack,
                                        &m_warp,
                                        &m_pipeline_reg[ID_OC_SP],
+									   &m_pipeline_reg[ID_OC_DP],
                                        &m_pipeline_reg[ID_OC_SFU],
                                        &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
@@ -215,8 +238,9 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     }
     
     //op collector configuration
-    enum { SP_CUS, SFU_CUS, TENSOR_CORE_CUS,  MEM_CUS, GEN_CUS };
+    enum { SP_CUS, DP_CUS, SFU_CUS, MEM_CUS, TENSOR_CORE_CUS, GEN_CUS };
     m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp);
+    m_operand_collector.add_cu_set(DP_CUS, m_config->gpgpu_operand_collector_num_units_dp, m_config->gpgpu_operand_collector_num_out_ports_dp);
     m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu);
     m_operand_collector.add_cu_set(TENSOR_CORE_CUS, config->gpgpu_operand_collector_num_units_tensor_core, config->gpgpu_operand_collector_num_out_ports_tensor_core);
     m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem);
@@ -234,6 +258,15 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
         in_ports.clear(),out_ports.clear(),cu_sets.clear();
     }
     
+    for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_dp; i++) {
+            in_ports.push_back(&m_pipeline_reg[ID_OC_DP]);
+            out_ports.push_back(&m_pipeline_reg[OC_EX_DP]);
+            cu_sets.push_back((unsigned)DP_CUS);
+            cu_sets.push_back((unsigned)GEN_CUS);
+            m_operand_collector.add_port(in_ports,out_ports,cu_sets);
+            in_ports.clear(),out_ports.clear(),cu_sets.clear();
+        }
+
     for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sfu; i++) {
         in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
@@ -279,7 +312,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     m_operand_collector.init( m_config->gpgpu_num_reg_banks, this );
     
     // execute
-    m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + config->gpgpu_num_tensor_core_units + 1; // sp_unit, sfu, ldst_unit
+    m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_dp_units + m_config->gpgpu_num_sfu_units + m_config->gpgpu_num_tensor_core_units + 1; // sp_unit, sfu, ldst_unit
     //m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ];
     //m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ];
     
@@ -291,6 +324,12 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
         m_issue_port.push_back(OC_EX_SP);
     }
     
+    for (int k = 0; k < m_config->gpgpu_num_dp_units; k++) {
+            m_fu.push_back(new dp_unit( &m_pipeline_reg[EX_WB], m_config, this ));
+            m_dispatch_port.push_back(ID_OC_DP);
+            m_issue_port.push_back(OC_EX_DP);
+        }
+
     for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) {
         m_fu.push_back(new sfu( &m_pipeline_reg[EX_WB], m_config, this ));
         m_dispatch_port.push_back(ID_OC_SFU);
@@ -307,7 +346,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     m_fu.push_back(m_ldst_unit);
     m_dispatch_port.push_back(ID_OC_MEM);
     m_issue_port.push_back(OC_EX_MEM);
-    
+   
     assert(m_num_function_units == m_fu.size() and m_fu.size() == m_dispatch_port.size() and m_fu.size() == m_issue_port.size());
     
     //there are as many result buses as the width of the EX_WB stage
@@ -341,6 +380,7 @@ void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread, bool re
        m_occupied_ctas = 0;
        m_occupied_hwtid.reset();
        m_occupied_cta_to_hwtid.clear();
+       m_active_warps = 0;
 
    }
    for (unsigned i = start_thread; i<end_thread; i++) {
@@ -375,6 +415,7 @@ void shader_core_ctx::init_warps( unsigned cta_id, unsigned start_thread, unsign
             m_warp[i].init(start_pc,cta_id,i,active_threads, m_dynamic_warp_id);
             ++m_dynamic_warp_id;
             m_not_completed += n_active;
+            ++m_active_warps;
       }
    }
 }
@@ -402,6 +443,18 @@ void shader_core_ctx::get_pdom_stack_top_info( unsigned tid, unsigned *pc, unsig
     m_simt_stack[warp_id]->get_pdom_stack_top_info(pc,rpc);
 }
 
+float shader_core_ctx::get_current_occupancy( unsigned long long & active, unsigned long long & total ) const
+{
+    // To match the achieved_occupancy in nvprof, only SMs that are active are counted toward the occupancy.
+    if ( m_active_warps > 0 ) {
+        total += m_warp.size();
+        active += m_active_warps;
+        return float(active) / float(total);
+    } else {
+        return 0;
+    }
+}
+
 void shader_core_stats::print( FILE* fout ) const
 {
 	unsigned long long  thread_icount_uarch=0;
@@ -436,15 +489,15 @@ void shader_core_stats::print( FILE* fout ) const
    fprintf(fout, "gpgpu_n_intrawarp_mshr_merge = %d\n", gpgpu_n_intrawarp_mshr_merge);
    fprintf(fout, "gpgpu_n_cmem_portconflict = %d\n", gpgpu_n_cmem_portconflict);
 
-   fprintf(fout, "gpgpu_stall_shd_mem[c_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]);
-   fprintf(fout, "gpgpu_stall_shd_mem[c_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][MSHR_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[c_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][ICNT_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[c_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][DATA_PORT_STALL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[t_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][MSHR_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[t_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][ICNT_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[t_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][DATA_PORT_STALL]);
+   fprintf(fout, "gpgpu_stall_shd_mem[c_mem][resource_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][MSHR_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][ICNT_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][DATA_PORT_STALL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[t_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][MSHR_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[t_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][ICNT_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[t_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][DATA_PORT_STALL]);
    fprintf(fout, "gpgpu_stall_shd_mem[s_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[S_MEM][BK_CONF]);
-   fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][bk_conf] = %d\n", 
+   fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][resource_stall] = %d\n",
            gpu_stall_shd_mem_breakdown[G_MEM_LD][BK_CONF] + 
            gpu_stall_shd_mem_breakdown[G_MEM_ST][BK_CONF] + 
            gpu_stall_shd_mem_breakdown[L_MEM_LD][BK_CONF] + 
@@ -462,22 +515,22 @@ void shader_core_stats::print( FILE* fout ) const
            gpu_stall_shd_mem_breakdown[L_MEM_LD][DATA_PORT_STALL] + 
            gpu_stall_shd_mem_breakdown[L_MEM_ST][DATA_PORT_STALL]    
            ); // data port stall at data cache 
-   fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][MSHR_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][ICNT_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_ICNT_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_CACHE_RSRV_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][MSHR_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][ICNT_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_ICNT_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_CACHE_RSRV_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][MSHR_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][ICNT_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_ICNT_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_CACHE_RSRV_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][MSHR_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][ICNT_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_ICNT_RC_FAIL]);
-   fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_CACHE_RSRV_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][MSHR_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][ICNT_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_ICNT_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_CACHE_RSRV_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][MSHR_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][ICNT_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_ICNT_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_CACHE_RSRV_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][MSHR_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][ICNT_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_ICNT_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_CACHE_RSRV_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][MSHR_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][ICNT_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_ICNT_RC_FAIL]);
+   //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_CACHE_RSRV_FAIL]);
 
    fprintf(fout, "gpu_reg_bank_conflict_stalls = %d\n", gpu_reg_bank_conflict_stalls);
 
@@ -488,6 +541,14 @@ void shader_core_stats::print( FILE* fout ) const
    for (unsigned i = 3; i < m_config->warp_size + 3; i++) 
       fprintf(fout, "\tW%d:%d", i-2, shader_cycle_distro[i]);
    fprintf(fout, "\n");
+   fprintf(fout, "single_issue_nums: ");
+   for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++)
+        fprintf(fout, "WS%d:%d\t", i, single_issue_nums[i]);
+   fprintf(fout, "\n");
+   fprintf(fout, "dual_issue_nums: ");
+   for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++)
+          fprintf(fout, "WS%d:%d\t", i, dual_issue_nums[i]);
+   fprintf(fout, "\n");
 
    m_outgoing_traffic_stats->print(fout); 
    m_incoming_traffic_stats->print(fout); 
@@ -669,13 +730,15 @@ void shader_core_ctx::fetch()
                     }
                     if( did_exit ) 
                         m_warp[warp_id].set_done_exit();
+                        --m_active_warps;
+                        assert(m_active_warps >= 0);
                 }
 
                 // this code fetches instructions from the i-cache or generates memory requests
                 if( !m_warp[warp_id].functional_done() && !m_warp[warp_id].imiss_pending() && m_warp[warp_id].ibuffer_empty() ) {
                     address_type pc  = m_warp[warp_id].get_pc();
                     address_type ppc = pc + PROGRAM_MEM_START;
-                    unsigned nbytes=16; 
+                    unsigned nbytes=16;
                     unsigned offset_in_block = pc & (m_config->m_L1I_config.get_line_sz()-1);
                     if( (offset_in_block+nbytes) > m_config->m_L1I_config.get_line_sz() )
                         nbytes = (m_config->m_L1I_config.get_line_sz()-offset_in_block);
@@ -750,10 +813,19 @@ void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t*
 }
 
 void shader_core_ctx::issue(){
+
+     //Ensure fair round robin issu between schedulers 
+     unsigned j;
+     for (unsigned i = 0; i < schedulers.size(); i++) {
+	j = (Issue_Prio + i) % schedulers.size();
+	  schedulers[j]->cycle();
+     }
+     Issue_Prio = (Issue_Prio+1)% schedulers.size();
+
     //really is issue;
-    for (unsigned i = 0; i < schedulers.size(); i++) {
-        schedulers[i]->cycle();
-    }
+    //for (unsigned i = 0; i < schedulers.size(); i++) {
+    //    schedulers[i]->cycle();
+    //}
 }
 
 shd_warp_t& scheduler_unit::warp(int i){
@@ -868,7 +940,10 @@ void scheduler_unit::cycle()
         unsigned warp_id = (*iter)->get_warp_id();
         unsigned checked=0;
         unsigned issued=0;
-        unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp;
+        exec_unit_type_t previous_issued_inst_exec_type = exec_unit_type_t::NONE;
+	unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp;
+	bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units;
+
         while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) {
             const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst();
             //Jin: handle cdp latency;
@@ -901,18 +976,21 @@ void scheduler_unit::cycle()
                         ready_inst = true;
                         const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask();
                         assert( warp(warp_id).inst_in_pipeline() );
-                        if ( (pI->op == LOAD_OP)||(pI->op ==TENSOR_CORE_LOAD_OP)|| (pI->op == STORE_OP)|| (pI->op==TENSOR_CORE_STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) {
-                            if( m_mem_out->has_free() ) {
-                                m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id);
-                                issued++;
-                                issued_inst=true;
-                                warp_inst_issued = true;
-                            }
+                        if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP)||(pI->op==TENSOR_CORE_LOAD_OP)||(pI->op==TENSOR_CORE_STORE_OP) ) {
+                        	if( m_mem_out->has_free() && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::MEM)) 			{
+                                	m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id);
+                                	issued++;
+                               	 	issued_inst=true;
+                                	warp_inst_issued = true;
+                                	previous_issued_inst_exec_type = exec_unit_type_t::MEM;
+                            	}
                         } else {
+
                             bool sp_pipe_avail = m_sp_out->has_free();
                             bool sfu_pipe_avail = m_sfu_out->has_free();
                             bool tensor_core_pipe_avail = m_tensor_core_out->has_free();
-                            if( sp_pipe_avail && (pI->op != SFU_OP) && (pI->op != TENSOR_CORE_OP) ) {
+                            bool dp_pipe_avail = m_dp_out->has_free();
+                            if( sp_pipe_avail && (pI->op != TENSOR_CORE_OP) && (pI->op != SFU_OP && pI->op != DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SP)) {
                                 
                                 //Jin: special for CDP api
                                 if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) {
@@ -937,12 +1015,23 @@ void scheduler_unit::cycle()
                                 issued++;
                                 issued_inst=true;
                                 warp_inst_issued = true;
-                            } else if ( (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP) ) {
+                                previous_issued_inst_exec_type = exec_unit_type_t::SP;
+                            } else if ( (m_shader->m_config->gpgpu_num_dp_units != 0) && (pI->op == DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::DP)) {
+                                if( dp_pipe_avail ) {
+                                    m_shader->issue_warp(*m_dp_out,pI,active_mask,warp_id);
+                                    issued++;
+                                    issued_inst=true;
+                                    warp_inst_issued = true;
+                                    previous_issued_inst_exec_type = exec_unit_type_t::DP;
+                                }
+                            }  //If the DP units = 0 (like in Fermi archi), then change DP inst to SFU inst
+                            else if ( ((m_shader->m_config->gpgpu_num_dp_units == 0 && pI->op == DP_OP) || (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP)) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SFU)) {
                                 if( sfu_pipe_avail ) {
                                     m_shader->issue_warp(*m_sfu_out,pI,active_mask,warp_id);
                                     issued++;
                                     issued_inst=true;
                                     warp_inst_issued = true;
+                                    previous_issued_inst_exec_type = exec_unit_type_t::SFU;
                                 }
                             }                         
                              else if ( (pI->op == TENSOR_CORE_OP) ) {
@@ -952,12 +1041,12 @@ void scheduler_unit::cycle()
                                     issued_inst=true;
                                     warp_inst_issued = true;
                                 }
-				}
-                                                }
-                    } else {
+			    }
+                         }//end of else
+                   } else {
                         SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails scoreboard\n",
                                        (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() );
-                    }
+                   }
                 }
             } else if( valid ) {
                // this case can happen after a return instruction in diverged warp
@@ -988,6 +1077,14 @@ void scheduler_unit::cycle()
                     m_last_supervised_issued = supervised_iter;
                 }
             }
+
+            if(issued == 1)
+            	m_stats->single_issue_nums[m_id]++;
+            else if(issued > 1)
+            	m_stats->dual_issue_nums[m_id]++;
+            else
+            	abort();   //issued should be > 0
+
             break;
         } 
     }
@@ -1045,6 +1142,16 @@ void gto_scheduler::order_warps()
                        scheduler_unit::sort_warps_by_oldest_dynamic_id );
 }
 
+void oldest_scheduler::order_warps()
+{
+    order_by_priority( m_next_cycle_prioritized_warps,
+                       m_supervised_warps,
+                       m_last_supervised_issued,
+                       m_supervised_warps.size(),
+		       ORDERED_PRIORITY_FUNC_ONLY,
+                       scheduler_unit::sort_warps_by_oldest_dynamic_id );
+}
+
 void
 two_level_active_scheduler::do_on_warp_issued( unsigned warp_id,
                                                unsigned num_issued,
@@ -1117,12 +1224,13 @@ swl_scheduler::swl_scheduler ( shader_core_stats* stats, shader_core_ctx* shader
                                Scoreboard* scoreboard, simt_stack** simt,
                                std::vector<shd_warp_t>* warp,
                                register_set* sp_out,
+							   register_set* dp_out,
                                register_set* sfu_out,
                                register_set* tensor_core_out,
                                register_set* mem_out,
                                int id,
                                char* config_string )
-    : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out,  mem_out, id )
+    : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id )
 {
     unsigned m_prioritization_readin;
     int ret = sscanf( config_string,
@@ -1386,8 +1494,14 @@ ldst_unit::process_cache_access( cache_t* cache,
     mem_stage_stall_type result = NO_RC_FAIL;
     bool write_sent = was_write_sent(events);
     bool read_sent = was_read_sent(events);
-    if( write_sent ) 
-        m_core->inc_store_req( inst.warp_id() );
+    if( write_sent ) {
+    	unsigned inc_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)?
+    			(mf->get_data_size()/SECTOR_SIZE) : 1;
+
+		for(unsigned i=0; i< inc_ack; ++i)
+			m_core->inc_store_req( inst.warp_id() );
+
+    }
     if ( status == HIT ) {
         assert( !read_sent );
         inst.accessq_pop_back();
@@ -1399,7 +1513,7 @@ ldst_unit::process_cache_access( cache_t* cache,
         if( !write_sent ) 
             delete mf;
     } else if ( status == RESERVATION_FAIL ) {
-        result = COAL_STALL;
+        result = BK_CONF;
         assert( !read_sent );
         assert( !write_sent );
         delete mf;
@@ -1408,8 +1522,8 @@ ldst_unit::process_cache_access( cache_t* cache,
         //inst.clear_active( access.get_warp_mask() ); // threads in mf writeback when mf returns
         inst.accessq_pop_back();
     }
-    if( !inst.accessq_empty() )
-        result = BK_CONF;
+    if( !inst.accessq_empty() && result == NO_RC_FAIL)
+        result = COAL_STALL;
     return result;
 }
 
@@ -1429,6 +1543,111 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue( cache_t *cache, war
     return process_cache_access( cache, mf->get_addr(), inst, events, mf, status );
 }
 
+mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache( l1_cache *cache, warp_inst_t &inst )
+{
+    mem_stage_stall_type result = NO_RC_FAIL;
+    if( inst.accessq_empty() )
+        return result;
+
+    mem_fetch *mf = m_mf_allocator->alloc(inst,inst.accessq_back());
+
+    if(m_config->m_L1D_config.l1_latency > 0)
+	{
+    	if((l1_latency_queue[m_config->m_L1D_config.l1_latency-1]) == NULL)
+    	{
+    		l1_latency_queue[m_config->m_L1D_config.l1_latency-1] = mf;
+
+    		if( mf->get_inst().is_store() ) {
+				unsigned inc_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)?
+						(mf->get_data_size()/SECTOR_SIZE) : 1;
+
+				for(unsigned i=0; i< inc_ack; ++i)
+					m_core->inc_store_req( inst.warp_id() );
+			}
+
+    		inst.accessq_pop_back();
+    	}
+    	else
+        {
+        	result = BK_CONF;
+        	delete mf;
+        }
+        if( !inst.accessq_empty() &&  result !=BK_CONF)
+		   result = COAL_STALL;
+	   return result;
+	}
+    else
+    {
+		std::list<cache_event> events;
+		enum cache_request_status status = cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle,events);
+		return process_cache_access( cache, mf->get_addr(), inst, events, mf, status );
+    }
+}
+
+void ldst_unit::L1_latency_queue_cycle()
+{
+	//std::deque< std::pair<mem_fetch*,bool> >::iterator it = m_latency_queue.begin();
+	if((l1_latency_queue[0]) != NULL)
+    {
+		    mem_fetch* mf_next = l1_latency_queue[0];
+			std::list<cache_event> events;
+			enum cache_request_status status = m_L1D->access(mf_next->get_addr(),mf_next,gpu_sim_cycle+gpu_tot_sim_cycle,events);
+
+		   bool write_sent = was_write_sent(events);
+		   bool read_sent = was_read_sent(events);
+
+		   if ( status == HIT ) {
+			   assert( !read_sent );
+			   l1_latency_queue[0] = NULL;
+			   if ( mf_next->get_inst().is_load() ) {
+				   for ( unsigned r=0; r < 4; r++)
+					   if (mf_next->get_inst().out[r] > 0)
+					   {
+						   assert(m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]]>0);
+						   unsigned still_pending = --m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]];
+						   if(!still_pending)
+						   {
+							m_pending_writes[mf_next->get_inst().warp_id()].erase(mf_next->get_inst().out[r]);
+							m_scoreboard->releaseRegister(mf_next->get_inst().warp_id(),mf_next->get_inst().out[r]);
+							m_core->warp_inst_complete(mf_next->get_inst());
+						   }
+					   }
+			   }
+
+			   //For write hit in WB policy
+			   if(mf_next->get_inst().is_store() && !write_sent)
+			   {
+				   unsigned dec_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)?
+				   						(mf_next->get_data_size()/SECTOR_SIZE) : 1;
+
+				   mf_next->set_reply();
+
+				   for(unsigned i=0; i< dec_ack; ++i)
+				      m_core->store_ack(mf_next);
+			   }
+
+			   if( !write_sent )
+				   delete mf_next;
+
+		   } else if ( status == RESERVATION_FAIL ) {
+			   assert( !read_sent );
+			   assert( !write_sent );
+		   } else {
+			   assert( status == MISS || status == HIT_RESERVED );
+			   l1_latency_queue[0] = NULL;
+	   }
+    }
+
+	 for( unsigned stage = 0; stage<m_config->m_L1D_config.l1_latency-1; ++stage)
+	  if( l1_latency_queue[stage] == NULL) {
+		   l1_latency_queue[stage] = l1_latency_queue[stage+1] ;
+		   l1_latency_queue[stage+1] = NULL;
+	   }
+
+}
+
+
+
 bool ldst_unit::constant_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type)
 {
    if( inst.empty() || ((inst.space.get_type() != const_space) && (inst.space.get_type() != param_space_kernel)) )
@@ -1478,7 +1697,7 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea
        bypassL1D = true; 
    } else if (inst.space.is_global()) { // global memory access 
        // skip L1 cache if the option is enabled
-       if (m_core->get_config()->gmem_skip_L1D) 
+       if (m_core->get_config()->gmem_skip_L1D && (CACHE_L1 != inst.cache_op))
            bypassL1D = true; 
    }
    if( bypassL1D ) {
@@ -1502,9 +1721,9 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea
        }
    } else {
        assert( CACHE_UNDEFINED != inst.cache_op );
-       stall_cond = process_memory_access_queue(m_L1D,inst);
+       stall_cond = process_memory_access_queue_l1cache(m_L1D,inst);
    }
-   if( !inst.accessq_empty() ) 
+   if( !inst.accessq_empty() && stall_cond == NO_RC_FAIL)
        stall_cond = COAL_STALL;
    if (stall_cond != NO_RC_FAIL) {
       stall_reason = stall_cond;
@@ -1534,6 +1753,11 @@ void ldst_unit::flush(){
 	m_L1D->flush();
 }
 
+void ldst_unit::invalidate(){
+	// Flush L1D cache
+	m_L1D->invalidate();
+}
+
 simd_function_unit::simd_function_unit( const shader_core_config *config )
 { 
     m_config=config;
@@ -1586,6 +1810,13 @@ void sp_unit::active_lanes_in_pipeline(){
 	m_core->incfuactivelanes_stat(active_count);
 	m_core->incfumemactivelanes_stat(active_count);
 }
+void dp_unit::active_lanes_in_pipeline(){
+	unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
+	assert(active_count<=m_core->get_config()->warp_size);
+	m_core->incspactivelanes_stat(active_count);
+	m_core->incfuactivelanes_stat(active_count);
+	m_core->incfumemactivelanes_stat(active_count);
+}
 
 void sfu::active_lanes_in_pipeline(){
 	unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
@@ -1610,6 +1841,12 @@ sp_unit::sp_unit( register_set* result_port, const shader_core_config *config,sh
     m_name = "SP "; 
 }
 
+dp_unit::dp_unit( register_set* result_port, const shader_core_config *config,shader_core_ctx *core)
+    : pipelined_simd_unit(result_port,config,config->max_sfu_latency,core)
+{
+    m_name = "DP ";
+}
+
 void sp_unit :: issue(register_set& source_reg)
 {
     warp_inst_t** ready_reg = source_reg.get_ready();
@@ -1619,6 +1856,14 @@ void sp_unit :: issue(register_set& source_reg)
 	pipelined_simd_unit::issue(source_reg);
 }
 
+void dp_unit :: issue(register_set& source_reg)
+{
+    warp_inst_t** ready_reg = source_reg.get_ready();
+	//m_core->incexecstat((*ready_reg));
+	(*ready_reg)->op_pipe=DP__OP;
+	m_core->incsp_stat(m_core->get_config()->warp_size,(*ready_reg)->latency);
+	pipelined_simd_unit::issue(source_reg);
+}
 
 pipelined_simd_unit::pipelined_simd_unit( register_set* result_port, const shader_core_config *config, unsigned max_latency,shader_core_ctx *core )
     : simd_function_unit(config) 
@@ -1712,8 +1957,9 @@ ldst_unit::ldst_unit( mem_fetch_interface *icnt,
                       const memory_config *mem_config,  
                       shader_core_stats *stats,
                       unsigned sid,
-                      unsigned tpc ) : pipelined_simd_unit(NULL,config,3,core), m_next_wb(config)
+                      unsigned tpc ) : pipelined_simd_unit(NULL,config,config->smem_latency,core), m_next_wb(config)
 {
+	assert(config->smem_latency > 1);
     init( icnt,
           mf_allocator,
           core, 
@@ -1734,6 +1980,12 @@ ldst_unit::ldst_unit( mem_fetch_interface *icnt,
                               m_icnt,
                               m_mf_allocator,
                               IN_L1D_MISS_QUEUE );
+
+        if(m_config->m_L1D_config.l1_latency > 0)
+	    {
+        	for(int i=0; i<m_config->m_L1D_config.l1_latency; i++ )
+        		l1_latency_queue.push_back((mem_fetch*)NULL);
+	    }
     }
 }
 
@@ -1916,12 +2168,12 @@ void ldst_unit::cycle()
 
    if( !m_response_fifo.empty() ) {
        mem_fetch *mf = m_response_fifo.front();
-       if (mf->istexture()) {
+       if (mf->get_access_type() == TEXTURE_ACC_R) {
            if (m_L1T->fill_port_free()) {
                m_L1T->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle);
                m_response_fifo.pop_front(); 
            }
-       } else if (mf->isconst())  {
+       } else if (mf->get_access_type() == CONST_ACC_R)  {
            if (m_L1C->fill_port_free()) {
                mf->set_status(IN_SHADER_FETCHED,gpu_sim_cycle+gpu_tot_sim_cycle);
                m_L1C->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle);
@@ -1960,7 +2212,11 @@ void ldst_unit::cycle()
 
    m_L1T->cycle();
    m_L1C->cycle();
-   if( m_L1D ) m_L1D->cycle();
+   if( m_L1D ) {
+	   m_L1D->cycle();
+	   if(m_config->m_L1D_config.l1_latency > 0)
+	   		L1_latency_queue_cycle();
+   }
 
    warp_inst_t &pipe_reg = *m_dispatch_reg;
    enum mem_stage_stall_type rc_fail = NO_RC_FAIL;
@@ -1983,9 +2239,9 @@ void ldst_unit::cycle()
        unsigned warp_id = pipe_reg.warp_id();
        if( pipe_reg.is_load() ) {
            if( pipe_reg.space.get_type() == shared_space ) {
-               if( m_pipeline_reg[2]->empty() ) {
+               if( m_pipeline_reg[m_config->smem_latency-1]->empty() ) {
                    // new shared memory request
-                   move_warp(m_pipeline_reg[2],m_dispatch_reg);
+                   move_warp(m_pipeline_reg[m_config->smem_latency-1],m_dispatch_reg);
                    m_dispatch_reg->clear();
                }
            } else {
@@ -2562,9 +2818,42 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const
     assert( result <= MAX_CTA_PER_SHADER );
     if (result < 1) {
        printf ("GPGPU-Sim uArch: ERROR ** Kernel requires more resources than shader has.\n");
+       if(gpgpu_ignore_resources_limitation) {
+    	   printf ("GPGPU-Sim uArch: gpgpu_ignore_resources_limitation is set, ignore the ERROR!\n");
+    	   return 1;
+       }
        abort();
     }
 
+    if(adpative_volta_cache_config && !k.volta_cache_config_set) {
+    	//For Volta, we assign the remaining shared memory to L1 cache
+    	//For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
+    	unsigned total_shmed = kernel_info->smem * result;
+    	assert(total_shmed >=0 && total_shmed <= gpgpu_shmem_size);
+    	assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
+    	assert(m_L1D_config.get_nset() == 4);  //Volta L1 has four sets
+    	if(total_shmed < gpgpu_shmem_size){
+    		if(total_shmed == 0)
+    			m_L1D_config.set_assoc(256);  //L1 is 128KB ans shd=0
+    		else if(total_shmed > 0 && total_shmed <= 8192)
+    			m_L1D_config.set_assoc(240);  //L1 is 120KB ans shd=8KB
+    		else if(total_shmed > 8192 && total_shmed <= 16384)
+    		    m_L1D_config.set_assoc(224);  //L1 is 112KB ans shd=16KB
+    		else if(total_shmed > 16384 && total_shmed <= 32768)
+    		    m_L1D_config.set_assoc(192);  //L1 is 96KB ans shd=32KB
+    		else if(total_shmed > 32768 && total_shmed <= 65536)
+    		    m_L1D_config.set_assoc(128);	//L1 is 64KB ans shd=64KB
+    		else if(total_shmed > 65536 && total_shmed <= gpgpu_shmem_size)
+    		     m_L1D_config.set_assoc(64); //L1 is 32KB and shd=96KB
+    		else
+    			assert(0);
+
+    		 printf ("GPGPU-Sim: Reconfigure L1 cache in Volta Archi to %uKB\n", m_L1D_config.get_total_size_inKB());
+    	}
+
+    	k.volta_cache_config_set = true;
+    }
+
     return result;
 }
 
@@ -2586,6 +2875,11 @@ void shader_core_ctx::cache_flush()
    m_ldst_unit->flush();
 }
 
+void shader_core_ctx::cache_invalidate()
+{
+   m_ldst_unit->invalidate();
+}
+
 // modifiers
 std::list<opndcoll_rfu_t::op_t> opndcoll_rfu_t::arbiter_t::allocate_reads() 
 {
@@ -3340,6 +3634,15 @@ void simt_core_cluster::print_not_completed( FILE *fp ) const
     }
 }
 
+
+float simt_core_cluster::get_current_occupancy( unsigned long long& active, unsigned long long& total ) const {
+    float aggregate = 0.f;
+    for( unsigned i=0; i < m_config->n_simt_cores_per_cluster; i++ ) {
+        aggregate+=m_core[i]->get_current_occupancy( active, total );
+    }
+    return aggregate / m_config->n_simt_cores_per_cluster;
+}
+
 unsigned simt_core_cluster::get_n_active_cta() const
 {
     unsigned n=0;
@@ -3403,6 +3706,12 @@ void simt_core_cluster::cache_flush()
         m_core[i]->cache_flush();
 }
 
+void simt_core_cluster::cache_invalidate()
+{
+    for( unsigned i=0; i < m_config->n_simt_cores_per_cluster; i++ )
+        m_core[i]->cache_invalidate();
+}
+
 bool simt_core_cluster::icnt_injection_buffer_full(unsigned size, bool write)
 {
     unsigned request_size = size;
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 97e438f..437506c 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -70,6 +70,14 @@
 
 #define WRITE_MASK_SIZE 8
 
+enum exec_unit_type_t
+{
+  NONE = 0,
+  SP = 1,
+  SFU = 2,
+  MEM = 3,
+  DP = 4
+};
 
 class thread_ctx_t {
 public:
@@ -308,6 +316,7 @@ enum concrete_scheduler
     CONCRETE_SCHEDULER_GTO,
     CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE,
     CONCRETE_SCHEDULER_WARP_LIMITING,
+    CONCRETE_SCHEDULER_OLDEST_FIRST,
     NUM_CONCRETE_SCHEDULERS
 };
 
@@ -317,13 +326,14 @@ public:
                    Scoreboard* scoreboard, simt_stack** simt, 
                    std::vector<shd_warp_t>* warp, 
                    register_set* sp_out,
+				   register_set* dp_out,
                    register_set* sfu_out,
                    register_set* tensor_core_out,
                    register_set* mem_out,
                    int id) 
         : m_supervised_warps(), m_stats(stats), m_shader(shader),
         m_scoreboard(scoreboard), m_simt_stack(simt), /*m_pipeline_reg(pipe_regs),*/ m_warp(warp),
-        m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){}
+        m_sp_out(sp_out),m_dp_out(dp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){}
     virtual ~scheduler_unit(){}
     virtual void add_supervised_warp_id(int i) {
         m_supervised_warps.push_back(&warp(i));
@@ -395,6 +405,7 @@ protected:
     //warp_inst_t** m_pipeline_reg;
     std::vector<shd_warp_t>* m_warp;
     register_set* m_sp_out;
+    register_set* m_dp_out;
     register_set* m_sfu_out;
     register_set* m_tensor_core_out;
     register_set* m_mem_out;
@@ -408,11 +419,12 @@ public:
                     Scoreboard* scoreboard, simt_stack** simt,
                     std::vector<shd_warp_t>* warp,
                     register_set* sp_out,
+					register_set* dp_out,
                     register_set* sfu_out,
                     register_set* tensor_core_out,
                     register_set* mem_out,
                     int id )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out,  mem_out, id ){}
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){}
 	virtual ~lrr_scheduler () {}
 	virtual void order_warps ();
     virtual void done_adding_supervised_warps() {
@@ -426,11 +438,12 @@ public:
                     Scoreboard* scoreboard, simt_stack** simt,
                     std::vector<shd_warp_t>* warp,
                     register_set* sp_out,
+					register_set* dp_out,
                     register_set* sfu_out,
                     register_set* tensor_core_out,
                     register_set* mem_out,
                     int id )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){}
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){}
 	virtual ~gto_scheduler () {}
 	virtual void order_warps ();
     virtual void done_adding_supervised_warps() {
@@ -439,6 +452,25 @@ public:
 
 };
 
+class oldest_scheduler : public scheduler_unit {
+public:
+	oldest_scheduler ( shader_core_stats* stats, shader_core_ctx* shader,
+                    Scoreboard* scoreboard, simt_stack** simt,
+                    std::vector<shd_warp_t>* warp,
+                    register_set* sp_out,
+					register_set* dp_out,
+                    register_set* sfu_out,
+                          register_set* tensor_core_out,
+                    register_set* mem_out,
+                    int id )
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){}
+	virtual ~oldest_scheduler () {}
+	virtual void order_warps ();
+        virtual void done_adding_supervised_warps() {
+        m_last_supervised_issued = m_supervised_warps.begin();
+    }
+
+};
 
 class two_level_active_scheduler : public scheduler_unit {
 public:
@@ -446,12 +478,13 @@ public:
                           Scoreboard* scoreboard, simt_stack** simt,
                           std::vector<shd_warp_t>* warp,
                           register_set* sp_out,
+						  register_set* dp_out,
                           register_set* sfu_out,
                           register_set* tensor_core_out,
                           register_set* mem_out,
                           int id,
                           char* config_str )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out,  mem_out, id ),
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ),
 	  m_pending_warps() 
     {
         unsigned inner_level_readin;
@@ -497,6 +530,7 @@ public:
                     Scoreboard* scoreboard, simt_stack** simt,
                     std::vector<shd_warp_t>* warp,
                     register_set* sp_out,
+					register_set* dp_out,
                     register_set* sfu_out,
                     register_set* tensor_core_out,
                     register_set* mem_out,
@@ -1060,6 +1094,23 @@ public:
         switch(inst.op) {
         case SFU_OP: break;
         case ALU_SFU_OP: break;
+        case DP_OP: break;     //for compute <= 29 (i..e Fermi and GT200)
+        default: return false;
+        }
+        return pipelined_simd_unit::can_issue(inst);
+    }
+    virtual void active_lanes_in_pipeline();
+    virtual void issue(  register_set& source_reg );
+};
+
+class dp_unit : public pipelined_simd_unit
+{
+public:
+	dp_unit( register_set* result_port, const shader_core_config *config, shader_core_ctx *core );
+    virtual bool can_issue( const warp_inst_t &inst ) const
+    {
+        switch(inst.op) {
+        case DP_OP: break;
         default: return false;
         }
         return pipelined_simd_unit::can_issue(inst);
@@ -1098,6 +1149,7 @@ public:
         case STORE_OP: return false;
         case TENSOR_CORE_STORE_OP: return false;
         case MEMORY_BARRIER_OP: return false;
+        case DP_OP: return false;
         default: break;
         }
         return pipelined_simd_unit::can_issue(inst);
@@ -1129,6 +1181,7 @@ public:
      
     void fill( mem_fetch *mf );
     void flush();
+    void invalidate();
     void writeback();
 
     // accessors
@@ -1195,6 +1248,7 @@ protected:
                                                       mem_fetch *mf,
                                                       enum cache_request_status status );
    mem_stage_stall_type process_memory_access_queue( cache_t *cache, warp_inst_t &inst );
+   mem_stage_stall_type process_memory_access_queue_l1cache( l1_cache *cache, warp_inst_t &inst );
 
    const memory_config *m_memory_config;
    class mem_fetch_interface *m_icnt;
@@ -1223,13 +1277,18 @@ protected:
    // for debugging
    unsigned long long m_last_inst_gpu_sim_cycle;
    unsigned long long m_last_inst_gpu_tot_sim_cycle;
+
+   std::deque<mem_fetch* > l1_latency_queue;
+   void L1_latency_queue_cycle();
 };
 
 enum pipeline_stage_name_t {
     ID_OC_SP=0,
+	ID_OC_DP,
     ID_OC_SFU,  
     ID_OC_MEM,  
     OC_EX_SP,
+	OC_EX_DP,
     OC_EX_SFU,
     OC_EX_MEM,
     EX_WB,
@@ -1240,9 +1299,11 @@ enum pipeline_stage_name_t {
 
 const char* const pipeline_stage_name_decode[] = {
     "ID_OC_SP",
+	"ID_OC_DP",
     "ID_OC_SFU",  
     "ID_OC_MEM",  
     "OC_EX_SP",
+	"OC_EX_DP",
     "OC_EX_SFU",
     "OC_EX_MEM",
     "EX_WB",
@@ -1340,27 +1401,29 @@ struct shader_core_config : public core_config
     mutable cache_config m_L1C_config;
     mutable l1d_cache_config m_L1D_config;
 
-    bool gmem_skip_L1D; // on = global memory access always skip the L1 cache 
-    
     bool gpgpu_dwf_reg_bankconflict;
 
     int gpgpu_num_sched_per_core;
     int gpgpu_max_insn_issue_per_warp;
+    bool gpgpu_dual_issue_diff_exec_units;
 
     //op collector
     int gpgpu_operand_collector_num_units_sp;
+    int gpgpu_operand_collector_num_units_dp;
     int gpgpu_operand_collector_num_units_sfu;
     int gpgpu_operand_collector_num_units_tensor_core;
     int gpgpu_operand_collector_num_units_mem;
     int gpgpu_operand_collector_num_units_gen;
 
     unsigned int gpgpu_operand_collector_num_in_ports_sp;
+    unsigned int gpgpu_operand_collector_num_in_ports_dp;
     unsigned int gpgpu_operand_collector_num_in_ports_sfu;
     unsigned int gpgpu_operand_collector_num_in_ports_tensor_core;
     unsigned int gpgpu_operand_collector_num_in_ports_mem;
     unsigned int gpgpu_operand_collector_num_in_ports_gen;
 
     unsigned int gpgpu_operand_collector_num_out_ports_sp;
+    unsigned int gpgpu_operand_collector_num_out_ports_dp;
     unsigned int gpgpu_operand_collector_num_out_ports_sfu;
     unsigned int gpgpu_operand_collector_num_out_ports_tensor_core;
     unsigned int gpgpu_operand_collector_num_out_ports_mem;
@@ -1368,6 +1431,7 @@ struct shader_core_config : public core_config
 
     int gpgpu_num_sp_units;
     int gpgpu_tensor_core_avail;
+    int gpgpu_num_dp_units;
     int gpgpu_num_sfu_units;
     int gpgpu_num_tensor_core_units;
     int gpgpu_num_mem_units;
@@ -1379,6 +1443,7 @@ struct shader_core_config : public core_config
     unsigned gpgpu_num_reg_banks;
     bool gpgpu_reg_bank_use_warp_id;
     bool gpgpu_local_mem_map;
+    bool gpgpu_ignore_resources_limitation;
     
     unsigned max_sp_latency;
     unsigned max_sfu_latency;
@@ -1391,10 +1456,14 @@ struct shader_core_config : public core_config
 
     int simt_core_sim_order; 
     
+    unsigned smem_latency;
+
     unsigned mem2device(unsigned memid) const { return memid + n_simt_clusters; }
 
     //Jin: concurrent kernel on sm
     bool gpgpu_concurrent_kernel_sm;
+
+    bool adpative_volta_cache_config;
 };
 
 struct shader_core_stats_pod {
@@ -1457,6 +1526,8 @@ struct shader_core_stats_pod {
     unsigned *last_shader_cycle_distro;
     unsigned *num_warps_issuable;
     unsigned gpgpu_n_stall_shd_mem;
+    unsigned* single_issue_nums;
+    unsigned* dual_issue_nums;
 
     //memory access classification
     int gpgpu_n_mem_read_local;
@@ -1528,6 +1599,8 @@ public:
         m_n_diverge = (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         shader_cycle_distro = (unsigned*) calloc(config->warp_size+3, sizeof(unsigned));
         last_shader_cycle_distro = (unsigned*) calloc(m_config->warp_size+3, sizeof(unsigned));
+        single_issue_nums = (unsigned*) calloc(config->gpgpu_num_sched_per_core,sizeof(unsigned));
+        dual_issue_nums = (unsigned*) calloc(config->gpgpu_num_sched_per_core, sizeof(unsigned));
 
         n_simt_to_mem = (long *)calloc(config->num_shader(), sizeof(long));
         n_mem_to_simt = (long *)calloc(config->num_shader(), sizeof(long));
@@ -1651,6 +1724,7 @@ public:
     void issue_block2core( class kernel_info_t &kernel );
 
     void cache_flush();
+    void cache_invalidate();
     void accept_fetch_response( mem_fetch *mf );
     void accept_ldst_unit_response( class mem_fetch * mf );
     void broadcast_barrier_reduction(unsigned cta_id, unsigned bar_id,warp_set_t warps);
@@ -1679,6 +1753,7 @@ public:
     // accessors
     virtual bool warp_waiting_at_barrier( unsigned warp_id ) const;
     void get_pdom_stack_top_info( unsigned tid, unsigned *pc, unsigned *rpc ) const;
+    float get_current_occupancy( unsigned long long & active, unsigned long long & total ) const;
 
 // used by pipeline timing model components:
     // modifiers
@@ -1885,10 +1960,14 @@ public:
     std::vector<register_set> m_pipeline_reg;
     Scoreboard               *m_scoreboard;
     opndcoll_rfu_t            m_operand_collector;
+    int m_active_warps;
 
     //schedule
     std::vector<scheduler_unit*>  schedulers;
 
+    //issue
+    unsigned int Issue_Prio;
+
     // execute
     unsigned m_num_function_units;
     std::vector<pipeline_stage_name_t> m_dispatch_port;
@@ -1940,6 +2019,7 @@ public:
     void reinit();
     unsigned issue_block2core();
     void cache_flush();
+    void cache_invalidate();
     bool icnt_injection_buffer_full(unsigned size, bool write);
     void icnt_inject_request_packet(class mem_fetch *mf);
 
@@ -1970,6 +2050,7 @@ public:
     void get_L1T_sub_stats(struct cache_sub_stats &css) const;
 
     void get_icnt_stats(long &n_simt_to_mem, long &n_mem_to_simt) const;
+    float get_current_occupancy( unsigned long long& active, unsigned long long & total ) const;
 
 private:
     unsigned m_cluster_id;
diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc
index ede9f20..52e2f5e 100644
--- a/src/gpgpusim_entrypoint.cc
+++ b/src/gpgpusim_entrypoint.cc
@@ -172,6 +172,7 @@ void *gpgpu_sim_thread_concurrent(void*)
         g_sim_active = false;
         pthread_mutex_unlock(&g_sim_lock);
     } while( !g_sim_done );
+
     printf("GPGPU-Sim: *** simulation thread exiting ***\n");
     fflush(stdout);
 
diff --git a/src/gpuwattch/makefile b/src/gpuwattch/makefile
index ab718cc..354c9ec 100644
--- a/src/gpuwattch/makefile
+++ b/src/gpuwattch/makefile
@@ -11,10 +11,10 @@ opt: $(TAR).mk obj_opt
 	@$(MAKE) TAG=opt -C . -f $(TAR).mk
 
 obj_dbg:
-	mkdir $@
+	mkdir -p $@
 
 obj_opt:
-	mkdir $@
+	mkdir -p $@
 
 depend:
 	@$(MAKE) TAG=opt -C . -f $(TAR).mk depend
diff --git a/src/intersim2/Makefile b/src/intersim2/Makefile
index bd42000..7d10b3f 100644
--- a/src/intersim2/Makefile
+++ b/src/intersim2/Makefile
@@ -36,7 +36,7 @@ DEBUG ?= 0
 LEX = flex
 YACC   = bison -y
 DEFINE = #-DTRACK_STALLS -DTRACK_BUFFERS -DTRACK_FLOWS -DTRACK_CREDITS
-INCPATH = -I. -Iarbiters -Iallocators -Irouters -Inetworks -Ipower
+INCPATH = -I. -Iarbiters -Iallocators -Irouters -Inetworks -Ipower -I$(GPGPUSIM_ROOT)/src
 
 ifeq ($(CREATE_LIBRARY),1)
 INCPATH += -I$(GPGPUSIM_ROOT)/src/gpgpu-sim/
diff --git a/src/intersim2/interconnect_interface.cpp b/src/intersim2/interconnect_interface.cpp
index 4386821..1e1a2d7 100644
--- a/src/intersim2/interconnect_interface.cpp
+++ b/src/intersim2/interconnect_interface.cpp
@@ -44,6 +44,7 @@
 #include "booksim.hpp"
 #include "intersim_config.hpp"
 #include "network.hpp"
+#include "trace.h"
 
 InterconnectInterface* InterconnectInterface::New(const char* const config_file)
 {
@@ -147,6 +148,8 @@ void InterconnectInterface::Push(unsigned input_deviceID, unsigned output_device
 {
   // it should have free buffer
   assert(HasBuffer(input_deviceID, size));
+
+  DPRINTF(INTERCONNECT, "Sent %d bytes from %d to %d", size, input_deviceID, output_deviceID);
   
   int output_icntID = _node_map[output_deviceID];
   int input_icntID = _node_map[input_deviceID];
@@ -178,7 +181,11 @@ void InterconnectInterface::Push(unsigned input_deviceID, unsigned output_device
     case WRITE_REQUEST: packet_type = Flit::WRITE_REQUEST  ;break;
     case READ_REPLY:    packet_type = Flit::READ_REPLY     ;break;
     case WRITE_ACK:     packet_type = Flit::WRITE_REPLY    ;break;
-    default: assert (0);
+    default:
+    	{
+    		cout<<"Type "<<mf->get_type()<<" is undefined!"<<endl;
+    		assert (0 && "Type is undefined");
+    	}
   }
 
   //TODO: _include_queuing ?
diff --git a/src/trace_streams.tup b/src/trace_streams.tup
index fd68a16..074c7c8 100644
--- a/src/trace_streams.tup
+++ b/src/trace_streams.tup
@@ -29,6 +29,8 @@ TS_TUP_BEGIN( trace_streams_type )
     TS_TUP( WARP_SCHEDULER ),
     TS_TUP( SCOREBOARD ),
     TS_TUP( MEMORY_PARTITION_UNIT ),
+    TS_TUP( MEMORY_SUBPARTITION_UNIT ),
+    TS_TUP( INTERCONNECT ),
     TS_TUP( LIVENESS ),
     TS_TUP( NUM_TRACE_STREAMS )
 TS_TUP_END( trace_streams_type )
diff --git a/version b/version
index c70c6ac..1a1a990 100644
--- a/version
+++ b/version
@@ -1 +1 @@
-const char *g_gpgpusim_version_string = "GPGPU-Sim Simulator Version 3.2.2 ";
+const char *g_gpgpusim_version_string = "GPGPU-Sim Simulator Version 4.0.0 ";
-- 
cgit v1.3


From b150969498792d50583674947d7c240cd6a11a68 Mon Sep 17 00:00:00 2001
From: aamir <araihan@ece.ubc.ca>
Date: Mon, 5 Nov 2018 16:50:52 -0800
Subject: addressed the deadlock issue

---
 CHANGES                                        | 16 ++++++++++++++--
 README                                         |  4 ++++
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config |  6 +++---
 src/gpgpu-sim/shader.cc                        |  6 +++---
 src/gpgpu-sim/shader.h                         |  2 +-
 5 files changed, 25 insertions(+), 9 deletions(-)

(limited to 'configs')

diff --git a/CHANGES b/CHANGES
index 60be885..a208986 100644
--- a/CHANGES
+++ b/CHANGES
@@ -3,11 +3,20 @@ Version 4.0.0 (development branch) versus 3.2.3
 -Front-End:
 1- Support .nc cache modifier and __ldg function to access the read-only L1D cache
 2- Partially-support some SASS_60 in the PTXP_PLUS (not completed yet)
--GPU Core:
+3- Added parsing support for wmma.load,wmma.mma and wmma.store ptx instructions
+4- Implmented cudaLaunchKernel for CUTLASS library
+-GPU Core Functional Simulation
+1- Implemented bfi and prmt instruction 
+2- Implemented wmma.load and wmma.store supporting all the layout configuration for TITANV GPU
+3- Implemented wmma.mma instructions supporting all of its 32 configuration for TITANV GPU
+4- debug support for wmma instruction using debug_tensorcore flag
+-GPU Core Performance Simulation:
 1- Fermi/Pascal coalescer: coalescing on 32-bytes sectors.
 2- Adding separate dp unit pipeline.
 3- diff dual issue: allow scheduler to issue diff insts at a time
 4- Fair memory issue from multiple schedulers.
+5- Added tensorcore unit pipeline.
+6- Corrected the bug in vector load instruction
 -Cache System:
 1- Sector L1/L2 cache
 2- Fetch-on-write and lazy-fetch-on-read write allocation policy.
@@ -23,12 +32,15 @@ Version 4.0.0 (development branch) versus 3.2.3
 1- Adding more detailed cache statistics to define and analyze cache bottlenecks.
 2- Adding more detailed memory statistics (BLP, RBL, etc) to define and analyze memory bottlenecks.
 3- Addig new system stats: gpu occupancy, L2BW, etc
+-Library:
+1  Enabled CUTLASS Library on GPGPU-Sim
+-Regression:
+1- Added TensorCore Regression Kernel
 -Configs:
 Adding the Pascal and Volta config files that has been correlated against real hardware.
 See the correlation website here: 
 https://engineering.purdue.edu/tgrogers/group/correlator.html
 
-
 Version 3.2.3+edits (development branch) versus 3.2.3
 - Support for running regression tests using Travis
 - Support added for CUDA dynamic parallelism (courtesy of Jin Wang from Georgia Tech)
diff --git a/README b/README
index 7eaae5d..e0692e8 100644
--- a/README
+++ b/README
@@ -24,6 +24,10 @@ Mahmoud Khairy, Jain Akshay, Tor Aamodt, Timothy G Rogers,
 Exploring Modern GPU Memory System Design Challenges through Accurate Modeling, arXiv:1810.07269, 
 https://arxiv.org/abs/1810.07269
 
+If you use the tensorcore in GPGPU-Sim or CUTLASS Library in your research
+please cite:
+	add the arxiv link here
+
 If you use the GPUWattch energy model in your research, please cite:
 
 Jingwen Leng, Tayler Hetherington, Ahmed ElTantawy, Syed Gilani, Nam Sung Kim,
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index c8351da..7532c01 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -12,6 +12,7 @@
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
 -gpgpu_ptx_force_max_capability 70 
+-gpgpu_tensor_core_avail 1
 
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
@@ -41,14 +42,13 @@
 -gpgpu_simd_model 1 
 
 # Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
 ## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
+-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12,1,1
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 4
 -gpgpu_num_dp_units 4
-
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
 # All Div operations are executed on SFU unit
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 0c0707c..cd2ed26 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1179,7 +1179,7 @@ void two_level_active_scheduler::order_warps()
     for (   std::vector< shd_warp_t* >::iterator iter = m_next_cycle_prioritized_warps.begin();
             iter != m_next_cycle_prioritized_warps.end(); ) {
         bool waiting = (*iter)->waiting();
-        for (int i=0; i<4; i++){
+        for (int i=0; i<MAX_INPUT_VALUES; i++){
             const warp_inst_t* inst = (*iter)->ibuffer_next_inst();
             //Is the instruction waiting on a long operation?
             if ( inst && inst->in[i] > 0 && this->m_scoreboard->islongop((*iter)->get_warp_id(), inst->in[i])){
@@ -1599,7 +1599,7 @@ void ldst_unit::L1_latency_queue_cycle()
 			   assert( !read_sent );
 			   l1_latency_queue[0] = NULL;
 			   if ( mf_next->get_inst().is_load() ) {
-				   for ( unsigned r=0; r < 4; r++)
+				   for ( unsigned r=0; r < MAX_OUTPUT_VALUES; r++)
 					   if (mf_next->get_inst().out[r] > 0)
 					   {
 						   assert(m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]]>0);
@@ -2146,7 +2146,7 @@ void ldst_unit::issue( register_set &reg_set )
    if (inst->is_load() and inst->space.get_type() != shared_space) {
       unsigned warp_id = inst->warp_id(); 
       unsigned n_accesses = inst->accessq_count(); 
-      for (unsigned r = 0; r < 4; r++) {
+      for (unsigned r = 0; r < MAX_OUTPUT_VALUES; r++) {
          unsigned reg_id = inst->out[r]; 
          if (reg_id > 0) {
             m_pending_writes[warp_id][reg_id] += n_accesses; 
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 437506c..3542120 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1360,7 +1360,7 @@ struct shader_core_config : public core_config
         max_sp_latency = 32;
         
 	max_tensor_core_latency = 64;
-        gpgpu_num_tensor_core_units=8;
+        gpgpu_num_tensor_core_units=4;//It will be (#TENSORCORE INSIDE SM)/2 (One warp is allocated to 2 Tensor Core)
         gpgpu_operand_collector_num_units_tensor_core=24;
         gpgpu_operand_collector_num_in_ports_tensor_core=8;
         gpgpu_operand_collector_num_out_ports_tensor_core=8;
-- 
cgit v1.3


From f799cd5485a36de48abce286b2f69cee75d2be38 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Mon, 5 Nov 2018 20:01:42 -0500
Subject: adding Volta sub_core model and double L1 BW

---
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config |  29 ++---
 src/abstract_hardware_model.h                  |  20 ++-
 src/gpgpu-sim/gpu-sim.cc                       |  11 +-
 src/gpgpu-sim/shader.cc                        | 161 +++++++++++++++----------
 src/gpgpu-sim/shader.h                         |  36 ++++--
 5 files changed, 168 insertions(+), 89 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 03ef5b9..2093cc0 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -42,9 +42,9 @@
 
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## Volta GV100 has 4 SP SIMD units, 4SFU units, 4 DP units per core
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,12
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,8
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 4
 -gpgpu_num_dp_units 4
@@ -72,6 +72,8 @@
 # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
 # disable this mode in case of multi kernels/apps execution
 -adpative_volta_cache_config 1
+# Volta unified cache has four ports
+-mem_unit_ports 4
 -gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_shmem_size 98304
 -gmem_skip_L1D 0
@@ -96,20 +98,15 @@
 # 64 KB Const
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
 
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
-# two banks per scheduler
+# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 1
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
 -gpgpu_num_reg_banks 8
 
 # shared memory bankconflict detection 
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 8333247..d0f7066 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -336,6 +336,7 @@ struct core_config {
     unsigned gpgpu_shmem_sizeDefault;
     unsigned gpgpu_shmem_sizePrefL1;
     unsigned gpgpu_shmem_sizePrefShared;
+    unsigned mem_unit_ports;
 
     // texture and constant cache line sizes (used to determine number of memory accesses)
     unsigned gpgpu_cache_texl1_linesize;
@@ -908,7 +909,7 @@ public:
     { 
         m_empty=true; 
     }
-    void issue( const active_mask_t &mask, unsigned warp_id, unsigned long long cycle, int dynamic_warp_id ) 
+    void issue( const active_mask_t &mask, unsigned warp_id, unsigned long long cycle, int dynamic_warp_id, int sch_id )
     {
         m_warp_active_mask = mask;
         m_warp_issued_mask = mask; 
@@ -919,6 +920,7 @@ public:
         cycles = initiation_interval;
         m_cache_hit=false;
         m_empty=false;
+        m_scheduler_id=sch_id;
     }
     const active_mask_t & get_active_mask() const
     {
@@ -1037,6 +1039,7 @@ public:
 
     void print( FILE *fout ) const;
     unsigned get_uid() const { return m_uid; }
+    unsigned get_schd_id() const { return m_scheduler_id; }
 
 
 protected:
@@ -1069,6 +1072,8 @@ protected:
 
     static unsigned sm_next_uid;
 
+    unsigned m_scheduler_id;  //the scheduler that issues this inst
+
     //Jin: cdp support
 public:
     int m_is_cdp;
@@ -1161,6 +1166,10 @@ public:
 		}
 		return false;
 	}
+	bool has_free(unsigned reg_id){
+		assert(reg_id < regs.size());
+		return regs[reg_id]->empty();
+	}
 	bool has_ready(){
 		for( unsigned i = 0; i < regs.size(); i++ ) {
 			if( not regs[i]->empty() ) {
@@ -1216,6 +1225,15 @@ public:
 		return NULL;
 	}
 
+	warp_inst_t ** get_free(unsigned reg_id){
+		assert(reg_id < regs.size());
+		if( regs[reg_id]->empty() ) {
+			return &regs[reg_id];
+		}
+		assert(0 && "No free register found");
+		return NULL;
+	}
+
 private:
 	std::vector<warp_inst_t*> regs;
 	const char* m_name;
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 8bbadf5..f318f7d 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -329,6 +329,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts,  
                  "Number of portions a warp is divided into for shared memory bank conflict check ",
                  "2");
+    option_parser_register(opp, "-mem_unit_ports", OPT_INT32, &mem_unit_ports,
+                 "The number of memory transactions allowed per core cycle",
+                 "1");
     option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts,
 				 "Number of portions a warp is divided into for shared memory bank conflict check ",
 				 "2");
@@ -347,8 +350,14 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_reg_bank_use_warp_id", OPT_BOOL, &gpgpu_reg_bank_use_warp_id,
              "Use warp ID in mapping registers to banks (default = off)",
              "0");
+    option_parser_register(opp, "-sub_core_model", OPT_BOOL, &sub_core_model,
+             "Sub Core Volta/Pascal model (default = off)",
+             "0");
+    option_parser_register(opp, "-enable_specialized_operand_collector", OPT_BOOL, &enable_specialized_operand_collector,
+                "enable_specialized_operand_collector",
+                "1");
     option_parser_register(opp, "-gpgpu_operand_collector_num_units_sp", OPT_INT32, &gpgpu_operand_collector_num_units_sp,
-                "number of collector units (default = 4)", 
+                "number of collector units (default = 4)",
                 "4");
     option_parser_register(opp, "-gpgpu_operand_collector_num_units_dp", OPT_INT32, &gpgpu_operand_collector_num_units_dp,
                    "number of collector units (default = 0)",
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 8a84970..300871e 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -234,52 +234,12 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     
     //op collector configuration
     enum { SP_CUS, DP_CUS, SFU_CUS, MEM_CUS, GEN_CUS };
-    m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp);
-    m_operand_collector.add_cu_set(DP_CUS, m_config->gpgpu_operand_collector_num_units_dp, m_config->gpgpu_operand_collector_num_out_ports_dp);
-    m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu);
-    m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem);
-    m_operand_collector.add_cu_set(GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen, m_config->gpgpu_operand_collector_num_out_ports_gen);
-    
     opndcoll_rfu_t::port_vector_t in_ports;
     opndcoll_rfu_t::port_vector_t out_ports;
     opndcoll_rfu_t::uint_vector_t cu_sets;
-    for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sp; i++) {
-        in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
-        out_ports.push_back(&m_pipeline_reg[OC_EX_SP]);
-        cu_sets.push_back((unsigned)SP_CUS);
-        cu_sets.push_back((unsigned)GEN_CUS);
-        m_operand_collector.add_port(in_ports,out_ports,cu_sets);
-        in_ports.clear(),out_ports.clear(),cu_sets.clear();
-    }
-    
-    for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_dp; i++) {
-            in_ports.push_back(&m_pipeline_reg[ID_OC_DP]);
-            out_ports.push_back(&m_pipeline_reg[OC_EX_DP]);
-            cu_sets.push_back((unsigned)DP_CUS);
-            cu_sets.push_back((unsigned)GEN_CUS);
-            m_operand_collector.add_port(in_ports,out_ports,cu_sets);
-            in_ports.clear(),out_ports.clear(),cu_sets.clear();
-        }
 
-    for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sfu; i++) {
-        in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
-        out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
-        cu_sets.push_back((unsigned)SFU_CUS);
-        cu_sets.push_back((unsigned)GEN_CUS);
-        m_operand_collector.add_port(in_ports,out_ports,cu_sets);
-        in_ports.clear(),out_ports.clear(),cu_sets.clear();
-    }
-    
-    for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_mem; i++) {
-        in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
-        out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
-        cu_sets.push_back((unsigned)MEM_CUS);
-        cu_sets.push_back((unsigned)GEN_CUS);                       
-        m_operand_collector.add_port(in_ports,out_ports,cu_sets);
-        in_ports.clear(),out_ports.clear(),cu_sets.clear();
-    }   
-    
-    
+    //configure generic collectors
+    m_operand_collector.add_cu_set(GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen, m_config->gpgpu_operand_collector_num_out_ports_gen);
     for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_gen; i++) {
         in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
         in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
@@ -287,10 +247,57 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
         out_ports.push_back(&m_pipeline_reg[OC_EX_SP]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
-        cu_sets.push_back((unsigned)GEN_CUS);   
+        if(m_config->gpgpu_num_dp_units > 0) {
+			in_ports.push_back(&m_pipeline_reg[ID_OC_DP]);
+			out_ports.push_back(&m_pipeline_reg[OC_EX_DP]);
+        }
+        cu_sets.push_back((unsigned)GEN_CUS);
         m_operand_collector.add_port(in_ports,out_ports,cu_sets);
         in_ports.clear(),out_ports.clear(),cu_sets.clear();
     }
+
+    if(m_config->enable_specialized_operand_collector) {
+		m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp);
+		m_operand_collector.add_cu_set(DP_CUS, m_config->gpgpu_operand_collector_num_units_dp, m_config->gpgpu_operand_collector_num_out_ports_dp);
+		m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu);
+		m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem);
+
+		for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sp; i++) {
+			in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
+			out_ports.push_back(&m_pipeline_reg[OC_EX_SP]);
+			cu_sets.push_back((unsigned)SP_CUS);
+			cu_sets.push_back((unsigned)GEN_CUS);
+			m_operand_collector.add_port(in_ports,out_ports,cu_sets);
+			in_ports.clear(),out_ports.clear(),cu_sets.clear();
+		}
+
+		for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_dp; i++) {
+				in_ports.push_back(&m_pipeline_reg[ID_OC_DP]);
+				out_ports.push_back(&m_pipeline_reg[OC_EX_DP]);
+				cu_sets.push_back((unsigned)DP_CUS);
+				cu_sets.push_back((unsigned)GEN_CUS);
+				m_operand_collector.add_port(in_ports,out_ports,cu_sets);
+				in_ports.clear(),out_ports.clear(),cu_sets.clear();
+			}
+
+		for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sfu; i++) {
+			in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
+			out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
+			cu_sets.push_back((unsigned)SFU_CUS);
+			cu_sets.push_back((unsigned)GEN_CUS);
+			m_operand_collector.add_port(in_ports,out_ports,cu_sets);
+			in_ports.clear(),out_ports.clear(),cu_sets.clear();
+		}
+
+		for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_mem; i++) {
+			in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
+			out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
+			cu_sets.push_back((unsigned)MEM_CUS);
+			cu_sets.push_back((unsigned)GEN_CUS);
+			m_operand_collector.add_port(in_ports,out_ports,cu_sets);
+			in_ports.clear(),out_ports.clear(),cu_sets.clear();
+		}
+    }
     
     m_operand_collector.init( m_config->gpgpu_num_reg_banks, this );
     
@@ -761,15 +768,19 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst )
         inst.generate_mem_accesses();
 }
 
-void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* next_inst, const active_mask_t &active_mask, unsigned warp_id )
+void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* next_inst, const active_mask_t &active_mask, unsigned warp_id, unsigned sch_id )
 {
-    warp_inst_t** pipe_reg = pipe_reg_set.get_free();
+	warp_inst_t** pipe_reg;
+	if(m_config->sub_core_model)
+		 pipe_reg = pipe_reg_set.get_free(sch_id);
+	else
+		pipe_reg = pipe_reg_set.get_free();
     assert(pipe_reg);
 
     m_warp[warp_id].ibuffer_free();
     assert(next_inst->valid());
     **pipe_reg = *next_inst; // static instruction information
-    (*pipe_reg)->issue( active_mask, warp_id, gpu_tot_sim_cycle + gpu_sim_cycle, m_warp[warp_id].get_dynamic_warp_id() ); // dynamic instruction information
+    (*pipe_reg)->issue( active_mask, warp_id, gpu_tot_sim_cycle + gpu_sim_cycle, m_warp[warp_id].get_dynamic_warp_id(), sch_id ); // dynamic instruction information
     m_stats->shader_cycle_distro[2+(*pipe_reg)->active_count()]++;
     func_exec_inst( **pipe_reg );
     if( next_inst->op == BARRIER_OP ){
@@ -950,8 +961,8 @@ void scheduler_unit::cycle()
                         const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask();
                         assert( warp(warp_id).inst_in_pipeline() );
                         if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) {
-                        	if( m_mem_out->has_free() && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::MEM)) {
-                                m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id);
+                        	if( m_mem_out->has_free(m_id) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::MEM)) {
+                                m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id,m_id);
                                 issued++;
                                 issued_inst=true;
                                 warp_inst_issued = true;
@@ -959,9 +970,9 @@ void scheduler_unit::cycle()
                             }
                         } else {
 
-                            bool sp_pipe_avail = m_sp_out->has_free();
-                            bool sfu_pipe_avail = m_sfu_out->has_free();
-                            bool dp_pipe_avail = m_dp_out->has_free();
+                            bool sp_pipe_avail = m_sp_out->has_free(m_id);
+                            bool sfu_pipe_avail = m_sfu_out->has_free(m_id);
+                            bool dp_pipe_avail = m_dp_out->has_free(m_id);
                             if( sp_pipe_avail && (pI->op != SFU_OP && pI->op != DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SP)) {
                                 
                                 //Jin: special for CDP api
@@ -983,14 +994,14 @@ void scheduler_unit::cycle()
                                 }
 
                                 // always prefer SP pipe for operations that can use both SP and SFU pipelines
-                                m_shader->issue_warp(*m_sp_out,pI,active_mask,warp_id);
+                                m_shader->issue_warp(*m_sp_out,pI,active_mask,warp_id,m_id);
                                 issued++;
                                 issued_inst=true;
                                 warp_inst_issued = true;
                                 previous_issued_inst_exec_type = exec_unit_type_t::SP;
                             } else if ( (m_shader->m_config->gpgpu_num_dp_units != 0) && (pI->op == DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::DP)) {
                                 if( dp_pipe_avail ) {
-                                    m_shader->issue_warp(*m_dp_out,pI,active_mask,warp_id);
+                                    m_shader->issue_warp(*m_dp_out,pI,active_mask,warp_id,m_id);
                                     issued++;
                                     issued_inst=true;
                                     warp_inst_issued = true;
@@ -999,7 +1010,7 @@ void scheduler_unit::cycle()
                             }  //If the DP units = 0 (like in Fermi archi), then change DP inst to SFU inst
                             else if ( ((m_shader->m_config->gpgpu_num_dp_units == 0 && pI->op == DP_OP) || (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP)) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SFU)) {
                                 if( sfu_pipe_avail ) {
-                                    m_shader->issue_warp(*m_sfu_out,pI,active_mask,warp_id);
+                                    m_shader->issue_warp(*m_sfu_out,pI,active_mask,warp_id,m_id);
                                     issued++;
                                     issued_inst=true;
                                     warp_inst_issued = true;
@@ -2068,7 +2079,11 @@ void ldst_unit::writeback()
 
 unsigned ldst_unit::clock_multiplier() const
 { 
-    return m_config->mem_warp_parts; 
+	//to model multiple read port, we give multiple cycles for the memory units
+	if(m_config->mem_unit_ports)
+		return m_config->mem_unit_ports;
+	else
+		return m_config->mem_warp_parts;
 }
 /*
 void ldst_unit::issue( register_set &reg_set )
@@ -3305,18 +3320,34 @@ void opndcoll_rfu_t::init( unsigned num_banks, shader_core_ctx *shader )
    m_bank_warp_shift = (unsigned)(int) (log(m_warp_size+0.5) / log(2.0));
    assert( (m_bank_warp_shift == 5) || (m_warp_size != 32) );
 
+   sub_core_model = shader->get_config()->sub_core_model;
+   m_num_warp_sceds = shader->get_config()->gpgpu_num_sched_per_core;
+   if(sub_core_model)
+	   assert(num_banks % shader->get_config()->gpgpu_num_sched_per_core == 0);
+   m_num_banks_per_sched = num_banks / shader->get_config()->gpgpu_num_sched_per_core;
+
    for( unsigned j=0; j<m_cu.size(); j++) {
-       m_cu[j]->init(j,num_banks,m_bank_warp_shift,shader->get_config(),this);
+       m_cu[j]->init(j,num_banks,m_bank_warp_shift,shader->get_config(),this, sub_core_model, m_num_banks_per_sched );
    }
    m_initialized=true;
+
+
+
+
 }
 
-int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift)
+int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift, bool sub_core_model, unsigned banks_per_sched, unsigned sched_id)
 {
    int bank = regnum;
    if (bank_warp_shift)
       bank += wid;
-   return bank % num_banks;
+   if(sub_core_model) {
+	   unsigned bank_num  = (bank % banks_per_sched) + (sched_id * banks_per_sched);
+	   assert(bank_num < num_banks);
+	   return bank_num;
+   }
+   else
+	   return bank % num_banks;
 }
 
 bool opndcoll_rfu_t::writeback( const warp_inst_t &inst )
@@ -3327,9 +3358,9 @@ bool opndcoll_rfu_t::writeback( const warp_inst_t &inst )
    unsigned n=0;
    for( r=regs.begin(); r!=regs.end();r++,n++ ) {
       unsigned reg = *r;
-      unsigned bank = register_bank(reg,inst.warp_id(),m_num_banks,m_bank_warp_shift);
+      unsigned bank = register_bank(reg,inst.warp_id(),m_num_banks,m_bank_warp_shift, sub_core_model, m_num_banks_per_sched, inst.get_schd_id());
       if( m_arbiter.bank_idle(bank) ) {
-          m_arbiter.allocate_bank_for_write(bank,op_t(&inst,reg,m_num_banks,m_bank_warp_shift));
+          m_arbiter.allocate_bank_for_write(bank,op_t(&inst,reg,m_num_banks,m_bank_warp_shift, sub_core_model, m_num_banks_per_sched, inst.get_schd_id()));
       } else {
           return false;
       }
@@ -3413,7 +3444,7 @@ void opndcoll_rfu_t::allocate_reads()
       const op_t &rr = *r;
       unsigned reg = rr.get_reg();
       unsigned wid = rr.get_wid();
-      unsigned bank = register_bank(reg,wid,m_num_banks,m_bank_warp_shift);
+      unsigned bank = register_bank(reg,wid,m_num_banks,m_bank_warp_shift,sub_core_model, m_num_banks_per_sched, rr.get_sid());
       m_arbiter.allocate_for_read(bank,rr);
       read_ops[bank] = rr;
    }
@@ -3464,7 +3495,9 @@ void opndcoll_rfu_t::collector_unit_t::init( unsigned n,
                                              unsigned num_banks, 
                                              unsigned log2_warp_size,
                                              const core_config *config,
-                                             opndcoll_rfu_t *rfu ) 
+                                             opndcoll_rfu_t *rfu,
+											 bool sub_core_model,
+											 unsigned banks_per_sched)
 { 
    m_rfu=rfu;
    m_cuid=n; 
@@ -3472,6 +3505,8 @@ void opndcoll_rfu_t::collector_unit_t::init( unsigned n,
    assert(m_warp==NULL); 
    m_warp = new warp_inst_t(config);
    m_bank_warp_shift=log2_warp_size;
+   m_sub_core_model = sub_core_model;
+   m_num_banks_per_sched = banks_per_sched;
 }
 
 bool opndcoll_rfu_t::collector_unit_t::allocate( register_set* pipeline_reg_set, register_set* output_reg_set ) 
@@ -3486,7 +3521,7 @@ bool opndcoll_rfu_t::collector_unit_t::allocate( register_set* pipeline_reg_set,
       for( unsigned op=0; op < MAX_REG_OPERANDS; op++ ) {
          int reg_num = (*pipeline_reg)->arch_reg.src[op]; // this math needs to match that used in function_info::ptx_decode_inst
          if( reg_num >= 0 ) { // valid register
-            m_src_op[op] = op_t( this, op, reg_num, m_num_banks, m_bank_warp_shift );
+            m_src_op[op] = op_t( this, op, reg_num, m_num_banks, m_bank_warp_shift, m_sub_core_model, m_num_banks_per_sched, (*pipeline_reg)->get_schd_id() );
             m_not_ready.set(op);
          } else 
             m_src_op[op] = op_t();
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 4a87126..e6132f5 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -291,7 +291,7 @@ inline unsigned wid_from_hw_tid(unsigned tid, unsigned warp_size){return tid/war
 const unsigned WARP_PER_CTA_MAX = 64;
 typedef std::bitset<WARP_PER_CTA_MAX> warp_set_t;
 
-int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift);
+int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift, bool sub_core_model, unsigned banks_per_sched, unsigned sched_id );
 
 class shader_core_ctx;
 struct shader_core_config;
@@ -378,6 +378,8 @@ public:
     // m_supervised_warps with their scheduling policies
     virtual void order_warps() = 0;
 
+    int get_schd_id() const {return m_id;}
+
 protected:
     virtual void do_on_warp_issued( unsigned warp_id,
                                     unsigned num_issued,
@@ -601,23 +603,25 @@ private:
    public:
 
       op_t() { m_valid = false; }
-      op_t( collector_unit_t *cu, unsigned op, unsigned reg, unsigned num_banks, unsigned bank_warp_shift )
+      op_t( collector_unit_t *cu, unsigned op, unsigned reg, unsigned num_banks, unsigned bank_warp_shift, bool sub_core_model, unsigned banks_per_sched, unsigned sched_id )
       {
          m_valid = true;
          m_warp=NULL;
          m_cu = cu;
          m_operand = op;
          m_register = reg;
-         m_bank = register_bank(reg,cu->get_warp_id(),num_banks,bank_warp_shift);
+         m_shced_id = sched_id;
+         m_bank = register_bank(reg,cu->get_warp_id(),num_banks,bank_warp_shift, sub_core_model, banks_per_sched, sched_id);
       }
-      op_t( const warp_inst_t *warp, unsigned reg, unsigned num_banks, unsigned bank_warp_shift )
+      op_t( const warp_inst_t *warp, unsigned reg, unsigned num_banks, unsigned bank_warp_shift, bool sub_core_model, unsigned banks_per_sched, unsigned sched_id )
       {
          m_valid=true;
          m_warp=warp;
          m_register=reg;
          m_cu=NULL;
          m_operand = -1;
-         m_bank = register_bank(reg,warp->warp_id(),num_banks,bank_warp_shift);
+         m_shced_id = sched_id;
+         m_bank = register_bank(reg,warp->warp_id(),num_banks,bank_warp_shift, sub_core_model, banks_per_sched, sched_id);
       }
 
       // accessors
@@ -633,6 +637,10 @@ private:
           else if( m_cu ) return m_cu->get_warp_id();
           else abort();
       }
+      unsigned get_sid() const
+	  {
+		 return m_shced_id;
+	  }
       unsigned get_active_count() const
       {
           if( m_warp ) return m_warp->active_count();
@@ -677,6 +685,7 @@ private:
       unsigned  m_operand; // operand offset in instruction. e.g., add r1,r2,r3; r2 is oprd 0, r3 is 1 (r1 is dst)
       unsigned  m_register;
       unsigned  m_bank;
+      unsigned  m_shced_id; //scheduler id that has issued this inst
    };
 
    enum alloc_t {
@@ -697,7 +706,7 @@ private:
          else if( m_allocation == WRITE_ALLOC ) { fprintf(fp,"wr: "); m_op.dump(fp); }
          fprintf(fp,"\n");
       }
-      void alloc_read( const op_t &op )  { assert(is_free()); m_allocation=READ_ALLOC; m_op=op; }
+      void alloc_read( const op_t &op )  { assert(is_free()); m_allocation=READ_ALLOC; m_op=op;  }
       void alloc_write( const op_t &op ) { assert(is_free()); m_allocation=WRITE_ALLOC; m_op=op; }
       void reset() { m_allocation = NO_ALLOC; }
    private:
@@ -851,7 +860,9 @@ private:
                 unsigned num_banks, 
                 unsigned log2_warp_size,
                 const core_config *config,
-                opndcoll_rfu_t *rfu ); 
+                opndcoll_rfu_t *rfu,
+				bool m_sub_core_model,
+				unsigned num_banks_per_sched);
       bool allocate( register_set* pipeline_reg, register_set* output_reg );
 
       void collect_operand( unsigned op )
@@ -879,6 +890,9 @@ private:
       unsigned m_bank_warp_shift;
       opndcoll_rfu_t *m_rfu;
 
+      unsigned m_num_banks_per_sched;
+      bool m_sub_core_model;
+
    };
 
    class dispatch_unit_t {
@@ -921,6 +935,10 @@ private:
    std::vector<collector_unit_t *> m_cu;
    arbiter_t m_arbiter;
 
+   unsigned m_num_banks_per_sched;
+   unsigned m_num_warp_sceds;
+   bool sub_core_model;
+
    //unsigned m_num_ports;
    //std::vector<warp_inst_t**> m_input;
    //std::vector<warp_inst_t**> m_output;
@@ -1361,6 +1379,7 @@ struct shader_core_config : public core_config
     bool gpgpu_dual_issue_diff_exec_units;
 
     //op collector
+    bool enable_specialized_operand_collector;
     int gpgpu_operand_collector_num_units_sp;
     int gpgpu_operand_collector_num_units_dp;
     int gpgpu_operand_collector_num_units_sfu;
@@ -1392,6 +1411,7 @@ struct shader_core_config : public core_config
     bool gpgpu_reg_bank_use_warp_id;
     bool gpgpu_local_mem_map;
     bool gpgpu_ignore_resources_limitation;
+    bool sub_core_model;
     
     unsigned max_sp_latency;
     unsigned max_sfu_latency;
@@ -1848,7 +1868,7 @@ public:
     friend class scheduler_unit; //this is needed to use private issue warp.
     friend class TwoLevelScheduler;
     friend class LooseRoundRobbinScheduler;
-    void issue_warp( register_set& warp, const warp_inst_t *pI, const active_mask_t &active_mask, unsigned warp_id );
+    void issue_warp( register_set& warp, const warp_inst_t *pI, const active_mask_t &active_mask, unsigned warp_id, unsigned sch_id );
     void func_exec_inst( warp_inst_t &inst );
 
      // Returns numbers of addresses in translated_addrs
-- 
cgit v1.3


From 7d42f5849aa1abb4f081803843ea78009d5b20ce Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Tue, 6 Nov 2018 19:48:52 -0500
Subject: adding tensor cores config

---
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config |  5 +++--
 src/abstract_hardware_model.h                  |  4 ++++
 src/gpgpu-sim/shader.cc                        | 11 ++++++++++-
 src/gpgpu-sim/shader.h                         |  4 ----
 4 files changed, 17 insertions(+), 7 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 5ac734d..7b0369a 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -12,7 +12,6 @@
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
 -gpgpu_ptx_force_max_capability 70 
--gpgpu_tensor_core_avail 1
 
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
@@ -45,10 +44,12 @@
 # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
 ## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,8,1,1
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,8,4,4
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 4
 -gpgpu_num_dp_units 4
+-gpgpu_tensor_core_avail 1
+-gpgpu_num_tensor_core_units 4
 
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 5543a71..edd48a1 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -1269,6 +1269,10 @@ public:
 		return NULL;
 	}
 
+	unsigned get_size(){
+		return regs.size();
+	}
+
 private:
 	std::vector<warp_inst_t*> regs;
 	const char* m_name;
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 78facbd..c52ba35 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -90,6 +90,15 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     for (int j = 0; j<N_PIPELINE_STAGES; j++) {
         m_pipeline_reg.push_back(register_set(m_config->pipe_widths[j],pipeline_stage_name_decode[j]));
     }
+    if(m_config->sub_core_model) {
+    	//in subcore model, each scheduler should has its own issue register, so num scheduler = reg width
+    	assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SP].get_size() );
+    	if(m_config->gpgpu_num_dp_units > 0)
+    		assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_DP].get_size() );
+    	assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SFU].get_size() );
+    	assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_MEM].get_size() );
+    	assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_TENSOR_CORE].get_size() );
+    }
     
     m_threadState = (thread_ctx_t*) calloc(sizeof(thread_ctx_t), config->n_thread_per_shader);
     
@@ -1045,7 +1054,7 @@ void scheduler_unit::cycle()
                             }                         
                              else if ( (pI->op == TENSOR_CORE_OP) ) {
                                 if( tensor_core_pipe_avail ) {
-                                    m_shader->issue_warp(*m_tensor_core_out,pI,active_mask,warp_id);
+                                    m_shader->issue_warp(*m_tensor_core_out,pI,active_mask,warp_id,m_id);
                                     issued++;
                                     issued_inst=true;
                                     warp_inst_issued = true;
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index fcd134d..7b33c14 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1378,10 +1378,6 @@ struct shader_core_config : public core_config
         max_sp_latency = 32;
         
 	max_tensor_core_latency = 64;
-        gpgpu_num_tensor_core_units=4;//It will be (#TENSORCORE INSIDE SM)/2 (One warp is allocated to 2 Tensor Core)
-        gpgpu_operand_collector_num_units_tensor_core=24;
-        gpgpu_operand_collector_num_in_ports_tensor_core=8;
-        gpgpu_operand_collector_num_out_ports_tensor_core=8;
         
 	m_L1I_config.init(m_L1I_config.m_config_string,FuncCachePreferNone);
         m_L1T_config.init(m_L1T_config.m_config_string,FuncCachePreferNone);
-- 
cgit v1.3


From 111cca2a061fe4f247be930cb44fdcdaec2b59f5 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 7 Nov 2018 20:30:02 -0500
Subject: Adding INT unit, fixing tensor core latency, updating config files

---
 configs/tested-cfgs/SM2_GTX480/gpgpusim.config |   7 +-
 configs/tested-cfgs/SM6_TITANX/gpgpusim.config |   7 +-
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config |   8 +-
 src/abstract_hardware_model.h                  |   3 +
 src/cuda-sim/cuda-sim.cc                       |  35 ++++--
 src/gpgpu-sim/gpu-sim.cc                       |  16 ++-
 src/gpgpu-sim/shader.cc                        | 165 +++++++++++++++++++------
 src/gpgpu-sim/shader.h                         |  57 +++++++--
 8 files changed, 232 insertions(+), 66 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index 4096b09..d71b2fd 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -30,9 +30,10 @@
 -gpgpu_simd_model 1 
 
 # Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-#For Fermi, DP unit =0, DP inst is executed on SFU
--gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
+# For Fermi, DP unit =0, DP inst is executed on SFU
+# For Fermi, INT unit =0, INT inst is executed on SP
+-gpgpu_pipeline_widths 2,0,0,1,1,2,0,0,1,1,2
 -gpgpu_num_sp_units 2
 -gpgpu_num_sfu_units 1
 -gpgpu_num_dp_units 0
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index ed35531..cb23ab3 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -35,10 +35,11 @@
 -gpgpu_simd_model 1 
 
 # Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 4 SFU units
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs
+# There is no int unit in Pascal
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
+-gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5
 -gpgpu_num_sp_units 2
 -gpgpu_num_sfu_units 2
 -gpgpu_num_dp_units 1
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 7b0369a..e143f31 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -41,13 +41,14 @@
 -gpgpu_simd_model 1 
 
 # Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
 ## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,8,4,4
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 4
 -gpgpu_num_dp_units 4
+-gpgpu_num_int_units 4
 -gpgpu_tensor_core_avail 1
 -gpgpu_num_tensor_core_units 4
 
@@ -64,7 +65,8 @@
 -ptx_opcode_initiation_dp 4,4,4,4,130
 -ptx_opcode_latency_sfu 100
 -ptx_opcode_initiation_sfu 8
-
+-ptx_opcode_latency_tesnor 64
+-ptx_opcode_initiation_tensor 64
 
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index edd48a1..b65df81 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -83,6 +83,8 @@ enum uarch_op_t {
    SFU_OP,
    TENSOR_CORE_OP,
    DP_OP,
+   SP_OP,
+   INTP_OP,
    ALU_SFU_OP,
    LOAD_OP,
    TENSOR_CORE_LOAD_OP,
@@ -141,6 +143,7 @@ enum operation_pipeline_t {
     UNKOWN_OP,
     SP__OP,
 	DP__OP,
+	INTP__OP,
     SFU__OP,
     TENSOR_CORE__OP,
     MEM__OP
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index c9ac8cb..7dc20cd 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -62,8 +62,8 @@ addr_t g_debug_pc = 0xBEEF1518;
 unsigned g_ptx_sim_num_insn = 0;
 unsigned gpgpu_param_num_shaders = 0;
 
-char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp,*opcode_latency_sfu;
-char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp,*opcode_initiation_sfu;
+char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp,*opcode_latency_sfu,*opcode_latency_tensor;
+char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp,*opcode_initiation_sfu,*opcode_initiation_tensor;
 char *cdp_latency_str;
 unsigned cdp_latency[5];
 
@@ -84,6 +84,10 @@ void ptx_opcocde_latency_options (option_parser_t opp) {
 			"Opcode latencies for SFU instructions"
 			"Default 8",
 			"8");
+	option_parser_register(opp, "-ptx_opcode_latency_tesnor", OPT_CSTR, &opcode_latency_tensor,
+			"Opcode latencies for Tensor instructions"
+			"Default 64",
+			"64");
 	option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int,
 			"Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV>"
 			"Default 1,1,4,4,32",
@@ -100,6 +104,10 @@ void ptx_opcocde_latency_options (option_parser_t opp) {
 			"Opcode initiation intervals for sfu instructions"
 			"Default 8",
 			"8");
+	option_parser_register(opp, "-ptx_opcode_initiation_tensor", OPT_CSTR, &opcode_initiation_tensor,
+			"Opcode initiation intervals for tensor instructions"
+			"Default 64",
+			"64");
 	option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str,
 			"CDP API latency <cudaStreamCreateWithFlags, \
 cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, \
@@ -609,10 +617,12 @@ void ptx_instruction::set_opcode_and_latency()
 	unsigned fp_latency[5];
 	unsigned dp_latency[5];
 	unsigned sfu_latency;
+	unsigned tensor_latency;
 	unsigned int_init[5];
 	unsigned fp_init[5];
 	unsigned dp_init[5];
 	unsigned sfu_init;
+	unsigned tensor_init;
 	/*
 	 * [0] ADD,SUB
 	 * [1] MAX,Min
@@ -631,6 +641,8 @@ void ptx_instruction::set_opcode_and_latency()
 			&dp_latency[3],&dp_latency[4]);
 	sscanf(opcode_latency_sfu, "%u",
 			&sfu_latency);
+	sscanf(opcode_latency_tensor, "%u",
+			&tensor_latency);
 	sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u",
 			&int_init[0],&int_init[1],&int_init[2],
 			&int_init[3],&int_init[4]);
@@ -642,6 +654,8 @@ void ptx_instruction::set_opcode_and_latency()
 			&dp_init[3],&dp_init[4]);
 	sscanf(opcode_initiation_sfu, "%u",
 			&sfu_init);
+	sscanf(opcode_initiation_tensor, "%u",
+			&tensor_init);
 	sscanf(cdp_latency_str, "%u,%u,%u,%u,%u",
 			&cdp_latency[0],&cdp_latency[1],&cdp_latency[2],
             &cdp_latency[3],&cdp_latency[4]);
@@ -701,6 +715,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   case F32_TYPE:
 		   latency = fp_latency[0];
 		   initiation_interval = fp_init[0];
+		   op = SP_OP;
 		   break;
 	   case F64_TYPE:
 	   case FF64_TYPE:
@@ -714,6 +729,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   default: //Use int settings for default
 		   latency = int_latency[0];
 		   initiation_interval = int_init[0];
+		   op = INTP_OP;
 		   break;
 	   }
 	   break;
@@ -723,6 +739,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   case F32_TYPE:
 		   latency = fp_latency[1];
 		   initiation_interval = fp_init[1];
+		   op = SP_OP;
 		   break;
 	   case F64_TYPE:
 	   case FF64_TYPE:
@@ -736,6 +753,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   default: //Use int settings for default
 		   latency = int_latency[1];
 		   initiation_interval = int_init[1];
+		   op = INTP_OP;
 		   break;
 	   }
 	   break;
@@ -745,6 +763,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   case F32_TYPE:
 		   latency = fp_latency[2];
 		   initiation_interval = fp_init[2];
+		   op = SP_OP;
 		   break;
 	   case F64_TYPE:
 	   case FF64_TYPE:
@@ -758,7 +777,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   default: //Use int settings for default
 		   latency = int_latency[2];
 		   initiation_interval = int_init[2];
-		   op = SFU_OP;
+		   op = INTP_OP;
 		   break;
 	   }
 	   break;
@@ -768,6 +787,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   case F32_TYPE:
 		   latency = fp_latency[3];
 		   initiation_interval = fp_init[3];
+		   op = SP_OP;
 		   break;
 	   case F64_TYPE:
 	   case FF64_TYPE:
@@ -781,7 +801,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   default: //Use int settings for default
 		   latency = int_latency[3];
 		   initiation_interval = int_init[3];
-		   op = SFU_OP;
+		   op = INTP_OP;
 		   break;
 	   }
 	   break;
@@ -808,15 +828,14 @@ void ptx_instruction::set_opcode_and_latency()
 	   }
 	   break;
    case SQRT_OP: case SIN_OP: case COS_OP: case EX2_OP: case LG2_OP: case RSQRT_OP: case RCP_OP:
-	   //Using double to approximate those
 	  latency = sfu_latency;
 	  initiation_interval = sfu_init;
       op = SFU_OP;
       break;
    case MMA_OP:
-	   latency = 64;
-	   initiation_interval = 64;
-           op=TENSOR_CORE_OP;
+	   latency = tensor_latency;
+	   initiation_interval = tensor_init;
+       op=TENSOR_CORE_OP;
 	   break;
    case SHFL_OP:
 	   latency = 32;
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index fdc8e08..6cb4779 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -365,6 +365,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_units_sfu", OPT_INT32, &gpgpu_operand_collector_num_units_sfu,
                 "number of collector units (default = 4)", 
                 "4");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_units_int", OPT_INT32, &gpgpu_operand_collector_num_units_int,
+                "number of collector units (default = 0)",
+                "0");
     option_parser_register(opp, "-gpgpu_operand_collector_num_units_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_units_tensor_core,
                 "number of collector units (default = 4)", 
                 "4");
@@ -383,6 +386,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_sfu", OPT_INT32, &gpgpu_operand_collector_num_in_ports_sfu,
                            "number of collector unit in ports (default = 1)", 
                            "1");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_int", OPT_INT32, &gpgpu_operand_collector_num_in_ports_int,
+                           "number of collector unit in ports (default = 0)",
+                           "0");
     option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_in_ports_tensor_core,
                            "number of collector unit in ports (default = 1)", 
                            "1");
@@ -401,6 +407,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_sfu", OPT_INT32, &gpgpu_operand_collector_num_out_ports_sfu,
                            "number of collector unit in ports (default = 1)", 
                            "1");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_int", OPT_INT32, &gpgpu_operand_collector_num_out_ports_int,
+                           "number of collector unit in ports (default = 0)",
+                           "0");
     option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_out_ports_tensor_core,
                            "number of collector unit in ports (default = 1)", 
                            "1");
@@ -427,8 +436,8 @@ void shader_core_config::reg_options(class OptionParser * opp)
                             "1");
     option_parser_register(opp, "-gpgpu_pipeline_widths", OPT_CSTR, &pipeline_widths_string,
                             "Pipeline widths "
-                            "ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE",
-                            "1,1,1,1,1,1,1,1,1,1,1" );
+                            "ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE",
+                            "1,1,1,1,1,1,1,1,1,1,1,1,1" );
     option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_INT32, &gpgpu_tensor_core_avail,
                             "Tensor Core Available (default=0)",
                             "0");
@@ -438,6 +447,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_num_dp_units", OPT_INT32, &gpgpu_num_dp_units,
                             "Number of DP units (default=0)",
                             "0");
+    option_parser_register(opp, "-gpgpu_num_int_units", OPT_INT32, &gpgpu_num_int_units,
+                            "Number of INT units (default=0)",
+                            "0");
     option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_INT32, &gpgpu_num_sfu_units,
                             "Number of SF units (default=1)",
                             "1");
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index c52ba35..12ea9d8 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -93,11 +93,14 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     if(m_config->sub_core_model) {
     	//in subcore model, each scheduler should has its own issue register, so num scheduler = reg width
     	assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SP].get_size() );
-    	if(m_config->gpgpu_num_dp_units > 0)
-    		assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_DP].get_size() );
     	assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SFU].get_size() );
     	assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_MEM].get_size() );
-    	assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_TENSOR_CORE].get_size() );
+    	if(m_config->gpgpu_tensor_core_avail)
+    		 assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_TENSOR_CORE].get_size() );
+    	if(m_config->gpgpu_num_dp_units > 0)
+    		assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_DP].get_size() );
+    	if(m_config->gpgpu_num_int_units > 0)
+    	    assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_INT].get_size() );
     }
     
     m_threadState = (thread_ctx_t*) calloc(sizeof(thread_ctx_t), config->n_thread_per_shader);
@@ -161,6 +164,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        &m_pipeline_reg[ID_OC_SP],
 									   &m_pipeline_reg[ID_OC_DP],
                                        &m_pipeline_reg[ID_OC_SFU],
+									   &m_pipeline_reg[ID_OC_INT],
                                        &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
                                        i
@@ -177,6 +181,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                                     &m_pipeline_reg[ID_OC_SP],
 													&m_pipeline_reg[ID_OC_DP],
                                                     &m_pipeline_reg[ID_OC_SFU],
+													&m_pipeline_reg[ID_OC_INT],
                                                     &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                                     &m_pipeline_reg[ID_OC_MEM],
                                                     i,
@@ -194,6 +199,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        &m_pipeline_reg[ID_OC_SP],
 									   &m_pipeline_reg[ID_OC_DP],
                                        &m_pipeline_reg[ID_OC_SFU],
+									   &m_pipeline_reg[ID_OC_INT],
                                        &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
                                        i
@@ -210,7 +216,8 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
 					  &m_pipeline_reg[ID_OC_SP],
 					  &m_pipeline_reg[ID_OC_DP],
 					  &m_pipeline_reg[ID_OC_SFU],
-                                       	  &m_pipeline_reg[ID_OC_TENSOR_CORE],
+					  &m_pipeline_reg[ID_OC_INT],
+                      &m_pipeline_reg[ID_OC_TENSOR_CORE],
 					  &m_pipeline_reg[ID_OC_MEM],
 					  i
 					 )
@@ -226,6 +233,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        &m_pipeline_reg[ID_OC_SP],
 									   &m_pipeline_reg[ID_OC_DP],
                                        &m_pipeline_reg[ID_OC_SFU],
+									   &m_pipeline_reg[ID_OC_INT],
                                        &m_pipeline_reg[ID_OC_TENSOR_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
                                        i,
@@ -248,7 +256,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     
     //op collector configuration
 
-	enum { SP_CUS, DP_CUS, SFU_CUS, TENSOR_CORE_CUS, MEM_CUS,  GEN_CUS };
+	enum { SP_CUS, DP_CUS, SFU_CUS, TENSOR_CORE_CUS, INT_CUS, MEM_CUS,  GEN_CUS };
 
     opndcoll_rfu_t::port_vector_t in_ports;
     opndcoll_rfu_t::port_vector_t out_ports;
@@ -260,16 +268,22 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_gen; i++) {
         in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
         in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
-        in_ports.push_back(&m_pipeline_reg[ID_OC_TENSOR_CORE]);
         in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_SP]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
-        out_ports.push_back(&m_pipeline_reg[OC_EX_TENSOR_CORE]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
+        if(m_config->gpgpu_tensor_core_avail) {
+        	in_ports.push_back(&m_pipeline_reg[ID_OC_TENSOR_CORE]);
+        	out_ports.push_back(&m_pipeline_reg[OC_EX_TENSOR_CORE]);
+        }
         if(m_config->gpgpu_num_dp_units > 0) {
 			in_ports.push_back(&m_pipeline_reg[ID_OC_DP]);
 			out_ports.push_back(&m_pipeline_reg[OC_EX_DP]);
         }
+        if(m_config->gpgpu_num_int_units > 0) {
+			in_ports.push_back(&m_pipeline_reg[ID_OC_INT]);
+			out_ports.push_back(&m_pipeline_reg[OC_EX_INT]);
+        }
         cu_sets.push_back((unsigned)GEN_CUS);
         m_operand_collector.add_port(in_ports,out_ports,cu_sets);
         in_ports.clear(),out_ports.clear(),cu_sets.clear();
@@ -281,6 +295,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
 	    m_operand_collector.add_cu_set(TENSOR_CORE_CUS, config->gpgpu_operand_collector_num_units_tensor_core, config->gpgpu_operand_collector_num_out_ports_tensor_core);
 	    m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu);
 		m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem);
+		m_operand_collector.add_cu_set(INT_CUS, m_config->gpgpu_operand_collector_num_units_int, m_config->gpgpu_operand_collector_num_out_ports_int);
 
 		for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sp; i++) {
 			in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
@@ -326,11 +341,20 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
 			m_operand_collector.add_port(in_ports,out_ports,cu_sets);
 			in_ports.clear(),out_ports.clear(),cu_sets.clear();
 		}
+
+		for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_int; i++) {
+			in_ports.push_back(&m_pipeline_reg[ID_OC_INT]);
+			out_ports.push_back(&m_pipeline_reg[OC_EX_INT]);
+			cu_sets.push_back((unsigned)INT_CUS);
+			cu_sets.push_back((unsigned)GEN_CUS);
+			m_operand_collector.add_port(in_ports,out_ports,cu_sets);
+			in_ports.clear(),out_ports.clear(),cu_sets.clear();
+		}
     }
     
     m_operand_collector.init( m_config->gpgpu_num_reg_banks, this );
     
-    m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_dp_units + m_config->gpgpu_num_sfu_units + m_config->gpgpu_num_tensor_core_units + 1; // sp_unit, sfu, ldst_unit
+    m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_dp_units + m_config->gpgpu_num_sfu_units + m_config->gpgpu_num_tensor_core_units + m_config->gpgpu_num_int_units + 1; // sp_unit, sfu, dp, tensor, int, ldst_unit
     //m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ];
     //m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ];
     
@@ -347,6 +371,11 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
             m_dispatch_port.push_back(ID_OC_DP);
             m_issue_port.push_back(OC_EX_DP);
         }
+    for (int k = 0; k < m_config->gpgpu_num_int_units; k++) {
+            m_fu.push_back(new int_unit( &m_pipeline_reg[EX_WB], m_config, this ));
+            m_dispatch_port.push_back(ID_OC_INT);
+            m_issue_port.push_back(OC_EX_INT);
+        }
 
     for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) {
         m_fu.push_back(new sfu( &m_pipeline_reg[EX_WB], m_config, this ));
@@ -359,6 +388,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
         m_dispatch_port.push_back(ID_OC_TENSOR_CORE);
         m_issue_port.push_back(OC_EX_TENSOR_CORE);
     }
+
     m_ldst_unit = new ldst_unit( m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, config, mem_config, stats, shader_id, tpc_id );
     m_fu.push_back(m_ldst_unit);
     m_dispatch_port.push_back(ID_OC_MEM);
@@ -958,8 +988,8 @@ void scheduler_unit::cycle()
         unsigned checked=0;
         unsigned issued=0;
         exec_unit_type_t previous_issued_inst_exec_type = exec_unit_type_t::NONE;
-	unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp;
-	bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units;
+        unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp;
+        bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units;  //In tis mode, we only allow dual issue to diff execution units (as in Maxwell and Pascal)
 
         while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) {
             const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst();
@@ -1008,33 +1038,62 @@ void scheduler_unit::cycle()
                             bool sfu_pipe_avail = m_sfu_out->has_free(m_shader->m_config->sub_core_model, m_id);
                             bool tensor_core_pipe_avail = m_tensor_core_out->has_free(m_shader->m_config->sub_core_model, m_id);
                             bool dp_pipe_avail = m_dp_out->has_free(m_shader->m_config->sub_core_model, m_id);
-                            if( sp_pipe_avail && (pI->op != TENSOR_CORE_OP) && (pI->op != SFU_OP && pI->op != DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SP)) {
-                                
-                                //Jin: special for CDP api
-                                if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) {
-                                    assert(warp(warp_id).m_cdp_latency == 0);
-                                    
-                                    extern unsigned cdp_latency[5];
-                                    if(pI->m_is_cdp == 1)
-                                        warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1];
-                                    else //cudaLaunchDeviceV2 and cudaGetParameterBufferV2
-                                        warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1]
-                                            + cdp_latency[pI->m_is_cdp] * active_mask.count();
-                                    warp(warp_id).m_cdp_dummy = true;
-                                    break;
-                                }
-                                else if(pI->m_is_cdp && warp(warp_id).m_cdp_dummy) {
-                                    assert(warp(warp_id).m_cdp_latency == 0);
-                                    warp(warp_id).m_cdp_dummy = false;
-                                }
+                            bool int_pipe_avail = m_int_out->has_free(m_shader->m_config->sub_core_model, m_id);
 
-                                // always prefer SP pipe for operations that can use both SP and SFU pipelines
-                                m_shader->issue_warp(*m_sp_out,pI,active_mask,warp_id,m_id);
-                                issued++;
-                                issued_inst=true;
-                                warp_inst_issued = true;
-                                previous_issued_inst_exec_type = exec_unit_type_t::SP;
-                            } else if ( (m_shader->m_config->gpgpu_num_dp_units != 0) && (pI->op == DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::DP)) {
+                            //This code need to be refactored
+                            if(pI->op != TENSOR_CORE_OP && pI->op != SFU_OP && pI->op != DP_OP) {
+                                
+									bool execute_on_SP = false;
+									bool execute_on_INT = false;
+
+									//if INT unit pipline exist, then execute ALU and INT operations on INT unit and SP-FPU on SP unit (like in Volta)
+									//if INT unit pipline does not exist, then execute all ALU, INT and SP operations on SP unit (as in Fermi, Pascal GPUs)
+									if(m_shader->m_config->gpgpu_num_int_units > 0 &&
+											int_pipe_avail &&
+											pI->op != SP_OP &&
+											!(diff_exec_units && previous_issued_inst_exec_type == exec_unit_type_t::INT))
+										execute_on_INT = true;
+									else if (sp_pipe_avail &&
+											(m_shader->m_config->gpgpu_num_int_units == 0 ||
+											(m_shader->m_config->gpgpu_num_int_units > 0 && pI->op == SP_OP)) &&
+											!(diff_exec_units && previous_issued_inst_exec_type == exec_unit_type_t::SP) )
+										execute_on_SP = true;
+
+
+									if(execute_on_INT || execute_on_SP) {
+										//Jin: special for CDP api
+										if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) {
+											assert(warp(warp_id).m_cdp_latency == 0);
+
+											extern unsigned cdp_latency[5];
+											if(pI->m_is_cdp == 1)
+												warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1];
+											else //cudaLaunchDeviceV2 and cudaGetParameterBufferV2
+												warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1]
+													+ cdp_latency[pI->m_is_cdp] * active_mask.count();
+											warp(warp_id).m_cdp_dummy = true;
+											break;
+										}
+										else if(pI->m_is_cdp && warp(warp_id).m_cdp_dummy) {
+											assert(warp(warp_id).m_cdp_latency == 0);
+											warp(warp_id).m_cdp_dummy = false;
+										}
+									}
+
+									if(execute_on_SP) {
+										m_shader->issue_warp(*m_sp_out,pI,active_mask,warp_id,m_id);
+										issued++;
+										issued_inst=true;
+										warp_inst_issued = true;
+										previous_issued_inst_exec_type = exec_unit_type_t::SP;
+									} else if (execute_on_INT) {
+										m_shader->issue_warp(*m_int_out,pI,active_mask,warp_id,m_id);
+										issued++;
+										issued_inst=true;
+										warp_inst_issued = true;
+										previous_issued_inst_exec_type = exec_unit_type_t::INT;
+                                   }
+                            } else if ( (m_shader->m_config->gpgpu_num_dp_units > 0) && (pI->op == DP_OP) && !(diff_exec_units && previous_issued_inst_exec_type == exec_unit_type_t::DP)) {
                                 if( dp_pipe_avail ) {
                                     m_shader->issue_warp(*m_dp_out,pI,active_mask,warp_id,m_id);
                                     issued++;
@@ -1042,8 +1101,8 @@ void scheduler_unit::cycle()
                                     warp_inst_issued = true;
                                     previous_issued_inst_exec_type = exec_unit_type_t::DP;
                                 }
-                            }  //If the DP units = 0 (like in Fermi archi), then change DP inst to SFU inst
-                            else if ( ((m_shader->m_config->gpgpu_num_dp_units == 0 && pI->op == DP_OP) || (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP)) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SFU)) {
+                            }  //If the DP units = 0 (like in Fermi archi), then execute DP inst on SFU unit
+                            else if ( ((m_shader->m_config->gpgpu_num_dp_units == 0 && pI->op == DP_OP) || (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP)) && !(diff_exec_units && previous_issued_inst_exec_type == exec_unit_type_t::SFU)) {
                                 if( sfu_pipe_avail ) {
                                     m_shader->issue_warp(*m_sfu_out,pI,active_mask,warp_id,m_id);
                                     issued++;
@@ -1052,12 +1111,13 @@ void scheduler_unit::cycle()
                                     previous_issued_inst_exec_type = exec_unit_type_t::SFU;
                                 }
                             }                         
-                             else if ( (pI->op == TENSOR_CORE_OP) ) {
+                             else if ( (pI->op == TENSOR_CORE_OP) && !(diff_exec_units && previous_issued_inst_exec_type == exec_unit_type_t::SP) ) {
                                 if( tensor_core_pipe_avail ) {
                                     m_shader->issue_warp(*m_tensor_core_out,pI,active_mask,warp_id,m_id);
                                     issued++;
                                     issued_inst=true;
                                     warp_inst_issued = true;
+                                    previous_issued_inst_exec_type = exec_unit_type_t::TENSOR;
                                 }
 			    }
                          }//end of else
@@ -1245,11 +1305,12 @@ swl_scheduler::swl_scheduler ( shader_core_stats* stats, shader_core_ctx* shader
                                register_set* sp_out,
 							   register_set* dp_out,
                                register_set* sfu_out,
+							   register_set* int_out,
                                register_set* tensor_core_out,
                                register_set* mem_out,
                                int id,
                                char* config_string )
-    : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id )
+    : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, int_out, tensor_core_out, mem_out, id )
 {
     unsigned m_prioritization_readin;
     int ret = sscanf( config_string,
@@ -1822,6 +1883,7 @@ void ldst_unit::active_lanes_in_pipeline(){
 	assert(active_count<=m_core->get_config()->warp_size);
 	m_core->incfumemactivelanes_stat(active_count);
 }
+
 void sp_unit::active_lanes_in_pipeline(){
 	unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
 	assert(active_count<=m_core->get_config()->warp_size);
@@ -1837,6 +1899,13 @@ void dp_unit::active_lanes_in_pipeline(){
 	m_core->incfumemactivelanes_stat(active_count);
 }
 
+void int_unit::active_lanes_in_pipeline(){
+	unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
+	assert(active_count<=m_core->get_config()->warp_size);
+	m_core->incspactivelanes_stat(active_count);
+	m_core->incfuactivelanes_stat(active_count);
+	m_core->incfumemactivelanes_stat(active_count);
+}
 void sfu::active_lanes_in_pipeline(){
 	unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
 	assert(active_count<=m_core->get_config()->warp_size);
@@ -1866,6 +1935,12 @@ dp_unit::dp_unit( register_set* result_port, const shader_core_config *config,sh
     m_name = "DP ";
 }
 
+int_unit::int_unit( register_set* result_port, const shader_core_config *config,shader_core_ctx *core)
+    : pipelined_simd_unit(result_port,config,config->max_sp_latency,core)
+{
+    m_name = "INT ";
+}
+
 void sp_unit :: issue(register_set& source_reg)
 {
     warp_inst_t** ready_reg = source_reg.get_ready();
@@ -1884,6 +1959,15 @@ void dp_unit :: issue(register_set& source_reg)
 	pipelined_simd_unit::issue(source_reg);
 }
 
+void int_unit :: issue(register_set& source_reg)
+{
+    warp_inst_t** ready_reg = source_reg.get_ready();
+	//m_core->incexecstat((*ready_reg));
+	(*ready_reg)->op_pipe=INTP__OP;
+	m_core->incsp_stat(m_core->get_config()->warp_size,(*ready_reg)->latency);
+	pipelined_simd_unit::issue(source_reg);
+}
+
 pipelined_simd_unit::pipelined_simd_unit( register_set* result_port, const shader_core_config *config, unsigned max_latency,shader_core_ctx *core )
     : simd_function_unit(config) 
 {
@@ -2006,6 +2090,7 @@ ldst_unit::ldst_unit( mem_fetch_interface *icnt,
         		l1_latency_queue.push_back((mem_fetch*)NULL);
 	    }
     }
+    m_name = "MEM ";
 }
 
 ldst_unit::ldst_unit( mem_fetch_interface *icnt,
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 7b33c14..45cf8e4 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -76,7 +76,9 @@ enum exec_unit_type_t
   SP = 1,
   SFU = 2,
   MEM = 3,
-  DP = 4
+  DP = 4,
+  INT = 5,
+  TENSOR = 6
 };
 
 class thread_ctx_t {
@@ -328,12 +330,13 @@ public:
                    register_set* sp_out,
 				   register_set* dp_out,
                    register_set* sfu_out,
+				   register_set* int_out,
                    register_set* tensor_core_out,
                    register_set* mem_out,
                    int id) 
         : m_supervised_warps(), m_stats(stats), m_shader(shader),
         m_scoreboard(scoreboard), m_simt_stack(simt), /*m_pipeline_reg(pipe_regs),*/ m_warp(warp),
-        m_sp_out(sp_out),m_dp_out(dp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){}
+        m_sp_out(sp_out),m_dp_out(dp_out),m_sfu_out(sfu_out),m_int_out(int_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){}
     virtual ~scheduler_unit(){}
     virtual void add_supervised_warp_id(int i) {
         m_supervised_warps.push_back(&warp(i));
@@ -409,6 +412,7 @@ protected:
     register_set* m_sp_out;
     register_set* m_dp_out;
     register_set* m_sfu_out;
+    register_set* m_int_out;
     register_set* m_tensor_core_out;
     register_set* m_mem_out;
 
@@ -423,10 +427,11 @@ public:
                     register_set* sp_out,
 					register_set* dp_out,
                     register_set* sfu_out,
+					register_set* int_out,
                     register_set* tensor_core_out,
                     register_set* mem_out,
                     int id )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){}
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, int_out, tensor_core_out, mem_out, id ){}
 	virtual ~lrr_scheduler () {}
 	virtual void order_warps ();
     virtual void done_adding_supervised_warps() {
@@ -442,10 +447,11 @@ public:
                     register_set* sp_out,
 					register_set* dp_out,
                     register_set* sfu_out,
+					register_set* int_out,
                     register_set* tensor_core_out,
                     register_set* mem_out,
                     int id )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){}
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, int_out, tensor_core_out, mem_out, id ){}
 	virtual ~gto_scheduler () {}
 	virtual void order_warps ();
     virtual void done_adding_supervised_warps() {
@@ -462,10 +468,11 @@ public:
                     register_set* sp_out,
 					register_set* dp_out,
                     register_set* sfu_out,
-                          register_set* tensor_core_out,
+					register_set* int_out,
+                    register_set* tensor_core_out,
                     register_set* mem_out,
                     int id )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){}
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, int_out, tensor_core_out, mem_out, id ){}
 	virtual ~oldest_scheduler () {}
 	virtual void order_warps ();
         virtual void done_adding_supervised_warps() {
@@ -482,11 +489,12 @@ public:
                           register_set* sp_out,
 						  register_set* dp_out,
                           register_set* sfu_out,
+						  register_set* int_out,
                           register_set* tensor_core_out,
                           register_set* mem_out,
                           int id,
                           char* config_str )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ),
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, int_out, tensor_core_out, mem_out, id ),
 	  m_pending_warps() 
     {
         unsigned inner_level_readin;
@@ -534,6 +542,7 @@ public:
                     register_set* sp_out,
 					register_set* dp_out,
                     register_set* sfu_out,
+					register_set* int_out,
                     register_set* tensor_core_out,
                     register_set* mem_out,
                     int id,
@@ -1046,6 +1055,9 @@ public:
         fprintf(fp,"%s dispatch= ", m_name.c_str() );
         m_dispatch_reg->print(fp);
     }
+    const char* get_name() {
+    	return m_name.c_str();
+    }
 protected:
     std::string m_name;
     const shader_core_config *m_config;
@@ -1154,6 +1166,29 @@ public:
 };
 
 
+class int_unit : public pipelined_simd_unit
+{
+public:
+	int_unit( register_set* result_port, const shader_core_config *config, shader_core_ctx *core );
+    virtual bool can_issue( const warp_inst_t &inst ) const
+    {
+        switch(inst.op) {
+        case SFU_OP: return false;
+	    case LOAD_OP: return false;
+	    case TENSOR_CORE_LOAD_OP: return false;
+		case STORE_OP: return false;
+		case TENSOR_CORE_STORE_OP: return false;
+		case MEMORY_BARRIER_OP: return false;
+	    case SP_OP: return false;
+	    case DP_OP: return false;
+        default: break;
+        }
+        return pipelined_simd_unit::can_issue(inst);
+    }
+    virtual void active_lanes_in_pipeline();
+    virtual void issue(  register_set& source_reg );
+};
+
 class sp_unit : public pipelined_simd_unit
 {
 public:
@@ -1303,10 +1338,12 @@ protected:
 enum pipeline_stage_name_t {
     ID_OC_SP=0,
 	ID_OC_DP,
+	ID_OC_INT,
     ID_OC_SFU,  
     ID_OC_MEM,  
     OC_EX_SP,
 	OC_EX_DP,
+	OC_EX_INT,
     OC_EX_SFU,
     OC_EX_MEM,
     EX_WB,
@@ -1318,10 +1355,12 @@ enum pipeline_stage_name_t {
 const char* const pipeline_stage_name_decode[] = {
     "ID_OC_SP",
 	"ID_OC_DP",
+	"ID_OC_INT",
     "ID_OC_SFU",  
     "ID_OC_MEM",  
     "OC_EX_SP",
 	"OC_EX_DP",
+	"OC_EX_INT",
     "OC_EX_SFU",
     "OC_EX_MEM",
     "EX_WB",
@@ -1429,6 +1468,7 @@ struct shader_core_config : public core_config
     int gpgpu_operand_collector_num_units_tensor_core;
     int gpgpu_operand_collector_num_units_mem;
     int gpgpu_operand_collector_num_units_gen;
+    int gpgpu_operand_collector_num_units_int;
 
     unsigned int gpgpu_operand_collector_num_in_ports_sp;
     unsigned int gpgpu_operand_collector_num_in_ports_dp;
@@ -1436,6 +1476,7 @@ struct shader_core_config : public core_config
     unsigned int gpgpu_operand_collector_num_in_ports_tensor_core;
     unsigned int gpgpu_operand_collector_num_in_ports_mem;
     unsigned int gpgpu_operand_collector_num_in_ports_gen;
+    unsigned int gpgpu_operand_collector_num_in_ports_int;
 
     unsigned int gpgpu_operand_collector_num_out_ports_sp;
     unsigned int gpgpu_operand_collector_num_out_ports_dp;
@@ -1443,6 +1484,7 @@ struct shader_core_config : public core_config
     unsigned int gpgpu_operand_collector_num_out_ports_tensor_core;
     unsigned int gpgpu_operand_collector_num_out_ports_mem;
     unsigned int gpgpu_operand_collector_num_out_ports_gen;
+    unsigned int gpgpu_operand_collector_num_out_ports_int;
 
     int gpgpu_num_sp_units;
     int gpgpu_tensor_core_avail;
@@ -1450,6 +1492,7 @@ struct shader_core_config : public core_config
     int gpgpu_num_sfu_units;
     int gpgpu_num_tensor_core_units;
     int gpgpu_num_mem_units;
+    int gpgpu_num_int_units;
 
     //Shader core resources
     unsigned gpgpu_shader_registers;
-- 
cgit v1.3


From 72c30bd7a251081eb7453ff4706ddcda30c744ac Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Fri, 9 Nov 2018 19:16:35 -0500
Subject: disable sub_core_model for now

---
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index e143f31..8ed4cd0 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -104,7 +104,7 @@
 
 # Volta has sub core model, in which each scheduler has its own reisiter file and EUs
 # i.e. schedulers are isolated
--sub_core_model 1
+-sub_core_model 0
 # disable specialized operand collectors and use generic operand collectors instead
 -enable_specialized_operand_collector 0
 -gpgpu_operand_collector_num_units_gen 8
-- 
cgit v1.3


From 5147dae0dfd32d4cbf71379d3504ce7b718712ec Mon Sep 17 00:00:00 2001
From: Rohan Mahapatra <rmahapatra@wisc.edu>
Date: Mon, 14 Jan 2019 12:48:57 -0600
Subject: Updated GTX1080 config file to conform to recent changes with
 TensorCore pipeline stages and cache configuration.

---
 configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

(limited to 'configs')

diff --git a/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
index fb044c6..3261d5a 100644
--- a/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
+++ b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
@@ -31,12 +31,14 @@
 -gpgpu_simd_model 1 
 
 # Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+# ID_OC_SP, ID_OC_DP, ID_OC_INT, ID_OC_SFU, ID_OC_MEM, OC_EX_SP, OC_EX_DP, OC_EX_INT, OC_EX_SFU, OC_EX_MEM, EX_WB
 ## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_pipeline_widths 4,0,0,1,1,4,0,0,1,1,6
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 1
+-gpgpu_tensor_core_avail 0
+-gpgpu_num_tensor_core_units 0
 
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
@@ -54,20 +56,20 @@
 # Pascal GP102 has 96KB Shared memory
 # Pascal GP102 has 64KB L1 cache
 # The default is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,8
+-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,A:128:8,8
 -gpgpu_shmem_size 98304
 -gmem_skip_L1D 1
 
 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
+-gpgpu_cache:dl2 N:64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
 -gpgpu_cache:dl2_texture_only 0 
 
 # 4 KB Inst.
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,A:2:48,4
 # 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
 # 12 KB Const
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,A:2:64,4
 
 # enable operand collector 
 ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
-- 
cgit v1.3


From 7baae0e937143e0acfc71382eb432bdc42d4ca41 Mon Sep 17 00:00:00 2001
From: Nick <CoffeeBeforeArch@gmail.com>
Date: Mon, 18 Feb 2019 11:21:14 -0500
Subject: Fix spelling from adpative -> adaptive for volta cache config

---
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +-
 src/gpgpu-sim/gpu-sim.cc                       | 4 ++--
 src/gpgpu-sim/shader.cc                        | 2 +-
 src/gpgpu-sim/shader.h                         | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 8ed4cd0..b283095 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -75,7 +75,7 @@
 # if the assigned shd mem = 0, then L1 cache = 128KB
 # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
 # disable this mode in case of multi kernels/apps execution
--adpative_volta_cache_config 1
+-adaptive_volta_cache_config 1
 # Volta unified cache has four ports
 -mem_unit_ports 4
 -gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index ec570bf..abc2dd6 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -315,8 +315,8 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size,
                  "Size of shared memory per shader core (default 16kB)",
                  "16384");
-    option_parser_register(opp, "-adpative_volta_cache_config", OPT_BOOL, &adpative_volta_cache_config,
-                 "adpative_volta_cache_config",
+    option_parser_register(opp, "-adaptive_volta_cache_config", OPT_BOOL, &adaptive_volta_cache_config,
+                 "adaptive_volta_cache_config",
                  "0");
     option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_sizeDefault,
                  "Size of shared memory per shader core (default 16kB)",
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 3db988b..2cecd0c 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -2949,7 +2949,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const
        abort();
     }
 
-    if(adpative_volta_cache_config && !k.volta_cache_config_set) {
+    if(adaptive_volta_cache_config && !k.volta_cache_config_set) {
     	//For Volta, we assign the remaining shared memory to L1 cache
     	//For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
     	unsigned total_shmed = kernel_info->smem * result;
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 9abd223..473d6b0 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1523,7 +1523,7 @@ struct shader_core_config : public core_config
     //Jin: concurrent kernel on sm
     bool gpgpu_concurrent_kernel_sm;
 
-    bool adpative_volta_cache_config;
+    bool adaptive_volta_cache_config;
 };
 
 struct shader_core_stats_pod {
-- 
cgit v1.3


From bb7ed349e146ea6b9ef1100d81fa7ac5ef2751cb Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Thu, 11 Apr 2019 19:53:23 -0400
Subject: adding local xbar and fast execution mode

---
 .../SM7_TITANV_fastlocalxbar/gpgpusim.config       | 192 ++++++++++++++
 src/cuda-sim/cuda-sim.h                            |   2 +
 src/gpgpu-sim/gpu-sim.cc                           |   4 +
 src/gpgpu-sim/icnt_wrapper.cc                      |  90 ++++++-
 src/gpgpu-sim/icnt_wrapper.h                       |   5 +-
 src/gpgpu-sim/local_interconnect.cc                | 277 +++++++++++++++++++++
 src/gpgpu-sim/local_interconnect.h                 | 116 +++++++++
 src/gpgpu-sim/shader.cc                            |  78 +++++-
 src/gpgpu-sim/shader.h                             |  26 +-
 src/gpgpusim_entrypoint.cc                         |   6 +-
 10 files changed, 773 insertions(+), 23 deletions(-)
 create mode 100644 configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
 create mode 100644 src/gpgpu-sim/local_interconnect.cc
 create mode 100644 src/gpgpu-sim/local_interconnect.h

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
new file mode 100644
index 0000000..73516e1
--- /dev/null
+++ b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
@@ -0,0 +1,192 @@
+# This config models the Volta Titan X
+# For more info about volta architecture:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 24
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA V100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:1455.0:1455.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 70
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
+## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+-gpgpu_num_int_units 4
+-gpgpu_tensor_core_avail 1
+-gpgpu_num_tensor_core_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+-ptx_opcode_latency_tesnor 64
+-ptx_opcode_initiation_tensor 64
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+# Volta unified cache has four ports
+-mem_unit_ports 4
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+-gpgpu_flush_l1_cache 1
+
+# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
+-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 1
+-memory_partition_indexing 0
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 0
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
+-gpgpu_num_reg_banks 8
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Volta, a warp scheduler can issue 1 inst per cycle
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 2 
+-inter_config_file config_fermi_islip.icnt
+-inct_in_buffer_limit 512
+-inct_out_buffer_limit 512
+-inct_subnets 2
+-fast_execution_mode 1
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 100
+-power_simulation_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/src/cuda-sim/cuda-sim.h b/src/cuda-sim/cuda-sim.h
index abd32f9..e690356 100644
--- a/src/cuda-sim/cuda-sim.h
+++ b/src/cuda-sim/cuda-sim.h
@@ -47,6 +47,8 @@ extern int g_debug_thread_uid;
 extern void ** g_inst_classification_stat;
 extern void ** g_inst_op_classification_stat;
 extern int g_ptx_kernel_count; // used for classification stat collection purposes 
+extern char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp,*opcode_latency_sfu,*opcode_latency_tensor;
+
 
 void ptx_opcocde_latency_options (option_parser_t opp);
 extern class kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry,
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index ec570bf..81d9b69 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -476,6 +476,10 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_concurrent_kernel_sm", OPT_BOOL, &gpgpu_concurrent_kernel_sm, 
                 "Support concurrent kernels on a SM (default = disabled)", 
                 "0");
+
+    option_parser_register(opp, "-fast_execution_mode", OPT_BOOL, &fast_execution_mode,
+                "fast_execution_mode (default = disabled)",
+                "0");
 }
 
 void gpgpu_sim_config::reg_options(option_parser_t opp)
diff --git a/src/gpgpu-sim/icnt_wrapper.cc b/src/gpgpu-sim/icnt_wrapper.cc
index ee58ece..075e371 100644
--- a/src/gpgpu-sim/icnt_wrapper.cc
+++ b/src/gpgpu-sim/icnt_wrapper.cc
@@ -29,6 +29,8 @@
 #include <assert.h>
 #include "../intersim2/globals.hpp"
 #include "../intersim2/interconnect_interface.hpp"
+#include "local_interconnect.h"
+
 
 icnt_create_p                icnt_create;
 icnt_init_p                  icnt_init;
@@ -42,9 +44,13 @@ icnt_display_overall_stats_p icnt_display_overall_stats;
 icnt_display_state_p         icnt_display_state;
 icnt_get_flit_size_p         icnt_get_flit_size;
 
-int   g_network_mode;
+unsigned   g_network_mode;
 char* g_network_config_filename;
 
+
+struct inct_config g_inct_config;
+LocalInterconnect *g_localicnt_interface;
+
 #include "../option_parser.h"
 
 // Wrapper to intersim2 to accompany old icnt_wrapper
@@ -105,10 +111,78 @@ static unsigned intersim2_get_flit_size()
    return g_icnt_interface->GetFlitSize();
 }
 
+
+//////////////////////////////////////////////////////
+
+static void LocalInterconnect_create(unsigned int n_shader, unsigned int n_mem)
+{
+	g_localicnt_interface->CreateInterconnect(n_shader, n_mem);
+}
+
+static void LocalInterconnect_init()
+{
+	g_localicnt_interface->Init();
+}
+
+static bool LocalInterconnect_has_buffer(unsigned input, unsigned int size)
+{
+   return g_localicnt_interface->HasBuffer(input, size);
+}
+
+static void LocalInterconnect_push(unsigned input, unsigned output, void* data, unsigned int size)
+{
+	g_localicnt_interface->Push(input, output, data, size);
+}
+
+static void* LocalInterconnect_pop(unsigned output)
+{
+   return g_localicnt_interface->Pop(output);
+}
+
+static void LocalInterconnect_transfer()
+{
+	g_localicnt_interface->Advance();
+}
+
+static bool LocalInterconnect_busy()
+{
+   return g_localicnt_interface->Busy();
+}
+
+static void LocalInterconnect_display_stats()
+{
+	g_localicnt_interface->DisplayStats();
+}
+
+static void LocalInterconnect_display_overall_stats()
+{
+	g_localicnt_interface->DisplayOverallStats();
+}
+
+static void LocalInterconnect_display_state(FILE *fp)
+{
+	g_localicnt_interface->DisplayState(fp);
+}
+
+static unsigned LocalInterconnect_get_flit_size()
+{
+   return g_localicnt_interface->GetFlitSize();
+}
+
+
+///////////////////////////
+
 void icnt_reg_options( class OptionParser * opp )
 {
    option_parser_register(opp, "-network_mode", OPT_INT32, &g_network_mode, "Interconnection network mode", "1");
    option_parser_register(opp, "-inter_config_file", OPT_CSTR, &g_network_config_filename, "Interconnection network config file", "mesh");
+
+
+   //parameters for local xbar
+   option_parser_register(opp, "-inct_in_buffer_limit", OPT_UINT32, &g_inct_config.in_buffer_limit, "in_buffer_limit", "64");
+   option_parser_register(opp, "-inct_out_buffer_limit", OPT_UINT32, &g_inct_config.out_buffer_limit, "out_buffer_limit", "64");
+   option_parser_register(opp, "-inct_subnets", OPT_UINT32, &g_inct_config.subnets, "subnets", "2");
+
 }
 
 void icnt_wrapper_init()
@@ -129,6 +203,20 @@ void icnt_wrapper_init()
          icnt_display_state = intersim2_display_state;
          icnt_get_flit_size = intersim2_get_flit_size;
          break;
+      case LOCAL_XBAR:
+    	  g_localicnt_interface = LocalInterconnect::New(g_inct_config);
+		  icnt_create     = LocalInterconnect_create;
+		  icnt_init       = LocalInterconnect_init;
+		  icnt_has_buffer = LocalInterconnect_has_buffer;
+		  icnt_push       = LocalInterconnect_push;
+		  icnt_pop        = LocalInterconnect_pop;
+		  icnt_transfer   = LocalInterconnect_transfer;
+		  icnt_busy       = LocalInterconnect_busy;
+		  icnt_display_stats = LocalInterconnect_display_stats;
+		  icnt_display_overall_stats = LocalInterconnect_display_overall_stats;
+		  icnt_display_state = LocalInterconnect_display_state;
+		  icnt_get_flit_size = LocalInterconnect_get_flit_size;
+		  break;
       default:
          assert(0);
          break;
diff --git a/src/gpgpu-sim/icnt_wrapper.h b/src/gpgpu-sim/icnt_wrapper.h
index a4d123e..e1086f9 100644
--- a/src/gpgpu-sim/icnt_wrapper.h
+++ b/src/gpgpu-sim/icnt_wrapper.h
@@ -57,13 +57,16 @@ extern icnt_display_stats_p icnt_display_stats;
 extern icnt_display_overall_stats_p icnt_display_overall_stats;
 extern icnt_display_state_p icnt_display_state;
 extern icnt_get_flit_size_p icnt_get_flit_size;
-extern int g_network_mode;
+extern unsigned g_network_mode;
 
 enum network_mode {
    INTERSIM = 1,
+   LOCAL_XBAR = 2,
    N_NETWORK_MODE
 };
 
+
+
 void icnt_wrapper_init();
 void icnt_reg_options( class OptionParser * opp );
 
diff --git a/src/gpgpu-sim/local_interconnect.cc b/src/gpgpu-sim/local_interconnect.cc
new file mode 100644
index 0000000..1d93fe6
--- /dev/null
+++ b/src/gpgpu-sim/local_interconnect.cc
@@ -0,0 +1,277 @@
+// Copyright (c) 2009-2013, Tor M. Aamodt, Dongdong Li, Ali Bakhoda
+// The University of British Columbia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice, this
+// list of conditions and the following disclaimer.
+// Redistributions in binary form must reproduce the above copyright notice, this
+// list of conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution.
+// Neither the name of The University of British Columbia nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include <fstream>
+#include <iostream>
+#include <sstream>
+#include <iomanip>
+#include <cmath>
+#include <utility>
+#include <algorithm>
+
+#include "local_interconnect.h"
+#include "mem_fetch.h"
+
+xbar_router::xbar_router(unsigned router_id, unsigned n_shader, unsigned n_mem, unsigned m_in_buffer_limit, unsigned m_out_buffer_limit)
+{
+	m_id=router_id;
+   _n_mem = n_mem;
+   _n_shader = n_shader;
+   total_nodes = n_shader+n_mem;
+   in_buffers.resize(total_nodes);
+   out_buffers.resize(total_nodes);
+   next_node=0;
+   in_buffer_limit = m_in_buffer_limit;
+   out_buffer_limit = m_out_buffer_limit;
+
+   cycles = 0;
+   conflicts= 0;
+   out_buffer_full=0;
+   packets_num=0;
+}
+
+
+xbar_router::~xbar_router()
+{
+
+}
+
+void xbar_router::Push(unsigned input_deviceID, unsigned output_deviceID, void* data, unsigned int size)
+{
+	assert(input_deviceID < total_nodes);
+	in_buffers[input_deviceID].push(Packet(data, output_deviceID));
+	packets_num++;
+}
+
+void* xbar_router::Pop(unsigned ouput_deviceID)
+{
+	assert(ouput_deviceID < total_nodes);
+	void* data = NULL;
+
+	if(!out_buffers[ouput_deviceID].empty()) {
+		data = out_buffers[ouput_deviceID].front().data;
+		out_buffers[ouput_deviceID].pop();
+	}
+
+	return data;
+}
+
+
+bool xbar_router::Has_Buffer_In(unsigned input_deviceID, unsigned size) const{
+
+	assert(input_deviceID < total_nodes);
+	return (in_buffers[input_deviceID].size() + size <= in_buffer_limit);
+
+}
+
+bool xbar_router::Has_Buffer_Out(unsigned output_deviceID, unsigned size) const{
+	return (out_buffers[output_deviceID].size() + size <= out_buffer_limit);
+}
+
+void xbar_router::Advance() {
+	cycles++;
+
+	vector<bool> issued(total_nodes, false);
+
+	for(unsigned i=0; i<total_nodes; ++i){
+		unsigned node_id = (i+next_node)%total_nodes;
+
+		if(!in_buffers[node_id].empty()) {
+			Packet _packet = in_buffers[node_id].front();
+			//ensure that the outbuffer has space and not issued before in this cycle
+			if(Has_Buffer_Out(_packet.output_deviceID, 1)){
+				if(!issued[_packet.output_deviceID]) {
+					out_buffers[_packet.output_deviceID].push(_packet);
+					in_buffers[node_id].pop();
+					issued[_packet.output_deviceID]=true;
+				}
+				else
+					conflicts++;
+			}
+			else
+				out_buffer_full++;
+		}
+	}
+
+	next_node = (++next_node % total_nodes);
+}
+
+bool xbar_router::Busy() const {
+
+	for(unsigned i=0; i<total_nodes; ++i){
+		if(!in_buffers[i].empty())
+			return true;
+
+		if(!out_buffers[i].empty())
+			return true;
+	}
+	return false;
+}
+
+
+////////////////////////////////////////////////////
+/////////////LocalInterconnect/////////////////////
+
+//assume all the packets are one flit
+#define LOCAL_INCT_FLIT_SIZE 40
+
+LocalInterconnect* LocalInterconnect::New(const struct inct_config& m_localinct_config)
+{
+
+  LocalInterconnect* icnt_interface = new LocalInterconnect(m_localinct_config);
+
+  return icnt_interface;
+}
+
+LocalInterconnect::LocalInterconnect(const struct inct_config& m_localinct_config): m_inct_config(m_localinct_config)
+{
+	n_shader=0;
+	n_mem=0;
+	n_subnets = m_localinct_config.subnets;
+
+}
+
+LocalInterconnect::~LocalInterconnect()
+{
+  for (int i=0; i<m_inct_config.subnets; ++i) {
+    delete net[i];
+  }
+}
+
+void LocalInterconnect::CreateInterconnect(unsigned m_n_shader, unsigned m_n_mem)
+{
+  n_shader = m_n_shader;
+  n_mem = m_n_mem;
+
+  net.resize(n_subnets);
+  for (unsigned i = 0; i < n_subnets; ++i) {
+    net[i] = new xbar_router( i, m_n_shader, m_n_mem, m_inct_config.in_buffer_limit, m_inct_config.out_buffer_limit );
+  }
+
+}
+
+
+void LocalInterconnect::Init() {
+
+	//empty
+	//there is nothing to do
+
+}
+
+void LocalInterconnect::Push(unsigned input_deviceID, unsigned output_deviceID, void* data, unsigned int size){
+
+	unsigned subnet;
+	  if (n_subnets == 1) {
+		subnet = 0;
+	  } else {
+		if (input_deviceID < n_shader ) {
+		  subnet = 0;
+		} else {
+		  subnet = 1;
+		}
+	  }
+
+	 // it should have free buffer
+	  //assume all the packets have size of one
+	  //no flits are implemented
+	  assert(net[subnet]->Has_Buffer_In(input_deviceID, 1));
+
+	  net[subnet]->Push(input_deviceID, output_deviceID, data, size);
+
+}
+
+void* LocalInterconnect::Pop(unsigned ouput_deviceID){
+
+	// 0-_n_shader-1 indicates reply(network 1), otherwise request(network 0)
+	  int subnet = 0;
+	  if (ouput_deviceID < n_shader)
+	    subnet = 1;
+
+	  return net[subnet]->Pop(ouput_deviceID);
+
+}
+
+void LocalInterconnect::Advance(){
+
+	for (unsigned i = 0; i < n_subnets; ++i) {
+	    net[i]->Advance();
+	  }
+
+}
+
+bool  LocalInterconnect::Busy() const{
+
+	for (unsigned i = 0; i < n_subnets; ++i) {
+		 if(net[i]->Busy())
+			 return true;
+	}
+	return false;
+}
+
+bool  LocalInterconnect::HasBuffer(unsigned deviceID, unsigned int size) const{
+
+	 bool has_buffer = false;
+
+	 has_buffer = net[0]->Has_Buffer_In(deviceID, size);
+
+	  if ((n_subnets>1) && deviceID >= n_shader) // deviceID is memory node
+			 has_buffer = net[1]->Has_Buffer_In(deviceID, size);
+
+	  return has_buffer;
+
+}
+
+void  LocalInterconnect::DisplayStats() const{
+
+	cout<<"Req_Network_injected_packets_num = "<<net[0]->packets_num<<endl;
+	cout<<"Req_Network_cycles = "<<net[0]->cycles<<endl;
+	cout<<"Req_Network_injected_packets_per_cycle = "<<(float)(net[0]->packets_num) / (net[0]->cycles)<<endl;
+	cout<<"Req_Network_conflicts_per_cycle = "<<(float)(net[0]->conflicts) / (net[0]->cycles)<<endl;
+	cout<<"Req_Network_out_buffer_full_per_cycle = "<<(float)(net[0]->out_buffer_full) / (net[0]->cycles)<<endl;
+
+	cout<<endl;
+	cout<<"Reply_Network_injected_packets_num = "<<net[1]->packets_num<<endl;
+	cout<<"ReplyNetwork_cycles = "<<net[1]->cycles<<endl;
+	cout<<"ReplyNetwork_injected_packets_per_cycle = "<<(float)(net[1]->packets_num) / (net[1]->cycles)<<endl;
+	cout<<"ReplyNetwork_conflicts_per_cycle = "<<(float)(net[1]->conflicts) / (net[1]->cycles)<<endl;
+	cout<<"ReplyNetwork_out_buffer_full_per_cycle = "<<(float)(net[1]->out_buffer_full) / (net[1]->cycles)<<endl;
+
+}
+
+void  LocalInterconnect::DisplayOverallStats() const{
+
+}
+
+unsigned  LocalInterconnect::GetFlitSize() const{
+	return LOCAL_INCT_FLIT_SIZE;
+}
+
+void  LocalInterconnect::DisplayState(FILE* fp) const{
+
+	  fprintf(fp, "GPGPU-Sim uArch: ICNT:Display State: Under implementation\n");
+}
+
diff --git a/src/gpgpu-sim/local_interconnect.h b/src/gpgpu-sim/local_interconnect.h
new file mode 100644
index 0000000..727a782
--- /dev/null
+++ b/src/gpgpu-sim/local_interconnect.h
@@ -0,0 +1,116 @@
+// Copyright (c) 2009-2013, Tor M. Aamodt, Dongdong Li, Ali Bakhoda
+// The University of British Columbia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice, this
+// list of conditions and the following disclaimer.
+// Redistributions in binary form must reproduce the above copyright notice, this
+// list of conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution.
+// Neither the name of The University of British Columbia nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#ifndef _LOCAL_INTERCONNECT_HPP_
+#define _LOCAL_INTERCONNECT_HPP_
+
+#include <vector>
+#include <queue>
+#include <iostream>
+#include <map>
+using namespace std;
+
+
+struct inct_config
+{
+
+	//config for local interconnect
+	unsigned   in_buffer_limit;
+	unsigned   out_buffer_limit;
+	unsigned   subnets;
+};
+
+class xbar_router {
+
+public:
+  xbar_router(unsigned router_id, unsigned n_shader, unsigned n_mem, unsigned m_in_buffer_limit, unsigned m_out_buffer_limit);
+  ~xbar_router();
+   void Push(unsigned input_deviceID, unsigned output_deviceID, void* data, unsigned int size);
+   void* Pop(unsigned ouput_deviceID);
+   void Advance();
+   bool Busy() const;
+   bool Has_Buffer_In(unsigned input_deviceID, unsigned size) const;
+   bool Has_Buffer_Out(unsigned output_deviceID, unsigned size) const;
+
+   //some stats
+   unsigned long long cycles;
+   unsigned long long conflicts;
+   unsigned long long out_buffer_full;
+   unsigned long long packets_num;
+
+private:
+  struct Packet{
+	  Packet(void* m_data, unsigned m_output_deviceID) {
+		  data = m_data;
+		  output_deviceID = m_output_deviceID;
+	  }
+	  void* data;
+	  unsigned output_deviceID;
+  };
+  vector<queue<Packet> > in_buffers;
+  vector<queue<Packet> > out_buffers;
+  unsigned _n_shader, _n_mem, total_nodes;
+  unsigned in_buffer_limit, out_buffer_limit;
+  unsigned next_node;
+  unsigned m_id;
+
+};
+
+class LocalInterconnect {
+public:
+  LocalInterconnect(const struct inct_config& m_localinct_config);
+  ~LocalInterconnect();
+  static LocalInterconnect* New(const struct inct_config& m_inct_config);
+  void CreateInterconnect(unsigned n_shader, unsigned n_mem);
+  
+  //node side functions
+  void Init();
+  void Push(unsigned input_deviceID, unsigned output_deviceID, void* data, unsigned int size);
+  void* Pop(unsigned ouput_deviceID);
+  void Advance();
+  bool Busy() const;
+  bool HasBuffer(unsigned deviceID, unsigned int size) const;
+  void DisplayStats() const;
+  void DisplayOverallStats() const;
+  unsigned GetFlitSize() const;
+  
+  void DisplayState(FILE* fp) const;
+  
+  
+protected:
+
+  const inct_config& m_inct_config;
+  
+  unsigned n_shader, n_mem;
+  unsigned n_subnets;
+  vector<xbar_router *> net;
+
+};
+
+#endif
+
+
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 3db988b..25a765a 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1893,6 +1893,17 @@ void tensor_core::issue( register_set& source_reg )
 	pipelined_simd_unit::issue(source_reg);
 }
 
+unsigned pipelined_simd_unit::get_active_lanes_in_pipeline(){
+	active_mask_t active_lanes;
+	active_lanes.reset();
+	 if(!m_config->fast_execution_mode || active_insts_in_pipeline){
+		for( unsigned stage=0; (stage+1)<m_pipeline_depth; stage++ ){
+			if( !m_pipeline_reg[stage]->empty() )
+				active_lanes|=m_pipeline_reg[stage]->get_active_mask();
+		}
+	 }
+	return active_lanes.count();
+}
 
 void ldst_unit::active_lanes_in_pipeline(){
 	unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
@@ -1946,13 +1957,13 @@ sp_unit::sp_unit( register_set* result_port, const shader_core_config *config,sh
 }
 
 dp_unit::dp_unit( register_set* result_port, const shader_core_config *config,shader_core_ctx *core)
-    : pipelined_simd_unit(result_port,config,config->max_sfu_latency,core)
+    : pipelined_simd_unit(result_port,config,config->max_dp_latency,core)
 {
     m_name = "DP ";
 }
 
 int_unit::int_unit( register_set* result_port, const shader_core_config *config,shader_core_ctx *core)
-    : pipelined_simd_unit(result_port,config,config->max_sp_latency,core)
+    : pipelined_simd_unit(result_port,config,config->max_int_latency,core)
 {
     m_name = "INT ";
 }
@@ -1993,19 +2004,25 @@ pipelined_simd_unit::pipelined_simd_unit( register_set* result_port, const shade
     for( unsigned i=0; i < m_pipeline_depth; i++ ) 
 	m_pipeline_reg[i] = new warp_inst_t( config );
     m_core=core;
+    active_insts_in_pipeline=0;
 }
 
 void pipelined_simd_unit::cycle()
 {
     if( !m_pipeline_reg[0]->empty() ){
         m_result_port->move_in(m_pipeline_reg[0]);
+        assert(active_insts_in_pipeline > 0);
+        active_insts_in_pipeline--;
+    }
+    if(!m_config->fast_execution_mode || active_insts_in_pipeline){
+		for( unsigned stage=0; (stage+1)<m_pipeline_depth; stage++ )
+			move_warp(m_pipeline_reg[stage], m_pipeline_reg[stage+1]);
     }
-    for( unsigned stage=0; (stage+1)<m_pipeline_depth; stage++ )
-        move_warp(m_pipeline_reg[stage], m_pipeline_reg[stage+1]);
     if( !m_dispatch_reg->empty() ) {
         if( !m_dispatch_reg->dispatch_delay()){
             int start_stage = m_dispatch_reg->latency - m_dispatch_reg->initiation_interval;
             move_warp(m_pipeline_reg[start_stage],m_dispatch_reg);
+            active_insts_in_pipeline++;
         }
     }
     occupied >>=1;
@@ -2981,8 +2998,61 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const
     return result;
 }
 
+void shader_core_config::set_pipeline_latency() {
+
+    if(fast_execution_mode) {
+		//calculate the max latency  based on the input
+
+		unsigned int_latency[5];
+		unsigned fp_latency[5];
+		unsigned dp_latency[5];
+		unsigned sfu_latency;
+		unsigned tensor_latency;
+
+			/*
+			 * [0] ADD,SUB
+			 * [1] MAX,Min
+			 * [2] MUL
+			 * [3] MAD
+			 * [4] DIV
+			 */
+			sscanf(opcode_latency_int, "%u,%u,%u,%u,%u",
+					&int_latency[0],&int_latency[1],&int_latency[2],
+					&int_latency[3],&int_latency[4]);
+			sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u",
+					&fp_latency[0],&fp_latency[1],&fp_latency[2],
+					&fp_latency[3],&fp_latency[4]);
+			sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u",
+					&dp_latency[0],&dp_latency[1],&dp_latency[2],
+					&dp_latency[3],&dp_latency[4]);
+			sscanf(opcode_latency_sfu, "%u",
+					&sfu_latency);
+			sscanf(opcode_latency_tensor, "%u",
+					&tensor_latency);
+
+		//all div operation are executed on sfu
+		//assume that the max latency are dp div or normal sfu_latency
+		max_sfu_latency = std::max(dp_latency[4],sfu_latency);
+		//assume that the max operation has the max latency
+		max_sp_latency = fp_latency[1];
+		max_int_latency = int_latency[1];
+		max_dp_latency = dp_latency[1];
+		max_tensor_core_latency = tensor_latency;
+    } else {
+    	max_sfu_latency = 512;
+		max_sp_latency = 32;
+		max_int_latency = 32;
+		max_dp_latency = 512;
+		max_tensor_core_latency = 64;
+    }
+
+}
+
 void shader_core_ctx::cycle()
 {
+	if(m_config->fast_execution_mode && !isactive() && get_not_completed() == 0)
+		return;
+
 	m_stats->shader_cycles[m_sid]++;
     writeback();
     execute();
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 9abd223..2204697 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -55,7 +55,6 @@
 #include "traffic_breakdown.h"
 
 
-
 #define NO_OP_FLAG            0xFF
 
 /* READ_PACKET_SIZE:
@@ -1073,16 +1072,8 @@ public:
     //modifiers
     virtual void cycle();
     virtual void issue( register_set& source_reg );
-    virtual unsigned get_active_lanes_in_pipeline()
-    {
-    	active_mask_t active_lanes;
-    	active_lanes.reset();
-        for( unsigned stage=0; (stage+1)<m_pipeline_depth; stage++ ){
-        	if( !m_pipeline_reg[stage]->empty() )
-        		active_lanes|=m_pipeline_reg[stage]->get_active_mask();
-        }
-        return active_lanes.count();
-    }
+    virtual unsigned get_active_lanes_in_pipeline();
+
     virtual void active_lanes_in_pipeline() = 0;
 /*
     virtual void issue( register_set& source_reg )
@@ -1113,6 +1104,9 @@ protected:
     warp_inst_t **m_pipeline_reg;
     register_set *m_result_port;
     class shader_core_ctx *m_core;
+
+    unsigned active_insts_in_pipeline;
+
 };
 
 class sfu : public pipelined_simd_unit
@@ -1413,10 +1407,8 @@ struct shader_core_config : public core_config
         }
         max_warps_per_shader =  n_thread_per_shader/warp_size;
         assert( !(n_thread_per_shader % warp_size) );
-        max_sfu_latency = 512;
-        max_sp_latency = 32;
-        
-	max_tensor_core_latency = 64;
+
+        set_pipeline_latency();
         
 	m_L1I_config.init(m_L1I_config.m_config_string,FuncCachePreferNone);
         m_L1T_config.init(m_L1T_config.m_config_string,FuncCachePreferNone);
@@ -1432,6 +1424,7 @@ struct shader_core_config : public core_config
     unsigned sid_to_cluster( unsigned sid ) const { return sid / n_simt_cores_per_cluster; }
     unsigned sid_to_cid( unsigned sid )     const { return sid % n_simt_cores_per_cluster; }
     unsigned cid_to_sid( unsigned cid, unsigned cluster_id ) const { return cluster_id*n_simt_cores_per_cluster + cid; }
+    void set_pipeline_latency();
 
 // data
     char *gpgpu_shader_core_pipeline_opt;
@@ -1506,7 +1499,9 @@ struct shader_core_config : public core_config
     bool sub_core_model;
     
     unsigned max_sp_latency;
+    unsigned max_int_latency;
     unsigned max_sfu_latency;
+    unsigned max_dp_latency;
     unsigned max_tensor_core_latency;
     
     unsigned n_simt_cores_per_cluster;
@@ -1524,6 +1519,7 @@ struct shader_core_config : public core_config
     bool gpgpu_concurrent_kernel_sm;
 
     bool adpative_volta_cache_config;
+    bool fast_execution_mode;
 };
 
 struct shader_core_stats_pod {
diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc
index 270bace..9e2bfa2 100644
--- a/src/gpgpusim_entrypoint.cc
+++ b/src/gpgpusim_entrypoint.cc
@@ -222,10 +222,12 @@ gpgpu_sim *gpgpu_ptx_sim_init_perf()
    read_parser_environment_variables();
    option_parser_t opp = option_parser_create();
 
-   icnt_reg_options(opp);
-   g_the_gpu_config.reg_options(opp); // register GPU microrachitecture options
    ptx_reg_options(opp);
    ptx_opcocde_latency_options(opp);
+
+   icnt_reg_options(opp);
+   g_the_gpu_config.reg_options(opp); // register GPU microrachitecture options
+
    option_parser_cmdline(opp, sg_argc, sg_argv); // parse configuration options
    fprintf(stdout, "GPGPU-Sim: Configuration options:\n\n");
    option_parser_print(opp, stdout);
-- 
cgit v1.3


From 74289a429633176e37116353347f60c75f2b644a Mon Sep 17 00:00:00 2001
From: Suchita Pati <spati@cs.wisc.edu>
Date: Wed, 17 Apr 2019 23:30:20 -0500
Subject: Modified config files to add device limit configurations

---
 configs/tested-cfgs/SM2_GTX480/gpgpusim.config |  3 +++
 configs/tested-cfgs/SM6_TITANX/gpgpusim.config |  6 +++++
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config |  6 +++++
 libcuda/cuda_runtime_api.cc                    | 35 ++++++++++++++++++--------
 4 files changed, 40 insertions(+), 10 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index d71b2fd..8d54d8b 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -3,6 +3,9 @@
 -gpgpu_ptx_sim_mode 0
 -gpgpu_ptx_force_max_capability 20 
 
+# Device Limits
+-gpgpu_stack_size_limit 1024
+-gpgpu_heap_size_limit 8388608
 
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index cb23ab3..3371186 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -8,6 +8,12 @@
 -gpgpu_ptx_force_max_capability 61 
 -gpgpu_ignore_resources_limitation 1
 
+# Device Limits
+-gpgpu_stack_size_limit 1024
+-gpgpu_heap_size_limit 8388608
+-gpgpu_runtime_sync_depth_limit 2
+-gpgpu_runtime_pending_launch_count_limit 2048
+
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 8ed4cd0..1af64ac 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -13,6 +13,12 @@
 -gpgpu_ptx_sim_mode 0
 -gpgpu_ptx_force_max_capability 70 
 
+# Device Limits
+-gpgpu_stack_size_limit 1024
+-gpgpu_heap_size_limit 8388608
+-gpgpu_runtime_sync_depth_limit 2
+-gpgpu_runtime_pending_launch_count_limit 2048
+
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc
index 86435b9..6f1ab08 100644
--- a/libcuda/cuda_runtime_api.cc
+++ b/libcuda/cuda_runtime_api.cc
@@ -1121,10 +1121,10 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic
                         *value= 0;
                         break;
                 case 75:
-                        *value= 7 ;
+                        *value= 7 ;  //cudaDevAttrComputeCapabilityMajor for Volta architecture	
                         break;
                 case 76:
-                        *value= 0 ;
+                        *value= 0 ;  //cudaDevAttrComputeCapabilityMinor for Volta architecture
                         break;
                 case 78:
                         *value= 0 ; //TODO: as of now, we dont support stream priorities.
@@ -1206,20 +1206,35 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetLimit ( size_t* pValue, cudaLimit li
             announce_call(__my_func__);
    	 }
         _cuda_device_id *dev = GPGPUSim_Init();
+	const struct cudaDeviceProp *prop = dev->get_prop();
 	const gpgpu_sim_config& config=dev->get_gpgpu()->get_config();
         switch(limit) {
         case 0:  // cudaLimitStackSize
-                                 *pValue=config.stack_limit();
-                                 break;
+        	*pValue=config.stack_limit();
+                break;
         case 2:  // cudaLimitMallocHeapSize
-                                 *pValue=config.heap_limit();
-                                 break;
+                *pValue=config.heap_limit();
+                break;
+#if (CUDART_VERSION > 5050)
         case 3: // cudaLimitDevRuntimeSyncDepth
-                                 *pValue=config.sync_depth_limit();
-                                 break;
+		if(prop->major > 2){
+			*pValue=config.sync_depth_limit();
+	                break;
+		}
+		else{
+			printf("ERROR:Limit %s is not supported on this architecture \n",limit);
+			abort();
+		}
         case 4: // cudaLimitDevRuntimePendingLaunchCount
-                                 *pValue=config.pending_launch_count_limit();
-                                 break;
+		if(prop->major > 2){
+     	        	*pValue=config.pending_launch_count_limit();
+	                break;
+		}
+		else{
+			printf("ERROR:Limit %s is not supported on this architecture \n",limit);
+			abort();
+		}
+#endif
         default:
                         printf("ERROR:Limit %s unimplemented \n",limit);
                         abort();
-- 
cgit v1.3


From 537b342ab102b75a6da694b968b2226719b267c3 Mon Sep 17 00:00:00 2001
From: Preyesh Dalmia <preyesh@taltal.cs.wisc.edu>
Date: Thu, 18 Apr 2019 17:13:06 -0500
Subject: changes for compute capability major/minor

---
 configs/tested-cfgs/SM2_GTX480/gpgpusim.config |  4 ++++
 configs/tested-cfgs/SM6_TITANX/gpgpusim.config |  4 ++++
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config |  6 ++++++
 libcuda/cuda_runtime_api.cc                    | 12 ++++++------
 src/gpgpu-sim/gpu-sim.cc                       | 17 +++++++++++++++++
 src/gpgpu-sim/gpu-sim.h                        |  8 ++++++++
 6 files changed, 45 insertions(+), 6 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index 8d54d8b..cf3627b 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -7,6 +7,10 @@
 -gpgpu_stack_size_limit 1024
 -gpgpu_heap_size_limit 8388608
 
+# Compute Capability
+-gpgpu_compute_capability_major 2
+-gpgpu_compute_capability_minor 0
+
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index 3371186..23d044c 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -14,6 +14,10 @@
 -gpgpu_runtime_sync_depth_limit 2
 -gpgpu_runtime_pending_launch_count_limit 2048
 
+# Compute Capability
+-gpgpu_compute_capability_major 6
+-gpgpu_compute_capability_minor 1
+
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 1af64ac..a5b427f 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -13,12 +13,18 @@
 -gpgpu_ptx_sim_mode 0
 -gpgpu_ptx_force_max_capability 70 
 
+
 # Device Limits
 -gpgpu_stack_size_limit 1024
 -gpgpu_heap_size_limit 8388608
 -gpgpu_runtime_sync_depth_limit 2
 -gpgpu_runtime_pending_launch_count_limit 2048
 
+# Compute Capability
+-gpgpu_compute_capability_major 7
+-gpgpu_compute_capability_minor 0
+
+
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc
index 6f1ab08..9068700 100644
--- a/libcuda/cuda_runtime_api.cc
+++ b/libcuda/cuda_runtime_api.cc
@@ -354,8 +354,8 @@ struct _cuda_device_id *GPGPUSim_Init()
 
 		cudaDeviceProp *prop = (cudaDeviceProp *) calloc(sizeof(cudaDeviceProp),1);
 		snprintf(prop->name,256,"GPGPU-Sim_v%s", g_gpgpusim_version_string );
-		prop->major = 5;
-		prop->minor = 2;
+		prop->major = the_gpu->compute_capability_major();
+		prop->minor = the_gpu->compute_capability_minor();
 		prop->totalGlobalMem = 0x80000000 /* 2 GB */;
 		prop->memPitch = 0;
 		if(prop->major >= 2) {
@@ -1120,11 +1120,11 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic
                 case 41:
                         *value= 0;
                         break;
-                case 75:
-                        *value= 7 ;  //cudaDevAttrComputeCapabilityMajor for Volta architecture	
+                case 75:// Major compute capability version number 
+                        *value= prop->major ;
                         break;
-                case 76:
-                        *value= 0 ;  //cudaDevAttrComputeCapabilityMinor for Volta architecture
+                case 76:// Minor compute capability version number
+                        *value= prop->minor ;
                         break;
                 case 78:
                         *value= 0 ; //TODO: as of now, we dont support stream priorities.
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 2a862a4..358c0f7 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -499,6 +499,12 @@ void gpgpu_sim_config::reg_options(option_parser_t opp)
    option_parser_register(opp, "-liveness_message_freq", OPT_INT64, &liveness_message_freq, 
                "Minimum number of seconds between simulation liveness messages (0 = always print)",
                "1");
+   option_parser_register(opp, "-gpgpu_compute_capability_major", OPT_UINT32, &gpgpu_compute_capability_major,
+                 "Major compute capability version number",
+                 "7");
+   option_parser_register(opp, "-gpgpu_compute_capability_minor", OPT_UINT32, &gpgpu_compute_capability_minor,
+                 "Minor compute capability version number",
+                 "0");
    option_parser_register(opp, "-gpgpu_flush_l1_cache", OPT_BOOL, &gpgpu_flush_l1_cache,
                 "Flush L1 cache at the end of each kernel call",
                 "0");
@@ -802,6 +808,17 @@ void gpgpu_sim::set_prop( cudaDeviceProp *prop )
    m_cuda_properties = prop;
 }
 
+int gpgpu_sim::compute_capability_major() const
+{
+   printf("Everything works %d\n", m_config.gpgpu_compute_capability_major);
+   return m_config.gpgpu_compute_capability_major;
+}
+
+int gpgpu_sim::compute_capability_minor() const
+{
+   return m_config.gpgpu_compute_capability_minor;
+}
+
 const struct cudaDeviceProp *gpgpu_sim::get_prop() const
 {
    return m_cuda_properties;
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 11ffe49..39e1d9a 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -388,6 +388,10 @@ private:
     size_t runtime_sync_depth_limit;
     size_t runtime_pending_launch_count_limit;	
 
+ //gpu compute capability options
+    unsigned int gpgpu_compute_capability_major;
+    unsigned int gpgpu_compute_capability_minor;
+
     unsigned long long liveness_message_freq; 
 
     friend class gpgpu_sim;
@@ -447,6 +451,10 @@ public:
 
    int shared_mem_size() const;
    int shared_mem_per_block() const;
+   int compute_capability_major() const;
+   int compute_capability_minor() const;
+
+   
    int num_registers_per_core() const;
    int num_registers_per_block() const;
    int wrp_size() const;
-- 
cgit v1.3


From 73f1a8a424cff7d689c138eaa8a59780b86a76d1 Mon Sep 17 00:00:00 2001
From: Preyesh Dalmia <preyesh@taltal.cs.wisc.edu>
Date: Thu, 18 Apr 2019 17:26:40 -0500
Subject: changes for compute capabilty

---
 configs/tested-cfgs/SM2_GTX480/gpgpusim.config |  4 ++++
 configs/tested-cfgs/SM6_TITANX/gpgpusim.config |  4 ++++
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config |  4 ++++
 libcuda/cuda_runtime_api.cc                    | 12 ++++++------
 src/gpgpu-sim/gpu-sim.cc                       | 16 ++++++++++++++++
 src/gpgpu-sim/gpu-sim.h                        |  5 +++++
 6 files changed, 39 insertions(+), 6 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index 8d54d8b..cf3627b 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -7,6 +7,10 @@
 -gpgpu_stack_size_limit 1024
 -gpgpu_heap_size_limit 8388608
 
+# Compute Capability
+-gpgpu_compute_capability_major 2
+-gpgpu_compute_capability_minor 0
+
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index 3371186..23d044c 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -14,6 +14,10 @@
 -gpgpu_runtime_sync_depth_limit 2
 -gpgpu_runtime_pending_launch_count_limit 2048
 
+# Compute Capability
+-gpgpu_compute_capability_major 6
+-gpgpu_compute_capability_minor 1
+
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 1af64ac..f3a5f65 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -19,6 +19,10 @@
 -gpgpu_runtime_sync_depth_limit 2
 -gpgpu_runtime_pending_launch_count_limit 2048
 
+# Compute Capability
+-gpgpu_compute_capability_major 7
+-gpgpu_compute_capability_minor 0
+
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc
index 6f1ab08..9068700 100644
--- a/libcuda/cuda_runtime_api.cc
+++ b/libcuda/cuda_runtime_api.cc
@@ -354,8 +354,8 @@ struct _cuda_device_id *GPGPUSim_Init()
 
 		cudaDeviceProp *prop = (cudaDeviceProp *) calloc(sizeof(cudaDeviceProp),1);
 		snprintf(prop->name,256,"GPGPU-Sim_v%s", g_gpgpusim_version_string );
-		prop->major = 5;
-		prop->minor = 2;
+		prop->major = the_gpu->compute_capability_major();
+		prop->minor = the_gpu->compute_capability_minor();
 		prop->totalGlobalMem = 0x80000000 /* 2 GB */;
 		prop->memPitch = 0;
 		if(prop->major >= 2) {
@@ -1120,11 +1120,11 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic
                 case 41:
                         *value= 0;
                         break;
-                case 75:
-                        *value= 7 ;  //cudaDevAttrComputeCapabilityMajor for Volta architecture	
+                case 75:// Major compute capability version number 
+                        *value= prop->major ;
                         break;
-                case 76:
-                        *value= 0 ;  //cudaDevAttrComputeCapabilityMinor for Volta architecture
+                case 76:// Minor compute capability version number
+                        *value= prop->minor ;
                         break;
                 case 78:
                         *value= 0 ; //TODO: as of now, we dont support stream priorities.
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 2a862a4..3687448 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -499,6 +499,12 @@ void gpgpu_sim_config::reg_options(option_parser_t opp)
    option_parser_register(opp, "-liveness_message_freq", OPT_INT64, &liveness_message_freq, 
                "Minimum number of seconds between simulation liveness messages (0 = always print)",
                "1");
+   option_parser_register(opp, "-gpgpu_compute_capability_major", OPT_UINT32, &gpgpu_compute_capability_major,
+                 "Major compute capability version number",
+                 "7");
+   option_parser_register(opp, "-gpgpu_compute_capability_minor", OPT_UINT32, &gpgpu_compute_capability_minor,
+                 "Minor compute capability version number",
+                 "0");
    option_parser_register(opp, "-gpgpu_flush_l1_cache", OPT_BOOL, &gpgpu_flush_l1_cache,
                 "Flush L1 cache at the end of each kernel call",
                 "0");
@@ -802,6 +808,16 @@ void gpgpu_sim::set_prop( cudaDeviceProp *prop )
    m_cuda_properties = prop;
 }
 
+int gpgpu_sim::compute_capability_major() const
+{
+   return m_config.gpgpu_compute_capability_major;
+}
+
+int gpgpu_sim::compute_capability_minor() const
+{
+   return m_config.gpgpu_compute_capability_minor;
+}
+
 const struct cudaDeviceProp *gpgpu_sim::get_prop() const
 {
    return m_cuda_properties;
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 11ffe49..d4cc18f 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -388,6 +388,9 @@ private:
     size_t runtime_sync_depth_limit;
     size_t runtime_pending_launch_count_limit;	
 
+ //gpu compute capability options
+    unsigned int gpgpu_compute_capability_major;
+    unsigned int gpgpu_compute_capability_minor;
     unsigned long long liveness_message_freq; 
 
     friend class gpgpu_sim;
@@ -447,6 +450,8 @@ public:
 
    int shared_mem_size() const;
    int shared_mem_per_block() const;
+   int compute_capability_major() const;
+   int compute_capability_minor() const;
    int num_registers_per_core() const;
    int num_registers_per_block() const;
    int wrp_size() const;
-- 
cgit v1.3


From 7764a7f373a0f99d714d42fcb380fb48e00b9c54 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Thu, 25 Apr 2019 15:39:13 -0400
Subject: updating titanv config file

---
 .../tested-cfgs/SM7_TITANV/config_fermi_islip.icnt | 74 ----------------------
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config     | 16 ++---
 .../SM7_TITANV_fastlocalxbar/gpgpusim.config       | 13 ++--
 3 files changed, 14 insertions(+), 89 deletions(-)
 delete mode 100644 configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
deleted file mode 100644
index 615d0a9..0000000
--- a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ /dev/null
@@ -1,74 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 88;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 256;
-input_buffer_size = 256;
-ejection_buffer_size = 256;
-boundary_buffer_size = 256;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 2.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 8ed4cd0..f48e897 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -1,4 +1,4 @@
-# This config models the Volta Titan X
+# This config models the Volta Titan V
 # For more info about volta architecture:
 # http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
 # https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
@@ -25,7 +25,7 @@
 
 # volta clock domains
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA V100  clock domains are adopted from 
+# Volta NVIDIA TITANV  clock domains are adopted from 
 # https://en.wikipedia.org/wiki/Volta_(microarchitecture)
 -gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
 # boost mode
@@ -42,7 +42,7 @@
 
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core
+## Volta TITANV has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
 -gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
 -gpgpu_num_sp_units 4
@@ -104,7 +104,7 @@
 
 # Volta has sub core model, in which each scheduler has its own reisiter file and EUs
 # i.e. schedulers are isolated
--sub_core_model 0
+-sub_core_model 1
 # disable specialized operand collectors and use generic operand collectors instead
 -enable_specialized_operand_collector 0
 -gpgpu_operand_collector_num_units_gen 8
@@ -125,7 +125,7 @@
 
 # interconnection
 -network_mode 1 
--inter_config_file config_fermi_islip.icnt
+-inter_config_file config_volta_islip.icnt
 
 # memory partition latency config 
 -rop_latency 120
@@ -150,7 +150,7 @@
 #-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
 #                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
 
-# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ
+# Timing for 850 MHZ, Tesla TITANV HBM runs at 850 MHZ
 -gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
                         CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
 
@@ -163,7 +163,7 @@
 #-Seperate_Write_Queue_Enable 1
 #-Write_Queue_Size 64:56:32
 
-# Pascal has two schedulers per core
+# Volta has four schedulers per core
 -gpgpu_num_sched_per_core 4
 # Two Level Scheduler with active and pending pools
 #-gpgpu_scheduler two_level_active:6:0:1
@@ -178,7 +178,7 @@
 -enable_ptx_file_line_stats 1
 -visualizer_enabled 0
 
-# power model configs, disable it untill we create a real energy model for Pascal 100
+# power model configs, disable it untill we create a real energy model for Volta
 -power_simulation_enabled 0
 
 # tracing functionality
diff --git a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
index 73516e1..3e4a8fa 100644
--- a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
@@ -1,4 +1,4 @@
-# This config models the Volta Titan X
+# This config models the Volta Titan V
 # For more info about volta architecture:
 # http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
 # https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
@@ -25,7 +25,7 @@
 
 # volta clock domains
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA V100  clock domains are adopted from 
+# Volta NVIDIA TITANV clock domains are adopted from 
 # https://en.wikipedia.org/wiki/Volta_(microarchitecture)
 -gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
 # boost mode
@@ -42,7 +42,7 @@
 
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core
+## Volta TITANV has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
 -gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
 -gpgpu_num_sp_units 4
@@ -123,9 +123,8 @@
 -gpgpu_max_insn_issue_per_warp 1
 -gpgpu_dual_issue_diff_exec_units 1
 
-# interconnection
+# use local xbar interconnection
 -network_mode 2 
--inter_config_file config_fermi_islip.icnt
 -inct_in_buffer_limit 512
 -inct_out_buffer_limit 512
 -inct_subnets 2
@@ -167,7 +166,7 @@
 #-Seperate_Write_Queue_Enable 1
 #-Write_Queue_Size 64:56:32
 
-# Pascal has two schedulers per core
+# Volta has four schedulers per core
 -gpgpu_num_sched_per_core 4
 # Two Level Scheduler with active and pending pools
 #-gpgpu_scheduler two_level_active:6:0:1
@@ -182,7 +181,7 @@
 -enable_ptx_file_line_stats 1
 -visualizer_enabled 0
 
-# power model configs, disable it untill we create a real energy model for Pascal 100
+# power model configs, disable it untill we create a real energy model for Volta
 -power_simulation_enabled 0
 
 # tracing functionality
-- 
cgit v1.3


From 0cf1f587d5bcc449c679371ac966f26db706deca Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Thu, 25 Apr 2019 15:39:57 -0400
Subject: change name booksim file

---
 .../tested-cfgs/SM7_TITANV/config_volta_islip.icnt | 74 ++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt
new file mode 100644
index 0000000..615d0a9
--- /dev/null
+++ b/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 88;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
-- 
cgit v1.3


From d7fd62c23db88a71e1fb327b584504a5270d01e0 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Thu, 25 Apr 2019 16:01:03 -0400
Subject: adding v100 config file

---
 .../tested-cfgs/SM6_TITANX/config_fermi_islip.icnt |  73 --------
 .../SM6_TITANX/config_pascal_islip.icnt            |  73 ++++++++
 configs/tested-cfgs/SM6_TITANX/gpgpusim.config     |   2 +-
 .../SM6_TITANX_64/config_pascal_islip.icnt         |  73 ++++++++
 configs/tested-cfgs/SM6_TITANX_64/gpgpusim.config  | 181 +++++++++++++++++++
 .../tested-cfgs/SM7_V100/config_volta_islip.icnt   |  74 ++++++++
 configs/tested-cfgs/SM7_V100/gpgpusim.config       | 188 ++++++++++++++++++++
 .../SM7_V100_fastlocalxbar/gpgpusim.config         | 191 +++++++++++++++++++++
 8 files changed, 781 insertions(+), 74 deletions(-)
 delete mode 100644 configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
 create mode 100644 configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt
 create mode 100644 configs/tested-cfgs/SM6_TITANX_64/config_pascal_islip.icnt
 create mode 100644 configs/tested-cfgs/SM6_TITANX_64/gpgpusim.config
 create mode 100644 configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
 create mode 100644 configs/tested-cfgs/SM7_V100/gpgpusim.config
 create mode 100644 configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
deleted file mode 100644
index dec4789..0000000
--- a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
+++ /dev/null
@@ -1,73 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 52;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 64;
-input_buffer_size = 256;
-ejection_buffer_size = 64;
-boundary_buffer_size = 64;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 2.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt
new file mode 100644
index 0000000..dec4789
--- /dev/null
+++ b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 64;
+input_buffer_size = 256;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index cb23ab3..73e3951 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -92,7 +92,7 @@
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
 # 48 KB Tex 
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
 -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
 # 12 KB Const
 -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
diff --git a/configs/tested-cfgs/SM6_TITANX_64/config_pascal_islip.icnt b/configs/tested-cfgs/SM6_TITANX_64/config_pascal_islip.icnt
new file mode 100644
index 0000000..dec4789
--- /dev/null
+++ b/configs/tested-cfgs/SM6_TITANX_64/config_pascal_islip.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 64;
+input_buffer_size = 256;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM6_TITANX_64/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX_64/gpgpusim.config
new file mode 100644
index 0000000..dffc156
--- /dev/null
+++ b/configs/tested-cfgs/SM6_TITANX_64/gpgpusim.config
@@ -0,0 +1,181 @@
+# This config models the Pascal GP102 (NVIDIA TITAN X)
+# For more info about this card, see Nvidia White paper
+# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 61 
+-gpgpu_ignore_resources_limitation 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+# P102 has two semi-indp scheds per core, and two cores per cluster 
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 62
+
+# This implies a maximum of 32 warps/SM
+-gpgpu_shader_core_pipeline 1024:32 
+-gpgpu_shader_cta 16
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs
+# There is no int unit in Pascal
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 2
+-gpgpu_num_dp_units 1
+
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,8,8,8,130
+-ptx_opcode_initiation_sfu 4
+-ptx_opcode_latency_sfu 8
+
+
+# latencies and cache configs are adopted from:
+# https://arxiv.org/pdf/1804.06826.pdf
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
+# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres are used
+-gpgpu_cache:dl1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 49152
+-gpgpu_shmem_size_PrefL1 49152
+-gpgpu_shmem_size_PrefShared 49152
+# By default, L1 cache is disabled in Pascal P102.
+# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
+-gmem_skip_L1D 1
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 82
+-smem_latency 24
+-gpgpu_flush_l1_cache 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
+-perf_sim_memcpy 1
+-memory_partition_indexing 4
+
+# 4 KB Inst.
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+# 48 KB Tex 
+# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_operand_collector_num_in_ports_sfu 2
+-gpgpu_operand_collector_num_out_ports_sfu 2
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+# Use Pascal Coalsce arhitetecture
+-gpgpu_coalesce_arch 61
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_pascal_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 64
+
+# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
+# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing, scaled to 2500MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
+                        CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
+
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal 102 has four schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 102
+-power_simulation_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt b/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
new file mode 100644
index 0000000..2de1f6e
--- /dev/null
+++ b/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 104;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM7_V100/gpgpusim.config b/configs/tested-cfgs/SM7_V100/gpgpusim.config
new file mode 100644
index 0000000..fb44257
--- /dev/null
+++ b/configs/tested-cfgs/SM7_V100/gpgpusim.config
@@ -0,0 +1,188 @@
+# This config models the Volta
+# For more info about volta architecture:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 32
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA V100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Nvidia_Tesla
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:875.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:1455.0:1455.0:875.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 70
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
+## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+-gpgpu_num_int_units 4
+-gpgpu_tensor_core_avail 1
+-gpgpu_num_tensor_core_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+-ptx_opcode_latency_tesnor 64
+-ptx_opcode_initiation_tensor 64
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+# Volta unified cache has four ports
+-mem_unit_ports 4
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+-gpgpu_flush_l1_cache 1
+
+# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
+-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 1
+-memory_partition_indexing 4
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 1
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
+-gpgpu_num_reg_banks 8
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Volta, a warp scheduler can issue 1 inst per cycle
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_volta_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Volta has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Volta
+-power_simulation_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
new file mode 100644
index 0000000..1e707f1
--- /dev/null
+++ b/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
@@ -0,0 +1,191 @@
+# This config models the Volta
+# For more info about volta architecture:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 32
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA V100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Nvidia_Tesla
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:875.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:1455.0:1455.0:875.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 70
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
+## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+-gpgpu_num_int_units 4
+-gpgpu_tensor_core_avail 1
+-gpgpu_num_tensor_core_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+-ptx_opcode_latency_tesnor 64
+-ptx_opcode_initiation_tensor 64
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+# Volta unified cache has four ports
+-mem_unit_ports 4
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+-gpgpu_flush_l1_cache 1
+
+# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
+-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 1
+-memory_partition_indexing 4
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 1
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
+-gpgpu_num_reg_banks 8
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Volta, a warp scheduler can issue 1 inst per cycle
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# use local xbar interconnection
+-network_mode 2 
+-inct_in_buffer_limit 512
+-inct_out_buffer_limit 512
+-inct_subnets 2
+-fast_execution_mode 1
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 850 MHZ, Tesla V100 HBM runs at 850 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Volta has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Volta
+-power_simulation_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
-- 
cgit v1.3


From 78b228ac310a8a3bc72816293ba0a611eb870215 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Thu, 25 Apr 2019 19:17:47 -0400
Subject: updating volta model

---
 configs/tested-cfgs/SM7_V100/config_volta_islip.icnt       | 2 +-
 configs/tested-cfgs/SM7_V100/gpgpusim.config               | 4 ++--
 configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt b/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
index 2de1f6e..f6e0833 100644
--- a/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
+++ b/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
@@ -7,7 +7,7 @@ network_count = 2;
 
 // Topology
 topology = fly;
-k = 104;
+k = 164;
 n = 1;
 
 // Routing
diff --git a/configs/tested-cfgs/SM7_V100/gpgpusim.config b/configs/tested-cfgs/SM7_V100/gpgpusim.config
index fb44257..d7ebe39 100644
--- a/configs/tested-cfgs/SM7_V100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_V100/gpgpusim.config
@@ -18,8 +18,8 @@
 -gpgpu_ptx_save_converted_ptxplus 0
 
 # high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
+-gpgpu_n_clusters 80
+-gpgpu_n_cores_per_cluster 1
 -gpgpu_n_mem 32
 -gpgpu_n_sub_partition_per_mchannel 2 
 
diff --git a/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
index 1e707f1..401aafd 100644
--- a/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
@@ -18,8 +18,8 @@
 -gpgpu_ptx_save_converted_ptxplus 0
 
 # high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
+-gpgpu_n_clusters 80
+-gpgpu_n_cores_per_cluster 1
 -gpgpu_n_mem 32
 -gpgpu_n_sub_partition_per_mchannel 2 
 
-- 
cgit v1.3


From 3764ceaff2110bcd191271cca341e516b9520338 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Thu, 25 Apr 2019 19:21:00 -0400
Subject: remove some config files

---
 .../SM6_TITANX_64/config_pascal_islip.icnt         |  73 ---------
 configs/tested-cfgs/SM6_TITANX_64/gpgpusim.config  | 181 ---------------------
 2 files changed, 254 deletions(-)
 delete mode 100644 configs/tested-cfgs/SM6_TITANX_64/config_pascal_islip.icnt
 delete mode 100644 configs/tested-cfgs/SM6_TITANX_64/gpgpusim.config

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM6_TITANX_64/config_pascal_islip.icnt b/configs/tested-cfgs/SM6_TITANX_64/config_pascal_islip.icnt
deleted file mode 100644
index dec4789..0000000
--- a/configs/tested-cfgs/SM6_TITANX_64/config_pascal_islip.icnt
+++ /dev/null
@@ -1,73 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 52;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 64;
-input_buffer_size = 256;
-ejection_buffer_size = 64;
-boundary_buffer_size = 64;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 2.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/tested-cfgs/SM6_TITANX_64/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX_64/gpgpusim.config
deleted file mode 100644
index dffc156..0000000
--- a/configs/tested-cfgs/SM6_TITANX_64/gpgpusim.config
+++ /dev/null
@@ -1,181 +0,0 @@
-# This config models the Pascal GP102 (NVIDIA TITAN X)
-# For more info about this card, see Nvidia White paper
-# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 61 
--gpgpu_ignore_resources_limitation 1
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
-# P102 has two semi-indp scheds per core, and two cores per cluster 
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 12
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
-
-# shader core pipeline config
--gpgpu_shader_registers 32768
--gpgpu_occupancy_sm_number 62
-
-# This implies a maximum of 32 warps/SM
--gpgpu_shader_core_pipeline 1024:32 
--gpgpu_shader_cta 16
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs
-# There is no int unit in Pascal
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 2
--gpgpu_num_dp_units 1
-
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 8,8,8,8,130
--ptx_opcode_initiation_sfu 4
--ptx_opcode_latency_sfu 8
-
-
-# latencies and cache configs are adopted from:
-# https://arxiv.org/pdf/1804.06826.pdf
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
-# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
-# The defulat is to disable the L1 cache, unless cache modifieres are used
--gpgpu_cache:dl1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 49152
--gpgpu_shmem_size_PrefL1 49152
--gpgpu_shmem_size_PrefShared 49152
-# By default, L1 cache is disabled in Pascal P102.
-# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
--gmem_skip_L1D 1
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 82
--smem_latency 24
--gpgpu_flush_l1_cache 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 32:32:32:32
--perf_sim_memcpy 1
--memory_partition_indexing 4
-
-# 4 KB Inst.
--gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
-# 48 KB Tex 
-# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_operand_collector_num_in_ports_sfu 2
--gpgpu_operand_collector_num_out_ports_sfu 2
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-# Use Pascal Coalsce arhitetecture
--gpgpu_coalesce_arch 61
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_pascal_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 64
-
-# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
-# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes 
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing, scaled to 2500MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
-                        CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
-
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal 102 has four schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 102
--power_simulation_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
-- 
cgit v1.3


From bbef52a122761bc8f02092e0acf867dbd87cbe70 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Thu, 2 May 2019 15:23:34 -0400
Subject: remove v100 config now till tested

---
 .../tested-cfgs/SM7_V100/config_volta_islip.icnt   |  74 --------
 configs/tested-cfgs/SM7_V100/gpgpusim.config       | 188 --------------------
 .../SM7_V100_fastlocalxbar/gpgpusim.config         | 191 ---------------------
 3 files changed, 453 deletions(-)
 delete mode 100644 configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
 delete mode 100644 configs/tested-cfgs/SM7_V100/gpgpusim.config
 delete mode 100644 configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt b/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
deleted file mode 100644
index f6e0833..0000000
--- a/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
+++ /dev/null
@@ -1,74 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 164;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 256;
-input_buffer_size = 256;
-ejection_buffer_size = 256;
-boundary_buffer_size = 256;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 2.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/tested-cfgs/SM7_V100/gpgpusim.config b/configs/tested-cfgs/SM7_V100/gpgpusim.config
deleted file mode 100644
index d7ebe39..0000000
--- a/configs/tested-cfgs/SM7_V100/gpgpusim.config
+++ /dev/null
@@ -1,188 +0,0 @@
-# This config models the Volta
-# For more info about volta architecture:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 80
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 32
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA V100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Nvidia_Tesla
--gpgpu_clock_domains 1200.0:1200.0:1200.0:875.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:1455.0:875.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 70
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
--gpgpu_num_int_units 4
--gpgpu_tensor_core_avail 1
--gpgpu_num_tensor_core_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
--ptx_opcode_latency_tesnor 64
--ptx_opcode_initiation_tensor 64
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 32KB DL1 and 96KB shared memory
-# In Volta, we assign the remaining shared memory to L1 cache 
-# if the assigned shd mem = 0, then L1 cache = 128KB
-# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
-# disable this mode in case of multi kernels/apps execution
--adpative_volta_cache_config 1
-# Volta unified cache has four ports
--mem_unit_ports 4
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 98304
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 28
--smem_latency 19
--gpgpu_flush_l1_cache 1
-
-# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
--gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
--gpgpu_cache:dl2_texture_only 0
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 1
--memory_partition_indexing 4
-
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-
-# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
-# i.e. schedulers are isolated
--sub_core_model 1
-# disable specialized operand collectors and use generic operand collectors instead
--enable_specialized_operand_collector 0
--gpgpu_operand_collector_num_units_gen 8
--gpgpu_operand_collector_num_in_ports_gen 8
--gpgpu_operand_collector_num_out_ports_gen 8
-# volta has 8 banks, 4 schedulers, two banks per scheduler
--gpgpu_num_reg_banks 8
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Volta, a warp scheduler can issue 1 inst per cycle
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_volta_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Volta has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Volta
--power_simulation_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
deleted file mode 100644
index 401aafd..0000000
--- a/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
+++ /dev/null
@@ -1,191 +0,0 @@
-# This config models the Volta
-# For more info about volta architecture:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 80
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 32
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA V100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Nvidia_Tesla
--gpgpu_clock_domains 1200.0:1200.0:1200.0:875.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:1455.0:875.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 70
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
--gpgpu_num_int_units 4
--gpgpu_tensor_core_avail 1
--gpgpu_num_tensor_core_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
--ptx_opcode_latency_tesnor 64
--ptx_opcode_initiation_tensor 64
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 32KB DL1 and 96KB shared memory
-# In Volta, we assign the remaining shared memory to L1 cache 
-# if the assigned shd mem = 0, then L1 cache = 128KB
-# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
-# disable this mode in case of multi kernels/apps execution
--adpative_volta_cache_config 1
-# Volta unified cache has four ports
--mem_unit_ports 4
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 98304
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 28
--smem_latency 19
--gpgpu_flush_l1_cache 1
-
-# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
--gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
--gpgpu_cache:dl2_texture_only 0
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 1
--memory_partition_indexing 4
-
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-
-# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
-# i.e. schedulers are isolated
--sub_core_model 1
-# disable specialized operand collectors and use generic operand collectors instead
--enable_specialized_operand_collector 0
--gpgpu_operand_collector_num_units_gen 8
--gpgpu_operand_collector_num_in_ports_gen 8
--gpgpu_operand_collector_num_out_ports_gen 8
-# volta has 8 banks, 4 schedulers, two banks per scheduler
--gpgpu_num_reg_banks 8
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Volta, a warp scheduler can issue 1 inst per cycle
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
-# use local xbar interconnection
--network_mode 2 
--inct_in_buffer_limit 512
--inct_out_buffer_limit 512
--inct_subnets 2
--fast_execution_mode 1
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 850 MHZ, Tesla V100 HBM runs at 850 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Volta has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Volta
--power_simulation_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
-- 
cgit v1.3


From ad37c917f8641930f9f58c3f04fa6e22600015cd Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Thu, 2 May 2019 15:49:03 -0400
Subject: fixing some typos in config files

---
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config               | 4 ++--
 configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 13d8c8f..f454240 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -53,7 +53,7 @@
 
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta TITANV has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
+## Volta TITANV has 4 SP SIMD units, 4 INT units, 4 SFU units, 4 DP units per core, 4 Tensor core units
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
 -gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
 -gpgpu_num_sp_units 4
@@ -113,7 +113,7 @@
 # 64 KB Const
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
 
-# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
+# Volta has sub core model, in which each scheduler has its own register file and EUs
 # i.e. schedulers are isolated
 -sub_core_model 1
 # disable specialized operand collectors and use generic operand collectors instead
diff --git a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
index 3e4a8fa..b1ce11c 100644
--- a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
@@ -102,9 +102,9 @@
 # 64 KB Const
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
 
-# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
+# Volta has sub core model, in which each scheduler has its own register file and EUs
 # i.e. schedulers are isolated
--sub_core_model 0
+-sub_core_model 1
 # disable specialized operand collectors and use generic operand collectors instead
 -enable_specialized_operand_collector 0
 -gpgpu_operand_collector_num_units_gen 8
-- 
cgit v1.3


From fe6506a14839b8614b5f4daa2d8331441feb6902 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Mon, 6 May 2019 20:23:39 -0400
Subject: adding volta configs

---
 .../tested-cfgs/SM7_V100/config_volta_islip.icnt   |  74 ++++++++
 configs/tested-cfgs/SM7_V100/gpgpusim.config       | 188 ++++++++++++++++++++
 .../SM7_V100_fastlocalxbar/gpgpusim.config         | 191 +++++++++++++++++++++
 3 files changed, 453 insertions(+)
 create mode 100644 configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
 create mode 100644 configs/tested-cfgs/SM7_V100/gpgpusim.config
 create mode 100644 configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt b/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
new file mode 100644
index 0000000..f6e0833
--- /dev/null
+++ b/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 164;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM7_V100/gpgpusim.config b/configs/tested-cfgs/SM7_V100/gpgpusim.config
new file mode 100644
index 0000000..d7ebe39
--- /dev/null
+++ b/configs/tested-cfgs/SM7_V100/gpgpusim.config
@@ -0,0 +1,188 @@
+# This config models the Volta
+# For more info about volta architecture:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 80
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 32
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA V100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Nvidia_Tesla
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:875.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:1455.0:1455.0:875.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 70
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
+## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+-gpgpu_num_int_units 4
+-gpgpu_tensor_core_avail 1
+-gpgpu_num_tensor_core_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+-ptx_opcode_latency_tesnor 64
+-ptx_opcode_initiation_tensor 64
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+# Volta unified cache has four ports
+-mem_unit_ports 4
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+-gpgpu_flush_l1_cache 1
+
+# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
+-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 1
+-memory_partition_indexing 4
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 1
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
+-gpgpu_num_reg_banks 8
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Volta, a warp scheduler can issue 1 inst per cycle
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_volta_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Volta has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Volta
+-power_simulation_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
new file mode 100644
index 0000000..401aafd
--- /dev/null
+++ b/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
@@ -0,0 +1,191 @@
+# This config models the Volta
+# For more info about volta architecture:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 80
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 32
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA V100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Nvidia_Tesla
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:875.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:1455.0:1455.0:875.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 70
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
+## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+-gpgpu_num_int_units 4
+-gpgpu_tensor_core_avail 1
+-gpgpu_num_tensor_core_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+-ptx_opcode_latency_tesnor 64
+-ptx_opcode_initiation_tensor 64
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+# Volta unified cache has four ports
+-mem_unit_ports 4
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+-gpgpu_flush_l1_cache 1
+
+# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
+-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 1
+-memory_partition_indexing 4
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 1
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
+-gpgpu_num_reg_banks 8
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Volta, a warp scheduler can issue 1 inst per cycle
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# use local xbar interconnection
+-network_mode 2 
+-inct_in_buffer_limit 512
+-inct_out_buffer_limit 512
+-inct_subnets 2
+-fast_execution_mode 1
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 850 MHZ, Tesla V100 HBM runs at 850 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Volta has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Volta
+-power_simulation_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
-- 
cgit v1.3


From 90755c4dbdd8295b70632bb8e8868a980c9fd9ab Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 8 May 2019 11:36:36 -0400
Subject: fixing the volta config

---
 configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
index b1ce11c..4625ac4 100644
--- a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
@@ -75,7 +75,7 @@
 # if the assigned shd mem = 0, then L1 cache = 128KB
 # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
 # disable this mode in case of multi kernels/apps execution
--adpative_volta_cache_config 1
+-adaptive_volta_cache_config 1
 # Volta unified cache has four ports
 -mem_unit_ports 4
 -gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
@@ -128,7 +128,6 @@
 -inct_in_buffer_limit 512
 -inct_out_buffer_limit 512
 -inct_subnets 2
--fast_execution_mode 1
 
 # memory partition latency config 
 -rop_latency 120
-- 
cgit v1.3


From d82c8bab428ebbb0d3240bf039dd81da21807a13 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 8 May 2019 11:39:11 -0400
Subject: fixing volta config

---
 configs/tested-cfgs/SM7_V100/gpgpusim.config               | 2 +-
 configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_V100/gpgpusim.config b/configs/tested-cfgs/SM7_V100/gpgpusim.config
index d7ebe39..ef93cea 100644
--- a/configs/tested-cfgs/SM7_V100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_V100/gpgpusim.config
@@ -75,7 +75,7 @@
 # if the assigned shd mem = 0, then L1 cache = 128KB
 # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
 # disable this mode in case of multi kernels/apps execution
--adpative_volta_cache_config 1
+-adaptive_volta_cache_config 1
 # Volta unified cache has four ports
 -mem_unit_ports 4
 -gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
diff --git a/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
index 401aafd..66f5251 100644
--- a/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
@@ -75,7 +75,7 @@
 # if the assigned shd mem = 0, then L1 cache = 128KB
 # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
 # disable this mode in case of multi kernels/apps execution
--adpative_volta_cache_config 1
+-adaptive_volta_cache_config 1
 # Volta unified cache has four ports
 -mem_unit_ports 4
 -gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
@@ -128,7 +128,6 @@
 -inct_in_buffer_limit 512
 -inct_out_buffer_limit 512
 -inct_subnets 2
--fast_execution_mode 1
 
 # memory partition latency config 
 -rop_latency 120
-- 
cgit v1.3


From 059dabc1af44b8eb60f0cacc8d5c2d06f1e85a00 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Mon, 13 May 2019 17:34:34 -0400
Subject: fixing local xbar again

---
 .travis.yml                                        |   2 +-
 .../SM7_TITANV_fastlocalxbar/gpgpusim.config       | 190 ---------------------
 2 files changed, 1 insertion(+), 191 deletions(-)
 delete mode 100644 configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config

(limited to 'configs')

diff --git a/.travis.yml b/.travis.yml
index bd86675..82f0604 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -20,7 +20,7 @@ matrix:
         - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-9.1/
     - services: docker
       env:
-        - CONFIG=TITANV-localxbar
+        - CONFIG=TITANV-LOCALXBAR
         - CUDA_INSTALL_PATH=/usr/local/cuda-9.1/
         - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-9.1/
 
diff --git a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
deleted file mode 100644
index 4625ac4..0000000
--- a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
+++ /dev/null
@@ -1,190 +0,0 @@
-# This config models the Volta Titan V
-# For more info about volta architecture:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA TITANV clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:1455.0:850.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 70
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta TITANV has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
--gpgpu_num_int_units 4
--gpgpu_tensor_core_avail 1
--gpgpu_num_tensor_core_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
--ptx_opcode_latency_tesnor 64
--ptx_opcode_initiation_tensor 64
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 32KB DL1 and 96KB shared memory
-# In Volta, we assign the remaining shared memory to L1 cache 
-# if the assigned shd mem = 0, then L1 cache = 128KB
-# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
-# disable this mode in case of multi kernels/apps execution
--adaptive_volta_cache_config 1
-# Volta unified cache has four ports
--mem_unit_ports 4
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 98304
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 28
--smem_latency 19
--gpgpu_flush_l1_cache 1
-
-# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
--gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
--gpgpu_cache:dl2_texture_only 0
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 1
--memory_partition_indexing 0
-
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-
-# Volta has sub core model, in which each scheduler has its own register file and EUs
-# i.e. schedulers are isolated
--sub_core_model 1
-# disable specialized operand collectors and use generic operand collectors instead
--enable_specialized_operand_collector 0
--gpgpu_operand_collector_num_units_gen 8
--gpgpu_operand_collector_num_in_ports_gen 8
--gpgpu_operand_collector_num_out_ports_gen 8
-# volta has 8 banks, 4 schedulers, two banks per scheduler
--gpgpu_num_reg_banks 8
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Volta, a warp scheduler can issue 1 inst per cycle
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
-# use local xbar interconnection
--network_mode 2 
--inct_in_buffer_limit 512
--inct_out_buffer_limit 512
--inct_subnets 2
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Volta has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Volta
--power_simulation_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
-- 
cgit v1.3


From 24659c165247c94eedab5615096f3384f9207e20 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Tue, 28 May 2019 18:04:34 -0400
Subject: adding QV100 config

---
 .../tested-cfgs/SM7_QV100/config_volta_islip.icnt  |  74 ++++++++
 configs/tested-cfgs/SM7_QV100/gpgpusim.config      | 201 +++++++++++++++++++++
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config     |   4 +-
 .../SM7_TITANV_fastlocalxbar/gpgpusim.config       | 190 -------------------
 .../tested-cfgs/SM7_V100/config_volta_islip.icnt   |  74 --------
 configs/tested-cfgs/SM7_V100/gpgpusim.config       | 188 -------------------
 .../SM7_V100_fastlocalxbar/gpgpusim.config         | 190 -------------------
 7 files changed, 278 insertions(+), 643 deletions(-)
 create mode 100644 configs/tested-cfgs/SM7_QV100/config_volta_islip.icnt
 create mode 100644 configs/tested-cfgs/SM7_QV100/gpgpusim.config
 delete mode 100644 configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
 delete mode 100644 configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
 delete mode 100644 configs/tested-cfgs/SM7_V100/gpgpusim.config
 delete mode 100644 configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_QV100/config_volta_islip.icnt b/configs/tested-cfgs/SM7_QV100/config_volta_islip.icnt
new file mode 100644
index 0000000..f6e0833
--- /dev/null
+++ b/configs/tested-cfgs/SM7_QV100/config_volta_islip.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 164;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
new file mode 100644
index 0000000..16c131b
--- /dev/null
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -0,0 +1,201 @@
+# This config models the Volta
+# For more info about volta architecture:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+
+# Device Limits
+-gpgpu_stack_size_limit 1024
+-gpgpu_heap_size_limit 8388608
+-gpgpu_runtime_sync_depth_limit 2
+-gpgpu_runtime_pending_launch_count_limit 2048
+
+# Compute Capability
+-gpgpu_compute_capability_major 7
+-gpgpu_compute_capability_minor 0
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 80
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 32
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Volta NVIDIA TITANV  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1132.0:1132.0:1132.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1628.0:1628.0:1628.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 70
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
+## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+-gpgpu_num_int_units 4
+-gpgpu_tensor_core_avail 1
+-gpgpu_num_tensor_core_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+-ptx_opcode_latency_tesnor 64
+-ptx_opcode_initiation_tensor 64
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adaptive_volta_cache_config 1
+# Volta unified cache has four ports
+-mem_unit_ports 4
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 28
+-smem_latency 19
+-gpgpu_flush_l1_cache 1
+
+# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
+-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 1
+-memory_partition_indexing 4
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+
+# Volta has sub core model, in which each scheduler has its own register file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 1
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
+-gpgpu_num_reg_banks 8
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Volta, a warp scheduler can issue 1 inst per cycle
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_volta_islip.icnt
+# for local xbar, use:
+# "-network_mode 2 -inct_in_buffer_limit 512  -inct_out_buffer_limit 512  -inct_subnets 2"
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 850 MHZ, V100 HBM runs at 850 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Volta has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Volta
+-power_simulation_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index ebd442f..b06f048 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -137,6 +137,8 @@
 # interconnection
 -network_mode 1 
 -inter_config_file config_volta_islip.icnt
+# for local xbar, use:
+# "-network_mode 2 -inct_in_buffer_limit 512  -inct_out_buffer_limit 512  -inct_subnets 2"
 
 # memory partition latency config 
 -rop_latency 120
@@ -161,7 +163,7 @@
 #-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
 #                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
 
-# Timing for 850 MHZ, Tesla TITANV HBM runs at 850 MHZ
+# Timing for 850 MHZ, TITANV HBM runs at 850 MHZ
 -gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
                         CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
 
diff --git a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
deleted file mode 100644
index 4625ac4..0000000
--- a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config
+++ /dev/null
@@ -1,190 +0,0 @@
-# This config models the Volta Titan V
-# For more info about volta architecture:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA TITANV clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:1455.0:850.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 70
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta TITANV has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
--gpgpu_num_int_units 4
--gpgpu_tensor_core_avail 1
--gpgpu_num_tensor_core_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
--ptx_opcode_latency_tesnor 64
--ptx_opcode_initiation_tensor 64
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 32KB DL1 and 96KB shared memory
-# In Volta, we assign the remaining shared memory to L1 cache 
-# if the assigned shd mem = 0, then L1 cache = 128KB
-# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
-# disable this mode in case of multi kernels/apps execution
--adaptive_volta_cache_config 1
-# Volta unified cache has four ports
--mem_unit_ports 4
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 98304
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 28
--smem_latency 19
--gpgpu_flush_l1_cache 1
-
-# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
--gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
--gpgpu_cache:dl2_texture_only 0
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 1
--memory_partition_indexing 0
-
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-
-# Volta has sub core model, in which each scheduler has its own register file and EUs
-# i.e. schedulers are isolated
--sub_core_model 1
-# disable specialized operand collectors and use generic operand collectors instead
--enable_specialized_operand_collector 0
--gpgpu_operand_collector_num_units_gen 8
--gpgpu_operand_collector_num_in_ports_gen 8
--gpgpu_operand_collector_num_out_ports_gen 8
-# volta has 8 banks, 4 schedulers, two banks per scheduler
--gpgpu_num_reg_banks 8
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Volta, a warp scheduler can issue 1 inst per cycle
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
-# use local xbar interconnection
--network_mode 2 
--inct_in_buffer_limit 512
--inct_out_buffer_limit 512
--inct_subnets 2
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Volta has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Volta
--power_simulation_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt b/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
deleted file mode 100644
index f6e0833..0000000
--- a/configs/tested-cfgs/SM7_V100/config_volta_islip.icnt
+++ /dev/null
@@ -1,74 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 164;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 256;
-input_buffer_size = 256;
-ejection_buffer_size = 256;
-boundary_buffer_size = 256;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 1;
-output_speedup    = 1;
-internal_speedup  = 2.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/tested-cfgs/SM7_V100/gpgpusim.config b/configs/tested-cfgs/SM7_V100/gpgpusim.config
deleted file mode 100644
index ef93cea..0000000
--- a/configs/tested-cfgs/SM7_V100/gpgpusim.config
+++ /dev/null
@@ -1,188 +0,0 @@
-# This config models the Volta
-# For more info about volta architecture:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 80
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 32
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA V100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Nvidia_Tesla
--gpgpu_clock_domains 1200.0:1200.0:1200.0:875.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:1455.0:875.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 70
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
--gpgpu_num_int_units 4
--gpgpu_tensor_core_avail 1
--gpgpu_num_tensor_core_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
--ptx_opcode_latency_tesnor 64
--ptx_opcode_initiation_tensor 64
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 32KB DL1 and 96KB shared memory
-# In Volta, we assign the remaining shared memory to L1 cache 
-# if the assigned shd mem = 0, then L1 cache = 128KB
-# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
-# disable this mode in case of multi kernels/apps execution
--adaptive_volta_cache_config 1
-# Volta unified cache has four ports
--mem_unit_ports 4
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 98304
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 28
--smem_latency 19
--gpgpu_flush_l1_cache 1
-
-# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
--gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
--gpgpu_cache:dl2_texture_only 0
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 1
--memory_partition_indexing 4
-
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-
-# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
-# i.e. schedulers are isolated
--sub_core_model 1
-# disable specialized operand collectors and use generic operand collectors instead
--enable_specialized_operand_collector 0
--gpgpu_operand_collector_num_units_gen 8
--gpgpu_operand_collector_num_in_ports_gen 8
--gpgpu_operand_collector_num_out_ports_gen 8
-# volta has 8 banks, 4 schedulers, two banks per scheduler
--gpgpu_num_reg_banks 8
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Volta, a warp scheduler can issue 1 inst per cycle
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_volta_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Volta has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Volta
--power_simulation_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
deleted file mode 100644
index 66f5251..0000000
--- a/configs/tested-cfgs/SM7_V100_fastlocalxbar/gpgpusim.config
+++ /dev/null
@@ -1,190 +0,0 @@
-# This config models the Volta
-# For more info about volta architecture:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 80
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 32
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA V100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Nvidia_Tesla
--gpgpu_clock_domains 1200.0:1200.0:1200.0:875.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:1455.0:875.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 70
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
--gpgpu_num_int_units 4
--gpgpu_tensor_core_avail 1
--gpgpu_num_tensor_core_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
--ptx_opcode_latency_tesnor 64
--ptx_opcode_initiation_tensor 64
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 32KB DL1 and 96KB shared memory
-# In Volta, we assign the remaining shared memory to L1 cache 
-# if the assigned shd mem = 0, then L1 cache = 128KB
-# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
-# disable this mode in case of multi kernels/apps execution
--adaptive_volta_cache_config 1
-# Volta unified cache has four ports
--mem_unit_ports 4
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 98304
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 28
--smem_latency 19
--gpgpu_flush_l1_cache 1
-
-# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
--gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
--gpgpu_cache:dl2_texture_only 0
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 1
--memory_partition_indexing 4
-
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-
-# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
-# i.e. schedulers are isolated
--sub_core_model 1
-# disable specialized operand collectors and use generic operand collectors instead
--enable_specialized_operand_collector 0
--gpgpu_operand_collector_num_units_gen 8
--gpgpu_operand_collector_num_in_ports_gen 8
--gpgpu_operand_collector_num_out_ports_gen 8
-# volta has 8 banks, 4 schedulers, two banks per scheduler
--gpgpu_num_reg_banks 8
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Volta, a warp scheduler can issue 1 inst per cycle
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
-# use local xbar interconnection
--network_mode 2 
--inct_in_buffer_limit 512
--inct_out_buffer_limit 512
--inct_subnets 2
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 850 MHZ, Tesla V100 HBM runs at 850 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Volta has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Volta
--power_simulation_enabled 0
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
-- 
cgit v1.3


From dc1d8114a3088de791833c336a2d2484a00a361f Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Tue, 28 May 2019 18:23:28 -0400
Subject: fixing quadro file

---
 configs/tested-cfgs/SM7_QV100/config_volta_islip.icnt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_QV100/config_volta_islip.icnt b/configs/tested-cfgs/SM7_QV100/config_volta_islip.icnt
index f6e0833..5ad7ecd 100644
--- a/configs/tested-cfgs/SM7_QV100/config_volta_islip.icnt
+++ b/configs/tested-cfgs/SM7_QV100/config_volta_islip.icnt
@@ -7,7 +7,7 @@ network_count = 2;
 
 // Topology
 topology = fly;
-k = 164;
+k = 144;
 n = 1;
 
 // Routing
-- 
cgit v1.3


From 17815dfdd7b6e9b558997bc5a9ba157a0493da16 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Fri, 12 Jul 2019 21:31:54 -0400
Subject: fixing device and function parameters config

---
 configs/tested-cfgs/SM2_GTX480/gpgpusim.config |  1 +
 configs/tested-cfgs/SM6_TITANX/gpgpusim.config |  1 +
 configs/tested-cfgs/SM7_QV100/gpgpusim.config  | 11 +++++++----
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config |  3 +++
 libcuda/cuda_runtime_api.cc                    | 21 ++++++++++++---------
 src/gpgpu-sim/gpu-sim.cc                       |  4 ++--
 6 files changed, 26 insertions(+), 15 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index cf3627b..4a7a3c3 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -61,6 +61,7 @@
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
 -gpgpu_cache:dl1  N:32:128:4,L:L:m:N:H,S:64:8,8
 -gpgpu_shmem_size 49152
+-gpgpu_shmem_sizeDefault 49152
 -icnt_flit_size 40
 -gmem_skip_L1D 0
 -gpgpu_n_cluster_ejection_buffer_size 32
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index 2fe898a..e6d8f1d 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -81,6 +81,7 @@
 -gpgpu_cache:dl1PrefL1  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_cache:dl1PrefShared  S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_shmem_size 49152
+-gpgpu_shmem_sizeDefault 49152
 -gpgpu_shmem_size_PrefL1 49152
 -gpgpu_shmem_size_PrefShared 49152
 # By default, L1 cache is disabled in Pascal P102.
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index 1a34d0f..5f64908 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -11,7 +11,7 @@
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 60 
+-gpgpu_ptx_force_max_capability 70 
 
 
 # Device Limits
@@ -21,7 +21,7 @@
 -gpgpu_runtime_pending_launch_count_limit 2048
 
 # Compute Capability
--gpgpu_compute_capability_major 6
+-gpgpu_compute_capability_major 7
 -gpgpu_compute_capability_minor 0
 
 # SASS execution (only supported with CUDA >= 4.0)
@@ -44,12 +44,13 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
--gpgpu_occupancy_sm_number 60
+-gpgpu_registers_per_block 65536
+-gpgpu_occupancy_sm_number 70
 
 # This implies a maximum of 64 warps/SM
 -gpgpu_shader_core_pipeline 2048:32 
 -gpgpu_shader_cta 32
--gpgpu_simd_model 1 
+-gpgpu_simd_model 1
 
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
@@ -91,6 +92,8 @@
 -mem_unit_ports 4
 -gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_shmem_size 98304
+-gpgpu_shmem_sizeDefault 98304
+-gpgpu_shmem_per_block 65536
 -gmem_skip_L1D 0
 -icnt_flit_size 40
 -gpgpu_n_cluster_ejection_buffer_size 32
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index b06f048..6c21dcb 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -44,6 +44,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
+-gpgpu_registers_per_block 65536
 -gpgpu_occupancy_sm_number 70
 
 # This implies a maximum of 64 warps/SM
@@ -91,6 +92,8 @@
 -mem_unit_ports 4
 -gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_shmem_size 98304
+-gpgpu_shmem_sizeDefault 98304
+-gpgpu_shmem_per_block 65536
 -gmem_skip_L1D 0
 -icnt_flit_size 40
 -gpgpu_n_cluster_ejection_buffer_size 32
diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc
index c70a570..45511d4 100644
--- a/libcuda/cuda_runtime_api.cc
+++ b/libcuda/cuda_runtime_api.cc
@@ -383,7 +383,7 @@ struct _cuda_device_id *GPGPUSim_Init()
   	        prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size();
 #endif	
 		prop->sharedMemPerBlock = the_gpu->shared_mem_per_block();
-		prop->regsPerBlock = the_gpu->num_registers_per_core();
+		prop->regsPerBlock = the_gpu->num_registers_per_block();
 		prop->warpSize = the_gpu->wrp_size();
 		prop->clockRate = the_gpu->shader_clock();
 #if (CUDART_VERSION >= 2010)
@@ -1014,7 +1014,7 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic
                 prop = dev->get_prop();
                 switch (attr) {
                 case 1:
-                        *value= prop->maxThreadsDim[0] * prop->maxThreadsDim[1] * prop->maxThreadsDim[2] * prop->maxGridSize[0] * prop->maxGridSize[1] * prop->maxGridSize[2];
+                        *value= prop->maxThreadsPerBlock;
                         break;
                 case 2:
                         *value= prop->maxThreadsDim[0];
@@ -1504,13 +1504,13 @@ __host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun )
 	{
 		dim3 gridDim = config.grid_dim();
 		dim3 blockDim = config.block_dim();
-		if (gridDim.x * gridDim.y * gridDim.z == 0 || blockDim.x * blockDim.y * blockDim.z == 0)
-		{
+		//if (gridDim.x * gridDim.y * gridDim.z == 0 || blockDim.x * blockDim.y * blockDim.z == 0)
+		//{
 			//can't launch
-			printf("can't launch a empty kernel\n");
-			g_cuda_launch_stack.pop_back();
-			return g_last_cudaError = cudaErrorInvalidConfiguration;
-		}
+		//	printf("can't launch a empty kernel\n");
+		//	g_cuda_launch_stack.pop_back();
+		//	return g_last_cudaError = cudaErrorInvalidConfiguration;
+		//}
 	}
 	struct CUstream_st *stream = config.get_stream();
 	if(g_stream_manager->is_blocking())
@@ -3151,9 +3151,12 @@ size_t getMaxThreadsPerBlock(struct cudaFuncAttributes *attr) {
 
   size_t max = prop.maxThreadsPerBlock;
 
-  if ((prop.regsPerBlock / attr->numRegs) < max)
+  if (attr->numRegs && (prop.regsPerBlock / attr->numRegs) < max)
     max = prop.regsPerBlock / attr->numRegs;
 
+  if (attr->sharedSizeBytes && (prop.sharedMemPerBlock / attr->sharedSizeBytes) < max)
+      max = prop.sharedMemPerBlock / attr->sharedSizeBytes;
+
   return max;
 }
 
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 6de5845..72cb32b 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -320,7 +320,7 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-adaptive_volta_cache_config", OPT_BOOL, &adaptive_volta_cache_config,
                  "adaptive_volta_cache_config",
                  "0");
-    option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_sizeDefault,
+    option_parser_register(opp, "-gpgpu_shmem_sizeDefault", OPT_UINT32, &gpgpu_shmem_sizeDefault,
                  "Size of shared memory per shader core (default 16kB)",
                  "16384");
     option_parser_register(opp, "-gpgpu_shmem_size_PrefL1", OPT_UINT32, &gpgpu_shmem_sizePrefL1,
@@ -1065,7 +1065,7 @@ void gpgpu_sim::change_cache_config(FuncCache cache_config)
 	if(cache_config != m_shader_config->m_L1D_config.get_cache_status()){
 		printf("FLUSH L1 Cache at configuration change between kernels\n");
 		for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++) {
-			m_cluster[i]->cache_flush();
+			m_cluster[i]->cache_invalidate();
 	    }
 	}
 
-- 
cgit v1.3


From e5e8fd34aa037aa510fa3936fa133f6b345e1825 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Thu, 18 Jul 2019 17:41:58 -0400
Subject: increase the tex cache in Volta

---
 configs/tested-cfgs/SM7_QV100/gpgpusim.config  | 6 +++---
 configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index 5f64908..b2fe5c0 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -101,7 +101,7 @@
 -smem_latency 19
 -gpgpu_flush_l1_cache 1
 
-# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
+# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache
 -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
 -gpgpu_cache:dl2_texture_only 0
 -gpgpu_dram_partition_queues 64:64:64:64
@@ -110,9 +110,9 @@
 
 # 128 KB Inst.
 -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
+# 128 KB Tex
 # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+-gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2
 # 64 KB Const
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
 
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 6c21dcb..786e75e 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -112,7 +112,7 @@
 -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
 # 48 KB Tex
 # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+-gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2
 # 64 KB Const
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
 
-- 
cgit v1.3


From 8127368f2611b0472dc729f3460ff091e87f51c9 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Sun, 21 Jul 2019 20:54:12 -0400
Subject: fixing cache/mem latency in V100 config

---
 configs/tested-cfgs/SM7_QV100/gpgpusim.config | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'configs')

diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index b2fe5c0..f70ad55 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -97,7 +97,7 @@
 -gmem_skip_L1D 0
 -icnt_flit_size 40
 -gpgpu_n_cluster_ejection_buffer_size 32
--l1_latency 28
+-l1_latency 80
 -smem_latency 19
 -gpgpu_flush_l1_cache 1
 
@@ -144,7 +144,7 @@
 # "-network_mode 2 -inct_in_buffer_limit 512  -inct_out_buffer_limit 512  -inct_subnets 2"
 
 # memory partition latency config 
--rop_latency 120
+-rop_latency 160
 -dram_latency 100
 
 # dram model config
-- 
cgit v1.3