From 6b22d6644e23bbf25e1575498a54e48857aee6be Mon Sep 17 00:00:00 2001 From: Ahmad Alawneh Date: Wed, 18 Jun 2025 23:05:33 -0400 Subject: rename conf (#123) --- .../NVIDIA_A100_80GB_PCIe/gpgpusim.config | 179 --------------------- configs/tested-cfgs/SM80_A100/gpgpusim.config | 179 +++++++++++++++++++++ 2 files changed, 179 insertions(+), 179 deletions(-) delete mode 100644 configs/tested-cfgs/NVIDIA_A100_80GB_PCIe/gpgpusim.config create mode 100644 configs/tested-cfgs/SM80_A100/gpgpusim.config (limited to 'configs') diff --git a/configs/tested-cfgs/NVIDIA_A100_80GB_PCIe/gpgpusim.config b/configs/tested-cfgs/NVIDIA_A100_80GB_PCIe/gpgpusim.config deleted file mode 100644 index 35f6d18..0000000 --- a/configs/tested-cfgs/NVIDIA_A100_80GB_PCIe/gpgpusim.config +++ /dev/null @@ -1,179 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 80 - -# Device Limits --gpgpu_stack_size_limit 1024 --gpgpu_heap_size_limit 8388608 --gpgpu_runtime_sync_depth_limit 2 --gpgpu_runtime_pending_launch_count_limit 2048 --gpgpu_kernel_launch_latency 5000 --gpgpu_TB_launch_latency 0 --gpgpu_max_concurrent_kernel 128 - -# Compute Capability --gpgpu_compute_capability_major 8 --gpgpu_compute_capability_minor 0 - -# PTX execution-driven --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 108 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 40 --gpgpu_n_sub_partition_per_mchannel 2 - -# clock domains -#-gpgpu_clock_domains ::: --gpgpu_clock_domains 1410:1410:1410:1512 - -# shader core pipeline config --gpgpu_shader_registers 65536 --gpgpu_registers_per_block 65536 --gpgpu_occupancy_sm_number 80 - --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE --gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 4 --gpgpu_num_int_units 4 --gpgpu_tensor_core_avail 1 --gpgpu_num_tensor_core_units 4 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit --ptx_opcode_latency_int 4,4,4,4,21 --ptx_opcode_initiation_int 2,2,2,2,2 --ptx_opcode_latency_fp 4,4,4,4,39 --ptx_opcode_initiation_fp 2,2,2,2,4 --ptx_opcode_latency_dp 6,6,6,6,330 --ptx_opcode_initiation_dp 4,4,4,4,130 --ptx_opcode_latency_sfu 23 --ptx_opcode_initiation_sfu 8 --ptx_opcode_latency_tesnor 25 --ptx_opcode_initiation_tensor 16 - -# sub core model: in which each scheduler has its own register file and EUs -# i.e. schedulers are isolated --gpgpu_sub_core_model 1 -# disable specialized operand collectors and use generic operand collectors instead --gpgpu_enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 8 --gpgpu_operand_collector_num_in_ports_gen 8 --gpgpu_operand_collector_num_out_ports_gen 8 -# register banks --gpgpu_num_reg_banks 32 --gpgpu_reg_file_port_throughput 2 - -# warp scheduling --gpgpu_num_sched_per_core 4 --gpgpu_scheduler lrr -# a warp scheduler issue mode --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 - -## L1/shared memory configuration -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# In adaptive cache, we adaptively assign the remaining shared memory to L1 cache -# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x --gpgpu_adaptive_cache_config 1 --gpgpu_shmem_option 0,8,16,32,64,164 --gpgpu_unified_l1d_size 192 -# L1 cache configuration --gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:64,16:0,32 --gpgpu_l1_latency 37 --gpgpu_gmem_skip_L1D 0 --gpgpu_flush_l1_cache 1 --gpgpu_n_cluster_ejection_buffer_size 32 --gpgpu_l1_cache_write_ratio 0 - -# shared memory configuration --gpgpu_shmem_size 167936 --gpgpu_shmem_sizeDefault 167936 --gpgpu_shmem_per_block 49152 --gpgpu_smem_latency 29 -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 80 - -# L2 cache --gpgpu_cache:dl2 S:256:128:16,L:B:m:L:X,A:192:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 --gpgpu_perf_sim_memcpy 1 --gpgpu_memory_partition_indexing 0 - -# 128 KB Inst. --gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 --gpgpu_inst_fetch_throughput 4 -# 128 KB Tex -# Note, TEX is deprected since Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod --gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 -# 64 KB Const --gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 --gpgpu_perfect_inst_const_cache 1 - -# interconnection -# use built-in local xbar --network_mode 2 --icnt_in_buffer_limit 512 --icnt_out_buffer_limit 512 --icnt_subnets 2 --icnt_flit_size 40 --icnt_arbiter_algo 1 - -# memory partition latency config --gpgpu_l2_rop_latency 224 --dram_latency 198 - -# dram sched config --gpgpu_dram_scheduler 1 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 - -# dram model config --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Mem timing --gpgpu_dram_timing_opt nbk=16:CCD=1:RRD=7:RCD=22:RAS=50:RP=22:RC=72:CL=22:WL=4:CDLR=5:WR=19:nbkgrp=4:CCDL=4:RTPL=7 --dram_dual_bus_interface 1 - -# select lower bits for bnkgrp to increase bnkgrp parallelism --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-dram_seperate_write_queue_enable 1 -#-dram_write_queue_size 64:56:32 - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model --power_simulation_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/tested-cfgs/SM80_A100/gpgpusim.config b/configs/tested-cfgs/SM80_A100/gpgpusim.config new file mode 100644 index 0000000..35f6d18 --- /dev/null +++ b/configs/tested-cfgs/SM80_A100/gpgpusim.config @@ -0,0 +1,179 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 80 + +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 +-gpgpu_runtime_sync_depth_limit 2 +-gpgpu_runtime_pending_launch_count_limit 2048 +-gpgpu_kernel_launch_latency 5000 +-gpgpu_TB_launch_latency 0 +-gpgpu_max_concurrent_kernel 128 + +# Compute Capability +-gpgpu_compute_capability_major 8 +-gpgpu_compute_capability_minor 0 + +# PTX execution-driven +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 108 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 40 +-gpgpu_n_sub_partition_per_mchannel 2 + +# clock domains +#-gpgpu_clock_domains ::: +-gpgpu_clock_domains 1410:1410:1410:1512 + +# shader core pipeline config +-gpgpu_shader_registers 65536 +-gpgpu_registers_per_block 65536 +-gpgpu_occupancy_sm_number 80 + +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE +-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 +-gpgpu_num_dp_units 4 +-gpgpu_num_int_units 4 +-gpgpu_tensor_core_avail 1 +-gpgpu_num_tensor_core_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +-ptx_opcode_latency_int 4,4,4,4,21 +-ptx_opcode_initiation_int 2,2,2,2,2 +-ptx_opcode_latency_fp 4,4,4,4,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 6,6,6,6,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 +-ptx_opcode_latency_sfu 23 +-ptx_opcode_initiation_sfu 8 +-ptx_opcode_latency_tesnor 25 +-ptx_opcode_initiation_tensor 16 + +# sub core model: in which each scheduler has its own register file and EUs +# i.e. schedulers are isolated +-gpgpu_sub_core_model 1 +# disable specialized operand collectors and use generic operand collectors instead +-gpgpu_enable_specialized_operand_collector 0 +-gpgpu_operand_collector_num_units_gen 8 +-gpgpu_operand_collector_num_in_ports_gen 8 +-gpgpu_operand_collector_num_out_ports_gen 8 +# register banks +-gpgpu_num_reg_banks 32 +-gpgpu_reg_file_port_throughput 2 + +# warp scheduling +-gpgpu_num_sched_per_core 4 +-gpgpu_scheduler lrr +# a warp scheduler issue mode +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +## L1/shared memory configuration +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# In adaptive cache, we adaptively assign the remaining shared memory to L1 cache +# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x +-gpgpu_adaptive_cache_config 1 +-gpgpu_shmem_option 0,8,16,32,64,164 +-gpgpu_unified_l1d_size 192 +# L1 cache configuration +-gpgpu_l1_banks 4 +-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:64,16:0,32 +-gpgpu_l1_latency 37 +-gpgpu_gmem_skip_L1D 0 +-gpgpu_flush_l1_cache 1 +-gpgpu_n_cluster_ejection_buffer_size 32 +-gpgpu_l1_cache_write_ratio 0 + +# shared memory configuration +-gpgpu_shmem_size 167936 +-gpgpu_shmem_sizeDefault 167936 +-gpgpu_shmem_per_block 49152 +-gpgpu_smem_latency 29 +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 80 + +# L2 cache +-gpgpu_cache:dl2 S:256:128:16,L:B:m:L:X,A:192:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 0 + +# 128 KB Inst. +-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +-gpgpu_inst_fetch_throughput 4 +# 128 KB Tex +# Note, TEX is deprected since Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod +-gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 +-gpgpu_perfect_inst_const_cache 1 + +# interconnection +# use built-in local xbar +-network_mode 2 +-icnt_in_buffer_limit 512 +-icnt_out_buffer_limit 512 +-icnt_subnets 2 +-icnt_flit_size 40 +-icnt_arbiter_algo 1 + +# memory partition latency config +-gpgpu_l2_rop_latency 224 +-dram_latency 198 + +# dram sched config +-gpgpu_dram_scheduler 1 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 192 + +# dram model config +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Mem timing +-gpgpu_dram_timing_opt nbk=16:CCD=1:RRD=7:RCD=22:RAS=50:RP=22:RC=72:CL=22:WL=4:CDLR=5:WR=19:nbkgrp=4:CCDL=4:RTPL=7 +-dram_dual_bus_interface 1 + +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-dram_seperate_write_queue_enable 1 +#-dram_write_queue_size 64:56:32 + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model +-power_simulation_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 -- cgit v1.3