From cdb5aa676caaf72fda2e39b662a3c3fddc93781e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 16 Oct 2019 16:35:03 -0400 Subject: updating l2 indexing, reg file and kernel lat in QV100 config --- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) (limited to 'configs') diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index c0d22ee..9903711 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -13,12 +13,13 @@ -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 70 - # Device Limits -gpgpu_stack_size_limit 1024 -gpgpu_heap_size_limit 8388608 -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 +-gpgpu_kernel_launch_latency 5000 +-gpgpu_TB_launch_latency 2 # Compute Capability -gpgpu_compute_capability_major 7 @@ -107,7 +108,7 @@ -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -perf_sim_memcpy 1 --memory_partition_indexing 4 +-memory_partition_indexing 2 # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 @@ -116,17 +117,18 @@ -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 # 64 KB Const -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 +-perfect_inst_const_cache 1 # Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated -sub_core_model 1 # disable specialized operand collectors and use generic operand collectors instead -enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 8 +-gpgpu_operand_collector_num_units_gen 32 -gpgpu_operand_collector_num_in_ports_gen 8 -gpgpu_operand_collector_num_out_ports_gen 8 # volta has 8 banks, 4 schedulers, two banks per scheduler --gpgpu_num_reg_banks 8 +-gpgpu_num_reg_banks 32 # shared memory bankconflict detection -gpgpu_shmem_num_banks 32 @@ -139,10 +141,14 @@ -gpgpu_dual_issue_diff_exec_units 1 # interconnection --network_mode 1 --inter_config_file config_volta_islip.icnt +#-network_mode 1 +#-inter_config_file config_volta_islip.icnt # for local xbar, use: -# "-network_mode 2 -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 -inct_subnets 2" +-network_mode 2 +-inct_in_buffer_limit 512 +-inct_out_buffer_limit 512 +-inct_subnets 2 +-arbiter_algo 1 # memory partition latency config -rop_latency 160 @@ -159,7 +165,7 @@ -gpgpu_dram_burst_length 2 -dram_data_command_freq_ratio 2 # HBM is DDR -gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS +-gpgpu_mem_addr_mapping dramid@6;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.CBCSSSSS # HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) # Timing for 1 GHZ -- cgit v1.3 From 64ad925bf08bd38ff32a427ac283fe0f4e595b08 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 18 Oct 2019 12:09:33 -0400 Subject: update v100 config and remove TB latency --- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs') diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 9903711..584ef8d 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -19,7 +19,7 @@ -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 -gpgpu_kernel_launch_latency 5000 --gpgpu_TB_launch_latency 2 +-gpgpu_TB_launch_latency 0 # Compute Capability -gpgpu_compute_capability_major 7 -- cgit v1.3 From 8e68772c7c8fc9fe0b7fc62cab76d45190225caf Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 18 Oct 2019 12:18:23 -0400 Subject: adding config to trace-driven mode --- .../SM7_QV100_SASS/config_volta_islip.icnt | 74 +++++++ configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config | 212 +++++++++++++++++++++ 2 files changed, 286 insertions(+) create mode 100644 configs/tested-cfgs/SM7_QV100_SASS/config_volta_islip.icnt create mode 100644 configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config (limited to 'configs') diff --git a/configs/tested-cfgs/SM7_QV100_SASS/config_volta_islip.icnt b/configs/tested-cfgs/SM7_QV100_SASS/config_volta_islip.icnt new file mode 100644 index 0000000..5ad7ecd --- /dev/null +++ b/configs/tested-cfgs/SM7_QV100_SASS/config_volta_islip.icnt @@ -0,0 +1,74 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 144; +n = 1; + +// Routing + +routing_function = dest_tag; + + +// Flow control + +num_vcs = 1; +vc_buf_size = 256; +input_buffer_size = 256; +ejection_buffer_size = 256; +boundary_buffer_size = 256; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config new file mode 100644 index 0000000..e544fe9 --- /dev/null +++ b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config @@ -0,0 +1,212 @@ +# This config models the Volta +# For more info about volta architecture: +# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf +# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf +# https://devblogs.nvidia.com/inside-volta/ +# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 +-trace_driven_mode 1 + +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 +-gpgpu_runtime_sync_depth_limit 2 +-gpgpu_runtime_pending_launch_count_limit 2048 +-gpgpu_kernel_launch_latency 5000 +-gpgpu_TB_launch_latency 0 + +# Compute Capability +-gpgpu_compute_capability_major 7 +-gpgpu_compute_capability_minor 0 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 80 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 32 +-gpgpu_n_sub_partition_per_mchannel 2 + +# volta clock domains +#-gpgpu_clock_domains ::: +# Volta NVIDIA TITANV clock domains are adopted from +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +-gpgpu_clock_domains 1132.0:1132.0:1132.0:850.0 +# boost mode +# -gpgpu_clock_domains 1628.0:1628.0:1628.0:850.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 +-gpgpu_registers_per_block 65536 +-gpgpu_occupancy_sm_number 70 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE +## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 +-gpgpu_num_dp_units 4 +-gpgpu_num_int_units 4 +-gpgpu_tensor_core_avail 1 +-gpgpu_num_tensor_core_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 +-ptx_opcode_latency_sfu 100 +-ptx_opcode_initiation_sfu 8 +-ptx_opcode_latency_tesnor 12 +-ptx_opcode_initiation_tensor 4 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Defualt config is 32KB DL1 and 96KB shared memory +# In Volta, we assign the remaining shared memory to L1 cache +# if the assigned shd mem = 0, then L1 cache = 128KB +# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x +# disable this mode in case of multi kernels/apps execution +-adaptive_cache_config 1 +# Volta unified cache has four banks +-l1_banks 4 +#-mem_unit_ports 4 +-gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_shmem_size 98304 +-gpgpu_shmem_sizeDefault 98304 +-gpgpu_shmem_per_block 65536 +-gmem_skip_L1D 0 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 +-l1_latency 20 +-smem_latency 20 +-gpgpu_flush_l1_cache 1 + +# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache +-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-perf_sim_memcpy 1 +-memory_partition_indexing 2 + +# 128 KB Inst. +-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +# 128 KB Tex +# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod +-gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 +-perfect_inst_const_cache 1 + +# Volta has sub core model, in which each scheduler has its own register file and EUs +# i.e. schedulers are isolated +-sub_core_model 1 +# disable specialized operand collectors and use generic operand collectors instead +-enable_specialized_operand_collector 0 +-gpgpu_operand_collector_num_units_gen 32 +-gpgpu_operand_collector_num_in_ports_gen 8 +-gpgpu_operand_collector_num_out_ports_gen 8 +# volta has 8 banks, 4 schedulers, two banks per scheduler +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +## In Volta, a warp scheduler can issue 1 inst per cycle +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +#-network_mode 1 +#-inter_config_file config_volta_islip.icnt +# for local xbar, use: +-network_mode 2 +-inct_in_buffer_limit 512 +-inct_out_buffer_limit 512 +-inct_subnets 2 +-arbiter_algo 1 + +# memory partition latency config +-rop_latency 160 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 192 + +# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@6;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.CBCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 850 MHZ, V100 HBM runs at 850 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3" + +# HBM has dual bus interface, in which it can issue two col and row commands at a time +-dual_bus_interface 1 +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Volta has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Volta +-power_simulation_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + -- cgit v1.3 From ab4324b69eb4ec7767706d3fb0db7a27c9670431 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 12 Nov 2019 18:35:05 -0500 Subject: updating SASS config for tensor cores --- configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'configs') diff --git a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config index e544fe9..0d4a812 100644 --- a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config @@ -79,8 +79,8 @@ -ptx_opcode_initiation_dp 4,4,4,4,130 -ptx_opcode_latency_sfu 100 -ptx_opcode_initiation_sfu 8 --ptx_opcode_latency_tesnor 12 --ptx_opcode_initiation_tensor 4 +-ptx_opcode_latency_tesnor 6 +-ptx_opcode_initiation_tensor 2 # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo -- cgit v1.3 From b2def455d573f66fbc38dabda4adbc3a56225910 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Sun, 9 Feb 2020 20:39:22 -0500 Subject: adding kepler sass, skip-first-kernel and update config file --- .../SM3_KEPLER_TITAN/config_kepler_islip.icnt | 73 ++++++++ .../tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 186 ++++++++++++++++++++ configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 34 ++-- configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config | 192 +++++++++++++++++++++ configs/tested-cfgs/SM7_QV100/gpgpusim.config | 2 +- configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config | 3 +- .../Turing_RTX2060/config_pascal_islip.icnt | 73 ++++++++ configs/tested-cfgs/Turing_RTX2060/gpgpusim.config | 186 ++++++++++++++++++++ src/gpgpu-sim/gpu-sim.cc | 3 + src/gpgpu-sim/gpu-sim.h | 4 +- src/trace-driven/gpgpusim_trace_driven_main.cc | 6 + src/trace-driven/kepler_opcode.h | 141 +++++++++++++++ src/trace-driven/pascal_opcode.h | 8 +- src/trace-driven/trace_driven.cc | 5 + src/trace-driven/trace_opcode.h | 7 +- 15 files changed, 899 insertions(+), 24 deletions(-) create mode 100644 configs/tested-cfgs/SM3_KEPLER_TITAN/config_kepler_islip.icnt create mode 100644 configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config create mode 100644 configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config create mode 100644 configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt create mode 100644 configs/tested-cfgs/Turing_RTX2060/gpgpusim.config create mode 100644 src/trace-driven/kepler_opcode.h (limited to 'configs') diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/config_kepler_islip.icnt b/configs/tested-cfgs/SM3_KEPLER_TITAN/config_kepler_islip.icnt new file mode 100644 index 0000000..2fe3b53 --- /dev/null +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/config_kepler_islip.icnt @@ -0,0 +1,73 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 38; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 64; +input_buffer_size = 256; +ejection_buffer_size = 64; +boundary_buffer_size = 64; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config new file mode 100644 index 0000000..323d2d9 --- /dev/null +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -0,0 +1,186 @@ +# This config models the KEPLER (TITAN) +# For more info about this card, see Nvidia White paper +# https://wr0.wr.inf.h-brs.de/wr/hardware/nodes3/nvidia/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 35 +-gpgpu_ignore_resources_limitation 1 + +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 +-gpgpu_runtime_sync_depth_limit 2 +-gpgpu_runtime_pending_launch_count_limit 2048 + +# Compute Capability +-gpgpu_compute_capability_major 3 +-gpgpu_compute_capability_minor 5 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +# P102 has two semi-indp scheds per core, and two cores per cluster +-gpgpu_n_clusters 14 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Kepler clock domains +#-gpgpu_clock_domains ::: +# Kepler NVIDIA TITAN clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_700_series +-gpgpu_clock_domains 837.0:837.0:837.0:1502.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 +-gpgpu_occupancy_sm_number 62 + +# This implies a maximum of 32 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 16 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB +## Kepler has 6 SP SIMD units and 2 SFU units per SM. +# There is no int unit in kepler +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 6,4,0,2,1,6,4,0,2,1,12 +-gpgpu_num_sp_units 6 +-gpgpu_num_sfu_units 2 +-gpgpu_num_dp_units 4 + + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 2,8,8,8,130 +-ptx_opcode_initiation_sfu 2 +-ptx_opcode_latency_sfu 200 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# The defulat is to disable the L1 cache, unless cache modifieres are used +-gpgpu_cache:dl1 S:4:128:32,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:4:128:32,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_shmem_size 49152 +-gpgpu_shmem_sizeDefault 49152 +-gpgpu_shmem_size_PrefL1 16384 +-gpgpu_shmem_size_PrefShared 49152 +# By default, L1 cache is disabled in Kepler P102 and only enabled for local memory +# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1 +-gmem_skip_L1D 1 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 +-l1_latency 82 +-smem_latency 24 +-gpgpu_flush_l1_cache 1 + +# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 1.5MB L2 cache +-gpgpu_cache:dl2 S:32:128:16,L:B:m:L:L,A:256:64,16:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 +-perf_sim_memcpy 1 +-memory_partition_indexing 0 + +# 4 KB Inst. +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_operand_collector_num_in_ports_sfu 2 +-gpgpu_operand_collector_num_out_ports_sfu 2 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +# Use kepler Coalsce arhitetecture +-gpgpu_coalesce_arch 35 + +## In Kepler, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 0 + +# interconnection +-network_mode 1 +-inter_config_file config_kepler_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 64 + +# for NVIDIA TITAN, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing, scaled to 2500MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" + +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Kepler TITAN has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Kepler +-power_simulation_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index e6d8f1d..f8689c2 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -25,7 +25,7 @@ # high level architecture configuration # P102 has two semi-indp scheds per core, and two cores per cluster -gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 2 +-gpgpu_n_cores_per_cluster 1 -gpgpu_n_mem 12 -gpgpu_n_sub_partition_per_mchannel 2 @@ -36,12 +36,12 @@ -gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 # shader core pipeline config --gpgpu_shader_registers 32768 +-gpgpu_shader_registers 65536 -gpgpu_occupancy_sm_number 62 # This implies a maximum of 32 warps/SM --gpgpu_shader_core_pipeline 1024:32 --gpgpu_shader_cta 16 +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 -gpgpu_simd_model 1 # Pipeline widths and number of FUs @@ -49,9 +49,9 @@ ## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs # There is no int unit in Pascal ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 2 +-gpgpu_pipeline_widths 4,1,0,4,1,4,1,0,4,1,9 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 -gpgpu_num_dp_units 1 @@ -74,16 +74,14 @@ # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB -# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres are used --gpgpu_cache:dl1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_shmem_size 49152 --gpgpu_shmem_sizeDefault 49152 --gpgpu_shmem_size_PrefL1 49152 --gpgpu_shmem_size_PrefShared 49152 +-gpgpu_cache:dl1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_shmem_size 98304 +-gpgpu_shmem_sizeDefault 98304 +-gpgpu_shmem_size_PrefL1 98304 +-gpgpu_shmem_size_PrefShared 98304 # By default, L1 cache is disabled in Pascal P102. # requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1 -gmem_skip_L1D 1 @@ -136,7 +134,7 @@ # interconnection -network_mode 1 --inter_config_file config_fermi_islip.icnt +-inter_config_file config_pascal_islip.icnt # memory partition latency config -rop_latency 120 @@ -168,7 +166,7 @@ #-Write_Queue_Size 64:56:32 # Pascal 102 has four schedulers per core --gpgpu_num_sched_per_core 2 +-gpgpu_num_sched_per_core 4 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 # Loose round robbin scheduler diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config new file mode 100644 index 0000000..17ad779 --- /dev/null +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config @@ -0,0 +1,192 @@ +# This config models the Pascal GP102 (NVIDIA TITAN X) +# For more info about this card, see Nvidia White paper +# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 61 +-gpgpu_ignore_resources_limitation 1 + +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 +-gpgpu_runtime_sync_depth_limit 2 +-gpgpu_runtime_pending_launch_count_limit 2048 + +# Compute Capability +-gpgpu_compute_capability_major 6 +-gpgpu_compute_capability_minor 1 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +# P102 has two semi-indp scheds per core, and two cores per cluster +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 +-gpgpu_occupancy_sm_number 62 + +# This implies a maximum of 32 warps/SM +-gpgpu_shader_core_pipeline 1024:32 +-gpgpu_shader_cta 16 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs +# There is no int unit in Pascal +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 2 +-gpgpu_num_dp_units 1 + + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,8,8,8,130 +-ptx_opcode_initiation_sfu 4 +-ptx_opcode_latency_sfu 8 + + +# latencies and cache configs are adopted from: +# https://arxiv.org/pdf/1804.06826.pdf +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB +# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache +# The defulat is to disable the L1 cache, unless cache modifieres are used +-gpgpu_cache:dl1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_shmem_size 49152 +-gpgpu_shmem_sizeDefault 49152 +-gpgpu_shmem_size_PrefL1 49152 +-gpgpu_shmem_size_PrefShared 49152 +# By default, L1 cache is disabled in Pascal P102. +# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1 +-gmem_skip_L1D 1 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 +-l1_latency 82 +-smem_latency 24 +-gpgpu_flush_l1_cache 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 +-perf_sim_memcpy 1 +-memory_partition_indexing 0 + +# 4 KB Inst. +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_operand_collector_num_in_ports_sfu 2 +-gpgpu_operand_collector_num_out_ports_sfu 2 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +# Use Pascal Coalsce arhitetecture +-gpgpu_coalesce_arch 61 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_pascal_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 64 + +# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing, scaled to 2500MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" + +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Pascal 102 has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 102 +-power_simulation_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 584ef8d..41aea78 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -165,7 +165,7 @@ -gpgpu_dram_burst_length 2 -dram_data_command_freq_ratio 2 # HBM is DDR -gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@6;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.CBCSSSSS +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS # HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) # Timing for 1 GHZ diff --git a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config index 0d4a812..ba50287 100644 --- a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config @@ -20,7 +20,6 @@ -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 -gpgpu_kernel_launch_latency 5000 --gpgpu_TB_launch_latency 0 # Compute Capability -gpgpu_compute_capability_major 7 @@ -166,7 +165,7 @@ -gpgpu_dram_burst_length 2 -dram_data_command_freq_ratio 2 # HBM is DDR -gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@6;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.CBCSSSSS +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS # HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) # Timing for 1 GHZ diff --git a/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt b/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt new file mode 100644 index 0000000..dec4789 --- /dev/null +++ b/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt @@ -0,0 +1,73 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 64; +input_buffer_size = 256; +ejection_buffer_size = 64; +boundary_buffer_size = 64; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/tested-cfgs/Turing_RTX2060/gpgpusim.config b/configs/tested-cfgs/Turing_RTX2060/gpgpusim.config new file mode 100644 index 0000000..ab324d8 --- /dev/null +++ b/configs/tested-cfgs/Turing_RTX2060/gpgpusim.config @@ -0,0 +1,186 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 +-gpgpu_runtime_sync_depth_limit 2 +-gpgpu_runtime_pending_launch_count_limit 2048 +-gpgpu_kernel_launch_latency 5000 +-gpgpu_TB_launch_latency 0 + +# Compute Capability +-gpgpu_compute_capability_major 7 +-gpgpu_compute_capability_minor 0 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 30 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# volta clock domains +#-gpgpu_clock_domains ::: +# Turing clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_20_series +-gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0 +# boost mode +# -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 +-gpgpu_registers_per_block 65536 +-gpgpu_occupancy_sm_number 70 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE +## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 +-gpgpu_num_dp_units 4 +-gpgpu_num_int_units 4 +-gpgpu_tensor_core_avail 1 +-gpgpu_num_tensor_core_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 +-ptx_opcode_latency_sfu 100 +-ptx_opcode_initiation_sfu 8 +-ptx_opcode_latency_tesnor 64 +-ptx_opcode_initiation_tensor 64 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +-adaptive_cache_config 0 +-l1_banks 4 +-gpgpu_cache:dl1 S:1:128:512,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_sizeDefault 65536 +-gpgpu_shmem_per_block 65536 +-gmem_skip_L1D 0 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 +-l1_latency 20 +-smem_latency 20 +-gpgpu_flush_l1_cache 1 + +# 32 sets, each 128 bytes 32-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache +-gpgpu_cache:dl2 S:32:128:32,L:B:m:L:L,A:192:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-perf_sim_memcpy 1 +-memory_partition_indexing 0 + +# 128 KB Inst. +-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +# 128 KB Tex +# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod +-gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 +-perfect_inst_const_cache 1 + +# i.e. schedulers are isolated +-sub_core_model 1 +# disable specialized operand collectors and use generic operand collectors instead +-enable_specialized_operand_collector 0 +-gpgpu_operand_collector_num_units_gen 32 +-gpgpu_operand_collector_num_in_ports_gen 8 +-gpgpu_operand_collector_num_out_ports_gen 8 +# volta has 8 banks, 4 schedulers, two banks per scheduler +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +## In Volta, a warp scheduler can issue 1 inst per cycle +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +#-network_mode 1 +#-inter_config_file config_volta_islip.icnt +# for local xbar, use: +-network_mode 2 +-inct_in_buffer_limit 512 +-inct_out_buffer_limit 512 +-inct_subnets 2 +-arbiter_algo 1 + +# memory partition latency config +-rop_latency 160 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 192 + +# GDDR6 +# http://monitorinsider.com/GDDR6.html +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 2 +-gpgpu_dram_burst_length 16 +-dram_data_command_freq_ratio 4 # GDDR6 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing, scaled to 3500MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=4:RRD=10:RCD=20:RAS=50:RP=20:RC=62: + CL=20:WL=8:CDLR=9:WR=20:nbkgrp=4:CCDL=4:RTPL=4" + +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Volta has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Volta +-power_simulation_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 7f9985e..4e38f67 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -573,6 +573,9 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) option_parser_register(opp, "-trace_driven_mode", OPT_BOOL, &trace_driven_mode, "Turn on trace_driven_mode", "0"); + option_parser_register(opp, "-trace_skip_first_kernel", OPT_BOOL, + &trace_skip_first_kernel, "skip first intiliztion kernel in trace mode", + "0"); option_parser_register(opp, "-trace", OPT_CSTR, &g_traces_filename, "traces kernel file" "traces kernel file directory", diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 1ac4fdb..abc905e 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -348,7 +348,8 @@ public: size_t sync_depth_limit() const {return runtime_sync_depth_limit; } size_t pending_launch_count_limit() const {return runtime_pending_launch_count_limit;} - unsigned is_trace_driven_mode() const { return trace_driven_mode; } + bool is_trace_driven_mode() const { return trace_driven_mode; } + bool is_skip_first_kernel() const { return trace_skip_first_kernel; } char* get_traces_filename() const { return g_traces_filename; } bool flush_l1() const { return gpgpu_flush_l1_cache; } @@ -408,6 +409,7 @@ private: //trace driven mode options bool trace_driven_mode; + bool trace_skip_first_kernel; char *g_traces_filename; friend class gpgpu_sim; diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc index 68b2ff7..0e3aced 100644 --- a/src/trace-driven/gpgpusim_trace_driven_main.cc +++ b/src/trace-driven/gpgpusim_trace_driven_main.cc @@ -50,6 +50,7 @@ int main ( int argc, const char **argv ) trace_parser tracer(m_gpgpu_sim->get_config().get_traces_filename(), m_gpgpu_sim, m_gpgpu_context); std::vector commandlist = tracer.parse_kernellist_file(); + bool first_kernel=true; for(unsigned i=0; iget_config().is_skip_first_kernel() && first_kernel) { + first_kernel = false; + continue; + } kernel_info = tracer.parse_kernel_info(commandlist[i]); m_gpgpu_sim->launch(kernel_info); } diff --git a/src/trace-driven/kepler_opcode.h b/src/trace-driven/kepler_opcode.h new file mode 100644 index 0000000..f85346f --- /dev/null +++ b/src/trace-driven/kepler_opcode.h @@ -0,0 +1,141 @@ +//developed by Mahmoud Khairy, Purdue Univ +//abdallm@purdue.edu + +#ifndef KEPLER_OPCODE_H +#define KEPLER_OPCODE_H + +#include "../abstract_hardware_model.h" +#include "trace_opcode.h" +#include +#include + +#define KEPLER_BINART_VERSION 35 +#define KEPLER_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 + +//TO DO: moving this to a yml or def files + +///Kepler ISA +//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html +static const std::unordered_map Kepler_OpcodeMap = { + //Floating Point 32 Instructions + {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, + {"FADD", OpcodeChar(OP_FADD, SP_OP)}, + {"FCMP", OpcodeChar(OP_FCMP, SP_OP)}, + {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, + {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, + {"FSWZ", OpcodeChar(OP_FSWZ, SP_OP)}, + {"FSET", OpcodeChar(OP_FSET, SP_OP)}, + {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, + {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, + {"RRO", OpcodeChar(OP_RRO, SP_OP)}, + //SFU + {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, + + + //Double Point Instructions + {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, + {"DADD", OpcodeChar(OP_DADD, DP_OP)}, + {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, + {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)}, + {"DSET", OpcodeChar(OP_DSET, DP_OP)}, + {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, + + //Integer Instructions + {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, + {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)}, + {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, + {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, + {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, + {"ISAD", OpcodeChar(OP_ISAD, INTP_OP)}, + {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, + {"BFE", OpcodeChar(OP_BFE, INTP_OP)}, + {"BFI", OpcodeChar(OP_BFI, INTP_OP)}, + {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, + {"SHL", OpcodeChar(OP_SHL, INTP_OP)}, + {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, + {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, + {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, + {"ISET", OpcodeChar(OP_ISET, INTP_OP)}, + {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, + {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)}, + {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, + + //Conversion Instructions + {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, + {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, + {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, + {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, + + //Movement Instructions + {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, + {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, + {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, + {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, + {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, + + //Predicate Instructions + {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, + {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, + {"CSET", OpcodeChar(OP_CSET, ALU_OP)}, + {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)}, + {"PSET", OpcodeChar(OP_PSET, ALU_OP)}, + {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, + + //Texture Instructions + //For now, we ignore texture loads, consider it as ALU_OP + {"TEX", OpcodeChar(OP_TEX, ALU_OP)}, + {"TLD", OpcodeChar(OP_TLD, ALU_OP)}, + {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)}, + {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)}, + + //Load/Store Instructions + //For now, we ignore constant loads, consider it as ALU_OP, TO DO + {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, + {"LD", OpcodeChar(OP_LD, LOAD_OP)}, + {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, + {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, + {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, + {"LDSLK", OpcodeChar(OP_LDSLK, LOAD_OP)}, + {"ST", OpcodeChar(OP_ST, STORE_OP)}, + {"STL", OpcodeChar(OP_STL, STORE_OP)}, + {"STS", OpcodeChar(OP_STS, STORE_OP)}, + {"STSCUL", OpcodeChar(OP_STSCUL, STORE_OP)}, + {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, + {"RED", OpcodeChar(OP_RED, STORE_OP)}, + {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, + {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, + {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, + + //surface memory instructions + {"SUCLAMP", OpcodeChar(OP_SUCLAMP, LOAD_OP)}, + {"SUBFM", OpcodeChar(OP_SUBFM, LOAD_OP)}, + {"SUEAU", OpcodeChar(OP_SUEAU, LOAD_OP)}, + {"SULDGA", OpcodeChar(OP_SULDGA, LOAD_OP)}, + {"SUSTGA", OpcodeChar(OP_SUSTGA, STORE_OP)}, + + //Control Instructions + {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)}, + {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)}, + {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)}, + {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)}, + {"CAL", OpcodeChar(OP_CAL, CALL_OPS)}, + {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)}, + {"RET", OpcodeChar(OP_RET, RET_OPS)}, + {"BRK", OpcodeChar(OP_BRK, RET_OPS)}, + {"CONT", OpcodeChar(OP_CONT, RET_OPS)}, + {"SSY", OpcodeChar(OP_SSY, RET_OPS)}, + {"PBK", OpcodeChar(OP_PBK, RET_OPS)}, + {"PCNT", OpcodeChar(OP_PCNT, RET_OPS)}, + {"PRET", OpcodeChar(OP_PRET, RET_OPS)}, + {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)}, + {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, + + //Miscellaneous Instructions + {"NOP", OpcodeChar(OP_NOP, ALU_OP)}, + {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, + {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, + {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, + {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, +}; + +#endif diff --git a/src/trace-driven/pascal_opcode.h b/src/trace-driven/pascal_opcode.h index d4f787d..2cacb28 100644 --- a/src/trace-driven/pascal_opcode.h +++ b/src/trace-driven/pascal_opcode.h @@ -70,6 +70,7 @@ static const std::unordered_map Pascal_OpcodeMap = { {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, + {"ISET", OpcodeChar(OP_ISET, INTP_OP)}, {"LEA", OpcodeChar(OP_LEA, INTP_OP)}, {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)}, @@ -85,6 +86,8 @@ static const std::unordered_map Pascal_OpcodeMap = { {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)}, {"SHL", OpcodeChar(OP_SHL, INTP_OP)}, {"XMAD", OpcodeChar(OP_XMAD, INTP_OP)}, + {"VMNMX", OpcodeChar(OP_VMNMX, INTP_OP)}, + //Conversion Instructions {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, @@ -109,7 +112,8 @@ static const std::unordered_map Pascal_OpcodeMap = { {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, {"CSET", OpcodeChar(OP_CSET, ALU_OP)}, {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)}, - {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, + {"PSET", OpcodeChar(OP_PSET, ALU_OP)}, + //Load/Store Instructions {"LD", OpcodeChar(OP_LD, LOAD_OP)}, @@ -157,6 +161,8 @@ static const std::unordered_map Pascal_OpcodeMap = { {"CALL", OpcodeChar(OP_CALL, CALL_OPS)}, {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)}, + {"SSY", OpcodeChar(OP_SSY, BRANCH_OP)}, + {"SYNC", OpcodeChar(OP_SYNC, BRANCH_OP)}, {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)}, {"KILL", OpcodeChar(OP_KILL, BRANCH_OP)}, {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)}, diff --git a/src/trace-driven/trace_driven.cc b/src/trace-driven/trace_driven.cc index fb8afdd..7b5c523 100644 --- a/src/trace-driven/trace_driven.cc +++ b/src/trace-driven/trace_driven.cc @@ -23,6 +23,7 @@ #include "volta_opcode.h" #include "turing_opcode.h" #include "pascal_opcode.h" +#include "kepler_opcode.h" #include "../gpgpusim_entrypoint.h" @@ -221,6 +222,10 @@ trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m OpcodeMap = &Volta_OpcodeMap; else if(m_binary_verion == PASCAL_TITANX_BINART_VERSION || m_binary_verion == PASCAL_P100_BINART_VERSION) OpcodeMap = &Pascal_OpcodeMap; + else if(m_binary_verion == KEPLER_BINART_VERSION) + OpcodeMap = &Kepler_OpcodeMap; + else if(m_binary_verion == TURING_BINART_VERSION) + OpcodeMap = &Turing_OpcodeMap; else assert(0 && "unsupported binary version"); } diff --git a/src/trace-driven/trace_opcode.h b/src/trace-driven/trace_opcode.h index 2b40ace..d60d0ae 100644 --- a/src/trace-driven/trace_opcode.h +++ b/src/trace-driven/trace_opcode.h @@ -10,6 +10,7 @@ enum TraceInstrOpcode { + //volta (common insts for others cards as well) OP_FADD = 1, OP_FADD32I, OP_FCHK, OP_FFMA32I, OP_FFMA, OP_FMNMX, OP_FMUL, OP_FMUL32I, OP_FSEL, OP_FSET, OP_FSETP, OP_FSWZADD, OP_MUFU, OP_HADD2, OP_HADD2_32I, OP_HFMA2, OP_HFMA2_32I, OP_HMUL2, OP_HMUL2_32I, OP_HSET2, OP_HSETP2, OP_HMMA, OP_DADD, OP_DFMA, OP_DMUL, OP_DSETP, @@ -23,8 +24,12 @@ enum TraceInstrOpcode { OP_TMML, OP_TXD, OP_TXQ, OP_BMOV, OP_BPT, OP_BRA, OP_BREAK, OP_BRX, OP_BSSY, OP_BSYNC, OP_CALL, OP_EXIT, OP_JMP, OP_JMX, OP_KILL, OP_NANOSLEEP, OP_RET, OP_RPCMOV, OP_RTT, OP_WARPSYNC, OP_YIELD, OP_B2R, OP_BAR, OP_CS2R, OP_CSMTEST, OP_DEPBAR, OP_GETLMEMBASE, OP_LEPC, OP_NOP, OP_PMTRIG, OP_R2B, OP_S2R, OP_SETCTAID, OP_SETLMEMBASE, OP_VOTE, OP_VOTE_VTG, + //unique insts for pascal OP_RRO, OP_DMNMX, OP_DSET, OP_BFE, OP_BFI, OP_ICMP, OP_IMADSP, OP_SHL, OP_XMAD, OP_CSET, OP_CSETP, - OP_TEXS, OP_TLD4S, OP_TLDS, OP_CAL, OP_JCAL, OP_PRET, OP_BRK, OP_PBK, OP_CONT, OP_PCNT, OP_PEXIT, + OP_TEXS, OP_TLD4S, OP_TLDS, OP_CAL, OP_JCAL, OP_PRET, OP_BRK, OP_PBK, OP_CONT, OP_PCNT, OP_PEXIT, OP_SSY, OP_SYNC, OP_PSET + , OP_VMNMX, OP_ISET, + //unique insts for kepler + OP_FCMP, OP_FSWZ, OP_ISAD, OP_LDSLK, OP_STSCUL, OP_SUCLAMP, OP_SUBFM, OP_SUEAU, OP_SULDGA, OP_SUSTGA, SASS_NUM_OPCODES /* The total number of opcodes. */ }; typedef enum TraceInstrOpcode sass_op_type; -- cgit v1.3 From f9e65c53a29b89c167e713afa6d5eb92709047af Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Thu, 2 Apr 2020 21:23:07 -0400 Subject: updating config files --- .../tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 79 +++++---- configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 88 +++++----- .../SM75_RTX2060/config_turing_islip.icnt | 73 ++++++++ configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 187 +++++++++++++++++++++ configs/tested-cfgs/SM7_QV100/gpgpusim.config | 55 +++--- configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config | 71 ++++---- .../Turing_RTX2060/config_pascal_islip.icnt | 73 -------- configs/tested-cfgs/Turing_RTX2060/gpgpusim.config | 186 -------------------- 8 files changed, 397 insertions(+), 415 deletions(-) create mode 100644 configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt create mode 100644 configs/tested-cfgs/SM75_RTX2060/gpgpusim.config delete mode 100644 configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt delete mode 100644 configs/tested-cfgs/Turing_RTX2060/gpgpusim.config (limited to 'configs') diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config index 323d2d9..1951a3f 100644 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -18,12 +18,13 @@ -gpgpu_compute_capability_major 3 -gpgpu_compute_capability_minor 5 -# SASS execution (only supported with CUDA >= 4.0) +# PTX execution-driven -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 +# SASS trace-driven mode execution +#-trace_driven_mode 1 # high level architecture configuration -# P102 has two semi-indp scheds per core, and two cores per cluster -gpgpu_n_clusters 14 -gpgpu_n_cores_per_cluster 1 -gpgpu_n_mem 12 @@ -46,15 +47,13 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB -## Kepler has 6 SP SIMD units and 2 SFU units per SM. -# There is no int unit in kepler -## we need to scale the number of pipeline registers to be equal to the number of SP units +## Kepler has 6 SP SIMD units, 4 DPs and 2 SFU units per SM. +# There is no INT unit in kepler -gpgpu_pipeline_widths 6,4,0,2,1,6,4,0,2,1,12 -gpgpu_num_sp_units 6 -gpgpu_num_sfu_units 2 -gpgpu_num_dp_units 4 - # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit @@ -68,6 +67,38 @@ -ptx_opcode_initiation_sfu 2 -ptx_opcode_latency_sfu 200 +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_operand_collector_num_in_ports_sfu 2 +-gpgpu_operand_collector_num_out_ports_sfu 2 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +-gpgpu_num_reg_banks 16 +-gpgpu_reg_file_port_throughput 2 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +# Use kepler Coalsce arhitetecture +-gpgpu_coalesce_arch 35 + +## In Kepler, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 0 + +# Kepler TITAN has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Greedy then oldest scheduler +-gpgpu_scheduler gto + # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. @@ -97,37 +128,12 @@ # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +-inst_fetch_throughput 8 # 48 KB Tex -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 # 12 KB Const -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 -# enable operand collector --gpgpu_operand_collector_num_units_sp 12 --gpgpu_operand_collector_num_units_sfu 6 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_units_dp 6 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_operand_collector_num_in_ports_sfu 2 --gpgpu_operand_collector_num_out_ports_sfu 2 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_operand_collector_num_in_ports_dp 1 --gpgpu_operand_collector_num_out_ports_dp 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 -# Use kepler Coalsce arhitetecture --gpgpu_coalesce_arch 35 - -## In Kepler, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 2 --gpgpu_dual_issue_diff_exec_units 0 - # interconnection -network_mode 1 -inter_config_file config_kepler_islip.icnt @@ -161,15 +167,6 @@ #-Seperate_Write_Queue_Enable 1 #-Write_Queue_Size 64:56:32 -# Kepler TITAN has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - # stat collection -gpgpu_memlatency_stat 14 -gpgpu_runtime_stat 500 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index f8689c2..d54b7d4 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -13,6 +13,7 @@ -gpgpu_heap_size_limit 8388608 -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 +-gpgpu_kernel_launch_latency 5000 # Compute Capability -gpgpu_compute_capability_major 6 @@ -23,7 +24,6 @@ -gpgpu_ptx_save_converted_ptxplus 0 # high level architecture configuration -# P102 has two semi-indp scheds per core, and two cores per cluster -gpgpu_n_clusters 28 -gpgpu_n_cores_per_cluster 1 -gpgpu_n_mem 12 @@ -46,35 +46,58 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs -# There is no int unit in Pascal -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,0,4,1,4,1,0,4,1,9 +## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. +# There is no INT unit in Pascal +-gpgpu_pipeline_widths 4,0,0,4,4,4,0,0,4,4,8 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 1 - # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_latency_int 4,13,4,4,145 -ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_latency_fp 4,13,4,4,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,8,8,8,130 -ptx_opcode_initiation_sfu 4 -ptx_opcode_latency_sfu 8 +# in sub_core_model, schedulers are isolated, each scheduler has its own register file and EUs +-sub_core_model 1 +# enable operand collector +# disable specialized operand collectors and use generic operand collectors instead +-enable_specialized_operand_collector 0 +-gpgpu_operand_collector_num_units_gen 8 +-gpgpu_operand_collector_num_in_ports_gen 8 +-gpgpu_operand_collector_num_out_ports_gen 8 +# 16 register banks, 4 banks per subcore +-gpgpu_num_reg_banks 16 +-gpgpu_reg_file_port_throughput 2 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +# Use Pascal Coalsce arhitetecture +-gpgpu_coalesce_arch 61 + +# Pascal 102 has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 1 -# latencies and cache configs are adopted from: -# https://arxiv.org/pdf/1804.06826.pdf +## L1/shared memory configuration # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # The defulat is to disable the L1 cache, unless cache modifieres are used +-l1_banks 2 -gpgpu_cache:dl1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_cache:dl1PrefL1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_cache:dl1PrefShared S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 @@ -92,45 +115,21 @@ -gpgpu_flush_l1_cache 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32 +-gpgpu_cache:dl2 S:1:128:1024,L:B:m:L:L,A:256:64,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 -perf_sim_memcpy 1 --memory_partition_indexing 0 +-memory_partition_indexing 4 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +-inst_fetch_throughput 8 # 48 KB Tex # Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 # 12 KB Const -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 12 --gpgpu_operand_collector_num_units_sfu 6 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_units_dp 6 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_operand_collector_num_in_ports_sfu 2 --gpgpu_operand_collector_num_out_ports_sfu 2 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_operand_collector_num_in_ports_dp 1 --gpgpu_operand_collector_num_out_ports_dp 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 -# Use Pascal Coalsce arhitetecture --gpgpu_coalesce_arch 61 - -## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units --gpgpu_max_insn_issue_per_warp 2 --gpgpu_dual_issue_diff_exec_units 1 +-perfect_inst_const_cache 1 # interconnection -network_mode 1 @@ -165,15 +164,6 @@ #-Seperate_Write_Queue_Enable 1 #-Write_Queue_Size 64:56:32 -# Pascal 102 has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - # stat collection -gpgpu_memlatency_stat 14 -gpgpu_runtime_stat 500 diff --git a/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt b/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt new file mode 100644 index 0000000..eed1c34 --- /dev/null +++ b/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt @@ -0,0 +1,73 @@ +//52*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 64; +input_buffer_size = 256; +ejection_buffer_size = 64; +boundary_buffer_size = 64; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config new file mode 100644 index 0000000..9d3992a --- /dev/null +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -0,0 +1,187 @@ +# This config models the Turing RTX 2060 +# For more info about turing architecture: +# https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf +# "RTX on—The NVIDIA Turing GPU", IEEE MICRO 2020 + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 +-gpgpu_runtime_sync_depth_limit 2 +-gpgpu_runtime_pending_launch_count_limit 2048 +-gpgpu_kernel_launch_latency 5000 + +# Compute Capability +-gpgpu_compute_capability_major 7 +-gpgpu_compute_capability_minor 5 + +# PTX execution-driven +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 +# SASS trace-driven mode execution +#-trace_driven_mode 1 + +# high level architecture configuration +-gpgpu_n_clusters 30 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# volta clock domains +#-gpgpu_clock_domains ::: +-gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0 +# boost mode +# -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 +-gpgpu_registers_per_block 65536 +-gpgpu_occupancy_sm_number 75 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE +## Turing has 4 SP SIMD units, 4 INT units, 4 SFU units, 8 Tensor core units +## We need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,0,4,4,4,4,0,4,4,4,8,4,4 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 +-gpgpu_num_int_units 4 +-gpgpu_tensor_core_avail 1 +-gpgpu_num_tensor_core_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 +-ptx_opcode_latency_sfu 100 +-ptx_opcode_initiation_sfu 8 +-ptx_opcode_latency_tesnor 64 +-ptx_opcode_initiation_tensor 64 + +# Trung has sub core model, in which each scheduler has its own register file and EUs +# i.e. schedulers are isolated +-sub_core_model 1 +# disable specialized operand collectors and use generic operand collectors instead +-enable_specialized_operand_collector 0 +-gpgpu_operand_collector_num_units_gen 8 +-gpgpu_operand_collector_num_in_ports_gen 8 +-gpgpu_operand_collector_num_out_ports_gen 8 +# turing has 8 banks dual-port, 4 schedulers, two banks per scheduler +# we increase #banks to 16 to mitigate the effect of Regisrer File Cache (RFC) which we do not implement in the current version +-gpgpu_num_reg_banks 16 +-gpgpu_reg_file_port_throughput 2 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +## In Turing, a warp scheduler can issue 1 inst per cycle +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +# Turing has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +-adaptive_cache_config 0 +-l1_banks 4 +-gpgpu_cache:dl1 S:1:128:512,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_sizeDefault 65536 +-gpgpu_shmem_per_block 65536 +-gmem_skip_L1D 0 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 +-l1_latency 20 +-smem_latency 20 +-gpgpu_flush_l1_cache 1 + +# 32 sets, each 128 bytes 32-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache +-gpgpu_cache:dl2 S:32:128:32,L:B:m:L:L,A:192:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-perf_sim_memcpy 1 +-memory_partition_indexing 0 + +# 128 KB Inst. +-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +-inst_fetch_throughput 4 +# 128 KB Tex +# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod +-gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 +-perfect_inst_const_cache 1 + +# interconnection +#-network_mode 1 +#-inter_config_file config_turing_islip.icnt +# use built-in local xbar +-network_mode 2 +-inct_in_buffer_limit 512 +-inct_out_buffer_limit 512 +-inct_subnets 2 +-arbiter_algo 1 + +# memory partition latency config +-rop_latency 160 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 192 + +# Turing has GDDR6 +# http://monitorinsider.com/GDDR6.html +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 2 +-gpgpu_dram_burst_length 16 +-dram_data_command_freq_ratio 4 # GDDR6 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing, scaled to 3500MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=4:RRD=10:RCD=20:RAS=50:RP=20:RC=62: + CL=20:WL=8:CDLR=9:WR=20:nbkgrp=4:CCDL=4:RTPL=4" + +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Volta +-power_simulation_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 41aea78..1ed4fb2 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -25,7 +25,7 @@ -gpgpu_compute_capability_major 7 -gpgpu_compute_capability_minor 0 -# SASS execution (only supported with CUDA >= 4.0) +# PTX execution-driven -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 @@ -37,8 +37,6 @@ # volta clock domains #-gpgpu_clock_domains ::: -# Volta NVIDIA TITANV clock domains are adopted from -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) -gpgpu_clock_domains 1132.0:1132.0:1132.0:850.0 # boost mode # -gpgpu_clock_domains 1628.0:1628.0:1628.0:850.0 @@ -68,8 +66,6 @@ # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf -ptx_opcode_latency_int 4,13,4,5,145 -ptx_opcode_initiation_int 2,2,2,2,8 -ptx_opcode_latency_fp 4,13,4,5,39 @@ -81,6 +77,30 @@ -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 +# Volta has sub core model, in which each scheduler has its own register file and EUs +# i.e. schedulers are isolated +-sub_core_model 1 +# disable specialized operand collectors and use generic operand collectors instead +-enable_specialized_operand_collector 0 +-gpgpu_operand_collector_num_units_gen 8 +-gpgpu_operand_collector_num_in_ports_gen 8 +-gpgpu_operand_collector_num_out_ports_gen 8 +# volta has 8 banks, 4 schedulers, two banks per scheduler +# we increase #banks to 16 to mitigate the effect of Regisrer File Cache (RFC) which we do not implement in the current version +-gpgpu_num_reg_banks 16 +-gpgpu_reg_file_port_throughput 2 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +## In Volta, a warp scheduler can issue 1 inst per cycle +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +## L1/shared memory configuration # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo # Defualt config is 32KB DL1 and 96KB shared memory @@ -91,7 +111,6 @@ -adaptive_cache_config 1 # Volta unified cache has four banks -l1_banks 4 -#-mem_unit_ports 4 -gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 @@ -112,6 +131,7 @@ # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +-inst_fetch_throughput 4 # 128 KB Tex # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 @@ -119,31 +139,10 @@ -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 -perfect_inst_const_cache 1 -# Volta has sub core model, in which each scheduler has its own register file and EUs -# i.e. schedulers are isolated --sub_core_model 1 -# disable specialized operand collectors and use generic operand collectors instead --enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 32 --gpgpu_operand_collector_num_in_ports_gen 8 --gpgpu_operand_collector_num_out_ports_gen 8 -# volta has 8 banks, 4 schedulers, two banks per scheduler --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Volta, a warp scheduler can issue 1 inst per cycle --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 - # interconnection #-network_mode 1 #-inter_config_file config_volta_islip.icnt -# for local xbar, use: +# use built-in local xbar -network_mode 2 -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 diff --git a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config index ba50287..0255f76 100644 --- a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config @@ -12,7 +12,6 @@ -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 70 --trace_driven_mode 1 # Device Limits -gpgpu_stack_size_limit 1024 @@ -25,7 +24,8 @@ -gpgpu_compute_capability_major 7 -gpgpu_compute_capability_minor 0 -# SASS execution (only supported with CUDA >= 4.0) +# SASS trace-driven mode support +-trace_driven_mode 1 -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 @@ -37,8 +37,6 @@ # volta clock domains #-gpgpu_clock_domains ::: -# Volta NVIDIA TITANV clock domains are adopted from -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) -gpgpu_clock_domains 1132.0:1132.0:1132.0:850.0 # boost mode # -gpgpu_clock_domains 1628.0:1628.0:1628.0:850.0 @@ -68,8 +66,6 @@ # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf -ptx_opcode_latency_int 4,13,4,5,145 -ptx_opcode_initiation_int 2,2,2,2,8 -ptx_opcode_latency_fp 4,13,4,5,39 @@ -81,6 +77,35 @@ -ptx_opcode_latency_tesnor 6 -ptx_opcode_initiation_tensor 2 +# Volta has sub core model, in which each scheduler has its own register file and EUs +# i.e. schedulers are isolated +-sub_core_model 1 +# disable specialized operand collectors and use generic operand collectors instead +-enable_specialized_operand_collector 0 +-gpgpu_operand_collector_num_units_gen 8 +-gpgpu_operand_collector_num_in_ports_gen 8 +-gpgpu_operand_collector_num_out_ports_gen 8 +# volta has 8 banks, 4 schedulers, two banks per scheduler +# we increase #banks to 16 to mitigate the effect of Regisrer File Cache (RFC) which we do not implement in the current version +-gpgpu_num_reg_banks 16 +-gpgpu_reg_file_port_throughput 2 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +## In Volta, a warp scheduler can issue 1 inst per cycle +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +# Volta has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +## L1/shared memory configuration # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo # Defualt config is 32KB DL1 and 96KB shared memory @@ -91,7 +116,6 @@ -adaptive_cache_config 1 # Volta unified cache has four banks -l1_banks 4 -#-mem_unit_ports 4 -gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 @@ -112,6 +136,7 @@ # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +-inst_fetch_throughput 4 # 128 KB Tex # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 @@ -119,31 +144,10 @@ -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 -perfect_inst_const_cache 1 -# Volta has sub core model, in which each scheduler has its own register file and EUs -# i.e. schedulers are isolated --sub_core_model 1 -# disable specialized operand collectors and use generic operand collectors instead --enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 32 --gpgpu_operand_collector_num_in_ports_gen 8 --gpgpu_operand_collector_num_out_ports_gen 8 -# volta has 8 banks, 4 schedulers, two banks per scheduler --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Volta, a warp scheduler can issue 1 inst per cycle --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 - # interconnection #-network_mode 1 #-inter_config_file config_volta_islip.icnt -# for local xbar, use: +# use built-in local xbar -network_mode 2 -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 @@ -186,15 +190,6 @@ #-Seperate_Write_Queue_Enable 1 #-Write_Queue_Size 64:56:32 -# Volta has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - # stat collection -gpgpu_memlatency_stat 14 -gpgpu_runtime_stat 500 diff --git a/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt b/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt deleted file mode 100644 index dec4789..0000000 --- a/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt +++ /dev/null @@ -1,73 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 40; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 52; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 64; -input_buffer_size = 256; -ejection_buffer_size = 64; -boundary_buffer_size = 64; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 1; -output_speedup = 1; -internal_speedup = 2.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/tested-cfgs/Turing_RTX2060/gpgpusim.config b/configs/tested-cfgs/Turing_RTX2060/gpgpusim.config deleted file mode 100644 index ab324d8..0000000 --- a/configs/tested-cfgs/Turing_RTX2060/gpgpusim.config +++ /dev/null @@ -1,186 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 - -# Device Limits --gpgpu_stack_size_limit 1024 --gpgpu_heap_size_limit 8388608 --gpgpu_runtime_sync_depth_limit 2 --gpgpu_runtime_pending_launch_count_limit 2048 --gpgpu_kernel_launch_latency 5000 --gpgpu_TB_launch_latency 0 - -# Compute Capability --gpgpu_compute_capability_major 7 --gpgpu_compute_capability_minor 0 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 30 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 12 --gpgpu_n_sub_partition_per_mchannel 2 - -# volta clock domains -#-gpgpu_clock_domains ::: -# Turing clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_20_series --gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0 -# boost mode -# -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 --gpgpu_registers_per_block 65536 --gpgpu_occupancy_sm_number 70 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE -## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 4 --gpgpu_num_int_units 4 --gpgpu_tensor_core_avail 1 --gpgpu_num_tensor_core_units 4 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 2,2,2,2,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,4,4,4,130 --ptx_opcode_latency_sfu 100 --ptx_opcode_initiation_sfu 8 --ptx_opcode_latency_tesnor 64 --ptx_opcode_initiation_tensor 64 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo --adaptive_cache_config 0 --l1_banks 4 --gpgpu_cache:dl1 S:1:128:512,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_shmem_size 65536 --gpgpu_shmem_sizeDefault 65536 --gpgpu_shmem_per_block 65536 --gmem_skip_L1D 0 --icnt_flit_size 40 --gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 20 --smem_latency 20 --gpgpu_flush_l1_cache 1 - -# 32 sets, each 128 bytes 32-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache --gpgpu_cache:dl2 S:32:128:32,L:B:m:L:L,A:192:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 1 --memory_partition_indexing 0 - -# 128 KB Inst. --gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 -# 128 KB Tex -# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod --gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 -# 64 KB Const --gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 --perfect_inst_const_cache 1 - -# i.e. schedulers are isolated --sub_core_model 1 -# disable specialized operand collectors and use generic operand collectors instead --enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 32 --gpgpu_operand_collector_num_in_ports_gen 8 --gpgpu_operand_collector_num_out_ports_gen 8 -# volta has 8 banks, 4 schedulers, two banks per scheduler --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Volta, a warp scheduler can issue 1 inst per cycle --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 - -# interconnection -#-network_mode 1 -#-inter_config_file config_volta_islip.icnt -# for local xbar, use: --network_mode 2 --inct_in_buffer_limit 512 --inct_out_buffer_limit 512 --inct_subnets 2 --arbiter_algo 1 - -# memory partition latency config --rop_latency 160 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 - -# GDDR6 -# http://monitorinsider.com/GDDR6.html --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 2 --gpgpu_dram_burst_length 16 --dram_data_command_freq_ratio 4 # GDDR6 is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing, scaled to 3500MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=4:RRD=10:RCD=20:RAS=50:RP=20:RC=62: - CL=20:WL=8:CDLR=9:WR=20:nbkgrp=4:CCDL=4:RTPL=4" - -# select lower bits for bnkgrp to increase bnkgrp parallelism --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Volta has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model for Volta --power_simulation_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - -- cgit v1.3 From fe8dd7eadbb67b9e917c92c9c540812db35fce37 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Thu, 2 Apr 2020 21:41:01 -0400 Subject: updating the turing config --- configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 2 +- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 18 +++++++++--------- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'configs') diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config index 1951a3f..77617d6 100644 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -40,7 +40,7 @@ -gpgpu_shader_registers 65536 -gpgpu_occupancy_sm_number 62 -# This implies a maximum of 32 warps/SM +# This implies a maximum of 64 warps/SM -gpgpu_shader_core_pipeline 2048:32 -gpgpu_shader_cta 16 -gpgpu_simd_model 1 diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 9d3992a..e8329dd 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -1,12 +1,12 @@ # This config models the Turing RTX 2060 # For more info about turing architecture: -# https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf -# "RTX on—The NVIDIA Turing GPU", IEEE MICRO 2020 +# 1- https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf +# 2- "RTX on—The NVIDIA Turing GPU", IEEE MICRO 2020 # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 +-gpgpu_ptx_force_max_capability 75 # Device Limits -gpgpu_stack_size_limit 1024 @@ -33,17 +33,17 @@ # volta clock domains #-gpgpu_clock_domains ::: --gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0 +-gpgpu_clock_domains 1365.0:1365.0:1365.0:7000.0 # boost mode -# -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0 +# -gpgpu_clock_domains 1680.0:1680.0:1680.0:7000.0 # shader core pipeline config -gpgpu_shader_registers 65536 -gpgpu_registers_per_block 65536 -gpgpu_occupancy_sm_number 75 -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 +# This implies a maximum of 32 warps/SM +-gpgpu_shader_core_pipeline 1024:32 -gpgpu_shader_cta 32 -gpgpu_simd_model 1 @@ -89,7 +89,7 @@ -gpgpu_shmem_num_banks 32 -gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 +-gpgpu_coalesce_arch 75 ## In Turing, a warp scheduler can issue 1 inst per cycle -gpgpu_max_insn_issue_per_warp 1 @@ -156,7 +156,7 @@ -gpgpu_n_mem_per_ctrlr 1 -gpgpu_dram_buswidth 2 -gpgpu_dram_burst_length 16 --dram_data_command_freq_ratio 4 # GDDR6 is QDR +-dram_data_command_freq_ratio 2 # GDDR6 is configured as DDR in Turing -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS -- cgit v1.3 From 52204ff08a9c9a21a99fee3f976d2a419c014fec Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 18 May 2020 21:49:34 -0400 Subject: fixing some failing apps --- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 6 +++--- configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config | 4 ++-- src/gpgpu-sim/gpu-sim.cc | 3 ++- src/gpgpu-sim/shader.cc | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) (limited to 'configs') diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index e8329dd..b89971e 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -33,9 +33,9 @@ # volta clock domains #-gpgpu_clock_domains ::: --gpgpu_clock_domains 1365.0:1365.0:1365.0:7000.0 +-gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0 # boost mode -# -gpgpu_clock_domains 1680.0:1680.0:1680.0:7000.0 +# -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0 # shader core pipeline config -gpgpu_shader_registers 65536 @@ -156,7 +156,7 @@ -gpgpu_n_mem_per_ctrlr 1 -gpgpu_dram_buswidth 2 -gpgpu_dram_burst_length 16 --dram_data_command_freq_ratio 2 # GDDR6 is configured as DDR in Turing +-dram_data_command_freq_ratio 4 -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS diff --git a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config index 0255f76..0df3eec 100644 --- a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config @@ -74,8 +74,8 @@ -ptx_opcode_initiation_dp 4,4,4,4,130 -ptx_opcode_latency_sfu 100 -ptx_opcode_initiation_sfu 8 --ptx_opcode_latency_tesnor 6 --ptx_opcode_initiation_tensor 2 +-ptx_opcode_latency_tesnor 8 +-ptx_opcode_initiation_tensor 4 # Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index e5b9c9d..cd5fa56 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1828,7 +1828,8 @@ void shader_core_ctx::dump_warp_state( FILE *fout ) const void gpgpu_sim::perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ) { if (m_memory_config->m_perf_sim_memcpy) { - assert (dst_start_addr % 32 == 0); + //if(!m_config.trace_driven_mode) //in trace-driven mode, CUDA runtime can start nre data structure at any position + // assert (dst_start_addr % 32 == 0); for ( unsigned counter = 0; counter < count; counter += 32 ) { const unsigned wr_addr = dst_start_addr + counter; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index ed0c25e..65ec113 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3091,7 +3091,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const case VOLTA: { //For Volta, we assign the remaining shared memory to L1 cache //For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x - assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared + //assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared //To Do: make it flexible and not tuned to 9KB share memory unsigned max_assoc = m_L1D_config.get_max_assoc(); -- cgit v1.3 From 84213ffa0416139c7711eb0784b8a46b0de8c538 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 22 May 2020 20:16:04 -0400 Subject: code reformatting --- configs/tested-cfgs/SM2_GTX480/gpgpusim.config | 12 +- .../tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 21 ++- configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 35 ++-- configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config | 192 ------------------- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 73 ++++---- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 61 +++--- .../SM7_QV100_SASS/config_volta_islip.icnt | 74 -------- configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config | 206 --------------------- .../tested-cfgs/SM7_TITANV/config_volta_islip.icnt | 74 -------- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 205 -------------------- src/abstract_hardware_model.h | 2 +- src/gpgpu-sim/addrdec.cc | 2 +- src/gpgpu-sim/gpu-sim.cc | 51 +++-- src/gpgpu-sim/icnt_wrapper.cc | 12 +- src/gpgpu-sim/shader.cc | 2 +- src/gpgpu-sim/shader.h | 7 + src/trace-driven/gpgpusim_trace_driven_main.cc | 3 +- src/trace-driven/kepler_opcode.h | 5 +- src/trace-driven/trace_driven.cc | 104 ++++------- src/trace-driven/trace_driven.h | 28 ++- 20 files changed, 225 insertions(+), 944 deletions(-) delete mode 100644 configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config delete mode 100644 configs/tested-cfgs/SM7_QV100_SASS/config_volta_islip.icnt delete mode 100644 configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config delete mode 100644 configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt delete mode 100644 configs/tested-cfgs/SM7_TITANV/gpgpusim.config (limited to 'configs') diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config index 4a7a3c3..5a12e2e 100644 --- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config +++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config @@ -63,10 +63,10 @@ -gpgpu_shmem_size 49152 -gpgpu_shmem_sizeDefault 49152 -icnt_flit_size 40 --gmem_skip_L1D 0 +-gpgpu_gmem_skip_L1D 0 -gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 35 --smem_latency 26 +-gpgpu_l1_latency 35 +-gpgpu_smem_latency 26 -gpgpu_flush_l1_cache 1 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected @@ -77,8 +77,8 @@ -gpgpu_cache:dl2 S:64:128:8,L:B:m:L:L,A:256:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 1 --memory_partition_indexing 0 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 0 -gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4 -gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,T:128:4,128:2 @@ -104,7 +104,7 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 +-gpgpu_l2_rop_latency 120 -dram_latency 100 # dram model config diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config index 77617d6..b7c0edc 100644 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -67,6 +67,11 @@ -ptx_opcode_initiation_sfu 2 -ptx_opcode_latency_sfu 200 +-trace_opcode_latency_initiation_int 4,1 +-trace_opcode_latency_initiation_sp 4,1 +-trace_opcode_latency_initiation_dp 20,2 +-trace_opcode_latency_initiation_sfu 200,2 + # enable operand collector -gpgpu_operand_collector_num_units_sp 12 -gpgpu_operand_collector_num_units_sfu 6 @@ -112,10 +117,10 @@ -gpgpu_shmem_size_PrefShared 49152 # By default, L1 cache is disabled in Kepler P102 and only enabled for local memory # requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1 --gmem_skip_L1D 1 +-gpgpu_gmem_skip_L1D 1 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 82 +-gpgpu_l1_latency 82 -smem_latency 24 -gpgpu_flush_l1_cache 1 @@ -123,12 +128,12 @@ -gpgpu_cache:dl2 S:32:128:16,L:B:m:L:L,A:256:64,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 --perf_sim_memcpy 1 --memory_partition_indexing 0 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 0 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 --inst_fetch_throughput 8 +-gpgpu_inst_fetch_throughput 8 # 48 KB Tex -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 # 12 KB Const @@ -139,7 +144,7 @@ -inter_config_file config_kepler_islip.icnt # memory partition latency config --rop_latency 120 +-gpgpu_l2_rop_latency 120 -dram_latency 100 # dram model config @@ -164,8 +169,8 @@ -dram_bnk_indexing_policy 0 -dram_bnkgrp_indexing_policy 1 -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 +#-dram_seperate_write_queue_enable 1 +#-dram_write_queue_size 64:56:32 # stat collection -gpgpu_memlatency_stat 14 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index d54b7d4..adbf66c 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -22,6 +22,8 @@ # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 +# SASS trace-driven mode execution +#-trace_driven_mode 1 # high level architecture configuration -gpgpu_n_clusters 28 @@ -62,13 +64,18 @@ -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,8,8,8,130 -ptx_opcode_initiation_sfu 4 --ptx_opcode_latency_sfu 8 +-ptx_opcode_latency_sfu 20 + +-trace_opcode_latency_initiation_int 4,1 +-trace_opcode_latency_initiation_sp 4,1 +-trace_opcode_latency_initiation_dp 20,8 +-trace_opcode_latency_initiation_sfu 20,4 # in sub_core_model, schedulers are isolated, each scheduler has its own register file and EUs --sub_core_model 1 +-gpgpu_sub_core_model 1 # enable operand collector # disable specialized operand collectors and use generic operand collectors instead --enable_specialized_operand_collector 0 +-gpgpu_enable_specialized_operand_collector 0 -gpgpu_operand_collector_num_units_gen 8 -gpgpu_operand_collector_num_in_ports_gen 8 -gpgpu_operand_collector_num_out_ports_gen 8 @@ -97,7 +104,7 @@ # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # The defulat is to disable the L1 cache, unless cache modifieres are used --l1_banks 2 +-gpgpu_l1_banks 2 -gpgpu_cache:dl1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_cache:dl1PrefL1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_cache:dl1PrefShared S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 @@ -107,36 +114,36 @@ -gpgpu_shmem_size_PrefShared 98304 # By default, L1 cache is disabled in Pascal P102. # requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1 --gmem_skip_L1D 1 +-gpgpu_gmem_skip_L1D 1 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 82 --smem_latency 24 +-gpgpu_l1_latency 82 +-gpgpu_smem_latency 24 -gpgpu_flush_l1_cache 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache -gpgpu_cache:dl2 S:1:128:1024,L:B:m:L:L,A:256:64,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 --perf_sim_memcpy 1 --memory_partition_indexing 4 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 4 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 --inst_fetch_throughput 8 +-gpgpu_inst_fetch_throughput 8 # 48 KB Tex # Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 # 12 KB Const -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 --perfect_inst_const_cache 1 +-gpgpu_perfect_inst_const_cache 1 # interconnection -network_mode 1 -inter_config_file config_pascal_islip.icnt # memory partition latency config --rop_latency 120 +-gpgpu_l2_rop_latency 120 -dram_latency 100 # dram model config @@ -161,8 +168,8 @@ -dram_bnk_indexing_policy 0 -dram_bnkgrp_indexing_policy 1 -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 +#-dram_seperate_write_queue_enable 1 +#-dram_write_queue_size 64:56:32 # stat collection -gpgpu_memlatency_stat 14 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config deleted file mode 100644 index 17ad779..0000000 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config +++ /dev/null @@ -1,192 +0,0 @@ -# This config models the Pascal GP102 (NVIDIA TITAN X) -# For more info about this card, see Nvidia White paper -# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 61 --gpgpu_ignore_resources_limitation 1 - -# Device Limits --gpgpu_stack_size_limit 1024 --gpgpu_heap_size_limit 8388608 --gpgpu_runtime_sync_depth_limit 2 --gpgpu_runtime_pending_launch_count_limit 2048 - -# Compute Capability --gpgpu_compute_capability_major 6 --gpgpu_compute_capability_minor 1 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration -# P102 has two semi-indp scheds per core, and two cores per cluster --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 12 --gpgpu_n_sub_partition_per_mchannel 2 - -# Pascal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA TITAN X clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 - -# shader core pipeline config --gpgpu_shader_registers 32768 --gpgpu_occupancy_sm_number 62 - -# This implies a maximum of 32 warps/SM --gpgpu_shader_core_pipeline 1024:32 --gpgpu_shader_cta 16 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs -# There is no int unit in Pascal -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 2 --gpgpu_num_dp_units 1 - - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,8,8,8,130 --ptx_opcode_initiation_sfu 4 --ptx_opcode_latency_sfu 8 - - -# latencies and cache configs are adopted from: -# https://arxiv.org/pdf/1804.06826.pdf -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB -# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache -# The defulat is to disable the L1 cache, unless cache modifieres are used --gpgpu_cache:dl1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_shmem_size 49152 --gpgpu_shmem_sizeDefault 49152 --gpgpu_shmem_size_PrefL1 49152 --gpgpu_shmem_size_PrefShared 49152 -# By default, L1 cache is disabled in Pascal P102. -# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1 --gmem_skip_L1D 1 --icnt_flit_size 40 --gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 82 --smem_latency 24 --gpgpu_flush_l1_cache 1 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 32:32:32:32 --perf_sim_memcpy 1 --memory_partition_indexing 0 - -# 4 KB Inst. --gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 -# 48 KB Tex -# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod --gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 12 --gpgpu_operand_collector_num_units_sfu 6 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_units_dp 6 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_operand_collector_num_in_ports_sfu 2 --gpgpu_operand_collector_num_out_ports_sfu 2 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_operand_collector_num_in_ports_dp 1 --gpgpu_operand_collector_num_out_ports_dp 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 -# Use Pascal Coalsce arhitetecture --gpgpu_coalesce_arch 61 - -## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units --gpgpu_max_insn_issue_per_warp 2 --gpgpu_dual_issue_diff_exec_units 1 - -# interconnection --network_mode 1 --inter_config_file config_pascal_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 64 - -# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) -# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition -# the atom size of GDDR5X (the smallest read request) is 32 bytes --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5X is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing, scaled to 2500MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: - CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" - --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Pascal 102 has four schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model for Pascal 102 --power_simulation_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index b89971e..75b3c99 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -72,11 +72,31 @@ -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 +-trace_opcode_latency_initiation_int 4,2 +-trace_opcode_latency_initiation_sp 4,2 +-trace_opcode_latency_initiation_dp 8,4 +-trace_opcode_latency_initiation_sfu 20,8 +-trace_opcode_latency_initiation_tensor 8,4 + +# Turing has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Greedy then oldest scheduler +-gpgpu_scheduler gto +## In Turing, a warp scheduler can issue 1 inst per cycle +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 75 + # Trung has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated --sub_core_model 1 +-gpgpu_sub_core_model 1 # disable specialized operand collectors and use generic operand collectors instead --enable_specialized_operand_collector 0 +-gpgpu_enable_specialized_operand_collector 0 -gpgpu_operand_collector_num_units_gen 8 -gpgpu_operand_collector_num_in_ports_gen 8 -gpgpu_operand_collector_num_out_ports_gen 8 @@ -85,65 +105,50 @@ -gpgpu_num_reg_banks 16 -gpgpu_reg_file_port_throughput 2 -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 75 - -## In Turing, a warp scheduler can issue 1 inst per cycle --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 - -# Turing has four schedulers per core --gpgpu_num_sched_per_core 4 -# Greedy then oldest scheduler --gpgpu_scheduler gto - # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo --adaptive_cache_config 0 --l1_banks 4 +-gpgpu_adaptive_cache_config 0 +-gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:1:128:512,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 65536 -gpgpu_shmem_sizeDefault 65536 -gpgpu_shmem_per_block 65536 --gmem_skip_L1D 0 --icnt_flit_size 40 +-gpgpu_gmem_skip_L1D 0 -gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 20 --smem_latency 20 +-gpgpu_l1_latency 20 +-gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 32-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache -gpgpu_cache:dl2 S:32:128:32,L:B:m:L:L,A:192:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 1 --memory_partition_indexing 0 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 0 # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 --inst_fetch_throughput 4 +-gpgpu_inst_fetch_throughput 4 # 128 KB Tex # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 # 64 KB Const -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 --perfect_inst_const_cache 1 +-gpgpu_perfect_inst_const_cache 1 # interconnection #-network_mode 1 #-inter_config_file config_turing_islip.icnt # use built-in local xbar -network_mode 2 --inct_in_buffer_limit 512 --inct_out_buffer_limit 512 --inct_subnets 2 --arbiter_algo 1 +-icnt_in_buffer_limit 512 +-icnt_out_buffer_limit 512 +-icnt_subnets 2 +-icnt_arbiter_algo 1 +-icnt_flit_size 40 # memory partition latency config --rop_latency 160 +-gpgpu_l2_rop_latency 160 -dram_latency 100 # dram model config @@ -168,8 +173,8 @@ -dram_bnk_indexing_policy 0 -dram_bnkgrp_indexing_policy 1 -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 +#-dram_seperate_write_queue_enable 1 +#-dram_write_queue_size 64:56:32 # stat collection -gpgpu_memlatency_stat 14 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 1ed4fb2..30b7d13 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -28,6 +28,8 @@ # PTX execution-driven -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 +# SASS trace-driven mode support +#-trace_driven_mode 1 # high level architecture configuration -gpgpu_n_clusters 80 @@ -77,11 +79,17 @@ -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 +-trace_opcode_latency_initiation_int 4,2 +-trace_opcode_latency_initiation_sp 4,2 +-trace_opcode_latency_initiation_dp 8,4 +-trace_opcode_latency_initiation_sfu 20,8 +-trace_opcode_latency_initiation_tensor 8,4 + # Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated --sub_core_model 1 +-gpgpu_sub_core_model 1 # disable specialized operand collectors and use generic operand collectors instead --enable_specialized_operand_collector 0 +-gpgpu_enable_specialized_operand_collector 0 -gpgpu_operand_collector_num_units_gen 8 -gpgpu_operand_collector_num_in_ports_gen 8 -gpgpu_operand_collector_num_out_ports_gen 8 @@ -96,6 +104,10 @@ -gpgpu_shmem_warp_parts 1 -gpgpu_coalesce_arch 60 +# Volta has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Greedy then oldest scheduler +-gpgpu_scheduler gto ## In Volta, a warp scheduler can issue 1 inst per cycle -gpgpu_max_insn_issue_per_warp 1 -gpgpu_dual_issue_diff_exec_units 1 @@ -108,49 +120,49 @@ # if the assigned shd mem = 0, then L1 cache = 128KB # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution --adaptive_cache_config 1 +-gpgpu_adaptive_cache_config 1 # Volta unified cache has four banks --l1_banks 4 +-gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 -gpgpu_shmem_per_block 65536 --gmem_skip_L1D 0 --icnt_flit_size 40 +-gpgpu_gmem_skip_L1D 0 -gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 20 --smem_latency 20 +-gpgpu_l1_latency 20 +-gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 1 --memory_partition_indexing 2 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 2 # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 --inst_fetch_throughput 4 +-gpgpu_inst_fetch_throughput 4 # 128 KB Tex # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 # 64 KB Const -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 --perfect_inst_const_cache 1 +-gpgpu_perfect_inst_const_cache 1 # interconnection #-network_mode 1 #-inter_config_file config_volta_islip.icnt # use built-in local xbar -network_mode 2 --inct_in_buffer_limit 512 --inct_out_buffer_limit 512 --inct_subnets 2 --arbiter_algo 1 +-icnt_in_buffer_limit 512 +-icnt_out_buffer_limit 512 +-icnt_subnets 2 +-icnt_flit_size 40 +-icnt_arbiter_algo 1 # memory partition latency config --rop_latency 160 +-gpgpu_l2_rop_latency 160 -dram_latency 100 # dram model config @@ -177,22 +189,13 @@ CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3" # HBM has dual bus interface, in which it can issue two col and row commands at a time --dual_bus_interface 1 +-dram_dual_bus_interface 1 # select lower bits for bnkgrp to increase bnkgrp parallelism -dram_bnk_indexing_policy 0 -dram_bnkgrp_indexing_policy 1 -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Volta has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto +#-dram_seperate_write_queue_enable 1 +#-dram_write_queue_size 64:56:32 # stat collection -gpgpu_memlatency_stat 14 diff --git a/configs/tested-cfgs/SM7_QV100_SASS/config_volta_islip.icnt b/configs/tested-cfgs/SM7_QV100_SASS/config_volta_islip.icnt deleted file mode 100644 index 5ad7ecd..0000000 --- a/configs/tested-cfgs/SM7_QV100_SASS/config_volta_islip.icnt +++ /dev/null @@ -1,74 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 40; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 144; -n = 1; - -// Routing - -routing_function = dest_tag; - - -// Flow control - -num_vcs = 1; -vc_buf_size = 256; -input_buffer_size = 256; -ejection_buffer_size = 256; -boundary_buffer_size = 256; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 1; -output_speedup = 1; -internal_speedup = 2.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config deleted file mode 100644 index 0df3eec..0000000 --- a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config +++ /dev/null @@ -1,206 +0,0 @@ -# This config models the Volta -# For more info about volta architecture: -# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf -# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) -# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf -# https://devblogs.nvidia.com/inside-volta/ -# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 - -# Device Limits --gpgpu_stack_size_limit 1024 --gpgpu_heap_size_limit 8388608 --gpgpu_runtime_sync_depth_limit 2 --gpgpu_runtime_pending_launch_count_limit 2048 --gpgpu_kernel_launch_latency 5000 - -# Compute Capability --gpgpu_compute_capability_major 7 --gpgpu_compute_capability_minor 0 - -# SASS trace-driven mode support --trace_driven_mode 1 --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 80 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 32 --gpgpu_n_sub_partition_per_mchannel 2 - -# volta clock domains -#-gpgpu_clock_domains ::: --gpgpu_clock_domains 1132.0:1132.0:1132.0:850.0 -# boost mode -# -gpgpu_clock_domains 1628.0:1628.0:1628.0:850.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 --gpgpu_registers_per_block 65536 --gpgpu_occupancy_sm_number 70 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE -## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 4 --gpgpu_num_int_units 4 --gpgpu_tensor_core_avail 1 --gpgpu_num_tensor_core_units 4 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 2,2,2,2,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,4,4,4,130 --ptx_opcode_latency_sfu 100 --ptx_opcode_initiation_sfu 8 --ptx_opcode_latency_tesnor 8 --ptx_opcode_initiation_tensor 4 - -# Volta has sub core model, in which each scheduler has its own register file and EUs -# i.e. schedulers are isolated --sub_core_model 1 -# disable specialized operand collectors and use generic operand collectors instead --enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 8 --gpgpu_operand_collector_num_in_ports_gen 8 --gpgpu_operand_collector_num_out_ports_gen 8 -# volta has 8 banks, 4 schedulers, two banks per scheduler -# we increase #banks to 16 to mitigate the effect of Regisrer File Cache (RFC) which we do not implement in the current version --gpgpu_num_reg_banks 16 --gpgpu_reg_file_port_throughput 2 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Volta, a warp scheduler can issue 1 inst per cycle --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 - -# Volta has four schedulers per core --gpgpu_num_sched_per_core 4 -# Greedy then oldest scheduler --gpgpu_scheduler gto - -## L1/shared memory configuration -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Defualt config is 32KB DL1 and 96KB shared memory -# In Volta, we assign the remaining shared memory to L1 cache -# if the assigned shd mem = 0, then L1 cache = 128KB -# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x -# disable this mode in case of multi kernels/apps execution --adaptive_cache_config 1 -# Volta unified cache has four banks --l1_banks 4 --gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_shmem_size 98304 --gpgpu_shmem_sizeDefault 98304 --gpgpu_shmem_per_block 65536 --gmem_skip_L1D 0 --icnt_flit_size 40 --gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 20 --smem_latency 20 --gpgpu_flush_l1_cache 1 - -# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache --gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 1 --memory_partition_indexing 2 - -# 128 KB Inst. --gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 --inst_fetch_throughput 4 -# 128 KB Tex -# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod --gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 -# 64 KB Const --gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 --perfect_inst_const_cache 1 - -# interconnection -#-network_mode 1 -#-inter_config_file config_volta_islip.icnt -# use built-in local xbar --network_mode 2 --inct_in_buffer_limit 512 --inct_out_buffer_limit 512 --inct_subnets 2 --arbiter_algo 1 - -# memory partition latency config --rop_latency 160 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 - -# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 # HBM is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS - -# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) -# Timing for 1 GHZ -# tRRDl and tWTR are missing, need to be added -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: -# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" - -# Timing for 850 MHZ, V100 HBM runs at 850 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3" - -# HBM has dual bus interface, in which it can issue two col and row commands at a time --dual_bus_interface 1 -# select lower bits for bnkgrp to increase bnkgrp parallelism --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model for Volta --power_simulation_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt deleted file mode 100644 index 615d0a9..0000000 --- a/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt +++ /dev/null @@ -1,74 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 40; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 88; -n = 1; - -// Routing - -routing_function = dest_tag; - - -// Flow control - -num_vcs = 1; -vc_buf_size = 256; -input_buffer_size = 256; -ejection_buffer_size = 256; -boundary_buffer_size = 256; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 1; -output_speedup = 1; -internal_speedup = 2.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config deleted file mode 100644 index 0339b0d..0000000 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ /dev/null @@ -1,205 +0,0 @@ -# This config models the Volta Titan V -# For more info about volta architecture: -# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf -# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) -# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf -# https://devblogs.nvidia.com/inside-volta/ -# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 - - -# Device Limits --gpgpu_stack_size_limit 1024 --gpgpu_heap_size_limit 8388608 --gpgpu_runtime_sync_depth_limit 2 --gpgpu_runtime_pending_launch_count_limit 2048 - -# Compute Capability --gpgpu_compute_capability_major 7 --gpgpu_compute_capability_minor 0 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 40 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 24 --gpgpu_n_sub_partition_per_mchannel 2 - -# volta clock domains -#-gpgpu_clock_domains ::: -# Volta NVIDIA TITANV clock domains are adopted from -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) --gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0 -# boost mode -# -gpgpu_clock_domains 1455.0:1455.0:1455.0:850.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 --gpgpu_registers_per_block 65536 --gpgpu_occupancy_sm_number 70 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE -## Volta TITANV has 4 SP SIMD units, 4 INT units, 4 SFU units, 4 DP units per core, 4 Tensor core units -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 4 --gpgpu_num_int_units 4 --gpgpu_tensor_core_avail 1 --gpgpu_num_tensor_core_units 4 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 2,2,2,2,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,4,4,4,130 --ptx_opcode_latency_sfu 100 --ptx_opcode_initiation_sfu 8 --ptx_opcode_latency_tesnor 64 --ptx_opcode_initiation_tensor 64 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Defualt config is 32KB DL1 and 96KB shared memory -# In Volta, we assign the remaining shared memory to L1 cache -# if the assigned shd mem = 0, then L1 cache = 128KB -# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x -# disable this mode in case of multi kernels/apps execution --adaptive_cache_config 1 -# Volta unified cache has four banks --l1_banks 4 -#-mem_unit_ports 4 --gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_shmem_size 98304 --gpgpu_shmem_sizeDefault 98304 --gpgpu_shmem_per_block 65536 --gmem_skip_L1D 0 --icnt_flit_size 40 --gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 20 --smem_latency 20 --gpgpu_flush_l1_cache 1 - -# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache --gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 1 --memory_partition_indexing 4 - -# 128 KB Inst. --gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 -# 48 KB Tex -# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod --gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 -# 64 KB Const --gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 - -# Volta has sub core model, in which each scheduler has its own register file and EUs -# i.e. schedulers are isolated --sub_core_model 1 -# disable specialized operand collectors and use generic operand collectors instead --enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 8 --gpgpu_operand_collector_num_in_ports_gen 8 --gpgpu_operand_collector_num_out_ports_gen 8 -# volta has 8 banks, 4 schedulers, two banks per scheduler --gpgpu_num_reg_banks 8 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Volta, a warp scheduler can issue 1 inst per cycle --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 - -# interconnection --network_mode 1 --inter_config_file config_volta_islip.icnt -# for local xbar, use: -# "-network_mode 2 -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 -inct_subnets 2" - -# memory partition latency config --rop_latency 160 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 - -# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 # HBM is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS - -# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) -# Timing for 1 GHZ -# tRRDl and tWTR are missing, need to be added -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: -# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" - -# Timing for 850 MHZ, TITANV HBM runs at 850 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3" - -# HBM has dual bus interface, in which it can issue two col and row commands at a time --dual_bus_interface 1 -# select lower bits for bnkgrp to increase bnkgrp parallelism --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Volta has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model for Volta --power_simulation_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 135b03b..6c19e2d 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -70,7 +70,7 @@ enum FuncCache enum AdaptiveCache { FIXED = 0, - VOLTA = 1 + ADAPTIVE_VOLTA = 1 }; #ifdef __cplusplus diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc index c34cb32..d430568 100644 --- a/src/gpgpu-sim/addrdec.cc +++ b/src/gpgpu-sim/addrdec.cc @@ -63,7 +63,7 @@ void linear_to_raw_address_translation::addrdec_setoption(option_parser_t opp) option_parser_register(opp, "-gpgpu_mem_address_mask", OPT_INT32, &gpgpu_mem_address_mask, "0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits", "0"); - option_parser_register(opp, "-memory_partition_indexing", OPT_UINT32, &memory_partition_indexing, + option_parser_register(opp, "-gpgpu_memory_partition_indexing", OPT_UINT32, &memory_partition_indexing, "0 = no indexing, 1 = bitwise xoring, 2 = IPoly, 3 = custom indexing", "0"); } diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index cd5fa56..641ddbc 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -137,9 +137,9 @@ void power_config::reg_options(class OptionParser * opp) void memory_config::reg_options(class OptionParser * opp) { - option_parser_register(opp, "-perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, + option_parser_register(opp, "-gpgpu_perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, "Fill the L2 cache on memcpy", "1"); - option_parser_register(opp, "-simple_dram_model", OPT_BOOL, &simple_dram_model, + option_parser_register(opp, "-gpgpu_simple_dram_model", OPT_BOOL, &simple_dram_model, "simple_dram_model with fixed latency and BW", "0"); option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, &scheduler_type, "0 = fifo, 1 = FR-FCFS (defaul)", "1"); @@ -187,13 +187,13 @@ void memory_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_dram_timing_opt", OPT_CSTR, &gpgpu_dram_timing_opt, "DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}", "4:2:8:12:21:13:34:9:4:5:13:1:0:0"); - option_parser_register(opp, "-rop_latency", OPT_UINT32, &rop_latency, + option_parser_register(opp, "-gpgpu_l2_rop_latency", OPT_UINT32, &rop_latency, "ROP queue latency (default 85)", "85"); option_parser_register(opp, "-dram_latency", OPT_UINT32, &dram_latency, "DRAM latency (default 30)", "30"); - option_parser_register(opp, "-dual_bus_interface", OPT_UINT32, &dual_bus_interface, + option_parser_register(opp, "-dram_dual_bus_interface", OPT_UINT32, &dual_bus_interface, "dual_bus_interface (default = 0) ", "0"); option_parser_register(opp, "-dram_bnk_indexing_policy", OPT_UINT32, &dram_bnk_indexing_policy, @@ -202,13 +202,13 @@ void memory_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-dram_bnkgrp_indexing_policy", OPT_UINT32, &dram_bnkgrp_indexing_policy, "dram_bnkgrp_indexing_policy (0 = take higher bits, 1 = take lower bits) (Default = 0)", "0"); - option_parser_register(opp, "-Seperate_Write_Queue_Enable", OPT_BOOL, &seperate_write_queue_enabled, + option_parser_register(opp, "-dram_seperate_write_queue_enable", OPT_BOOL, &seperate_write_queue_enabled, "Seperate_Write_Queue_Enable", "0"); - option_parser_register(opp, "-Write_Queue_Size", OPT_CSTR, &write_queue_size_opt, + option_parser_register(opp, "-dram_write_queue_size", OPT_CSTR, &write_queue_size_opt, "Write_Queue_Size", "32:28:16"); - option_parser_register(opp, "-Elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround, + option_parser_register(opp, "-dram_elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround, "elimnate_rw_turnaround i.e set tWTR and tRTW = 0", "0"); option_parser_register(opp, "-icnt_flit_size", OPT_UINT32, &icnt_flit_size, @@ -240,13 +240,13 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); - option_parser_register(opp, "-l1_banks", OPT_UINT32, &m_L1D_config.l1_banks, + option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32, &m_L1D_config.l1_banks, "The number of L1 cache banks", "1"); - option_parser_register(opp, "-l1_latency", OPT_UINT32, &m_L1D_config.l1_latency, + option_parser_register(opp, "-gpgpu_l1_latency", OPT_UINT32, &m_L1D_config.l1_latency, "L1 Hit Latency", "1"); - option_parser_register(opp, "-smem_latency", OPT_UINT32, &smem_latency, + option_parser_register(opp, "-gpgpu_smem_latency", OPT_UINT32, &smem_latency, "smem Latency", "3"); option_parser_register(opp, "-gpgpu_cache:dl1PrefL1", OPT_CSTR, &m_L1D_config.m_config_stringPrefL1, @@ -257,7 +257,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); - option_parser_register(opp, "-gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D, + option_parser_register(opp, "-gpgpu_gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D, "global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip)", "0"); @@ -306,7 +306,7 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); - option_parser_register(opp, "-adaptive_cache_config", OPT_UINT32, &adaptive_cache_config, + option_parser_register(opp, "-gpgpu_adaptive_cache_config", OPT_UINT32, &adaptive_cache_config, "adaptive_cache_config", "0"); option_parser_register(opp, "-gpgpu_shmem_sizeDefault", OPT_UINT32, &gpgpu_shmem_sizeDefault, @@ -327,7 +327,7 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts, "Number of portions a warp is divided into for shared memory bank conflict check ", "2"); - option_parser_register(opp, "-mem_unit_ports", OPT_INT32, &mem_unit_ports, + option_parser_register(opp, "-gpgpu_mem_unit_ports", OPT_INT32, &mem_unit_ports, "The number of memory transactions allowed per core cycle", "1"); option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts, @@ -348,10 +348,10 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_reg_bank_use_warp_id", OPT_BOOL, &gpgpu_reg_bank_use_warp_id, "Use warp ID in mapping registers to banks (default = off)", "0"); - option_parser_register(opp, "-sub_core_model", OPT_BOOL, &sub_core_model, + option_parser_register(opp, "-gpgpu_sub_core_model", OPT_BOOL, &sub_core_model, "Sub Core Volta/Pascal model (default = off)", "0"); - option_parser_register(opp, "-enable_specialized_operand_collector", OPT_BOOL, &enable_specialized_operand_collector, + option_parser_register(opp, "-gpgpu_enable_specialized_operand_collector", OPT_BOOL, &enable_specialized_operand_collector, "enable_specialized_operand_collector", "1"); option_parser_register(opp, "-gpgpu_operand_collector_num_units_sp", OPT_INT32, &gpgpu_operand_collector_num_units_sp, @@ -467,15 +467,32 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_concurrent_kernel_sm", OPT_BOOL, &gpgpu_concurrent_kernel_sm, "Support concurrent kernels on a SM (default = disabled)", "0"); - option_parser_register(opp, "-perfect_inst_const_cache", OPT_BOOL, &perfect_inst_const_cache, + option_parser_register(opp, "-gpgpu_perfect_inst_const_cache", OPT_BOOL, &perfect_inst_const_cache, "perfect inst and const cache mode, so all inst and const hits in the cache(default = disabled)", "0"); - option_parser_register(opp, "-inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput, + option_parser_register(opp, "-gpgpu_inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput, "the number of fetched intruction per warp each cycle", "1"); option_parser_register(opp, "-gpgpu_reg_file_port_throughput", OPT_INT32, ®_file_port_throughput, "the number ports of the register file", "1"); + + //used for trace-driven mode + option_parser_register(opp, "-trace_opcode_latency_initiation_int", OPT_CSTR, &trace_opcode_latency_initiation_int, + "Opcode latencies and initiation for integers in trace driven mode ", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_sp", OPT_CSTR, &trace_opcode_latency_initiation_sp, + "Opcode latencies and initiation for sp in trace driven mode ", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_dp", OPT_CSTR, &trace_opcode_latency_initiation_dp, + "Opcode latencies and initiation for dp in trace driven mode ", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_sfu", OPT_CSTR, &trace_opcode_latency_initiation_sfu, + "Opcode latencies and initiation for sfu in trace driven mode ", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_tensor", OPT_CSTR, &trace_opcode_latency_initiation_tensor, + "Opcode latencies and initiation for tensor in trace driven mode ", + "4,1"); } void gpgpu_sim_config::reg_options(option_parser_t opp) diff --git a/src/gpgpu-sim/icnt_wrapper.cc b/src/gpgpu-sim/icnt_wrapper.cc index e449bf1..6e3e596 100644 --- a/src/gpgpu-sim/icnt_wrapper.cc +++ b/src/gpgpu-sim/icnt_wrapper.cc @@ -179,12 +179,12 @@ void icnt_reg_options( class OptionParser * opp ) //parameters for local xbar - option_parser_register(opp, "-inct_in_buffer_limit", OPT_UINT32, &g_inct_config.in_buffer_limit, "in_buffer_limit", "64"); - option_parser_register(opp, "-inct_out_buffer_limit", OPT_UINT32, &g_inct_config.out_buffer_limit, "out_buffer_limit", "64"); - option_parser_register(opp, "-inct_subnets", OPT_UINT32, &g_inct_config.subnets, "subnets", "2"); - option_parser_register(opp, "-arbiter_algo", OPT_UINT32, &g_inct_config.arbiter_algo, "arbiter_algo", "1"); - option_parser_register(opp, "-inct_verbose", OPT_UINT32, &g_inct_config.verbose, "inct_verbose", "0"); - option_parser_register(opp, "-inct_grant_cycles", OPT_UINT32, &g_inct_config.grant_cycles, "grant_cycles", "1"); + option_parser_register(opp, "-icnt_in_buffer_limit", OPT_UINT32, &g_inct_config.in_buffer_limit, "in_buffer_limit", "64"); + option_parser_register(opp, "-icnt_out_buffer_limit", OPT_UINT32, &g_inct_config.out_buffer_limit, "out_buffer_limit", "64"); + option_parser_register(opp, "-icnt_subnets", OPT_UINT32, &g_inct_config.subnets, "subnets", "2"); + option_parser_register(opp, "-icnt_arbiter_algo", OPT_UINT32, &g_inct_config.arbiter_algo, "arbiter_algo", "1"); + option_parser_register(opp, "-icnt_verbose", OPT_UINT32, &g_inct_config.verbose, "inct_verbose", "0"); + option_parser_register(opp, "-icnt_grant_cycles", OPT_UINT32, &g_inct_config.grant_cycles, "grant_cycles", "1"); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 65ec113..900ec90 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3088,7 +3088,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const switch (adaptive_cache_config) { case FIXED: break; - case VOLTA: { + case ADAPTIVE_VOLTA: { //For Volta, we assign the remaining shared memory to L1 cache //For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x //assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 665e3a5..ca85903 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1527,6 +1527,13 @@ class shader_core_config : public core_config unsigned inst_fetch_throughput; unsigned reg_file_port_throughput; + char* trace_opcode_latency_initiation_int; + char* trace_opcode_latency_initiation_sp; + char* trace_opcode_latency_initiation_dp; + char* trace_opcode_latency_initiation_sfu; + char* trace_opcode_latency_initiation_tensor; + + }; struct shader_core_stats_pod { diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc index bedac4c..5e07ace 100644 --- a/src/trace-driven/gpgpusim_trace_driven_main.cc +++ b/src/trace-driven/gpgpusim_trace_driven_main.cc @@ -48,6 +48,7 @@ int main ( int argc, const char **argv ) //prints stats trace_parser tracer(m_gpgpu_sim->get_config().get_traces_filename(), m_gpgpu_sim, m_gpgpu_context); + trace_config config(m_gpgpu_sim); std::vector commandlist = tracer.parse_kernellist_file(); bool first_kernel=true; @@ -69,7 +70,7 @@ int main ( int argc, const char **argv ) first_kernel = false; continue; } - kernel_info = tracer.parse_kernel_info(commandlist[i]); + kernel_info = tracer.parse_kernel_info(commandlist[i], &config); m_gpgpu_sim->launch(kernel_info); } diff --git a/src/trace-driven/kepler_opcode.h b/src/trace-driven/kepler_opcode.h index f2bbc90..4aa8e0f 100644 --- a/src/trace-driven/kepler_opcode.h +++ b/src/trace-driven/kepler_opcode.h @@ -99,12 +99,13 @@ static const std::unordered_map Kepler_OpcodeMap = { //Load/Store Instructions //For now, we ignore constant loads, consider it as ALU_OP, TO DO {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, - {"LD", OpcodeChar(OP_LD, LOAD_OP)}, + //in Kepler, LD is load global so set it to LDG + {"LD", OpcodeChar(OP_LDG, LOAD_OP)}, {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, {"LDSLK", OpcodeChar(OP_LDSLK, LOAD_OP)}, - {"ST", OpcodeChar(OP_ST, STORE_OP)}, + {"ST", OpcodeChar(OP_STG, STORE_OP)}, {"STL", OpcodeChar(OP_STL, STORE_OP)}, {"STS", OpcodeChar(OP_STS, STORE_OP)}, {"STSCUL", OpcodeChar(OP_STSCUL, STORE_OP)}, diff --git a/src/trace-driven/trace_driven.cc b/src/trace-driven/trace_driven.cc index 35e953e..22c527e 100644 --- a/src/trace-driven/trace_driven.cc +++ b/src/trace-driven/trace_driven.cc @@ -98,7 +98,7 @@ void trace_parser::parse_memcpy_info(const std::string& memcpy_command, size_t& ss>>std::dec>>count; } -trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltraces_filepath) { +trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltraces_filepath, trace_config* config) { ifs.open(kerneltraces_filepath.c_str()); @@ -167,7 +167,7 @@ trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltr dim3 blockDim(tb_dim_x, tb_dim_y, tb_dim_z); trace_function_info* function_info = new trace_function_info(info, m_gpgpu_context); function_info->set_name(kernel_name.c_str()); - trace_kernel_info_t* kernel_info = new trace_kernel_info_t(gridDim, blockDim, binary_verion, function_info, &ifs, m_gpgpu_sim, m_gpgpu_context); + trace_kernel_info_t* kernel_info = new trace_kernel_info_t(gridDim, blockDim, binary_verion, function_info, &ifs, m_gpgpu_sim, m_gpgpu_context, config); return kernel_info; } @@ -211,11 +211,12 @@ address_type trace_shd_warp_t::get_pc(){ return warp_traces[trace_pc].pc; } -trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context):kernel_info_t(gridDim, blockDim, m_function_info) { +trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context, class trace_config* config):kernel_info_t(gridDim, blockDim, m_function_info) { ifs = inputstream; m_gpgpu_sim = gpgpu_sim; m_gpgpu_context = gpgpu_context; binary_verion = m_binary_verion; + m_tconfig = config; //resolve the binary version if(m_binary_verion == VOLTA_BINART_VERSION) @@ -285,8 +286,8 @@ bool trace_kernel_info_t::get_next_threadblock_traces(std::vectorgetShaderCoreConfig(), m_gpgpu_context); - inst.parse_from_string(line, OpcodeMap, binary_verion); + trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig(), m_gpgpu_context, m_tconfig); + inst.parse_from_string(line, OpcodeMap); threadblock_traces[warp_id]->push_back(inst); } } @@ -323,7 +324,7 @@ unsigned trace_warp_inst_t::get_datawidth_from_opcode(const std::vector* OpcodeMap, unsigned binary_verion){ +bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordered_map* OpcodeMap){ std::stringstream ss; ss.str(trace); @@ -473,7 +474,7 @@ bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordere //remove redundant registers //fill latency and initl - set_latency(op); + m_tconfig->set_latency(op, latency, initiation_interval); //fill addresses if(mem_width > 0) { @@ -548,10 +549,7 @@ bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordere //right now, we consider all loads are shared. assert(mem_width>0); data_size = get_datawidth_from_opcode(opcode_tokens); - if(binary_verion == KEPLER_BINART_VERSION) - space.set_type(global_space); - else - space.set_type(shared_space); + space.set_type(shared_space); if(m_opcode == OP_LD) memory_op = memory_load; else @@ -584,59 +582,29 @@ bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordere return true; } -void trace_warp_inst_t::set_latency(unsigned category) +trace_config::trace_config(gpgpu_sim* m_gpgpu_sim){ + + this->m_gpgpu_sim=m_gpgpu_sim; + parse_config(); +} + +void trace_config::parse_config() { - unsigned int_latency[5]; - unsigned fp_latency[5]; - unsigned dp_latency[5]; - unsigned sfu_latency; - unsigned tensor_latency; - unsigned int_init[5]; - unsigned fp_init[5]; - unsigned dp_init[5]; - unsigned sfu_init; - unsigned tensor_init; - - /* - * [0] ADD,SUB - * [1] MAX,Min - * [2] MUL - * [3] MAD - * [4] DIV - */ - sscanf(m_gpgpu_context->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u", - &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4]); - sscanf(m_gpgpu_context->func_sim->opcode_latency_fp, "%u,%u,%u,%u,%u", - &fp_latency[0],&fp_latency[1],&fp_latency[2], - &fp_latency[3],&fp_latency[4]); - sscanf(m_gpgpu_context->func_sim->opcode_latency_dp, "%u,%u,%u,%u,%u", - &dp_latency[0],&dp_latency[1],&dp_latency[2], - &dp_latency[3],&dp_latency[4]); - sscanf(m_gpgpu_context->func_sim->opcode_latency_sfu, "%u", - &sfu_latency); - sscanf(m_gpgpu_context->func_sim->opcode_latency_tensor, "%u", - &tensor_latency); - sscanf(m_gpgpu_context->func_sim->opcode_initiation_int, "%u,%u,%u,%u,%u", - &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4]); - sscanf(m_gpgpu_context->func_sim->opcode_initiation_fp, "%u,%u,%u,%u,%u", - &fp_init[0],&fp_init[1],&fp_init[2], - &fp_init[3],&fp_init[4]); - sscanf(m_gpgpu_context->func_sim->opcode_initiation_dp, "%u,%u,%u,%u,%u", - &dp_init[0],&dp_init[1],&dp_init[2], - &dp_init[3],&dp_init[4]); - sscanf(m_gpgpu_context->func_sim->opcode_initiation_sfu, "%u", - &sfu_init); - sscanf(m_gpgpu_context->func_sim->opcode_initiation_tensor, "%u", - &tensor_init); - sscanf(m_gpgpu_context->func_sim->cdp_latency_str, "%u,%u,%u,%u,%u", - &m_gpgpu_context->func_sim->cdp_latency[0], - &m_gpgpu_context->func_sim->cdp_latency[1], - &m_gpgpu_context->func_sim->cdp_latency[2], - &m_gpgpu_context->func_sim->cdp_latency[3], - &m_gpgpu_context->func_sim->cdp_latency[4]); + sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_int, "%u,%u", + &int_latency,&int_init); + sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_sp, "%u,%u", + &fp_latency,&fp_init); + sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_dp, "%u,%u", + &dp_latency,&dp_init); + sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_sfu, "%u,%u", + &sfu_latency,&sfu_init); + sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_tensor, "%u,%u", + &tensor_latency,&tensor_init); + +} +void trace_config::set_latency(unsigned category, unsigned& latency, unsigned& initiation_interval) +{ initiation_interval = latency = 1; switch(category){ @@ -645,16 +613,16 @@ void trace_warp_inst_t::set_latency(unsigned category) case BRANCH_OP: case CALL_OPS: case RET_OPS: - latency = int_latency[0]; - initiation_interval = int_init[0]; + latency = int_latency; + initiation_interval = int_init; break; case SP_OP: - latency = fp_latency[0]; - initiation_interval = fp_init[0]; + latency = fp_latency; + initiation_interval = fp_init; break; case DP_OP: - latency = dp_latency[0]; - initiation_interval = dp_init[0]; + latency = dp_latency; + initiation_interval = dp_init; break; case SFU_OP: latency = sfu_latency; diff --git a/src/trace-driven/trace_driven.h b/src/trace-driven/trace_driven.h index 9539e6d..2888f86 100644 --- a/src/trace-driven/trace_driven.h +++ b/src/trace-driven/trace_driven.h @@ -37,18 +37,20 @@ public: trace_warp_inst_t() { m_gpgpu_context=NULL; m_opcode=0; + m_tconfig=NULL; } - trace_warp_inst_t(const class core_config *config, gpgpu_context* gpgpu_context ):warp_inst_t(config) { + trace_warp_inst_t(const class core_config *config, gpgpu_context* gpgpu_context, class trace_config* tconfig ):warp_inst_t(config) { m_gpgpu_context = gpgpu_context; m_opcode=0; + m_tconfig=tconfig; } - bool parse_from_string(std::string trace, const std::unordered_map* OpcodeMap, unsigned binary_verion); + bool parse_from_string(std::string trace, const std::unordered_map* OpcodeMap); private: - void set_latency(unsigned cat); gpgpu_context* m_gpgpu_context; + class trace_config* m_tconfig; unsigned m_opcode; bool check_opcode_contain(const std::vector& opcode, std::string param); unsigned get_datawidth_from_opcode(const std::vector& opcode); @@ -56,7 +58,7 @@ private: class trace_kernel_info_t: public kernel_info_t { public: - trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context); + trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context, class trace_config* config); bool get_next_threadblock_traces(std::vector*> threadblock_traces); @@ -64,19 +66,35 @@ private: std::ifstream* ifs; gpgpu_sim * m_gpgpu_sim; gpgpu_context* m_gpgpu_context; + trace_config* m_tconfig; unsigned binary_verion; const std::unordered_map* OpcodeMap; }; +class trace_config { +public: + trace_config(gpgpu_sim * m_gpgpu_sim); + + void set_latency(unsigned category, unsigned& latency, unsigned& initiation_interval); + void parse_config(); + + +private: + + unsigned int_latency, fp_latency, dp_latency, sfu_latency, tensor_latency; + unsigned int_init, fp_init, dp_init, sfu_init, tensor_init; + gpgpu_sim* m_gpgpu_sim; + +}; class trace_parser { public: trace_parser(const char* kernellist_filepath, gpgpu_sim * m_gpgpu_sim, gpgpu_context* m_gpgpu_context); std::vector parse_kernellist_file(); - trace_kernel_info_t* parse_kernel_info(const std::string& kerneltraces_filepath); + trace_kernel_info_t* parse_kernel_info(const std::string& kerneltraces_filepath, trace_config* config); void parse_memcpy_info(const std::string& memcpy_command, size_t& add, size_t& count); void kernel_finalizer(trace_kernel_info_t* kernel_info); -- cgit v1.3 From 90a36a59f5619790b7f6d80375f69d05a75c0a82 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Sat, 23 May 2020 21:08:12 -0400 Subject: adding back titianC --- .../tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 4 +- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 4 +- .../tested-cfgs/SM7_TITANV/config_volta_islip.icnt | 74 ++++++++++++++++++++++ configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 18 ++++-- 4 files changed, 89 insertions(+), 11 deletions(-) create mode 100644 configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt (limited to 'configs') diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config index b7c0edc..9d0862a 100644 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -58,8 +58,8 @@ # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit # Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 1,1,1,1,4,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 75b3c99..5d23d1a 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -61,8 +61,8 @@ # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 2,2,2,2,8,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 2,2,2,2,4 -ptx_opcode_latency_dp 8,19,8,8,330 diff --git a/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt new file mode 100644 index 0000000..615d0a9 --- /dev/null +++ b/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt @@ -0,0 +1,74 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 88; +n = 1; + +// Routing + +routing_function = dest_tag; + + +// Flow control + +num_vcs = 1; +vc_buf_size = 256; +input_buffer_size = 256; +ejection_buffer_size = 256; +boundary_buffer_size = 256; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index eece246..b5f88ce 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -70,8 +70,8 @@ # All Div operations are executed on SFU unit # Throughput (initiation latency) are adopted from # http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 2,2,2,2,8,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 2,2,2,2,4 -ptx_opcode_latency_dp 8,19,8,8,330 @@ -124,7 +124,6 @@ -gpgpu_adaptive_cache_config 1 # Volta unified cache has four banks -gpgpu_l1_banks 4 -#-mem_unit_ports 4 -gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 @@ -153,11 +152,15 @@ -gpgpu_perfect_inst_const_cache 1 # interconnection --network_mode 1 --inter_config_file config_volta_islip.icnt +#-network_mode 1 +#-inter_config_file config_volta_islip.icnt +# use built-in local xbar +-network_mode 2 +-icnt_in_buffer_limit 512 +-icnt_out_buffer_limit 512 +-icnt_subnets 2 -icnt_flit_size 40 -# for local xbar, use: -# "-network_mode 2 -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 -inct_subnets 2" +-icnt_arbiter_algo 1 # memory partition latency config -gpgpu_l2_rop_latency 160 @@ -209,3 +212,4 @@ #-trace_components WARP_SCHEDULER,SCOREBOARD #-trace_sampling_core 0 + -- cgit v1.3 From 6b72554af7018a8dc42e607f6983a070fe5e5a42 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 28 May 2020 09:05:56 -0400 Subject: splitting execution-driven and trace-driven config files --- configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 5 ----- configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config | 4 ++++ configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 7 ------- configs/tested-cfgs/SM6_TITANX/trace.config | 4 ++++ configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 8 -------- configs/tested-cfgs/SM75_RTX2060/trace.config | 5 +++++ configs/tested-cfgs/SM7_QV100/gpgpusim.config | 8 -------- configs/tested-cfgs/SM7_QV100/trace.config | 6 ++++++ configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 8 -------- configs/tested-cfgs/SM7_TITANV/trace.config | 6 ++++++ 10 files changed, 25 insertions(+), 36 deletions(-) create mode 100644 configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config create mode 100644 configs/tested-cfgs/SM6_TITANX/trace.config create mode 100644 configs/tested-cfgs/SM75_RTX2060/trace.config create mode 100644 configs/tested-cfgs/SM7_QV100/trace.config create mode 100644 configs/tested-cfgs/SM7_TITANV/trace.config (limited to 'configs') diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config index 9d0862a..b173dd0 100644 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -67,11 +67,6 @@ -ptx_opcode_initiation_sfu 2 -ptx_opcode_latency_sfu 200 --trace_opcode_latency_initiation_int 4,1 --trace_opcode_latency_initiation_sp 4,1 --trace_opcode_latency_initiation_dp 20,2 --trace_opcode_latency_initiation_sfu 200,2 - # enable operand collector -gpgpu_operand_collector_num_units_sp 12 -gpgpu_operand_collector_num_units_sfu 6 diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config new file mode 100644 index 0000000..4c80036 --- /dev/null +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config @@ -0,0 +1,4 @@ +-trace_opcode_latency_initiation_int 4,1 +-trace_opcode_latency_initiation_sp 4,1 +-trace_opcode_latency_initiation_dp 20,2 +-trace_opcode_latency_initiation_sfu 200,2 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index a686238..ce6f745 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -22,8 +22,6 @@ # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 -# SASS trace-driven mode execution -#-trace_driven_mode 1 # high level architecture configuration -gpgpu_n_clusters 28 @@ -66,11 +64,6 @@ -ptx_opcode_initiation_sfu 4 -ptx_opcode_latency_sfu 20 --trace_opcode_latency_initiation_int 4,1 --trace_opcode_latency_initiation_sp 4,1 --trace_opcode_latency_initiation_dp 20,8 --trace_opcode_latency_initiation_sfu 20,4 - # in sub_core_model, schedulers are isolated, each scheduler has its own register file and EUs -gpgpu_sub_core_model 1 # enable operand collector diff --git a/configs/tested-cfgs/SM6_TITANX/trace.config b/configs/tested-cfgs/SM6_TITANX/trace.config new file mode 100644 index 0000000..88bcdc0 --- /dev/null +++ b/configs/tested-cfgs/SM6_TITANX/trace.config @@ -0,0 +1,4 @@ +-trace_opcode_latency_initiation_int 4,1 +-trace_opcode_latency_initiation_sp 4,1 +-trace_opcode_latency_initiation_dp 20,8 +-trace_opcode_latency_initiation_sfu 20,4 diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 5d23d1a..8a4be23 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -22,8 +22,6 @@ # PTX execution-driven -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 -# SASS trace-driven mode execution -#-trace_driven_mode 1 # high level architecture configuration -gpgpu_n_clusters 30 @@ -72,12 +70,6 @@ -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 --trace_opcode_latency_initiation_int 4,2 --trace_opcode_latency_initiation_sp 4,2 --trace_opcode_latency_initiation_dp 8,4 --trace_opcode_latency_initiation_sfu 20,8 --trace_opcode_latency_initiation_tensor 8,4 - # Turing has four schedulers per core -gpgpu_num_sched_per_core 4 # Greedy then oldest scheduler diff --git a/configs/tested-cfgs/SM75_RTX2060/trace.config b/configs/tested-cfgs/SM75_RTX2060/trace.config new file mode 100644 index 0000000..41987cf --- /dev/null +++ b/configs/tested-cfgs/SM75_RTX2060/trace.config @@ -0,0 +1,5 @@ +-trace_opcode_latency_initiation_int 4,2 +-trace_opcode_latency_initiation_sp 4,2 +-trace_opcode_latency_initiation_dp 8,4 +-trace_opcode_latency_initiation_sfu 20,8 +-trace_opcode_latency_initiation_tensor 8,4 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 5856e5d..c31c060 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -28,8 +28,6 @@ # PTX execution-driven -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 -# SASS trace-driven mode support -#-trace_driven_mode 1 # high level architecture configuration -gpgpu_n_clusters 80 @@ -79,12 +77,6 @@ -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 --trace_opcode_latency_initiation_int 4,2 --trace_opcode_latency_initiation_sp 4,2 --trace_opcode_latency_initiation_dp 8,4 --trace_opcode_latency_initiation_sfu 20,8 --trace_opcode_latency_initiation_tensor 8,4 - # Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated -gpgpu_sub_core_model 1 diff --git a/configs/tested-cfgs/SM7_QV100/trace.config b/configs/tested-cfgs/SM7_QV100/trace.config new file mode 100644 index 0000000..04ac009 --- /dev/null +++ b/configs/tested-cfgs/SM7_QV100/trace.config @@ -0,0 +1,6 @@ +-trace_opcode_latency_initiation_int 4,2 +-trace_opcode_latency_initiation_sp 4,2 +-trace_opcode_latency_initiation_dp 8,4 +-trace_opcode_latency_initiation_sfu 20,8 +-trace_opcode_latency_initiation_tensor 8,4 + diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index b5f88ce..ef28dd8 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -26,8 +26,6 @@ # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 -# SASS trace-driven mode support -#-trace_driven_mode 1 # high level architecture configuration -gpgpu_n_clusters 40 @@ -81,12 +79,6 @@ -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 --trace_opcode_latency_initiation_int 4,2 --trace_opcode_latency_initiation_sp 4,2 --trace_opcode_latency_initiation_dp 8,4 --trace_opcode_latency_initiation_sfu 20,8 --trace_opcode_latency_initiation_tensor 8,4 - # Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated -gpgpu_sub_core_model 1 diff --git a/configs/tested-cfgs/SM7_TITANV/trace.config b/configs/tested-cfgs/SM7_TITANV/trace.config new file mode 100644 index 0000000..04ac009 --- /dev/null +++ b/configs/tested-cfgs/SM7_TITANV/trace.config @@ -0,0 +1,6 @@ +-trace_opcode_latency_initiation_int 4,2 +-trace_opcode_latency_initiation_sp 4,2 +-trace_opcode_latency_initiation_dp 8,4 +-trace_opcode_latency_initiation_sfu 20,8 +-trace_opcode_latency_initiation_tensor 8,4 + -- cgit v1.3 From 3f051d4e5e24943575ac4c19c358e1a0e6de621c Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Sat, 30 May 2020 22:17:04 -0400 Subject: adding new specialization units --- configs/tested-cfgs/SM75_RTX2060/trace.config | 20 +++++ configs/tested-cfgs/SM7_QV100/trace.config | 13 +++ configs/tested-cfgs/SM7_TITANV/trace.config | 13 +++ src/abstract_hardware_model.h | 15 +++- src/gpgpu-sim/gpu-sim.cc | 11 +++ src/gpgpu-sim/shader.cc | 114 +++++++++++++++++++++++--- src/gpgpu-sim/shader.h | 79 ++++++++++++++++-- src/trace-driven/ISA_Def/turing_opcode.h | 113 +++++++++++++------------ src/trace-driven/ISA_Def/volta_opcode.h | 50 +++++------ src/trace-driven/trace_driven.cc | 15 ++++ src/trace-driven/trace_driven.h | 3 + 11 files changed, 347 insertions(+), 99 deletions(-) (limited to 'configs') diff --git a/configs/tested-cfgs/SM75_RTX2060/trace.config b/configs/tested-cfgs/SM75_RTX2060/trace.config index 41987cf..17b6cc7 100644 --- a/configs/tested-cfgs/SM75_RTX2060/trace.config +++ b/configs/tested-cfgs/SM75_RTX2060/trace.config @@ -3,3 +3,23 @@ -trace_opcode_latency_initiation_dp 8,4 -trace_opcode_latency_initiation_sfu 20,8 -trace_opcode_latency_initiation_tensor 8,4 + +#execute branch insts on spec unit 1 +#in Turing, there is a dedicated branch unit +#,,,,, +-specialized_unit_1 1,4,4,4,4,BRA +#, +-trace_opcode_latency_initiation_spec_op_1 4,4 + +#TEX unit, make fixed latency for all tex insts +-specialized_unit_2 1,1,200,4,4,TEX +-trace_opcode_latency_initiation_spec_op_2 200,4 + +#tensor unit +-specialized_unit_3 1,4,8,4,4,TENSOR +-trace_opcode_latency_initiation_spec_op_3 8,4 + +#UDP unit +#for more info about UDP, see https://www.hotchips.org/hc31/HC31_2.12_NVIDIA_final.pdf +-specialized_unit_4 1,4,4,4,4,UDP +-trace_opcode_latency_initiation_spec_op_4 4,2 diff --git a/configs/tested-cfgs/SM7_QV100/trace.config b/configs/tested-cfgs/SM7_QV100/trace.config index 04ac009..88f5706 100644 --- a/configs/tested-cfgs/SM7_QV100/trace.config +++ b/configs/tested-cfgs/SM7_QV100/trace.config @@ -4,3 +4,16 @@ -trace_opcode_latency_initiation_sfu 20,8 -trace_opcode_latency_initiation_tensor 8,4 +#execute branch insts on spec unit 1 +#in Volta, there is a dedicated branch unit +#,,,,, +-specialized_unit_1 1,4,4,4,4,BRA +-trace_opcode_latency_initiation_spec_op_1 4,4 + +#TEX unit, make fixed latency for all tex insts +-specialized_unit_2 1,4,200,4,4,TEX +-trace_opcode_latency_initiation_spec_op_2 200,4 + +#tensor unit +-specialized_unit_3 1,4,8,4,4,TENSOR +-trace_opcode_latency_initiation_spec_op_3 8,4 diff --git a/configs/tested-cfgs/SM7_TITANV/trace.config b/configs/tested-cfgs/SM7_TITANV/trace.config index 04ac009..88f5706 100644 --- a/configs/tested-cfgs/SM7_TITANV/trace.config +++ b/configs/tested-cfgs/SM7_TITANV/trace.config @@ -4,3 +4,16 @@ -trace_opcode_latency_initiation_sfu 20,8 -trace_opcode_latency_initiation_tensor 8,4 +#execute branch insts on spec unit 1 +#in Volta, there is a dedicated branch unit +#,,,,, +-specialized_unit_1 1,4,4,4,4,BRA +-trace_opcode_latency_initiation_spec_op_1 4,4 + +#TEX unit, make fixed latency for all tex insts +-specialized_unit_2 1,4,200,4,4,TEX +-trace_opcode_latency_initiation_spec_op_2 200,4 + +#tensor unit +-specialized_unit_3 1,4,8,4,4,TENSOR +-trace_opcode_latency_initiation_spec_op_3 8,4 diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index c58d39c..b22b5c4 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -79,6 +79,8 @@ typedef unsigned address_type; typedef unsigned addr_t; // the following are operations the timing model can see +#define SPECIALIZED_UNIT_NUM 8 +#define SPEC_UNIT_START_ID 100 enum uarch_op_t { NO_OP = -1, @@ -98,7 +100,15 @@ enum uarch_op_t { MEMORY_BARRIER_OP, CALL_OPS, RET_OPS, - EXIT_OPS + EXIT_OPS, + SPECIALIZED_UNIT_1_OP = SPEC_UNIT_START_ID, + SPECIALIZED_UNIT_2_OP, + SPECIALIZED_UNIT_3_OP, + SPECIALIZED_UNIT_4_OP, + SPECIALIZED_UNIT_5_OP, + SPECIALIZED_UNIT_6_OP, + SPECIALIZED_UNIT_7_OP, + SPECIALIZED_UNIT_8_OP }; typedef enum uarch_op_t op_type; @@ -135,7 +145,8 @@ enum operation_pipeline_t { INTP__OP, SFU__OP, TENSOR_CORE__OP, - MEM__OP + MEM__OP, + SPECIALIZED__OP, }; typedef enum operation_pipeline_t operation_pipeline; enum mem_operation_t { NOT_TEX, TEX }; diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index b62524e..03aebf3 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -529,6 +529,17 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register(opp, "-gpgpu_reg_file_port_throughput", OPT_INT32, ®_file_port_throughput, "the number ports of the register file", "1"); + + for (unsigned j = 0; j < SPECIALIZED_UNIT_NUM; ++j) { + std::stringstream ss; + ss << "-specialized_unit_" << j + 1; + option_parser_register(opp, ss.str().c_str(), OPT_CSTR, + &specialized_unit_string[j], + "specialized unit config" + " {,::,:,}", + "0,4,4,4,4,BRA"); + } } void gpgpu_sim_config::reg_options(option_parser_t opp) { diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 8efb88b..8b226b6 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -82,11 +82,30 @@ void exec_shader_core_ctx::create_shd_warp() { } void shader_core_ctx::create_front_pipeline() { - m_pipeline_reg.reserve(N_PIPELINE_STAGES); + // pipeline_stages is the sum of normal pipeline stages and specialized_unit + // stages * 2 (for ID and EX) + unsigned total_pipeline_stages = + N_PIPELINE_STAGES + m_config->m_specialized_unit.size() * 2; + m_pipeline_reg.reserve(total_pipeline_stages); for (int j = 0; j < N_PIPELINE_STAGES; j++) { m_pipeline_reg.push_back( register_set(m_config->pipe_widths[j], pipeline_stage_name_decode[j])); } + for (int j = 0; j < m_config->m_specialized_unit.size(); j++) { + m_pipeline_reg.push_back( + register_set(m_config->m_specialized_unit[j].id_oc_spec_reg_width, + m_config->m_specialized_unit[j].name)); + m_config->m_specialized_unit[j].ID_OC_SPEC_ID = m_pipeline_reg.size() - 1; + m_specilized_dispatch_reg.push_back( + &m_pipeline_reg[m_pipeline_reg.size() - 1]); + } + for (int j = 0; j < m_config->m_specialized_unit.size(); j++) { + m_pipeline_reg.push_back( + register_set(m_config->m_specialized_unit[j].oc_ex_spec_reg_width, + m_config->m_specialized_unit[j].name)); + m_config->m_specialized_unit[j].OC_EX_SPEC_ID = m_pipeline_reg.size() - 1; + } + if (m_config->sub_core_model) { // in subcore model, each scheduler should has its own issue register, so // num scheduler = reg width @@ -168,37 +187,40 @@ void shader_core_ctx::create_schedulers() { m_stats, this, m_scoreboard, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT], - &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], i)); + &m_pipeline_reg[ID_OC_TENSOR_CORE], m_specilized_dispatch_reg, + &m_pipeline_reg[ID_OC_MEM], i)); break; case CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE: schedulers.push_back(new two_level_active_scheduler( m_stats, this, m_scoreboard, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT], - &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], i, - m_config->gpgpu_scheduler_string)); + &m_pipeline_reg[ID_OC_TENSOR_CORE], m_specilized_dispatch_reg, + &m_pipeline_reg[ID_OC_MEM], i, m_config->gpgpu_scheduler_string)); break; case CONCRETE_SCHEDULER_GTO: schedulers.push_back(new gto_scheduler( m_stats, this, m_scoreboard, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT], - &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], i)); + &m_pipeline_reg[ID_OC_TENSOR_CORE], m_specilized_dispatch_reg, + &m_pipeline_reg[ID_OC_MEM], i)); break; case CONCRETE_SCHEDULER_OLDEST_FIRST: schedulers.push_back(new oldest_scheduler( m_stats, this, m_scoreboard, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT], - &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], i)); + &m_pipeline_reg[ID_OC_TENSOR_CORE], m_specilized_dispatch_reg, + &m_pipeline_reg[ID_OC_MEM], i)); break; case CONCRETE_SCHEDULER_WARP_LIMITING: schedulers.push_back(new swl_scheduler( m_stats, this, m_scoreboard, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT], - &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], i, - m_config->gpgpu_scheduler_string)); + &m_pipeline_reg[ID_OC_TENSOR_CORE], m_specilized_dispatch_reg, + &m_pipeline_reg[ID_OC_MEM], i, m_config->gpgpu_scheduler_string)); break; default: abort(); @@ -248,6 +270,14 @@ void shader_core_ctx::create_exec_pipeline() { in_ports.push_back(&m_pipeline_reg[ID_OC_INT]); out_ports.push_back(&m_pipeline_reg[OC_EX_INT]); } + if (m_config->m_specialized_unit.size() > 0) { + for (unsigned j = 0; j < m_config->m_specialized_unit.size(); ++j) { + in_ports.push_back( + &m_pipeline_reg[m_config->m_specialized_unit[j].ID_OC_SPEC_ID]); + out_ports.push_back( + &m_pipeline_reg[m_config->m_specialized_unit[j].OC_EX_SPEC_ID]); + } + } cu_sets.push_back((unsigned)GEN_CUS); m_operand_collector.add_port(in_ports, out_ports, cu_sets); in_ports.clear(), out_ports.clear(), cu_sets.clear(); @@ -340,7 +370,7 @@ void shader_core_ctx::create_exec_pipeline() { m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_dp_units + m_config->gpgpu_num_sfu_units + m_config->gpgpu_num_tensor_core_units + - m_config->gpgpu_num_int_units + + m_config->gpgpu_num_int_units + m_config->m_specialized_unit_num + 1; // sp_unit, sfu, dp, tensor, int, ldst_unit // m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ]; // m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ]; @@ -376,6 +406,17 @@ void shader_core_ctx::create_exec_pipeline() { m_issue_port.push_back(OC_EX_TENSOR_CORE); } + for (int j = 0; j < m_config->m_specialized_unit.size(); j++) { + for (unsigned k = 0; k < m_config->m_specialized_unit[j].num_units; k++) { + m_fu.push_back(new specialized_unit( + &m_pipeline_reg[EX_WB], m_config, this, SPEC_UNIT_START_ID + j, + m_config->m_specialized_unit[j].name, + m_config->m_specialized_unit[j].latency)); + m_dispatch_port.push_back(m_config->m_specialized_unit[j].ID_OC_SPEC_ID); + m_issue_port.push_back(m_config->m_specialized_unit[j].OC_EX_SPEC_ID); + } + } + m_ldst_unit = new ldst_unit(m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, m_config, m_memory_config, m_stats, m_sid, m_tpc); @@ -1204,7 +1245,7 @@ void scheduler_unit::cycle() { // This code need to be refactored if (pI->op != TENSOR_CORE_OP && pI->op != SFU_OP && - pI->op != DP_OP) { + pI->op != DP_OP && !(pI->op >= SPEC_UNIT_START_ID)) { bool execute_on_SP = false; bool execute_on_INT = false; @@ -1302,7 +1343,30 @@ void scheduler_unit::cycle() { warp_inst_issued = true; previous_issued_inst_exec_type = exec_unit_type_t::TENSOR; } + } else if ((pI->op >= SPEC_UNIT_START_ID) && + !(diff_exec_units && + previous_issued_inst_exec_type == + exec_unit_type_t::SPECIALIZED)) { + unsigned spec_id = pI->op - SPEC_UNIT_START_ID; + assert(spec_id < m_shader->m_config->m_specialized_unit.size()); + register_set *spec_reg_set = m_spec_cores_out[spec_id]; + bool spec_pipe_avail = + (m_shader->m_config->m_specialized_unit[spec_id].num_units > + 0) && + spec_reg_set->has_free(m_shader->m_config->sub_core_model, + m_id); + + if (spec_pipe_avail) { + m_shader->issue_warp(*spec_reg_set, pI, active_mask, warp_id, + m_id); + issued++; + issued_inst = true; + warp_inst_issued = true; + previous_issued_inst_exec_type = + exec_unit_type_t::SPECIALIZED; + } } + } // end of else } else { SCHED_DPRINTF( @@ -1475,9 +1539,11 @@ swl_scheduler::swl_scheduler(shader_core_stats *stats, shader_core_ctx *shader, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector &spec_cores_out, register_set *mem_out, int id, char *config_string) : scheduler_unit(stats, shader, scoreboard, simt, warp, sp_out, dp_out, - sfu_out, int_out, tensor_core_out, mem_out, id) { + sfu_out, int_out, tensor_core_out, spec_cores_out, mem_out, + id) { unsigned m_prioritization_readin; int ret = sscanf(config_string, "warp_limiting:%d:%d", &m_prioritization_readin, &m_num_warps_to_limit); @@ -1599,7 +1665,7 @@ void shader_core_ctx::execute() { unsigned multiplier = m_fu[n]->clock_multiplier(); for (unsigned c = 0; c < multiplier; c++) m_fu[n]->cycle(); m_fu[n]->active_lanes_in_pipeline(); - enum pipeline_stage_name_t issue_port = m_issue_port[n]; + unsigned issue_port = m_issue_port[n]; register_set &issue_inst = m_pipeline_reg[issue_port]; warp_inst_t **ready_reg = issue_inst.get_ready(); if (issue_inst.has_ready() && m_fu[n]->can_issue(**ready_reg)) { @@ -2108,6 +2174,13 @@ void dp_unit::active_lanes_in_pipeline() { m_core->incfuactivelanes_stat(active_count); m_core->incfumemactivelanes_stat(active_count); } +void specialized_unit::active_lanes_in_pipeline() { + unsigned active_count = pipelined_simd_unit::get_active_lanes_in_pipeline(); + assert(active_count <= m_core->get_config()->warp_size); + m_core->incspactivelanes_stat(active_count); + m_core->incfuactivelanes_stat(active_count); + m_core->incfumemactivelanes_stat(active_count); +} void int_unit::active_lanes_in_pipeline() { unsigned active_count = pipelined_simd_unit::get_active_lanes_in_pipeline(); @@ -2138,6 +2211,15 @@ sp_unit::sp_unit(register_set *result_port, const shader_core_config *config, m_name = "SP "; } +specialized_unit::specialized_unit(register_set *result_port, + const shader_core_config *config, + shader_core_ctx *core, unsigned supported_op, + char *unit_name, unsigned latency) + : pipelined_simd_unit(result_port, config, latency, core) { + m_name = unit_name; + m_supported_op = supported_op; +} + dp_unit::dp_unit(register_set *result_port, const shader_core_config *config, shader_core_ctx *core) : pipelined_simd_unit(result_port, config, config->max_dp_latency, core) { @@ -2166,6 +2248,14 @@ void dp_unit ::issue(register_set &source_reg) { pipelined_simd_unit::issue(source_reg); } +void specialized_unit ::issue(register_set &source_reg) { + warp_inst_t **ready_reg = source_reg.get_ready(); + // m_core->incexecstat((*ready_reg)); + (*ready_reg)->op_pipe = SPECIALIZED__OP; + m_core->incsp_stat(m_core->get_config()->warp_size, (*ready_reg)->latency); + pipelined_simd_unit::issue(source_reg); +} + void int_unit ::issue(register_set &source_reg) { warp_inst_t **ready_reg = source_reg.get_ready(); // m_core->incexecstat((*ready_reg)); diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index d77207d..65c8937 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -79,7 +79,8 @@ enum exec_unit_type_t { MEM = 3, DP = 4, INT = 5, - TENSOR = 6 + TENSOR = 6, + SPECIALIZED = 7 }; class thread_ctx_t { @@ -329,6 +330,7 @@ class scheduler_unit { // this can be copied freely, so can be used in std std::vector *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector &spec_cores_out, register_set *mem_out, int id) : m_supervised_warps(), m_stats(stats), @@ -341,6 +343,7 @@ class scheduler_unit { // this can be copied freely, so can be used in std m_sfu_out(sfu_out), m_int_out(int_out), m_tensor_core_out(tensor_core_out), + m_spec_cores_out(spec_cores_out), m_mem_out(mem_out), m_id(id) {} virtual ~scheduler_unit() {} @@ -422,6 +425,7 @@ class scheduler_unit { // this can be copied freely, so can be used in std register_set *m_int_out; register_set *m_tensor_core_out; register_set *m_mem_out; + std::vector &m_spec_cores_out; int m_id; }; @@ -433,9 +437,11 @@ class lrr_scheduler : public scheduler_unit { std::vector *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector &spec_cores_out, register_set *mem_out, int id) : scheduler_unit(stats, shader, scoreboard, simt, warp, sp_out, dp_out, - sfu_out, int_out, tensor_core_out, mem_out, id) {} + sfu_out, int_out, tensor_core_out, spec_cores_out, + mem_out, id) {} virtual ~lrr_scheduler() {} virtual void order_warps(); virtual void done_adding_supervised_warps() { @@ -450,9 +456,11 @@ class gto_scheduler : public scheduler_unit { std::vector *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector &spec_cores_out, register_set *mem_out, int id) : scheduler_unit(stats, shader, scoreboard, simt, warp, sp_out, dp_out, - sfu_out, int_out, tensor_core_out, mem_out, id) {} + sfu_out, int_out, tensor_core_out, spec_cores_out, + mem_out, id) {} virtual ~gto_scheduler() {} virtual void order_warps(); virtual void done_adding_supervised_warps() { @@ -467,9 +475,11 @@ class oldest_scheduler : public scheduler_unit { std::vector *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector &spec_cores_out, register_set *mem_out, int id) : scheduler_unit(stats, shader, scoreboard, simt, warp, sp_out, dp_out, - sfu_out, int_out, tensor_core_out, mem_out, id) {} + sfu_out, int_out, tensor_core_out, spec_cores_out, + mem_out, id) {} virtual ~oldest_scheduler() {} virtual void order_warps(); virtual void done_adding_supervised_warps() { @@ -485,9 +495,11 @@ class two_level_active_scheduler : public scheduler_unit { register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector &spec_cores_out, register_set *mem_out, int id, char *config_str) : scheduler_unit(stats, shader, scoreboard, simt, warp, sp_out, dp_out, - sfu_out, int_out, tensor_core_out, mem_out, id), + sfu_out, int_out, tensor_core_out, spec_cores_out, + mem_out, id), m_pending_warps() { unsigned inner_level_readin; unsigned outer_level_readin; @@ -533,6 +545,7 @@ class swl_scheduler : public scheduler_unit { std::vector *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector &spec_cores_out, register_set *mem_out, int id, char *config_string); virtual ~swl_scheduler() {} virtual void order_warps(); @@ -1211,6 +1224,24 @@ class sp_unit : public pipelined_simd_unit { virtual void issue(register_set &source_reg); }; +class specialized_unit : public pipelined_simd_unit { + public: + specialized_unit(register_set *result_port, const shader_core_config *config, + shader_core_ctx *core, unsigned supported_op, + char *unit_name, unsigned latency); + virtual bool can_issue(const warp_inst_t &inst) const { + if (inst.op != m_supported_op) { + return false; + } + return pipelined_simd_unit::can_issue(inst); + } + virtual void active_lanes_in_pipeline(); + virtual void issue(register_set &source_reg); + + private: + unsigned m_supported_op; +}; + class simt_core_cluster; class shader_memory_interface; class shader_core_mem_fetch_allocator; @@ -1361,6 +1392,16 @@ const char *const pipeline_stage_name_decode[] = { "OC_EX_SFU", "OC_EX_MEM", "EX_WB", "ID_OC_TENSOR_CORE", "OC_EX_TENSOR_CORE", "N_PIPELINE_STAGES"}; +struct specialized_unit_params { + unsigned latency; + unsigned num_units; + unsigned id_oc_spec_reg_width; + unsigned oc_ex_spec_reg_width; + char name[20]; + unsigned ID_OC_SPEC_ID; + unsigned OC_EX_SPEC_ID; +}; + class shader_core_config : public core_config { public: shader_core_config(gpgpu_context *ctx) : core_config(ctx) { @@ -1419,6 +1460,24 @@ class shader_core_config : public core_config { gpgpu_cache_texl1_linesize = m_L1T_config.get_line_sz(); gpgpu_cache_constl1_linesize = m_L1C_config.get_line_sz(); m_valid = true; + + m_specialized_unit_num = 0; + // parse the specialized units + for (unsigned i = 0; i < SPECIALIZED_UNIT_NUM; ++i) { + unsigned enabled; + specialized_unit_params sparam; + sscanf(specialized_unit_string[i], "%u,%u,%u,%u,%u,%s", &enabled, + &sparam.num_units, &sparam.latency, &sparam.id_oc_spec_reg_width, + &sparam.oc_ex_spec_reg_width, &sparam.name); + + if (enabled) { + m_specialized_unit.push_back(sparam); + strncpy(m_specialized_unit.back().name, sparam.name, + sizeof(m_specialized_unit.back().name)); + m_specialized_unit_num += sparam.num_units; + } else + break; // we only accept continuous specialized_units, i.e., 1,2,3,4 + } } void reg_options(class OptionParser *opp); unsigned max_cta(const kernel_info_t &k) const; @@ -1534,6 +1593,11 @@ class shader_core_config : public core_config { bool perfect_inst_const_cache; unsigned inst_fetch_throughput; unsigned reg_file_port_throughput; + + // specialized unit config strings + char *specialized_unit_string[SPECIALIZED_UNIT_NUM]; + mutable std::vector m_specialized_unit; + unsigned m_specialized_unit_num; }; struct shader_core_stats_pod { @@ -2154,6 +2218,7 @@ class shader_core_ctx : public core_t { Scoreboard *m_scoreboard; opndcoll_rfu_t m_operand_collector; int m_active_warps; + std::vector m_specilized_dispatch_reg; // schedule std::vector schedulers; @@ -2163,8 +2228,8 @@ class shader_core_ctx : public core_t { // execute unsigned m_num_function_units; - std::vector m_dispatch_port; - std::vector m_issue_port; + std::vector m_dispatch_port; + std::vector m_issue_port; std::vector m_fu; // stallable pipelines should be last in this array ldst_unit *m_ldst_unit; diff --git a/src/trace-driven/ISA_Def/turing_opcode.h b/src/trace-driven/ISA_Def/turing_opcode.h index 0374bdd..12bbe76 100644 --- a/src/trace-driven/ISA_Def/turing_opcode.h +++ b/src/trace-driven/ISA_Def/turing_opcode.h @@ -43,7 +43,8 @@ static const std::unordered_map Turing_OpcodeMap = { {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)}, // Tensor Core Instructions - {"HMMA", OpcodeChar(OP_HMMA, TENSOR_CORE_OP)}, + // Execute Tensor Core Instructions on SPECIALIZED_UNIT_3 + {"HMMA", OpcodeChar(OP_HMMA, SPECIALIZED_UNIT_3_OP)}, // Double Point Instructions {"DADD", OpcodeChar(OP_DADD, DP_OP)}, @@ -128,43 +129,46 @@ static const std::unordered_map Turing_OpcodeMap = { {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)}, - // Uniform Datapath Instruction // - {"R2UR", OpcodeChar(OP_R2UR, ALU_OP)}, - {"S2UR", OpcodeChar(OP_S2UR, ALU_OP)}, - {"UBMSK", OpcodeChar(OP_UBMSK, ALU_OP)}, - {"UBREV", OpcodeChar(OP_UBREV, ALU_OP)}, - {"UCLEA", OpcodeChar(OP_UCLEA, ALU_OP)}, - {"UFLO", OpcodeChar(OP_UFLO, ALU_OP)}, - {"UIADD3", OpcodeChar(OP_UIADD3, ALU_OP)}, - {"UIMAD", OpcodeChar(OP_UIMAD, ALU_OP)}, - {"UISETP", OpcodeChar(OP_UISETP, ALU_OP)}, - {"ULDC", OpcodeChar(OP_ULDC, ALU_OP)}, - {"ULEA", OpcodeChar(OP_ULEA, ALU_OP)}, - {"ULOP", OpcodeChar(OP_ULOP, ALU_OP)}, - {"ULOP3", OpcodeChar(OP_ULOP3, ALU_OP)}, - {"ULOP32I", OpcodeChar(OP_ULOP32I, ALU_OP)}, - {"UMOV", OpcodeChar(OP_UMOV, ALU_OP)}, - {"UP2UR", OpcodeChar(OP_UP2UR, ALU_OP)}, - {"UPLOP3", OpcodeChar(OP_UPLOP3, ALU_OP)}, - {"UPOPC", OpcodeChar(OP_UPOPC, ALU_OP)}, - {"UPRMT", OpcodeChar(OP_UPRMT, ALU_OP)}, - {"UPSETP", OpcodeChar(OP_UPSETP, ALU_OP)}, - {"UR2UP", OpcodeChar(OP_UR2UP, ALU_OP)}, - {"USEL", OpcodeChar(OP_USEL, ALU_OP)}, - {"USGXT", OpcodeChar(OP_USGXT, ALU_OP)}, - {"USHF", OpcodeChar(OP_USHF, ALU_OP)}, - {"USHL", OpcodeChar(OP_USHL, ALU_OP)}, - {"USHR", OpcodeChar(OP_USHR, ALU_OP)}, - {"VOTEU", OpcodeChar(OP_VOTEU, ALU_OP)}, + // Uniform Datapath Instruction + // UDP unit + // for more info about UDP, see + // https://www.hotchips.org/hc31/HC31_2.12_NVIDIA_final.pdf + {"R2UR", OpcodeChar(OP_R2UR, SPECIALIZED_UNIT_4_OP)}, + {"S2UR", OpcodeChar(OP_S2UR, SPECIALIZED_UNIT_4_OP)}, + {"UBMSK", OpcodeChar(OP_UBMSK, SPECIALIZED_UNIT_4_OP)}, + {"UBREV", OpcodeChar(OP_UBREV, SPECIALIZED_UNIT_4_OP)}, + {"UCLEA", OpcodeChar(OP_UCLEA, SPECIALIZED_UNIT_4_OP)}, + {"UFLO", OpcodeChar(OP_UFLO, SPECIALIZED_UNIT_4_OP)}, + {"UIADD3", OpcodeChar(OP_UIADD3, SPECIALIZED_UNIT_4_OP)}, + {"UIMAD", OpcodeChar(OP_UIMAD, SPECIALIZED_UNIT_4_OP)}, + {"UISETP", OpcodeChar(OP_UISETP, SPECIALIZED_UNIT_4_OP)}, + {"ULDC", OpcodeChar(OP_ULDC, SPECIALIZED_UNIT_4_OP)}, + {"ULEA", OpcodeChar(OP_ULEA, SPECIALIZED_UNIT_4_OP)}, + {"ULOP", OpcodeChar(OP_ULOP, SPECIALIZED_UNIT_4_OP)}, + {"ULOP3", OpcodeChar(OP_ULOP3, SPECIALIZED_UNIT_4_OP)}, + {"ULOP32I", OpcodeChar(OP_ULOP32I, SPECIALIZED_UNIT_4_OP)}, + {"UMOV", OpcodeChar(OP_UMOV, SPECIALIZED_UNIT_4_OP)}, + {"UP2UR", OpcodeChar(OP_UP2UR, SPECIALIZED_UNIT_4_OP)}, + {"UPLOP3", OpcodeChar(OP_UPLOP3, SPECIALIZED_UNIT_4_OP)}, + {"UPOPC", OpcodeChar(OP_UPOPC, SPECIALIZED_UNIT_4_OP)}, + {"UPRMT", OpcodeChar(OP_UPRMT, SPECIALIZED_UNIT_4_OP)}, + {"UPSETP", OpcodeChar(OP_UPSETP, SPECIALIZED_UNIT_4_OP)}, + {"UR2UP", OpcodeChar(OP_UR2UP, SPECIALIZED_UNIT_4_OP)}, + {"USEL", OpcodeChar(OP_USEL, SPECIALIZED_UNIT_4_OP)}, + {"USGXT", OpcodeChar(OP_USGXT, SPECIALIZED_UNIT_4_OP)}, + {"USHF", OpcodeChar(OP_USHF, SPECIALIZED_UNIT_4_OP)}, + {"USHL", OpcodeChar(OP_USHL, SPECIALIZED_UNIT_4_OP)}, + {"USHR", OpcodeChar(OP_USHR, SPECIALIZED_UNIT_4_OP)}, + {"VOTEU", OpcodeChar(OP_VOTEU, SPECIALIZED_UNIT_4_OP)}, // Texture Instructions // For now, we ignore texture loads, consider it as ALU_OP - {"TEX", OpcodeChar(OP_TEX, ALU_OP)}, - {"TLD", OpcodeChar(OP_TLD, ALU_OP)}, - {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)}, - {"TMML", OpcodeChar(OP_TMML, ALU_OP)}, - {"TXD", OpcodeChar(OP_TXD, ALU_OP)}, - {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)}, + {"TEX", OpcodeChar(OP_TEX, SPECIALIZED_UNIT_2_OP)}, + {"TLD", OpcodeChar(OP_TLD, SPECIALIZED_UNIT_2_OP)}, + {"TLD4", OpcodeChar(OP_TLD4, SPECIALIZED_UNIT_2_OP)}, + {"TMML", OpcodeChar(OP_TMML, SPECIALIZED_UNIT_2_OP)}, + {"TXD", OpcodeChar(OP_TXD, SPECIALIZED_UNIT_2_OP)}, + {"TXQ", OpcodeChar(OP_TXQ, SPECIALIZED_UNIT_2_OP)}, // Surface Instructions // {"SUATOM", OpcodeChar(OP_SUATOM, ALU_OP)}, @@ -173,26 +177,27 @@ static const std::unordered_map Turing_OpcodeMap = { {"SUST", OpcodeChar(OP_SUST, ALU_OP)}, // Control Instructions - {"BMOV", OpcodeChar(OP_BMOV, BRANCH_OP)}, - {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)}, - {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)}, - {"BREAK", OpcodeChar(OP_BREAK, BRANCH_OP)}, - {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)}, - {"BRXU", OpcodeChar(OP_BRXU, BRANCH_OP)}, // - {"BSSY", OpcodeChar(OP_BSSY, BRANCH_OP)}, - {"BSYNC", OpcodeChar(OP_BSYNC, BRANCH_OP)}, - {"CALL", OpcodeChar(OP_CALL, CALL_OPS)}, + // execute branch insts on a dedicated branch unit (SPECIALIZED_UNIT_1) + {"BMOV", OpcodeChar(OP_BMOV, SPECIALIZED_UNIT_1_OP)}, + {"BPT", OpcodeChar(OP_BPT, SPECIALIZED_UNIT_1_OP)}, + {"BRA", OpcodeChar(OP_BRA, SPECIALIZED_UNIT_1_OP)}, + {"BREAK", OpcodeChar(OP_BREAK, SPECIALIZED_UNIT_1_OP)}, + {"BRX", OpcodeChar(OP_BRX, SPECIALIZED_UNIT_1_OP)}, + {"BRXU", OpcodeChar(OP_BRXU, SPECIALIZED_UNIT_1_OP)}, // + {"BSSY", OpcodeChar(OP_BSSY, SPECIALIZED_UNIT_1_OP)}, + {"BSYNC", OpcodeChar(OP_BSYNC, SPECIALIZED_UNIT_1_OP)}, + {"CALL", OpcodeChar(OP_CALL, SPECIALIZED_UNIT_1_OP)}, {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, - {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)}, - {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)}, - {"JMXU", OpcodeChar(OP_JMXU, BRANCH_OP)}, /// - {"KILL", OpcodeChar(OP_KILL, BRANCH_OP)}, - {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)}, - {"RET", OpcodeChar(OP_RET, RET_OPS)}, - {"RPCMOV", OpcodeChar(OP_RPCMOV, BRANCH_OP)}, - {"RTT", OpcodeChar(OP_RTT, RET_OPS)}, - {"WARPSYNC", OpcodeChar(OP_WARPSYNC, BRANCH_OP)}, - {"YIELD", OpcodeChar(OP_YIELD, BRANCH_OP)}, + {"JMP", OpcodeChar(OP_JMP, SPECIALIZED_UNIT_1_OP)}, + {"JMX", OpcodeChar(OP_JMX, SPECIALIZED_UNIT_1_OP)}, + {"JMXU", OpcodeChar(OP_JMXU, SPECIALIZED_UNIT_1_OP)}, /// + {"KILL", OpcodeChar(OP_KILL, SPECIALIZED_UNIT_3_OP)}, + {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, SPECIALIZED_UNIT_1_OP)}, + {"RET", OpcodeChar(OP_RET, SPECIALIZED_UNIT_1_OP)}, + {"RPCMOV", OpcodeChar(OP_RPCMOV, SPECIALIZED_UNIT_1_OP)}, + {"RTT", OpcodeChar(OP_RTT, SPECIALIZED_UNIT_1_OP)}, + {"WARPSYNC", OpcodeChar(OP_WARPSYNC, SPECIALIZED_UNIT_1_OP)}, + {"YIELD", OpcodeChar(OP_YIELD, SPECIALIZED_UNIT_1_OP)}, // Miscellaneous Instructions {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, diff --git a/src/trace-driven/ISA_Def/volta_opcode.h b/src/trace-driven/ISA_Def/volta_opcode.h index 7bd6904..3358211 100644 --- a/src/trace-driven/ISA_Def/volta_opcode.h +++ b/src/trace-driven/ISA_Def/volta_opcode.h @@ -43,7 +43,8 @@ static const std::unordered_map Volta_OpcodeMap = { {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)}, // Tensor Core Instructions - {"HMMA", OpcodeChar(OP_HMMA, TENSOR_CORE_OP)}, + // Execute Tensor Core Instructions on SPECIALIZED_UNIT_3 + {"HMMA", OpcodeChar(OP_HMMA, SPECIALIZED_UNIT_3_OP)}, // Double Point Instructions {"DADD", OpcodeChar(OP_DADD, DP_OP)}, @@ -126,32 +127,33 @@ static const std::unordered_map Volta_OpcodeMap = { // Texture Instructions // For now, we ignore texture loads, consider it as ALU_OP - {"TEX", OpcodeChar(OP_TEX, ALU_OP)}, - {"TLD", OpcodeChar(OP_TLD, ALU_OP)}, - {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)}, - {"TMML", OpcodeChar(OP_TMML, ALU_OP)}, - {"TXD", OpcodeChar(OP_TXD, ALU_OP)}, - {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)}, + {"TEX", OpcodeChar(OP_TEX, SPECIALIZED_UNIT_2_OP)}, + {"TLD", OpcodeChar(OP_TLD, SPECIALIZED_UNIT_2_OP)}, + {"TLD4", OpcodeChar(OP_TLD4, SPECIALIZED_UNIT_2_OP)}, + {"TMML", OpcodeChar(OP_TMML, SPECIALIZED_UNIT_2_OP)}, + {"TXD", OpcodeChar(OP_TXD, SPECIALIZED_UNIT_2_OP)}, + {"TXQ", OpcodeChar(OP_TXQ, SPECIALIZED_UNIT_2_OP)}, // Control Instructions - {"BMOV", OpcodeChar(OP_BMOV, BRANCH_OP)}, - {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)}, - {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)}, - {"BREAK", OpcodeChar(OP_BREAK, BRANCH_OP)}, - {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)}, - {"BSSY", OpcodeChar(OP_BSSY, BRANCH_OP)}, - {"BSYNC", OpcodeChar(OP_BSYNC, BRANCH_OP)}, - {"CALL", OpcodeChar(OP_CALL, CALL_OPS)}, + // execute branch insts on a dedicated branch unit (SPECIALIZED_UNIT_1) + {"BMOV", OpcodeChar(OP_BMOV, SPECIALIZED_UNIT_1_OP)}, + {"BPT", OpcodeChar(OP_BPT, SPECIALIZED_UNIT_1_OP)}, + {"BRA", OpcodeChar(OP_BRA, SPECIALIZED_UNIT_1_OP)}, + {"BREAK", OpcodeChar(OP_BREAK, SPECIALIZED_UNIT_1_OP)}, + {"BRX", OpcodeChar(OP_BRX, SPECIALIZED_UNIT_1_OP)}, + {"BSSY", OpcodeChar(OP_BSSY, SPECIALIZED_UNIT_1_OP)}, + {"BSYNC", OpcodeChar(OP_BSYNC, SPECIALIZED_UNIT_1_OP)}, + {"CALL", OpcodeChar(OP_CALL, SPECIALIZED_UNIT_1_OP)}, {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, - {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)}, - {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)}, - {"KILL", OpcodeChar(OP_KILL, BRANCH_OP)}, - {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)}, - {"RET", OpcodeChar(OP_RET, RET_OPS)}, - {"RPCMOV", OpcodeChar(OP_RPCMOV, BRANCH_OP)}, - {"RTT", OpcodeChar(OP_RTT, RET_OPS)}, - {"WARPSYNC", OpcodeChar(OP_WARPSYNC, BRANCH_OP)}, - {"YIELD", OpcodeChar(OP_YIELD, BRANCH_OP)}, + {"JMP", OpcodeChar(OP_JMP, SPECIALIZED_UNIT_1_OP)}, + {"JMX", OpcodeChar(OP_JMX, SPECIALIZED_UNIT_1_OP)}, + {"KILL", OpcodeChar(OP_KILL, SPECIALIZED_UNIT_1_OP)}, + {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, SPECIALIZED_UNIT_1_OP)}, + {"RET", OpcodeChar(OP_RET, SPECIALIZED_UNIT_1_OP)}, + {"RPCMOV", OpcodeChar(OP_RPCMOV, SPECIALIZED_UNIT_1_OP)}, + {"RTT", OpcodeChar(OP_RTT, SPECIALIZED_UNIT_1_OP)}, + {"WARPSYNC", OpcodeChar(OP_WARPSYNC, SPECIALIZED_UNIT_1_OP)}, + {"YIELD", OpcodeChar(OP_YIELD, SPECIALIZED_UNIT_1_OP)}, // Miscellaneous Instructions {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, diff --git a/src/trace-driven/trace_driven.cc b/src/trace-driven/trace_driven.cc index d42ee65..0b1e24b 100644 --- a/src/trace-driven/trace_driven.cc +++ b/src/trace-driven/trace_driven.cc @@ -608,6 +608,16 @@ void trace_config::reg_options(option_parser_t opp) { "Opcode latencies and initiation for tensor in trace " "driven mode ", "4,1"); + + for (unsigned j = 0; j < SPECIALIZED_UNIT_NUM; ++j) { + std::stringstream ss; + ss << "-trace_opcode_latency_initiation_spec_op_" << j + 1; + option_parser_register(opp, ss.str().c_str(), OPT_CSTR, + &trace_opcode_latency_initiation_specialized_op[j], + "specialized unit config" + " ", + "4,4"); + } } void trace_config::parse_config() { @@ -617,6 +627,11 @@ void trace_config::parse_config() { sscanf(trace_opcode_latency_initiation_sfu, "%u,%u", &sfu_latency, &sfu_init); sscanf(trace_opcode_latency_initiation_tensor, "%u,%u", &tensor_latency, &tensor_init); + + for (unsigned j = 0; j < SPECIALIZED_UNIT_NUM; ++j) { + sscanf(trace_opcode_latency_initiation_specialized_op[j], "%u,%u", + &specialized_unit_latency[j], &specialized_unit_initiation[j]); + } } void trace_config::set_latency(unsigned category, unsigned& latency, unsigned& initiation_interval) { diff --git a/src/trace-driven/trace_driven.h b/src/trace-driven/trace_driven.h index ea315a1..3af99c3 100644 --- a/src/trace-driven/trace_driven.h +++ b/src/trace-driven/trace_driven.h @@ -93,6 +93,8 @@ class trace_config { private: unsigned int_latency, fp_latency, dp_latency, sfu_latency, tensor_latency; unsigned int_init, fp_init, dp_init, sfu_init, tensor_init; + unsigned specialized_unit_latency[SPECIALIZED_UNIT_NUM]; + unsigned specialized_unit_initiation[SPECIALIZED_UNIT_NUM]; char* g_traces_filename; char* trace_opcode_latency_initiation_int; @@ -100,6 +102,7 @@ class trace_config { char* trace_opcode_latency_initiation_dp; char* trace_opcode_latency_initiation_sfu; char* trace_opcode_latency_initiation_tensor; + char* trace_opcode_latency_initiation_specialized_op[SPECIALIZED_UNIT_NUM]; }; class trace_parser { -- cgit v1.3 From 3e580ee62a9cc8010930f692d8a6201a31ed77e0 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 1 Jun 2020 14:56:30 -0400 Subject: moving all ipoly equstions to one file --- .../tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 2 +- configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 2 +- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 4 +- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 2 +- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- src/gpgpu-sim/addrdec.cc | 149 ++++++--------------- src/gpgpu-sim/addrdec.h | 2 + src/gpgpu-sim/dram.cc | 24 +--- src/gpgpu-sim/gpu-cache.cc | 97 ++++++-------- src/gpgpu-sim/gpu-cache.h | 26 ++-- src/gpgpu-sim/gpu-sim.cc | 6 + 11 files changed, 116 insertions(+), 200 deletions(-) (limited to 'configs') diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config index b173dd0..c83159f 100644 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -120,7 +120,7 @@ -gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 1.5MB L2 cache --gpgpu_cache:dl2 S:32:128:16,L:B:m:L:L,A:256:64,16:0,32 +-gpgpu_cache:dl2 S:32:128:16,L:B:m:L:P,A:256:64,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 -gpgpu_perf_sim_memcpy 1 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index ce6f745..5b243a5 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -115,7 +115,7 @@ -gpgpu_flush_l1_cache 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 S:1:128:1024,L:B:m:L:L,A:256:64,16:0,32 +-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:256:64,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 -gpgpu_perf_sim_memcpy 1 diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 8a4be23..6fe04ee 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -111,8 +111,8 @@ -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 -# 32 sets, each 128 bytes 32-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache --gpgpu_cache:dl2 S:32:128:32,L:B:m:L:L,A:192:4,32:0,32 +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives us 3MB L2 cache +-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:192:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -gpgpu_perf_sim_memcpy 1 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index c31c060..c4818d1 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -126,7 +126,7 @@ -gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache --gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 +-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -gpgpu_perf_sim_memcpy 1 diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index ef28dd8..64edc67 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -127,7 +127,7 @@ -gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache --gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 +-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -gpgpu_perf_sim_memcpy 1 diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc index 91ba47f..c01b8fa 100644 --- a/src/gpgpu-sim/addrdec.cc +++ b/src/gpgpu-sim/addrdec.cc @@ -31,9 +31,12 @@ #include #include "../option_parser.h" #include "gpu-sim.h" +#include "hashing.h" static long int powli(long int x, long int y); static unsigned int LOGB2_32(unsigned int v); +static unsigned next_powerOf2(unsigned n); + static new_addr_type addrdec_packbits(new_addr_type mask, new_addr_type val, unsigned char high, unsigned char low); static void addrdec_getmasklimit(new_addr_type mask, unsigned char *high, @@ -133,121 +136,29 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, break; case BITWISE_PERMUTATION: { assert(!gap); - tlx->chip = (tlx->chip) ^ (rest_of_addr_high_bits & (m_n_channel - 1)); + tlx->chip = + bitwise_hash_function(rest_of_addr_high_bits, tlx->chip, m_n_channel); assert(tlx->chip < m_n_channel); break; } case IPOLY: { - /* - * Set Indexing function from "Pseudo-randomly interleaved memory." - * Rau, B. R et al. - * ISCA 1991 - * http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=348DEA37A3E440473B3C075EAABC63B6?doi=10.1.1.12.7149&rep=rep1&type=pdf - * - * equations are corresponding to IPOLY(37) and are adopted from: - * "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu - * cache management scheme." Khairy et al. IEEE TPDS 2017. - * - * equations for 32 banks are corresponding to IPOLY(37) - * equations for 64 banks are corresponding to IPOLY(67) - * To see all the IPOLY equations for all the degrees, see - * http://wireless-systems.ece.gatech.edu/6604/handouts/Peterson's%20Table.pdf - * - * We generate these equations using GF(2) arithmetic: - * http://www.ee.unb.ca/cgi-bin/tervo/calc.pl?num=&den=&f=d&e=1&m=1 - * - * We go through all the strides 128 (10000000), 256 (100000000),... and - * do modular arithmetic in GF(2) Then, we create the H-matrix and group - * each bit together, for more info read the ISCA 1991 paper - * - * IPOLY hashing guarantees conflict-free for all 2^n strides which widely - * exit in GPGPU applications and also show good performance for other - * strides. - */ - assert(!gap); - if (m_n_channel == 32 && m_n_sub_partition_in_channel == 1) { - std::bitset<64> a(rest_of_addr_high_bits); - std::bitset<5> chip(tlx->chip); - chip[0] = a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[6] ^ a[5] ^ a[3] ^ - a[0] ^ chip[0]; - chip[1] = a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[6] ^ a[4] ^ - a[1] ^ chip[1]; - chip[2] = a[14] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[3] ^ a[2] ^ - a[0] ^ chip[2]; - chip[3] = - a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[4] ^ a[3] ^ a[1] ^ chip[3]; - chip[4] = - a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ a[2] ^ chip[4]; - tlx->chip = chip.to_ulong(); - break; - } else if (m_n_channel == 16 && m_n_sub_partition_in_channel == 2) { - std::bitset<64> a(rest_of_addr_high_bits); - std::bitset<4> chip(tlx->chip); - std::bitset<32> bk(tlx->bk); - chip[0] = a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[6] ^ a[5] ^ a[3] ^ - a[0] ^ chip[0]; - chip[1] = a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[6] ^ a[4] ^ - a[1] ^ chip[1]; - chip[2] = a[14] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[3] ^ a[2] ^ - a[0] ^ chip[2]; - chip[3] = - a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[4] ^ a[3] ^ a[1] ^ chip[3]; - tlx->chip = chip.to_ulong(); - unsigned par_id = - a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ a[2] ^ bk[0]; - tlx->sub_partition = tlx->chip * m_n_sub_partition_in_channel + par_id; - assert(tlx->chip < m_n_channel); - assert(tlx->sub_partition < m_n_channel * m_n_sub_partition_in_channel); - return; - break; - } else if (m_n_channel == 32 && m_n_sub_partition_in_channel == 2) { - std::bitset<64> a(rest_of_addr_high_bits); - std::bitset<5> chip(tlx->chip); - std::bitset<32> bk(tlx->bk); - chip[0] = a[18] ^ a[17] ^ a[16] ^ a[15] ^ a[12] ^ a[10] ^ a[6] ^ a[5] ^ - a[0] ^ chip[0]; - chip[1] = a[15] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[5] ^ a[1] ^ - a[0] ^ chip[1]; - chip[2] = a[16] ^ a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[8] ^ a[6] ^ a[2] ^ - a[1] ^ chip[2]; - chip[3] = a[17] ^ a[15] ^ a[14] ^ a[13] ^ a[12] ^ a[9] ^ a[7] ^ a[3] ^ - a[2] ^ chip[3]; - chip[4] = a[18] ^ a[16] ^ a[15] ^ a[14] ^ a[13] ^ a[10] ^ a[8] ^ a[4] ^ - a[3] ^ chip[4]; - tlx->chip = chip.to_ulong(); - unsigned par_id = - a[17] ^ a[16] ^ a[15] ^ a[14] ^ a[11] ^ a[9] ^ a[5] ^ a[4] ^ bk[0]; - tlx->sub_partition = tlx->chip * m_n_sub_partition_in_channel + par_id; - assert(tlx->chip < m_n_channel); - assert(tlx->sub_partition < m_n_channel * m_n_sub_partition_in_channel); - return; - break; - } else { /* Else incorrect number of channels for the hashing function */ - assert( - "\nGPGPU-Sim memory_partition_indexing error: The number of " - "channels should be " - "32 or 64 for the hashing IPOLY index function.\n" && - 0); - } - assert(tlx->chip < m_n_channel); - break; - } - case PAE: { - // Page Address Entropy - // random selected bits from the page and bank bits - // similar to - // Liu, Yuxi, et al. "Get Out of the Valley: Power-Efficient Address - assert(!gap); - std::bitset<64> a(tlx->row); - std::bitset<5> chip(tlx->chip); - std::bitset<4> b(tlx->bk); - chip[0] = a[13] ^ a[10] ^ a[9] ^ a[5] ^ a[0] ^ b[3] ^ b[0] ^ chip[0]; - chip[1] = a[12] ^ a[11] ^ a[6] ^ a[1] ^ b[3] ^ b[2] ^ b[1] ^ chip[1]; - chip[2] = a[14] ^ a[9] ^ a[8] ^ a[7] ^ a[2] ^ b[1] ^ chip[2]; - chip[3] = a[11] ^ a[10] ^ a[8] ^ a[3] ^ b[2] ^ b[3] ^ chip[3]; - chip[4] = a[12] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ b[1] ^ b[0] ^ chip[4]; - tlx->chip = chip.to_ulong(); + // assert(!gap); + unsigned sub_partition_addr_mask = m_n_sub_partition_in_channel - 1; + unsigned sub_partition = tlx->chip * m_n_sub_partition_in_channel + + (tlx->bk & sub_partition_addr_mask); + sub_partition = ipoly_hash_function( + rest_of_addr_high_bits, sub_partition, + nextPowerOf2_m_n_channel * m_n_sub_partition_in_channel); + + if (gap) // if it is not 2^n partitions, then take modular + sub_partition = + sub_partition % (m_n_channel * m_n_sub_partition_in_channel); + + tlx->chip = sub_partition / m_n_channel; + tlx->sub_partition = sub_partition; assert(tlx->chip < m_n_channel); + assert(tlx->sub_partition < m_n_channel * m_n_sub_partition_in_channel); + return; break; } case RANDOM: { @@ -377,6 +288,8 @@ void linear_to_raw_address_translation::init( log2sub_partition = ::LOGB2_32(n_sub_partition_in_channel); m_n_channel = n_channel; m_n_sub_partition_in_channel = n_sub_partition_in_channel; + nextPowerOf2_m_n_channel = ::next_powerOf2(n_channel); + m_n_sub_partition_total = n_channel * n_sub_partition_in_channel; gap = (n_channel - ::powli(2, nchipbits)); if (gap) { @@ -663,6 +576,22 @@ static unsigned int LOGB2_32(unsigned int v) { return r; } +// compute power of two greater than or equal to n +// https://www.techiedelight.com/round-next-highest-power-2/ +unsigned next_powerOf2(unsigned n) { + // decrement n (to handle the case when n itself + // is a power of 2) + n = n - 1; + + // do till only one bit is left + while (n & n - 1) n = n & (n - 1); // unset rightmost bit + + // n is now a power of two (less than n) + + // return next power of 2 + return n << 1; +} + static new_addr_type addrdec_packbits(new_addr_type mask, new_addr_type val, unsigned char high, unsigned char low) { unsigned pos = 0; diff --git a/src/gpgpu-sim/addrdec.h b/src/gpgpu-sim/addrdec.h index dd0e5a0..d8db416 100644 --- a/src/gpgpu-sim/addrdec.h +++ b/src/gpgpu-sim/addrdec.h @@ -87,8 +87,10 @@ class linear_to_raw_address_translation { unsigned int gap; unsigned m_n_channel; int m_n_sub_partition_in_channel; + int m_n_sub_partition_total; unsigned log2channel; unsigned log2sub_partition; + unsigned nextPowerOf2_m_n_channel; }; #endif diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 041cfce..ca47c46 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -31,6 +31,7 @@ #include "dram_sched.h" #include "gpu-misc.h" #include "gpu-sim.h" +#include "hashing.h" #include "l2cache.h" #include "mem_fetch.h" #include "mem_latency_stat.h" @@ -207,8 +208,8 @@ dram_req_t::dram_req_t(class mem_fetch *mf, unsigned banks, } case BITWISE_XORING_BK_INDEX: { // xoring bank bits with lower bits of the page - int lbank = LOGB2(banks); - bk = tlx.bk ^ (tlx.row & ((1 << lbank) - 1)); + bk = bitwise_hash_function(tlx.row, tlx.bk, banks); + assert(bk < banks); break; } case IPOLY_BK_INDEX: { @@ -216,22 +217,9 @@ dram_req_t::dram_req_t(class mem_fetch *mf, unsigned banks, * memory." Rau, B. R et al. ISCA 1991 * http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=348DEA37A3E440473B3C075EAABC63B6?doi=10.1.1.12.7149&rep=rep1&type=pdf */ - if (banks == 16) { - std::bitset<64> a(tlx.row); - std::bitset<4> b(tlx.bk); - b[0] = a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[6] ^ a[4] ^ a[3] ^ a[0] ^ b[0]; - b[1] = a[12] ^ a[8] ^ a[7] ^ a[6] ^ a[5] ^ a[3] ^ a[1] ^ a[0] ^ b[1]; - b[2] = a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[4] ^ a[2] ^ a[1] ^ b[2]; - b[3] = a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[5] ^ a[3] ^ a[2] ^ b[3]; - bk = b.to_ulong(); - assert(bk < banks); - } else { /* Else incorrect number of channels for the hashing function */ - assert( - "\nGPGPU-Sim memory_banking indexing error: The number of banks " - "should be " - "16 for the hashing IPOLY index function.\n" && - 0); - } + // xoring bank bits with lower bits of the page + bk = ipoly_hash_function(tlx.row, tlx.bk, banks); + assert(bk < banks); break; } case CUSTOM_BK_INDEX: diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index adce3a2..75c3691 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -29,6 +29,7 @@ #include "gpu-cache.h" #include #include "gpu-sim.h" +#include "hashing.h" #include "stat-tool.h" // used to allocate memory that is large enough to adapt the changes in cache @@ -62,24 +63,31 @@ unsigned l1d_cache_config::set_bank(new_addr_type addr) const { // For sector cache, we select one sector per bank (sector interleaving) // This is what was found in Volta (one sector per bank, sector interleaving) // otherwise, line interleaving - if (m_cache_type == SECTOR) - return (addr >> m_sector_sz_log2) & (l1_banks - 1); - else - return (addr >> m_line_sz_log2) & (l1_banks - 1); + return cache_config::hash_function(addr, l1_banks, l1_banks_byte_interleaving, + m_l1_banks_log2, + l1_banks_hashing_function); +} + +unsigned cache_config::set_index(new_addr_type addr) const { + return cache_config::hash_function(addr, m_nset, m_line_sz_log2, m_nset_log2, + m_set_index_function); } -unsigned l1d_cache_config::set_index(new_addr_type addr) const { - unsigned set_index = m_nset; // Default to linear set index function - unsigned lower_xor = 0; - unsigned upper_xor = 0; +unsigned cache_config::hash_function(new_addr_type addr, unsigned m_nset, + unsigned m_line_sz_log2, + unsigned m_nset_log2, + unsigned m_index_function) const { + unsigned set_index = 0; - switch (m_set_index_function) { - case FERMI_HASH_SET_FUNCTION: - case BITWISE_XORING_FUNCTION: + switch (m_index_function) { + case FERMI_HASH_SET_FUNCTION: { /* * Set Indexing function from "A Detailed GPU Cache Model Based on Reuse * Distance Theory" Cedric Nugteren et al. HPCA 2014 */ + unsigned lower_xor = 0; + unsigned upper_xor = 0; + if (m_nset == 32 || m_nset == 64) { // Lower xor value is bits 7-11 lower_xor = (addr >> m_line_sz_log2) & 0x1F; @@ -102,54 +110,34 @@ unsigned l1d_cache_config::set_index(new_addr_type addr) const { 0); } break; + } - case HASH_IPOLY_FUNCTION: - /* - * Set Indexing function from "Pseudo-randomly interleaved memory." - * Rau, B. R et al. - * ISCA 1991 - * - * "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu - * cache management scheme." Khairy et al. IEEE TPDS 2017. - */ - if (m_nset == 32 || m_nset == 64) { - std::bitset<64> a(addr); - std::bitset<6> index; - index[0] = a[25] ^ a[24] ^ a[23] ^ a[22] ^ a[21] ^ a[18] ^ a[17] ^ - a[15] ^ a[12] ^ a[7]; // 10 - index[1] = a[26] ^ a[25] ^ a[24] ^ a[23] ^ a[22] ^ a[19] ^ a[18] ^ - a[16] ^ a[13] ^ a[8]; // 10 - index[2] = a[26] ^ a[22] ^ a[21] ^ a[20] ^ a[19] ^ a[18] ^ a[15] ^ - a[14] ^ a[12] ^ a[9]; // 10 - index[3] = a[23] ^ a[22] ^ a[21] ^ a[20] ^ a[19] ^ a[16] ^ a[15] ^ - a[13] ^ a[10]; // 9 - index[4] = a[24] ^ a[23] ^ a[22] ^ a[21] ^ a[20] ^ a[17] ^ a[16] ^ - a[14] ^ a[11]; // 9 - - if (m_nset == 64) index[5] = a[12]; - - set_index = index.to_ulong(); - - } else { /* Else incorrect number of sets for the hashing function */ - assert( - "\nGPGPU-Sim cache configuration error: The number of sets should " - "be " - "32 or 64 for the hashing set index function.\n" && - 0); - } + case BITWISE_XORING_FUNCTION: { + new_addr_type higher_bits = addr >> (m_line_sz_log2 + m_nset_log2); + unsigned index = (addr >> m_line_sz_log2) & (m_nset - 1); + set_index = bitwise_hash_function(higher_bits, index, m_nset); break; - - case CUSTOM_SET_FUNCTION: + } + case HASH_IPOLY_FUNCTION: { + new_addr_type higher_bits = addr >> (m_line_sz_log2 + m_nset_log2); + unsigned index = (addr >> m_line_sz_log2) & (m_nset - 1); + set_index = ipoly_hash_function(higher_bits, index, m_nset); + break; + } + case CUSTOM_SET_FUNCTION: { /* No custom set function implemented */ break; + } - case LINEAR_SET_FUNCTION: + case LINEAR_SET_FUNCTION: { set_index = (addr >> m_line_sz_log2) & (m_nset - 1); break; + } - default: + default: { assert("\nUndefined set index function.\n" && 0); break; + } } // Linear function selected or custom set index function not implemented @@ -166,13 +154,14 @@ void l2_cache_config::init(linear_to_raw_address_translation *address_mapping) { } unsigned l2_cache_config::set_index(new_addr_type addr) const { - if (!m_address_mapping) { - return (addr >> m_line_sz_log2) & (m_nset - 1); - } else { + new_addr_type part_addr = addr; + + if (m_address_mapping) { // Calculate set index without memory partition bits to reduce set camping - new_addr_type part_addr = m_address_mapping->partition_address(addr); - return (part_addr >> m_line_sz_log2) & (m_nset - 1); + part_addr = m_address_mapping->partition_address(addr); } + + return cache_config::set_index(part_addr); } tag_array::~tag_array() { diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 2a37876..5c28b41 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -686,17 +686,11 @@ class cache_config { m_line_sz * m_nset * m_assoc, m_nset, m_assoc, m_line_sz); } - virtual unsigned set_index(new_addr_type addr) const { - if (m_set_index_function != LINEAR_SET_FUNCTION) { - printf( - "\nGPGPU-Sim cache configuration error: Hashing or " - "custom set index function selected in configuration " - "file for a cache that has not overloaded the set_index " - "function\n"); - abort(); - } - return (addr >> m_line_sz_log2) & (m_nset - 1); - } + virtual unsigned set_index(new_addr_type addr) const; + + unsigned hash_function(new_addr_type addr, unsigned m_nset, + unsigned m_line_sz_log2, unsigned m_nset_log2, + unsigned m_index_function) const; new_addr_type tag(new_addr_type addr) const { // For generality, the tag includes both index and tag. This allows for more @@ -793,10 +787,18 @@ class cache_config { class l1d_cache_config : public cache_config { public: l1d_cache_config() : cache_config() {} - virtual unsigned set_index(new_addr_type addr) const; unsigned set_bank(new_addr_type addr) const; + void init(char *config, FuncCache status) { + m_banks_byte_interleaving_log2 = LOGB2(l1_banks_byte_interleaving); + m_l1_banks_log2 = LOGB2(l1_banks); + cache_config::init(config, status); + } unsigned l1_latency; unsigned l1_banks; + unsigned m_l1_banks_log2; + unsigned l1_banks_byte_interleaving; + unsigned m_banks_byte_interleaving_log2; + unsigned l1_banks_hashing_function; }; class l2_cache_config : public cache_config { diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 03aebf3..1650688 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -252,6 +252,12 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32, &m_L1D_config.l1_banks, "The number of L1 cache banks", "1"); + option_parser_register(opp, "-gpgpu_l1_banks_byte_interleaving", OPT_UINT32, + &m_L1D_config.l1_banks_byte_interleaving, + "l1 banks byte interleaving granularity", "32"); + option_parser_register(opp, "-gpgpu_l1_banks_hashing_function", OPT_UINT32, + &m_L1D_config.l1_banks_hashing_function, + "l1 banks hashing function", "0"); option_parser_register(opp, "-gpgpu_l1_latency", OPT_UINT32, &m_L1D_config.l1_latency, "L1 Hit Latency", "1"); option_parser_register(opp, "-gpgpu_smem_latency", OPT_UINT32, &smem_latency, -- cgit v1.3 From ee3c46354c5ce758bf71cfb7bd2e7da7718bcc8a Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 1 Jun 2020 15:09:34 -0400 Subject: renaming the executable --- Makefile | 6 +- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- src/trace-driven/gpgpusim_trace_driven_main.cc | 163 ------------------------- src/trace-driven/main.cc | 163 +++++++++++++++++++++++++ 4 files changed, 167 insertions(+), 167 deletions(-) delete mode 100644 src/trace-driven/gpgpusim_trace_driven_main.cc create mode 100644 src/trace-driven/main.cc (limited to 'configs') diff --git a/Makefile b/Makefile index ee48514..feb9dd0 100644 --- a/Makefile +++ b/Makefile @@ -75,7 +75,7 @@ else TARGETS += $(SIM_LIB_DIR)/libOpenCL.so endif TARGETS += cuobjdump_to_ptxplus/cuobjdump_to_ptxplus - TARGETS += $(SIM_LIB_DIR)/gpgpusim.out + TARGETS += $(SIM_LIB_DIR)/accelsim.out MCPAT= MCPAT_OBJ_DIR= @@ -171,7 +171,7 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.10.1 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.10.1; fi -$(SIM_LIB_DIR)/gpgpusim.out: makedirs $(LIBS) cudalib $(SIM_LIB_DIR)/libcudart.so +$(SIM_LIB_DIR)/accelsim.out: makedirs $(LIBS) cudalib $(SIM_LIB_DIR)/libcudart.so ar rvs $(SIM_LIB_DIR)/libgpgpusim_static.a\ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/*.o \ @@ -181,7 +181,7 @@ $(SIM_LIB_DIR)/gpgpusim.out: makedirs $(LIBS) cudalib $(SIM_LIB_DIR)/libcudart.s $(SIM_OBJ_FILES_DIR)/trace-driven/*.o \ $(SIM_OBJ_FILES_DIR)/*.o \ $(MCPAT) - g++ -std=c++0x -o $(SIM_LIB_DIR)/gpgpusim.out src/trace-driven/gpgpusim_trace_driven_main.cc -L$(SIM_LIB_DIR) -I$(CUDA_INSTALL_PATH)/include -lgpgpusim_static -lm -lz -lGL -pthread + g++ -std=c++0x -o $(SIM_LIB_DIR)/accelsim.out src/trace-driven/main.cc -L$(SIM_LIB_DIR) -I$(CUDA_INSTALL_PATH)/include -lgpgpusim_static -lm -lz -lGL -pthread $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 64edc67..3fa51ee 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -131,7 +131,7 @@ -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -gpgpu_perf_sim_memcpy 1 --gpgpu_memory_partition_indexing 0 +-gpgpu_memory_partition_indexing 2 # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc deleted file mode 100644 index f12d39a..0000000 --- a/src/trace-driven/gpgpusim_trace_driven_main.cc +++ /dev/null @@ -1,163 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ -// abdallm@purdue.edu - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../../libcuda/gpgpu_context.h" -#include "../abstract_hardware_model.h" -#include "../cuda-sim/cuda-sim.h" -#include "../gpgpu-sim/gpu-sim.h" -#include "../gpgpu-sim/icnt_wrapper.h" -#include "../gpgpusim_entrypoint.h" -#include "../option_parser.h" -#include "ISA_Def/trace_opcode.h" -#include "trace_driven.h" - -/* TO DO: - * NOTE: the current version of trace-driven is functionally working fine, - * but we still need to improve traces compression and simulation speed. - * This includes: - * 1- Prefetch concurrent thread that prefetches traces from disk (to not be - * limited by disk speed) 2- traces compression format a. cfg format and remove - * thread/block Id from the head b. using zlib library to save in binary format - * - * 3- Efficient memory improvement (save string not objects - parse only 10 in - * the buffer) 4- Seeking capability - thread scheduler (save tb index and warp - * index info in the traces header) 5- Get rid off traces intermediate files - - * change the tracer - */ -gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[], - gpgpu_context* m_gpgpu_context, - class trace_config* m_config); - -int main(int argc, const char** argv) { - gpgpu_context* m_gpgpu_context = new gpgpu_context(); - trace_config tconfig; - - gpgpu_sim* m_gpgpu_sim = - gpgpu_trace_sim_init_perf_model(argc, argv, m_gpgpu_context, &tconfig); - m_gpgpu_sim->init(); - - // for each kernel - // load file - // parse and create kernel info - // launch - // while loop till the end of the end kernel execution - // prints stats - - trace_parser tracer(tconfig.get_traces_filename(), m_gpgpu_sim, - m_gpgpu_context); - tconfig.parse_config(); - - std::vector commandlist = tracer.parse_kernellist_file(); - - for (unsigned i = 0; i < commandlist.size(); ++i) { - trace_kernel_info_t* kernel_info = NULL; - if (commandlist[i].substr(0, 6) == "Memcpy") { - size_t addre, Bcount; - tracer.parse_memcpy_info(commandlist[i], addre, Bcount); - std::cout << commandlist[i] << std::endl; - m_gpgpu_sim->perf_memcpy_to_gpu(addre, Bcount); - continue; - } else { - kernel_info = tracer.parse_kernel_info(commandlist[i], &tconfig); - m_gpgpu_sim->launch(kernel_info); - } - - bool active = false; - bool sim_cycles = false; - bool break_limit = false; - - do { - if (!m_gpgpu_sim->active()) break; - - // performance simulation - if (m_gpgpu_sim->active()) { - m_gpgpu_sim->cycle(); - sim_cycles = true; - m_gpgpu_sim->deadlock_check(); - } else { - if (m_gpgpu_sim->cycle_insn_cta_max_hit()) { - m_gpgpu_context->the_gpgpusim->g_stream_manager - ->stop_all_running_kernels(); - break_limit = true; - } - } - - active = m_gpgpu_sim->active(); - - } while (active); - - if (kernel_info) { - tracer.kernel_finalizer(kernel_info); - m_gpgpu_sim->print_stats(); - } - - if (sim_cycles) { - m_gpgpu_sim->update_stats(); - m_gpgpu_context->print_simulation_time(); - } - - if (break_limit) { - printf( - "GPGPU-Sim: ** break due to reaching the maximum cycles (or " - "instructions) **\n"); - fflush(stdout); - exit(1); - } - } - - // we print this message to inform the gpgpu-simulation stats_collect script - // that we are done - printf("GPGPU-Sim: *** simulation thread exiting ***\n"); - printf("GPGPU-Sim: *** exit detected ***\n"); - - return 1; -} - -gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[], - gpgpu_context* m_gpgpu_context, - trace_config* m_config) { - srand(1); - print_splash(); - - option_parser_t opp = option_parser_create(); - - m_gpgpu_context->ptx_reg_options(opp); - m_gpgpu_context->func_sim->ptx_opcocde_latency_options(opp); - - icnt_reg_options(opp); - - m_gpgpu_context->the_gpgpusim->g_the_gpu_config = - new gpgpu_sim_config(m_gpgpu_context); - m_gpgpu_context->the_gpgpusim->g_the_gpu_config->reg_options( - opp); // register GPU microrachitecture options - m_config->reg_options(opp); - - option_parser_cmdline(opp, argc, argv); // parse configuration options - fprintf(stdout, "GPGPU-Sim: Configuration options:\n\n"); - option_parser_print(opp, stdout); - // Set the Numeric locale to a standard locale where a decimal point is a - // "dot" not a "comma" so it does the parsing correctly independent of the - // system environment variables - assert(setlocale(LC_NUMERIC, "C")); - m_gpgpu_context->the_gpgpusim->g_the_gpu_config->init(); - - m_gpgpu_context->the_gpgpusim->g_the_gpu = new trace_gpgpu_sim( - *(m_gpgpu_context->the_gpgpusim->g_the_gpu_config), m_gpgpu_context); - - m_gpgpu_context->the_gpgpusim->g_stream_manager = - new stream_manager((m_gpgpu_context->the_gpgpusim->g_the_gpu), - m_gpgpu_context->func_sim->g_cuda_launch_blocking); - - m_gpgpu_context->the_gpgpusim->g_simulation_starttime = time((time_t*)NULL); - - return m_gpgpu_context->the_gpgpusim->g_the_gpu; -} diff --git a/src/trace-driven/main.cc b/src/trace-driven/main.cc new file mode 100644 index 0000000..f12d39a --- /dev/null +++ b/src/trace-driven/main.cc @@ -0,0 +1,163 @@ +// developed by Mahmoud Khairy, Purdue Univ +// abdallm@purdue.edu + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../libcuda/gpgpu_context.h" +#include "../abstract_hardware_model.h" +#include "../cuda-sim/cuda-sim.h" +#include "../gpgpu-sim/gpu-sim.h" +#include "../gpgpu-sim/icnt_wrapper.h" +#include "../gpgpusim_entrypoint.h" +#include "../option_parser.h" +#include "ISA_Def/trace_opcode.h" +#include "trace_driven.h" + +/* TO DO: + * NOTE: the current version of trace-driven is functionally working fine, + * but we still need to improve traces compression and simulation speed. + * This includes: + * 1- Prefetch concurrent thread that prefetches traces from disk (to not be + * limited by disk speed) 2- traces compression format a. cfg format and remove + * thread/block Id from the head b. using zlib library to save in binary format + * + * 3- Efficient memory improvement (save string not objects - parse only 10 in + * the buffer) 4- Seeking capability - thread scheduler (save tb index and warp + * index info in the traces header) 5- Get rid off traces intermediate files - + * change the tracer + */ +gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[], + gpgpu_context* m_gpgpu_context, + class trace_config* m_config); + +int main(int argc, const char** argv) { + gpgpu_context* m_gpgpu_context = new gpgpu_context(); + trace_config tconfig; + + gpgpu_sim* m_gpgpu_sim = + gpgpu_trace_sim_init_perf_model(argc, argv, m_gpgpu_context, &tconfig); + m_gpgpu_sim->init(); + + // for each kernel + // load file + // parse and create kernel info + // launch + // while loop till the end of the end kernel execution + // prints stats + + trace_parser tracer(tconfig.get_traces_filename(), m_gpgpu_sim, + m_gpgpu_context); + tconfig.parse_config(); + + std::vector commandlist = tracer.parse_kernellist_file(); + + for (unsigned i = 0; i < commandlist.size(); ++i) { + trace_kernel_info_t* kernel_info = NULL; + if (commandlist[i].substr(0, 6) == "Memcpy") { + size_t addre, Bcount; + tracer.parse_memcpy_info(commandlist[i], addre, Bcount); + std::cout << commandlist[i] << std::endl; + m_gpgpu_sim->perf_memcpy_to_gpu(addre, Bcount); + continue; + } else { + kernel_info = tracer.parse_kernel_info(commandlist[i], &tconfig); + m_gpgpu_sim->launch(kernel_info); + } + + bool active = false; + bool sim_cycles = false; + bool break_limit = false; + + do { + if (!m_gpgpu_sim->active()) break; + + // performance simulation + if (m_gpgpu_sim->active()) { + m_gpgpu_sim->cycle(); + sim_cycles = true; + m_gpgpu_sim->deadlock_check(); + } else { + if (m_gpgpu_sim->cycle_insn_cta_max_hit()) { + m_gpgpu_context->the_gpgpusim->g_stream_manager + ->stop_all_running_kernels(); + break_limit = true; + } + } + + active = m_gpgpu_sim->active(); + + } while (active); + + if (kernel_info) { + tracer.kernel_finalizer(kernel_info); + m_gpgpu_sim->print_stats(); + } + + if (sim_cycles) { + m_gpgpu_sim->update_stats(); + m_gpgpu_context->print_simulation_time(); + } + + if (break_limit) { + printf( + "GPGPU-Sim: ** break due to reaching the maximum cycles (or " + "instructions) **\n"); + fflush(stdout); + exit(1); + } + } + + // we print this message to inform the gpgpu-simulation stats_collect script + // that we are done + printf("GPGPU-Sim: *** simulation thread exiting ***\n"); + printf("GPGPU-Sim: *** exit detected ***\n"); + + return 1; +} + +gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[], + gpgpu_context* m_gpgpu_context, + trace_config* m_config) { + srand(1); + print_splash(); + + option_parser_t opp = option_parser_create(); + + m_gpgpu_context->ptx_reg_options(opp); + m_gpgpu_context->func_sim->ptx_opcocde_latency_options(opp); + + icnt_reg_options(opp); + + m_gpgpu_context->the_gpgpusim->g_the_gpu_config = + new gpgpu_sim_config(m_gpgpu_context); + m_gpgpu_context->the_gpgpusim->g_the_gpu_config->reg_options( + opp); // register GPU microrachitecture options + m_config->reg_options(opp); + + option_parser_cmdline(opp, argc, argv); // parse configuration options + fprintf(stdout, "GPGPU-Sim: Configuration options:\n\n"); + option_parser_print(opp, stdout); + // Set the Numeric locale to a standard locale where a decimal point is a + // "dot" not a "comma" so it does the parsing correctly independent of the + // system environment variables + assert(setlocale(LC_NUMERIC, "C")); + m_gpgpu_context->the_gpgpusim->g_the_gpu_config->init(); + + m_gpgpu_context->the_gpgpusim->g_the_gpu = new trace_gpgpu_sim( + *(m_gpgpu_context->the_gpgpusim->g_the_gpu_config), m_gpgpu_context); + + m_gpgpu_context->the_gpgpusim->g_stream_manager = + new stream_manager((m_gpgpu_context->the_gpgpusim->g_the_gpu), + m_gpgpu_context->func_sim->g_cuda_launch_blocking); + + m_gpgpu_context->the_gpgpusim->g_simulation_starttime = time((time_t*)NULL); + + return m_gpgpu_context->the_gpgpusim->g_the_gpu; +} -- cgit v1.3 From 68e873ef5cb3d0e88b8fb2a148e7870d09110748 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 1 Jun 2020 15:15:28 -0400 Subject: revmoing traces driven from gpgpusim --- configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config | 4 - configs/tested-cfgs/SM6_TITANX/trace.config | 4 - configs/tested-cfgs/SM75_RTX2060/trace.config | 25 - configs/tested-cfgs/SM7_QV100/trace.config | 19 - configs/tested-cfgs/SM7_TITANV/trace.config | 19 - src/trace-driven/ISA_Def/kepler_opcode.h | 148 ---- src/trace-driven/ISA_Def/pascal_opcode.h | 199 ------ src/trace-driven/ISA_Def/trace_opcode.h | 230 ------ src/trace-driven/ISA_Def/turing_opcode.h | 221 ------ src/trace-driven/ISA_Def/volta_opcode.h | 177 ----- src/trace-driven/main.cc | 163 ----- src/trace-driven/trace_driven.cc | 811 ---------------------- src/trace-driven/trace_driven.h | 210 ------ 13 files changed, 2230 deletions(-) delete mode 100644 configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config delete mode 100644 configs/tested-cfgs/SM6_TITANX/trace.config delete mode 100644 configs/tested-cfgs/SM75_RTX2060/trace.config delete mode 100644 configs/tested-cfgs/SM7_QV100/trace.config delete mode 100644 configs/tested-cfgs/SM7_TITANV/trace.config delete mode 100644 src/trace-driven/ISA_Def/kepler_opcode.h delete mode 100644 src/trace-driven/ISA_Def/pascal_opcode.h delete mode 100644 src/trace-driven/ISA_Def/trace_opcode.h delete mode 100644 src/trace-driven/ISA_Def/turing_opcode.h delete mode 100644 src/trace-driven/ISA_Def/volta_opcode.h delete mode 100644 src/trace-driven/main.cc delete mode 100644 src/trace-driven/trace_driven.cc delete mode 100644 src/trace-driven/trace_driven.h (limited to 'configs') diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config deleted file mode 100644 index 4c80036..0000000 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config +++ /dev/null @@ -1,4 +0,0 @@ --trace_opcode_latency_initiation_int 4,1 --trace_opcode_latency_initiation_sp 4,1 --trace_opcode_latency_initiation_dp 20,2 --trace_opcode_latency_initiation_sfu 200,2 diff --git a/configs/tested-cfgs/SM6_TITANX/trace.config b/configs/tested-cfgs/SM6_TITANX/trace.config deleted file mode 100644 index 88bcdc0..0000000 --- a/configs/tested-cfgs/SM6_TITANX/trace.config +++ /dev/null @@ -1,4 +0,0 @@ --trace_opcode_latency_initiation_int 4,1 --trace_opcode_latency_initiation_sp 4,1 --trace_opcode_latency_initiation_dp 20,8 --trace_opcode_latency_initiation_sfu 20,4 diff --git a/configs/tested-cfgs/SM75_RTX2060/trace.config b/configs/tested-cfgs/SM75_RTX2060/trace.config deleted file mode 100644 index 17b6cc7..0000000 --- a/configs/tested-cfgs/SM75_RTX2060/trace.config +++ /dev/null @@ -1,25 +0,0 @@ --trace_opcode_latency_initiation_int 4,2 --trace_opcode_latency_initiation_sp 4,2 --trace_opcode_latency_initiation_dp 8,4 --trace_opcode_latency_initiation_sfu 20,8 --trace_opcode_latency_initiation_tensor 8,4 - -#execute branch insts on spec unit 1 -#in Turing, there is a dedicated branch unit -#,,,,, --specialized_unit_1 1,4,4,4,4,BRA -#, --trace_opcode_latency_initiation_spec_op_1 4,4 - -#TEX unit, make fixed latency for all tex insts --specialized_unit_2 1,1,200,4,4,TEX --trace_opcode_latency_initiation_spec_op_2 200,4 - -#tensor unit --specialized_unit_3 1,4,8,4,4,TENSOR --trace_opcode_latency_initiation_spec_op_3 8,4 - -#UDP unit -#for more info about UDP, see https://www.hotchips.org/hc31/HC31_2.12_NVIDIA_final.pdf --specialized_unit_4 1,4,4,4,4,UDP --trace_opcode_latency_initiation_spec_op_4 4,2 diff --git a/configs/tested-cfgs/SM7_QV100/trace.config b/configs/tested-cfgs/SM7_QV100/trace.config deleted file mode 100644 index 88f5706..0000000 --- a/configs/tested-cfgs/SM7_QV100/trace.config +++ /dev/null @@ -1,19 +0,0 @@ --trace_opcode_latency_initiation_int 4,2 --trace_opcode_latency_initiation_sp 4,2 --trace_opcode_latency_initiation_dp 8,4 --trace_opcode_latency_initiation_sfu 20,8 --trace_opcode_latency_initiation_tensor 8,4 - -#execute branch insts on spec unit 1 -#in Volta, there is a dedicated branch unit -#,,,,, --specialized_unit_1 1,4,4,4,4,BRA --trace_opcode_latency_initiation_spec_op_1 4,4 - -#TEX unit, make fixed latency for all tex insts --specialized_unit_2 1,4,200,4,4,TEX --trace_opcode_latency_initiation_spec_op_2 200,4 - -#tensor unit --specialized_unit_3 1,4,8,4,4,TENSOR --trace_opcode_latency_initiation_spec_op_3 8,4 diff --git a/configs/tested-cfgs/SM7_TITANV/trace.config b/configs/tested-cfgs/SM7_TITANV/trace.config deleted file mode 100644 index 88f5706..0000000 --- a/configs/tested-cfgs/SM7_TITANV/trace.config +++ /dev/null @@ -1,19 +0,0 @@ --trace_opcode_latency_initiation_int 4,2 --trace_opcode_latency_initiation_sp 4,2 --trace_opcode_latency_initiation_dp 8,4 --trace_opcode_latency_initiation_sfu 20,8 --trace_opcode_latency_initiation_tensor 8,4 - -#execute branch insts on spec unit 1 -#in Volta, there is a dedicated branch unit -#,,,,, --specialized_unit_1 1,4,4,4,4,BRA --trace_opcode_latency_initiation_spec_op_1 4,4 - -#TEX unit, make fixed latency for all tex insts --specialized_unit_2 1,4,200,4,4,TEX --trace_opcode_latency_initiation_spec_op_2 200,4 - -#tensor unit --specialized_unit_3 1,4,8,4,4,TENSOR --trace_opcode_latency_initiation_spec_op_3 8,4 diff --git a/src/trace-driven/ISA_Def/kepler_opcode.h b/src/trace-driven/ISA_Def/kepler_opcode.h deleted file mode 100644 index c2f8548..0000000 --- a/src/trace-driven/ISA_Def/kepler_opcode.h +++ /dev/null @@ -1,148 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ -// abdallm@purdue.edu - -#ifndef KEPLER_OPCODE_H -#define KEPLER_OPCODE_H - -#include -#include -#include "trace_opcode.h" - -#define KEPLER_BINART_VERSION 35 -#define KEPLER_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 - -// TO DO: moving this to a yml or def files - -/// Kepler ISA -// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html -static const std::unordered_map Kepler_OpcodeMap = { - // Floating Point 32 Instructions - {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, - {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)}, - {"FADD", OpcodeChar(OP_FADD, SP_OP)}, - {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)}, - {"FCMP", OpcodeChar(OP_FCMP, SP_OP)}, - {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, - {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)}, - {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, - {"FSWZ", OpcodeChar(OP_FSWZ, SP_OP)}, - {"FSET", OpcodeChar(OP_FSET, SP_OP)}, - {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, - {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, - {"RRO", OpcodeChar(OP_RRO, SP_OP)}, - // SFU - {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, - - // Double Point Instructions - {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, - {"DADD", OpcodeChar(OP_DADD, DP_OP)}, - {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, - {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)}, - {"DSET", OpcodeChar(OP_DSET, DP_OP)}, - {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, - - // Integer Instructions - {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, - {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)}, - {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, - {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)}, - {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, - {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)}, - {"ISUB", OpcodeChar(OP_ISUB, INTP_OP)}, - {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, - {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, - {"ISAD", OpcodeChar(OP_ISAD, INTP_OP)}, - {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, - {"BFE", OpcodeChar(OP_BFE, INTP_OP)}, - {"BFI", OpcodeChar(OP_BFI, INTP_OP)}, - {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, - {"SHL", OpcodeChar(OP_SHL, INTP_OP)}, - {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, - {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, - {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)}, - {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, - {"ISET", OpcodeChar(OP_ISET, INTP_OP)}, - {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, - {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)}, - {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, - - // Conversion Instructions - {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, - {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, - {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, - {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, - - // Movement Instructions - {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, - {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, - {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, - {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, - {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, - - // Predicate Instructions - {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, - {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, - {"CSET", OpcodeChar(OP_CSET, ALU_OP)}, - {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)}, - {"PSET", OpcodeChar(OP_PSET, ALU_OP)}, - {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, - - // Texture Instructions - // For now, we ignore texture loads, consider it as ALU_OP - {"TEX", OpcodeChar(OP_TEX, ALU_OP)}, - {"TLD", OpcodeChar(OP_TLD, ALU_OP)}, - {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)}, - {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)}, - - // Load/Store Instructions - // For now, we ignore constant loads, consider it as ALU_OP, TO DO - {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, - // in Kepler, LD is load global so set it to LDG - {"LD", OpcodeChar(OP_LDG, LOAD_OP)}, - {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, - {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, - {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, - {"LDSLK", OpcodeChar(OP_LDSLK, LOAD_OP)}, - {"ST", OpcodeChar(OP_STG, STORE_OP)}, - {"STL", OpcodeChar(OP_STL, STORE_OP)}, - {"STS", OpcodeChar(OP_STS, STORE_OP)}, - {"STSCUL", OpcodeChar(OP_STSCUL, STORE_OP)}, - {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, - {"RED", OpcodeChar(OP_RED, STORE_OP)}, - {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, - {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, - {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, - - // surface memory instructions - {"SUCLAMP", OpcodeChar(OP_SUCLAMP, LOAD_OP)}, - {"SUBFM", OpcodeChar(OP_SUBFM, LOAD_OP)}, - {"SUEAU", OpcodeChar(OP_SUEAU, LOAD_OP)}, - {"SULDGA", OpcodeChar(OP_SULDGA, LOAD_OP)}, - {"SUSTGA", OpcodeChar(OP_SUSTGA, STORE_OP)}, - - // Control Instructions - {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)}, - {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)}, - {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)}, - {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)}, - {"CAL", OpcodeChar(OP_CAL, CALL_OPS)}, - {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)}, - {"RET", OpcodeChar(OP_RET, RET_OPS)}, - {"BRK", OpcodeChar(OP_BRK, RET_OPS)}, - {"CONT", OpcodeChar(OP_CONT, RET_OPS)}, - {"SSY", OpcodeChar(OP_SSY, RET_OPS)}, - {"PBK", OpcodeChar(OP_PBK, RET_OPS)}, - {"PCNT", OpcodeChar(OP_PCNT, RET_OPS)}, - {"PRET", OpcodeChar(OP_PRET, RET_OPS)}, - {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)}, - {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, - - // Miscellaneous Instructions - {"NOP", OpcodeChar(OP_NOP, ALU_OP)}, - {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, - {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, - {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, - {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, -}; - -#endif diff --git a/src/trace-driven/ISA_Def/pascal_opcode.h b/src/trace-driven/ISA_Def/pascal_opcode.h deleted file mode 100644 index 34fe400..0000000 --- a/src/trace-driven/ISA_Def/pascal_opcode.h +++ /dev/null @@ -1,199 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ -// abdallm@purdue.edu - -#ifndef PASCAL_OPCODE_H -#define PASCAL_OPCODE_H - -#include -#include -#include "trace_opcode.h" - -#define PASCAL_TITANX_BINART_VERSION 61 -#define PASCAL_P100_BINART_VERSION 60 - -#define PASCAL_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 - -// TO DO: moving this to a yml or def files - -/// Pascal SM_61 ISA -// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html -static const std::unordered_map Pascal_OpcodeMap = { - // Floating Point 32 Instructions - {"FADD", OpcodeChar(OP_FADD, SP_OP)}, - {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)}, - {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, - {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)}, - {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, - {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, - {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, - {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)}, - {"FSEL", OpcodeChar(OP_FSEL, SP_OP)}, - {"FSET", OpcodeChar(OP_FSET, SP_OP)}, - {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, - {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)}, - {"RRO", OpcodeChar(OP_RRO, SP_OP)}, - - // SFU - {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, - - // Floating Point 16 Instructions - {"HADD2", OpcodeChar(OP_HADD2, SP_OP)}, - {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)}, - {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)}, - {"HSET2", OpcodeChar(OP_HSET2, SP_OP)}, - {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)}, - - // Double Point Instructions - {"DADD", OpcodeChar(OP_DADD, DP_OP)}, - {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, - {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, - {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, - {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)}, - {"DSET", OpcodeChar(OP_DSET, DP_OP)}, - - // Integer Instructions - {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)}, - {"BREV", OpcodeChar(OP_BREV, INTP_OP)}, - {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, - {"IABS", OpcodeChar(OP_IABS, INTP_OP)}, - {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, - {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)}, - {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)}, - {"IDP", OpcodeChar(OP_IDP, INTP_OP)}, - {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)}, - {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, - {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)}, - {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, - {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, - {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)}, - {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, - {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, - {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, - {"ISET", OpcodeChar(OP_ISET, INTP_OP)}, - {"LEA", OpcodeChar(OP_LEA, INTP_OP)}, - {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, - {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)}, - {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)}, - {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, - {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, - {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, - {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)}, - {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)}, - {"BFE", OpcodeChar(OP_BFE, INTP_OP)}, - {"BFI", OpcodeChar(OP_BFI, INTP_OP)}, - {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)}, - {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)}, - {"SHL", OpcodeChar(OP_SHL, INTP_OP)}, - {"XMAD", OpcodeChar(OP_XMAD, INTP_OP)}, - {"VMNMX", OpcodeChar(OP_VMNMX, INTP_OP)}, - - // Conversion Instructions - {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, - {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, - {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, - {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, - {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)}, - {"FRND", OpcodeChar(OP_FRND, ALU_OP)}, - - // Movement Instructions - {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, - {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, - {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, - {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, - {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)}, - {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, - - // Predicate Instructions - {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)}, - {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, - {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, - {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, - {"CSET", OpcodeChar(OP_CSET, ALU_OP)}, - {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)}, - {"PSET", OpcodeChar(OP_PSET, ALU_OP)}, - - // Load/Store Instructions - {"LD", OpcodeChar(OP_LD, LOAD_OP)}, - // For now, we ignore constant loads, consider it as ALU_OP, TO DO - {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, - {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, - {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, - {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, - {"ST", OpcodeChar(OP_ST, STORE_OP)}, - {"STG", OpcodeChar(OP_STG, STORE_OP)}, - {"STL", OpcodeChar(OP_STL, STORE_OP)}, - {"STS", OpcodeChar(OP_STS, STORE_OP)}, - {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)}, - {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)}, - {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, - {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)}, - {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)}, - {"RED", OpcodeChar(OP_RED, STORE_OP)}, - {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, - {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, - {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)}, - {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, - {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)}, - - // Texture Instructions - // For now, we ignore texture loads, consider it as ALU_OP - {"TEX", OpcodeChar(OP_TEX, ALU_OP)}, - {"TLD", OpcodeChar(OP_TLD, ALU_OP)}, - {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)}, - {"TMML", OpcodeChar(OP_TMML, ALU_OP)}, - {"TXD", OpcodeChar(OP_TXD, ALU_OP)}, - {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)}, - {"TEXS", OpcodeChar(OP_TEXS, ALU_OP)}, - {"TLD4S", OpcodeChar(OP_TLD4S, ALU_OP)}, - {"TLDS", OpcodeChar(OP_TLDS, ALU_OP)}, - - // Control Instructions - {"BMOV", OpcodeChar(OP_BMOV, BRANCH_OP)}, - {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)}, - {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)}, - {"BREAK", OpcodeChar(OP_BREAK, BRANCH_OP)}, - {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)}, - {"BSSY", OpcodeChar(OP_BSSY, BRANCH_OP)}, - {"BSYNC", OpcodeChar(OP_BSYNC, BRANCH_OP)}, - {"CALL", OpcodeChar(OP_CALL, CALL_OPS)}, - {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, - {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)}, - {"SSY", OpcodeChar(OP_SSY, BRANCH_OP)}, - {"SYNC", OpcodeChar(OP_SYNC, BRANCH_OP)}, - {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)}, - {"KILL", OpcodeChar(OP_KILL, BRANCH_OP)}, - {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)}, - {"RET", OpcodeChar(OP_RET, RET_OPS)}, - {"RPCMOV", OpcodeChar(OP_RPCMOV, BRANCH_OP)}, - {"RTT", OpcodeChar(OP_RTT, RET_OPS)}, - {"WARPSYNC", OpcodeChar(OP_WARPSYNC, BRANCH_OP)}, - {"YIELD", OpcodeChar(OP_YIELD, BRANCH_OP)}, - {"CAL", OpcodeChar(OP_CAL, CALL_OPS)}, - {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)}, - {"PRET", OpcodeChar(OP_PRET, CALL_OPS)}, - {"BRK", OpcodeChar(OP_BRK, CALL_OPS)}, - {"PBK", OpcodeChar(OP_PBK, CALL_OPS)}, - {"CONT", OpcodeChar(OP_CONT, CALL_OPS)}, - {"PCNT", OpcodeChar(OP_PCNT, CALL_OPS)}, - {"PEXIT", OpcodeChar(OP_PEXIT, CALL_OPS)}, - - // Miscellaneous Instructions - {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, - {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, - {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)}, - {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)}, - {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)}, - {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)}, - {"LEPC", OpcodeChar(OP_LEPC, ALU_OP)}, - {"NOP", OpcodeChar(OP_NOP, ALU_OP)}, - {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)}, - {"R2B", OpcodeChar(OP_R2B, ALU_OP)}, - {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, - {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)}, - {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)}, - {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, - {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)}, - -}; - -#endif diff --git a/src/trace-driven/ISA_Def/trace_opcode.h b/src/trace-driven/ISA_Def/trace_opcode.h deleted file mode 100644 index 5675957..0000000 --- a/src/trace-driven/ISA_Def/trace_opcode.h +++ /dev/null @@ -1,230 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ -// abdallm@purdue.edu - -#ifndef TRACE_OPCODE_H -#define TRACE_OPCODE_H - -#include -#include -#include "../../abstract_hardware_model.h" - -enum TraceInstrOpcode { - // Volta (includes common insts for others cards as well) - OP_FADD = 1, - OP_FADD32I, - OP_FCHK, - OP_FFMA32I, - OP_FFMA, - OP_FMNMX, - OP_FMUL, - OP_FMUL32I, - OP_FSEL, - OP_FSET, - OP_FSETP, - OP_FSWZADD, - OP_MUFU, - OP_HADD2, - OP_HADD2_32I, - OP_HFMA2, - OP_HFMA2_32I, - OP_HMUL2, - OP_HMUL2_32I, - OP_HSET2, - OP_HSETP2, - OP_HMMA, - OP_DADD, - OP_DFMA, - OP_DMUL, - OP_DSETP, - OP_BMSK, - OP_BREV, - OP_FLO, - OP_IABS, - OP_IADD, - OP_IADD3, - OP_IADD32I, - OP_IDP, - OP_IDP4A, - OP_IMAD, - OP_IMMA, - OP_IMNMX, - OP_IMUL, - OP_IMUL32I, - OP_ISCADD, - OP_ISCADD32I, - OP_ISETP, - OP_LEA, - OP_LOP, - OP_LOP3, - OP_LOP32I, - OP_POPC, - OP_SHF, - OP_SHR, - OP_VABSDIFF, - OP_VABSDIFF4, - OP_F2F, - OP_F2I, - OP_I2F, - OP_I2I, - OP_I2IP, - OP_FRND, - OP_MOV, - OP_MOV32I, - OP_PRMT, - OP_SEL, - OP_SGXT, - OP_SHFL, - OP_PLOP3, - OP_PSETP, - OP_P2R, - OP_R2P, - OP_LD, - OP_LDC, - OP_LDG, - OP_LDL, - OP_LDS, - OP_ST, - OP_STG, - OP_STL, - OP_STS, - OP_MATCH, - OP_QSPC, - OP_ATOM, - OP_ATOMS, - OP_ATOMG, - OP_RED, - OP_CCTL, - OP_CCTLL, - OP_ERRBAR, - OP_MEMBAR, - OP_CCTLT, - OP_TEX, - OP_TLD, - OP_TLD4, - OP_TMML, - OP_TXD, - OP_TXQ, - OP_BMOV, - OP_BPT, - OP_BRA, - OP_BREAK, - OP_BRX, - OP_BSSY, - OP_BSYNC, - OP_CALL, - OP_EXIT, - OP_JMP, - OP_JMX, - OP_KILL, - OP_NANOSLEEP, - OP_RET, - OP_RPCMOV, - OP_RTT, - OP_WARPSYNC, - OP_YIELD, - OP_B2R, - OP_BAR, - OP_CS2R, - OP_CSMTEST, - OP_DEPBAR, - OP_GETLMEMBASE, - OP_LEPC, - OP_NOP, - OP_PMTRIG, - OP_R2B, - OP_S2R, - OP_SETCTAID, - OP_SETLMEMBASE, - OP_VOTE, - OP_VOTE_VTG, - // unique insts for pascal - OP_RRO, - OP_DMNMX, - OP_DSET, - OP_BFE, - OP_BFI, - OP_ICMP, - OP_IMADSP, - OP_SHL, - OP_XMAD, - OP_CSET, - OP_CSETP, - OP_TEXS, - OP_TLD4S, - OP_TLDS, - OP_CAL, - OP_JCAL, - OP_PRET, - OP_BRK, - OP_PBK, - OP_CONT, - OP_PCNT, - OP_PEXIT, - OP_SSY, - OP_SYNC, - OP_PSET, - OP_VMNMX, - OP_ISET, - // unique insts for turing - OP_BMMA, - OP_MOVM, - OP_LDSM, - OP_R2UR, - OP_S2UR, - OP_UBMSK, - OP_UBREV, - OP_UCLEA, - OP_UFLO, - OP_UIADD3, - OP_UIMAD, - OP_UISETP, - OP_ULDC, - OP_ULEA, - OP_ULOP, - OP_ULOP3, - OP_ULOP32I, - OP_UMOV, - OP_UP2UR, - OP_UPLOP3, - OP_UPOPC, - OP_UPRMT, - OP_UPSETP, - OP_UR2UP, - OP_USEL, - OP_USGXT, - OP_USHF, - OP_USHL, - OP_USHR, - OP_VOTEU, - OP_SUATOM, - OP_SULD, - OP_SURED, - OP_SUST, - OP_BRXU, - OP_JMXU, - // unique insts for kepler - OP_FCMP, - OP_FSWZ, - OP_ISAD, - OP_LDSLK, - OP_STSCUL, - OP_SUCLAMP, - OP_SUBFM, - OP_SUEAU, - OP_SULDGA, - OP_SUSTGA, - OP_ISUB, - SASS_NUM_OPCODES /* The total number of opcodes. */ -}; -typedef enum TraceInstrOpcode sass_op_type; - -struct OpcodeChar { - OpcodeChar(unsigned m_opcode, unsigned m_opcode_category) { - opcode = m_opcode; - opcode_category = m_opcode_category; - } - unsigned opcode; - unsigned opcode_category; -}; - -#endif diff --git a/src/trace-driven/ISA_Def/turing_opcode.h b/src/trace-driven/ISA_Def/turing_opcode.h deleted file mode 100644 index 12bbe76..0000000 --- a/src/trace-driven/ISA_Def/turing_opcode.h +++ /dev/null @@ -1,221 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ -// abdallm@purdue.edu - -#ifndef TURING_OPCODE_H -#define TURING_OPCODE_H - -#include -#include -#include "trace_opcode.h" - -#define TURING_BINART_VERSION 75 -#define TURING_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 - -// TO DO: moving this to a yml or def files - -/// Volta SM_70 ISA -// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html -static const std::unordered_map Turing_OpcodeMap = { - // Floating Point 32 Instructions - {"FADD", OpcodeChar(OP_FADD, SP_OP)}, - {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)}, - {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, - {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)}, - {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, - {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, - {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, - {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)}, - {"FSEL", OpcodeChar(OP_FSEL, SP_OP)}, - {"FSET", OpcodeChar(OP_FSET, SP_OP)}, - {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, - {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)}, - // SFU - {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, - - // Floating Point 16 Instructions - {"HADD2", OpcodeChar(OP_HADD2, SP_OP)}, - {"HADD2_32I", OpcodeChar(OP_HADD2_32I, SP_OP)}, - {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)}, - {"HFMA2_32I", OpcodeChar(OP_HFMA2_32I, SP_OP)}, - {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)}, - {"HMUL2_32I", OpcodeChar(OP_HMUL2_32I, SP_OP)}, - {"HSET2", OpcodeChar(OP_HSET2, SP_OP)}, - {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)}, - - // Tensor Core Instructions - // Execute Tensor Core Instructions on SPECIALIZED_UNIT_3 - {"HMMA", OpcodeChar(OP_HMMA, SPECIALIZED_UNIT_3_OP)}, - - // Double Point Instructions - {"DADD", OpcodeChar(OP_DADD, DP_OP)}, - {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, - {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, - {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, - - // Integer Instructions - {"BMMA", OpcodeChar(OP_BMMA, INTP_OP)}, //////// - {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)}, - {"BREV", OpcodeChar(OP_BREV, INTP_OP)}, - {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, - {"IABS", OpcodeChar(OP_IABS, INTP_OP)}, - {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, - {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)}, - {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)}, - {"IDP", OpcodeChar(OP_IDP, INTP_OP)}, - {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)}, - {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, - {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)}, - {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, - {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, - {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)}, - {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, - {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, - {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, - {"LEA", OpcodeChar(OP_LEA, INTP_OP)}, - {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, - {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)}, - {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)}, - {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, - {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, - {"SHL", OpcodeChar(OP_SHL, INTP_OP)}, ////////// - {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, - {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)}, - {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)}, - - // Conversion Instructions - {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, - {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, - {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, - {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, - {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)}, - {"FRND", OpcodeChar(OP_FRND, ALU_OP)}, - - // Movement Instructions - {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, - {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, - {"MOVM", OpcodeChar(OP_MOVM, ALU_OP)}, // move matrix - {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, - {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, - {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)}, - {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, - - // Predicate Instructions - {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)}, - {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, - {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, - {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, - - // Load/Store Instructions - {"LD", OpcodeChar(OP_LD, LOAD_OP)}, - // For now, we ignore constant loads, consider it as ALU_OP, TO DO - {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, - {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, - {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, - {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, - {"LDSM", OpcodeChar(OP_LDSM, LOAD_OP)}, // - {"ST", OpcodeChar(OP_ST, STORE_OP)}, - {"STG", OpcodeChar(OP_STG, STORE_OP)}, - {"STL", OpcodeChar(OP_STL, STORE_OP)}, - {"STS", OpcodeChar(OP_STS, STORE_OP)}, - {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)}, - {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)}, - {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, - {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)}, - {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)}, - {"RED", OpcodeChar(OP_RED, STORE_OP)}, - {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, - {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, - {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)}, - {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, - {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)}, - - // Uniform Datapath Instruction - // UDP unit - // for more info about UDP, see - // https://www.hotchips.org/hc31/HC31_2.12_NVIDIA_final.pdf - {"R2UR", OpcodeChar(OP_R2UR, SPECIALIZED_UNIT_4_OP)}, - {"S2UR", OpcodeChar(OP_S2UR, SPECIALIZED_UNIT_4_OP)}, - {"UBMSK", OpcodeChar(OP_UBMSK, SPECIALIZED_UNIT_4_OP)}, - {"UBREV", OpcodeChar(OP_UBREV, SPECIALIZED_UNIT_4_OP)}, - {"UCLEA", OpcodeChar(OP_UCLEA, SPECIALIZED_UNIT_4_OP)}, - {"UFLO", OpcodeChar(OP_UFLO, SPECIALIZED_UNIT_4_OP)}, - {"UIADD3", OpcodeChar(OP_UIADD3, SPECIALIZED_UNIT_4_OP)}, - {"UIMAD", OpcodeChar(OP_UIMAD, SPECIALIZED_UNIT_4_OP)}, - {"UISETP", OpcodeChar(OP_UISETP, SPECIALIZED_UNIT_4_OP)}, - {"ULDC", OpcodeChar(OP_ULDC, SPECIALIZED_UNIT_4_OP)}, - {"ULEA", OpcodeChar(OP_ULEA, SPECIALIZED_UNIT_4_OP)}, - {"ULOP", OpcodeChar(OP_ULOP, SPECIALIZED_UNIT_4_OP)}, - {"ULOP3", OpcodeChar(OP_ULOP3, SPECIALIZED_UNIT_4_OP)}, - {"ULOP32I", OpcodeChar(OP_ULOP32I, SPECIALIZED_UNIT_4_OP)}, - {"UMOV", OpcodeChar(OP_UMOV, SPECIALIZED_UNIT_4_OP)}, - {"UP2UR", OpcodeChar(OP_UP2UR, SPECIALIZED_UNIT_4_OP)}, - {"UPLOP3", OpcodeChar(OP_UPLOP3, SPECIALIZED_UNIT_4_OP)}, - {"UPOPC", OpcodeChar(OP_UPOPC, SPECIALIZED_UNIT_4_OP)}, - {"UPRMT", OpcodeChar(OP_UPRMT, SPECIALIZED_UNIT_4_OP)}, - {"UPSETP", OpcodeChar(OP_UPSETP, SPECIALIZED_UNIT_4_OP)}, - {"UR2UP", OpcodeChar(OP_UR2UP, SPECIALIZED_UNIT_4_OP)}, - {"USEL", OpcodeChar(OP_USEL, SPECIALIZED_UNIT_4_OP)}, - {"USGXT", OpcodeChar(OP_USGXT, SPECIALIZED_UNIT_4_OP)}, - {"USHF", OpcodeChar(OP_USHF, SPECIALIZED_UNIT_4_OP)}, - {"USHL", OpcodeChar(OP_USHL, SPECIALIZED_UNIT_4_OP)}, - {"USHR", OpcodeChar(OP_USHR, SPECIALIZED_UNIT_4_OP)}, - {"VOTEU", OpcodeChar(OP_VOTEU, SPECIALIZED_UNIT_4_OP)}, - - // Texture Instructions - // For now, we ignore texture loads, consider it as ALU_OP - {"TEX", OpcodeChar(OP_TEX, SPECIALIZED_UNIT_2_OP)}, - {"TLD", OpcodeChar(OP_TLD, SPECIALIZED_UNIT_2_OP)}, - {"TLD4", OpcodeChar(OP_TLD4, SPECIALIZED_UNIT_2_OP)}, - {"TMML", OpcodeChar(OP_TMML, SPECIALIZED_UNIT_2_OP)}, - {"TXD", OpcodeChar(OP_TXD, SPECIALIZED_UNIT_2_OP)}, - {"TXQ", OpcodeChar(OP_TXQ, SPECIALIZED_UNIT_2_OP)}, - - // Surface Instructions // - {"SUATOM", OpcodeChar(OP_SUATOM, ALU_OP)}, - {"SULD", OpcodeChar(OP_SULD, ALU_OP)}, - {"SURED", OpcodeChar(OP_SURED, ALU_OP)}, - {"SUST", OpcodeChar(OP_SUST, ALU_OP)}, - - // Control Instructions - // execute branch insts on a dedicated branch unit (SPECIALIZED_UNIT_1) - {"BMOV", OpcodeChar(OP_BMOV, SPECIALIZED_UNIT_1_OP)}, - {"BPT", OpcodeChar(OP_BPT, SPECIALIZED_UNIT_1_OP)}, - {"BRA", OpcodeChar(OP_BRA, SPECIALIZED_UNIT_1_OP)}, - {"BREAK", OpcodeChar(OP_BREAK, SPECIALIZED_UNIT_1_OP)}, - {"BRX", OpcodeChar(OP_BRX, SPECIALIZED_UNIT_1_OP)}, - {"BRXU", OpcodeChar(OP_BRXU, SPECIALIZED_UNIT_1_OP)}, // - {"BSSY", OpcodeChar(OP_BSSY, SPECIALIZED_UNIT_1_OP)}, - {"BSYNC", OpcodeChar(OP_BSYNC, SPECIALIZED_UNIT_1_OP)}, - {"CALL", OpcodeChar(OP_CALL, SPECIALIZED_UNIT_1_OP)}, - {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, - {"JMP", OpcodeChar(OP_JMP, SPECIALIZED_UNIT_1_OP)}, - {"JMX", OpcodeChar(OP_JMX, SPECIALIZED_UNIT_1_OP)}, - {"JMXU", OpcodeChar(OP_JMXU, SPECIALIZED_UNIT_1_OP)}, /// - {"KILL", OpcodeChar(OP_KILL, SPECIALIZED_UNIT_3_OP)}, - {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, SPECIALIZED_UNIT_1_OP)}, - {"RET", OpcodeChar(OP_RET, SPECIALIZED_UNIT_1_OP)}, - {"RPCMOV", OpcodeChar(OP_RPCMOV, SPECIALIZED_UNIT_1_OP)}, - {"RTT", OpcodeChar(OP_RTT, SPECIALIZED_UNIT_1_OP)}, - {"WARPSYNC", OpcodeChar(OP_WARPSYNC, SPECIALIZED_UNIT_1_OP)}, - {"YIELD", OpcodeChar(OP_YIELD, SPECIALIZED_UNIT_1_OP)}, - - // Miscellaneous Instructions - {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, - {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, - {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)}, - {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)}, - {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)}, - {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)}, - {"LEPC", OpcodeChar(OP_LEPC, ALU_OP)}, - {"NOP", OpcodeChar(OP_NOP, ALU_OP)}, - {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)}, - {"R2B", OpcodeChar(OP_R2B, ALU_OP)}, - {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, - {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)}, - {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)}, - {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, - {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)}, - -}; - -#endif diff --git a/src/trace-driven/ISA_Def/volta_opcode.h b/src/trace-driven/ISA_Def/volta_opcode.h deleted file mode 100644 index 3358211..0000000 --- a/src/trace-driven/ISA_Def/volta_opcode.h +++ /dev/null @@ -1,177 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ -// abdallm@purdue.edu - -#ifndef VOLTA_OPCODE_H -#define VOLTA_OPCODE_H - -#include -#include -#include "trace_opcode.h" - -#define VOLTA_BINART_VERSION 70 -#define VOLTA_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 - -// TO DO: moving this to a yml or def files - -/// Volta SM_70 ISA -// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html -static const std::unordered_map Volta_OpcodeMap = { - // Floating Point 32 Instructions - {"FADD", OpcodeChar(OP_FADD, SP_OP)}, - {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)}, - {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, - {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)}, - {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, - {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, - {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, - {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)}, - {"FSEL", OpcodeChar(OP_FSEL, SP_OP)}, - {"FSET", OpcodeChar(OP_FSET, SP_OP)}, - {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, - {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)}, - // SFU - {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, - - // Floating Point 16 Instructions - {"HADD2", OpcodeChar(OP_HADD2, SP_OP)}, - {"HADD2_32I", OpcodeChar(OP_HADD2_32I, SP_OP)}, - {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)}, - {"HFMA2_32I", OpcodeChar(OP_HFMA2_32I, SP_OP)}, - {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)}, - {"HMUL2_32I", OpcodeChar(OP_HMUL2_32I, SP_OP)}, - {"HSET2", OpcodeChar(OP_HSET2, SP_OP)}, - {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)}, - - // Tensor Core Instructions - // Execute Tensor Core Instructions on SPECIALIZED_UNIT_3 - {"HMMA", OpcodeChar(OP_HMMA, SPECIALIZED_UNIT_3_OP)}, - - // Double Point Instructions - {"DADD", OpcodeChar(OP_DADD, DP_OP)}, - {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, - {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, - {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, - - // Integer Instructions - {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)}, - {"BREV", OpcodeChar(OP_BREV, INTP_OP)}, - {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, - {"IABS", OpcodeChar(OP_IABS, INTP_OP)}, - {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, - {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)}, - {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)}, - {"IDP", OpcodeChar(OP_IDP, INTP_OP)}, - {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)}, - {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, - {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)}, - {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, - {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, - {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)}, - {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, - {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, - {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, - {"LEA", OpcodeChar(OP_LEA, INTP_OP)}, - {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, - {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)}, - {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)}, - {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, - {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, - {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, - {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)}, - {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)}, - - // Conversion Instructions - {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, - {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, - {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, - {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, - {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)}, - {"FRND", OpcodeChar(OP_FRND, ALU_OP)}, - - // Movement Instructions - {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, - {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, - {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, - {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, - {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)}, - {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, - - // Predicate Instructions - {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)}, - {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, - {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, - {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, - - // Load/Store Instructions - {"LD", OpcodeChar(OP_LD, LOAD_OP)}, - // For now, we ignore constant loads, consider it as ALU_OP, TO DO - {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, - {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, - {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, - {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, - {"ST", OpcodeChar(OP_ST, STORE_OP)}, - {"STG", OpcodeChar(OP_STG, STORE_OP)}, - {"STL", OpcodeChar(OP_STL, STORE_OP)}, - {"STS", OpcodeChar(OP_STS, STORE_OP)}, - {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)}, - {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)}, - {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, - {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)}, - {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)}, - {"RED", OpcodeChar(OP_RED, STORE_OP)}, - {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, - {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, - {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)}, - {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, - {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)}, - - // Texture Instructions - // For now, we ignore texture loads, consider it as ALU_OP - {"TEX", OpcodeChar(OP_TEX, SPECIALIZED_UNIT_2_OP)}, - {"TLD", OpcodeChar(OP_TLD, SPECIALIZED_UNIT_2_OP)}, - {"TLD4", OpcodeChar(OP_TLD4, SPECIALIZED_UNIT_2_OP)}, - {"TMML", OpcodeChar(OP_TMML, SPECIALIZED_UNIT_2_OP)}, - {"TXD", OpcodeChar(OP_TXD, SPECIALIZED_UNIT_2_OP)}, - {"TXQ", OpcodeChar(OP_TXQ, SPECIALIZED_UNIT_2_OP)}, - - // Control Instructions - // execute branch insts on a dedicated branch unit (SPECIALIZED_UNIT_1) - {"BMOV", OpcodeChar(OP_BMOV, SPECIALIZED_UNIT_1_OP)}, - {"BPT", OpcodeChar(OP_BPT, SPECIALIZED_UNIT_1_OP)}, - {"BRA", OpcodeChar(OP_BRA, SPECIALIZED_UNIT_1_OP)}, - {"BREAK", OpcodeChar(OP_BREAK, SPECIALIZED_UNIT_1_OP)}, - {"BRX", OpcodeChar(OP_BRX, SPECIALIZED_UNIT_1_OP)}, - {"BSSY", OpcodeChar(OP_BSSY, SPECIALIZED_UNIT_1_OP)}, - {"BSYNC", OpcodeChar(OP_BSYNC, SPECIALIZED_UNIT_1_OP)}, - {"CALL", OpcodeChar(OP_CALL, SPECIALIZED_UNIT_1_OP)}, - {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, - {"JMP", OpcodeChar(OP_JMP, SPECIALIZED_UNIT_1_OP)}, - {"JMX", OpcodeChar(OP_JMX, SPECIALIZED_UNIT_1_OP)}, - {"KILL", OpcodeChar(OP_KILL, SPECIALIZED_UNIT_1_OP)}, - {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, SPECIALIZED_UNIT_1_OP)}, - {"RET", OpcodeChar(OP_RET, SPECIALIZED_UNIT_1_OP)}, - {"RPCMOV", OpcodeChar(OP_RPCMOV, SPECIALIZED_UNIT_1_OP)}, - {"RTT", OpcodeChar(OP_RTT, SPECIALIZED_UNIT_1_OP)}, - {"WARPSYNC", OpcodeChar(OP_WARPSYNC, SPECIALIZED_UNIT_1_OP)}, - {"YIELD", OpcodeChar(OP_YIELD, SPECIALIZED_UNIT_1_OP)}, - - // Miscellaneous Instructions - {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, - {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, - {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)}, - {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)}, - {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)}, - {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)}, - {"LEPC", OpcodeChar(OP_LEPC, ALU_OP)}, - {"NOP", OpcodeChar(OP_NOP, ALU_OP)}, - {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)}, - {"R2B", OpcodeChar(OP_R2B, ALU_OP)}, - {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, - {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)}, - {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)}, - {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, - {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)}, - -}; - -#endif diff --git a/src/trace-driven/main.cc b/src/trace-driven/main.cc deleted file mode 100644 index f12d39a..0000000 --- a/src/trace-driven/main.cc +++ /dev/null @@ -1,163 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ -// abdallm@purdue.edu - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../../libcuda/gpgpu_context.h" -#include "../abstract_hardware_model.h" -#include "../cuda-sim/cuda-sim.h" -#include "../gpgpu-sim/gpu-sim.h" -#include "../gpgpu-sim/icnt_wrapper.h" -#include "../gpgpusim_entrypoint.h" -#include "../option_parser.h" -#include "ISA_Def/trace_opcode.h" -#include "trace_driven.h" - -/* TO DO: - * NOTE: the current version of trace-driven is functionally working fine, - * but we still need to improve traces compression and simulation speed. - * This includes: - * 1- Prefetch concurrent thread that prefetches traces from disk (to not be - * limited by disk speed) 2- traces compression format a. cfg format and remove - * thread/block Id from the head b. using zlib library to save in binary format - * - * 3- Efficient memory improvement (save string not objects - parse only 10 in - * the buffer) 4- Seeking capability - thread scheduler (save tb index and warp - * index info in the traces header) 5- Get rid off traces intermediate files - - * change the tracer - */ -gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[], - gpgpu_context* m_gpgpu_context, - class trace_config* m_config); - -int main(int argc, const char** argv) { - gpgpu_context* m_gpgpu_context = new gpgpu_context(); - trace_config tconfig; - - gpgpu_sim* m_gpgpu_sim = - gpgpu_trace_sim_init_perf_model(argc, argv, m_gpgpu_context, &tconfig); - m_gpgpu_sim->init(); - - // for each kernel - // load file - // parse and create kernel info - // launch - // while loop till the end of the end kernel execution - // prints stats - - trace_parser tracer(tconfig.get_traces_filename(), m_gpgpu_sim, - m_gpgpu_context); - tconfig.parse_config(); - - std::vector commandlist = tracer.parse_kernellist_file(); - - for (unsigned i = 0; i < commandlist.size(); ++i) { - trace_kernel_info_t* kernel_info = NULL; - if (commandlist[i].substr(0, 6) == "Memcpy") { - size_t addre, Bcount; - tracer.parse_memcpy_info(commandlist[i], addre, Bcount); - std::cout << commandlist[i] << std::endl; - m_gpgpu_sim->perf_memcpy_to_gpu(addre, Bcount); - continue; - } else { - kernel_info = tracer.parse_kernel_info(commandlist[i], &tconfig); - m_gpgpu_sim->launch(kernel_info); - } - - bool active = false; - bool sim_cycles = false; - bool break_limit = false; - - do { - if (!m_gpgpu_sim->active()) break; - - // performance simulation - if (m_gpgpu_sim->active()) { - m_gpgpu_sim->cycle(); - sim_cycles = true; - m_gpgpu_sim->deadlock_check(); - } else { - if (m_gpgpu_sim->cycle_insn_cta_max_hit()) { - m_gpgpu_context->the_gpgpusim->g_stream_manager - ->stop_all_running_kernels(); - break_limit = true; - } - } - - active = m_gpgpu_sim->active(); - - } while (active); - - if (kernel_info) { - tracer.kernel_finalizer(kernel_info); - m_gpgpu_sim->print_stats(); - } - - if (sim_cycles) { - m_gpgpu_sim->update_stats(); - m_gpgpu_context->print_simulation_time(); - } - - if (break_limit) { - printf( - "GPGPU-Sim: ** break due to reaching the maximum cycles (or " - "instructions) **\n"); - fflush(stdout); - exit(1); - } - } - - // we print this message to inform the gpgpu-simulation stats_collect script - // that we are done - printf("GPGPU-Sim: *** simulation thread exiting ***\n"); - printf("GPGPU-Sim: *** exit detected ***\n"); - - return 1; -} - -gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[], - gpgpu_context* m_gpgpu_context, - trace_config* m_config) { - srand(1); - print_splash(); - - option_parser_t opp = option_parser_create(); - - m_gpgpu_context->ptx_reg_options(opp); - m_gpgpu_context->func_sim->ptx_opcocde_latency_options(opp); - - icnt_reg_options(opp); - - m_gpgpu_context->the_gpgpusim->g_the_gpu_config = - new gpgpu_sim_config(m_gpgpu_context); - m_gpgpu_context->the_gpgpusim->g_the_gpu_config->reg_options( - opp); // register GPU microrachitecture options - m_config->reg_options(opp); - - option_parser_cmdline(opp, argc, argv); // parse configuration options - fprintf(stdout, "GPGPU-Sim: Configuration options:\n\n"); - option_parser_print(opp, stdout); - // Set the Numeric locale to a standard locale where a decimal point is a - // "dot" not a "comma" so it does the parsing correctly independent of the - // system environment variables - assert(setlocale(LC_NUMERIC, "C")); - m_gpgpu_context->the_gpgpusim->g_the_gpu_config->init(); - - m_gpgpu_context->the_gpgpusim->g_the_gpu = new trace_gpgpu_sim( - *(m_gpgpu_context->the_gpgpusim->g_the_gpu_config), m_gpgpu_context); - - m_gpgpu_context->the_gpgpusim->g_stream_manager = - new stream_manager((m_gpgpu_context->the_gpgpusim->g_the_gpu), - m_gpgpu_context->func_sim->g_cuda_launch_blocking); - - m_gpgpu_context->the_gpgpusim->g_simulation_starttime = time((time_t*)NULL); - - return m_gpgpu_context->the_gpgpusim->g_the_gpu; -} diff --git a/src/trace-driven/trace_driven.cc b/src/trace-driven/trace_driven.cc deleted file mode 100644 index 83b134e..0000000 --- a/src/trace-driven/trace_driven.cc +++ /dev/null @@ -1,811 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ -// abdallm@purdue.edu - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../../libcuda/gpgpu_context.h" -#include "../abstract_hardware_model.h" -#include "../cuda-sim/cuda-sim.h" -#include "../cuda-sim/ptx_ir.h" -#include "../cuda-sim/ptx_parser.h" -#include "../gpgpu-sim/gpu-sim.h" -#include "../gpgpusim_entrypoint.h" -#include "../option_parser.h" -#include "ISA_Def/kepler_opcode.h" -#include "ISA_Def/pascal_opcode.h" -#include "ISA_Def/trace_opcode.h" -#include "ISA_Def/turing_opcode.h" -#include "ISA_Def/volta_opcode.h" -#include "trace_driven.h" - -bool is_number(const std::string& s) { - std::string::const_iterator it = s.begin(); - while (it != s.end() && std::isdigit(*it)) ++it; - return !s.empty() && it == s.end(); -} - -void split(const std::string& str, std::vector& cont, - char delimi = ' ') { - std::stringstream ss(str); - std::string token; - while (std::getline(ss, token, delimi)) { - cont.push_back(token); - } -} - -trace_parser::trace_parser(const char* kernellist_filepath, - gpgpu_sim* m_gpgpu_sim, - gpgpu_context* m_gpgpu_context) { - this->m_gpgpu_sim = m_gpgpu_sim; - this->m_gpgpu_context = m_gpgpu_context; - kernellist_filename = kernellist_filepath; -} - -std::vector trace_parser::parse_kernellist_file() { - ifs.open(kernellist_filename); - - if (!ifs.is_open()) { - std::cout << "Unable to open file: " << kernellist_filename << std::endl; - exit(1); - } - - std::string directory(kernellist_filename); - const size_t last_slash_idx = directory.rfind('/'); - if (std::string::npos != last_slash_idx) { - directory = directory.substr(0, last_slash_idx); - } - - std::string line, filepath; - std::vector kernellist; - while (!ifs.eof()) { - getline(ifs, line); - if (line.empty()) - continue; - else if (line.substr(0, 6) == "Memcpy") { - kernellist.push_back(line); - } else if (line.substr(0, 6) == "kernel") { - filepath = directory + "/" + line; - kernellist.push_back(filepath); - } - } - - ifs.close(); - return kernellist; -} - -void trace_parser::parse_memcpy_info(const std::string& memcpy_command, - size_t& address, size_t& count) { - std::vector params; - split(memcpy_command, params, ','); - assert(params.size() == 3); - std::stringstream ss; - ss.str(params[1]); - ss >> std::hex >> address; - ss.clear(); - ss.str(params[2]); - ss >> std::dec >> count; -} - -trace_kernel_info_t* trace_parser::parse_kernel_info( - const std::string& kerneltraces_filepath, trace_config* config) { - ifs.open(kerneltraces_filepath.c_str()); - - if (!ifs.is_open()) { - std::cout << "Unable to open file: " << kerneltraces_filepath << std::endl; - exit(1); - } - - std::cout << "Processing kernel " << kerneltraces_filepath << std::endl; - - unsigned grid_dim_x = 0, grid_dim_y = 0, grid_dim_z = 0, tb_dim_x = 0, - tb_dim_y = 0, tb_dim_z = 0; - unsigned shmem = 0, nregs = 0, cuda_stream_id = 0, kernel_id = 0, - binary_verion = 0; - std::string line; - std::stringstream ss; - std::string string1, string2; - std::string kernel_name; - - while (!ifs.eof()) { - getline(ifs, line); - - if (line.length() == 0) { - continue; - } else if (line[0] == '#') { - // the trace format, ignore this and assume fixed format for now - break; // the begin of the instruction stream - } else if (line[0] == '-') { - ss.str(line); - ss.ignore(); - ss >> string1 >> string2; - if (string1 == "kernel" && string2 == "name") { - const size_t equal_idx = line.find('='); - kernel_name = line.substr(equal_idx + 1); - } else if (string1 == "kernel" && string2 == "id") { - sscanf(line.c_str(), "-kernel id = %d", &kernel_id); - } else if (string1 == "grid" && string2 == "dim") { - sscanf(line.c_str(), "-grid dim = (%d,%d,%d)", &grid_dim_x, &grid_dim_y, - &grid_dim_z); - } else if (string1 == "block" && string2 == "dim") { - sscanf(line.c_str(), "-block dim = (%d,%d,%d)", &tb_dim_x, &tb_dim_y, - &tb_dim_z); - } else if (string1 == "shmem") { - sscanf(line.c_str(), "-shmem = %d", &shmem); - } else if (string1 == "nregs") { - sscanf(line.c_str(), "-nregs = %d", &nregs); - } else if (string1 == "cuda" && string2 == "stream") { - sscanf(line.c_str(), "-cuda stream id = %d", &cuda_stream_id); - } else if (string1 == "binary" && string2 == "version") { - sscanf(line.c_str(), "-binary version = %d", &binary_verion); - } - std::cout << line << std::endl; - continue; - } - } - - gpgpu_ptx_sim_info info; - info.smem = shmem; - info.regs = nregs; - dim3 gridDim(grid_dim_x, grid_dim_y, grid_dim_z); - dim3 blockDim(tb_dim_x, tb_dim_y, tb_dim_z); - trace_function_info* function_info = - new trace_function_info(info, m_gpgpu_context); - function_info->set_name(kernel_name.c_str()); - trace_kernel_info_t* kernel_info = - new trace_kernel_info_t(gridDim, blockDim, binary_verion, function_info, - &ifs, m_gpgpu_sim, m_gpgpu_context, config); - - return kernel_info; -} - -void trace_parser::kernel_finalizer(trace_kernel_info_t* kernel_info) { - if (ifs.is_open()) ifs.close(); - - delete kernel_info->entry(); - delete kernel_info; -} - -const trace_warp_inst_t* trace_shd_warp_t::get_next_trace_inst() { - if (trace_pc < warp_traces.size()) { - return &warp_traces[trace_pc++]; - } else - return NULL; -} - -void trace_shd_warp_t::clear() { - trace_pc = 0; - warp_traces.clear(); -} - -// functional_done -bool trace_shd_warp_t::trace_done() { return trace_pc == (warp_traces.size()); } - -address_type trace_shd_warp_t::get_start_trace_pc() { - assert(warp_traces.size() > 0); - return warp_traces[0].pc; -} - -address_type trace_shd_warp_t::get_pc() { - assert(warp_traces.size() > 0); - assert(trace_pc < warp_traces.size()); - return warp_traces[trace_pc].pc; -} - -trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim, - unsigned m_binary_verion, - trace_function_info* m_function_info, - std::ifstream* inputstream, - gpgpu_sim* gpgpu_sim, - gpgpu_context* gpgpu_context, - class trace_config* config) - : kernel_info_t(gridDim, blockDim, m_function_info) { - ifs = inputstream; - m_gpgpu_sim = gpgpu_sim; - m_gpgpu_context = gpgpu_context; - binary_verion = m_binary_verion; - m_tconfig = config; - - // resolve the binary version - if (m_binary_verion == VOLTA_BINART_VERSION) - OpcodeMap = &Volta_OpcodeMap; - else if (m_binary_verion == PASCAL_TITANX_BINART_VERSION || - m_binary_verion == PASCAL_P100_BINART_VERSION) - OpcodeMap = &Pascal_OpcodeMap; - else if (m_binary_verion == KEPLER_BINART_VERSION) - OpcodeMap = &Kepler_OpcodeMap; - else if (m_binary_verion == TURING_BINART_VERSION) - OpcodeMap = &Turing_OpcodeMap; - else - assert(0 && "unsupported binary version"); -} - -bool trace_kernel_info_t::get_next_threadblock_traces( - std::vector*> threadblock_traces) { - for (unsigned i = 0; i < threadblock_traces.size(); ++i) { - threadblock_traces[i]->clear(); - } - - unsigned block_id_x = 0, block_id_y = 0, block_id_z = 0; - unsigned warp_id = 0; - unsigned insts_num = 0; - - bool start_of_tb_stream_found = false; - - while (!ifs->eof()) { - std::string line; - std::stringstream ss; - std::string string1, string2; - - getline(*ifs, line); - - if (line.length() == 0) { - continue; - } else { - ss.str(line); - ss >> string1 >> string2; - if (string1 == "#BEGIN_TB") { - if (!start_of_tb_stream_found) { - start_of_tb_stream_found = true; - } else - assert(0 && - "Parsing error: thread block start before the previous one " - "finish"); - } else if (string1 == "#END_TB") { - assert(start_of_tb_stream_found); - break; // end of TB stream - } else if (string1 == "thread" && string2 == "block") { - assert(start_of_tb_stream_found); - sscanf(line.c_str(), "thread block = %d,%d,%d", &block_id_x, - &block_id_y, &block_id_z); - std::cout << line << std::endl; - } else if (string1 == "warp") { - // the start of new warp stream - assert(start_of_tb_stream_found); - sscanf(line.c_str(), "warp = %d", &warp_id); - } else if (string1 == "insts") { - assert(start_of_tb_stream_found); - sscanf(line.c_str(), "insts = %d", &insts_num); - threadblock_traces[warp_id]->reserve(insts_num); - } else { - assert(start_of_tb_stream_found); - trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig(), - m_gpgpu_context, m_tconfig); - inst.parse_from_string(line, OpcodeMap); - threadblock_traces[warp_id]->push_back(inst); - } - } - } - - return true; -} - -bool trace_warp_inst_t::check_opcode_contain( - const std::vector& opcode, std::string param) { - for (unsigned i = 0; i < opcode.size(); ++i) - if (opcode[i] == param) return true; - - return false; -} - -unsigned trace_warp_inst_t::get_datawidth_from_opcode( - const std::vector& opcode) { - for (unsigned i = 0; i < opcode.size(); ++i) { - if (is_number(opcode[i])) { - return (std::stoi(opcode[i], NULL) / 8); - } else if (opcode[i][0] == 'U' && is_number(opcode[i].substr(1))) { - // handle the U* case - unsigned bits; - sscanf(opcode[i].c_str(), "U%u", &bits); - return bits / 8; - } - } - - return 4; // default is 4 bytes -} - -bool trace_warp_inst_t::parse_from_string( - std::string trace, - const std::unordered_map* OpcodeMap) { - std::stringstream ss; - ss.str(trace); - - std::string temp; - unsigned threadblock_x = 0, threadblock_y = 0, threadblock_z = 0, - warpid_tb = 0, sm_id = 0, warpid_sm = 0; - unsigned long long m_pc = 0; - unsigned mask = 0; - unsigned reg_dest[4]; - std::string opcode; - unsigned reg_dsts_num = 0; - unsigned reg_srcs_num = 0; - unsigned reg_srcs[4]; - unsigned mem_width = 0; - unsigned long long mem_addresses[warp_size()]; - unsigned address_mode = 0; - unsigned long long base_address = 0; - int stride = 0; - - // Start Parsing - ss >> std::dec >> threadblock_x >> threadblock_y >> threadblock_z >> - warpid_tb; - - // ignore core id - // ss>>std::dec>>sm_id>>warpid_sm; - - ss >> std::hex >> m_pc; - ss >> std::hex >> mask; - - std::bitset mask_bits(mask); - - ss >> std::dec >> reg_dsts_num; - for (unsigned i = 0; i < reg_dsts_num; ++i) { - ss >> std::dec >> temp; - sscanf(temp.c_str(), "R%d", ®_dest[i]); - } - - ss >> opcode; - - ss >> reg_srcs_num; - for (unsigned i = 0; i < reg_srcs_num; ++i) { - ss >> temp; - sscanf(temp.c_str(), "R%d", ®_srcs[i]); - } - - ss >> mem_width; - - if (mem_width > 0) // then it is a memory inst - { - ss >> std::dec >> address_mode; - if (address_mode == 0) { - // read addresses one by one from the file - for (int s = 0; s < warp_size(); s++) { - if (mask_bits.test(s)) - ss >> std::hex >> mem_addresses[s]; - else - mem_addresses[s] = 0; - } - } else if (address_mode == 1) { - // read addresses as base address and stride - ss >> std::hex >> base_address; - ss >> std::dec >> stride; - bool first_bit1_found = false; - bool last_bit1_found = false; - unsigned long long addra = base_address; - for (int s = 0; s < warp_size(); s++) { - if (mask_bits.test(s) && !first_bit1_found) { - first_bit1_found = true; - mem_addresses[s] = base_address; - } else if (first_bit1_found && !last_bit1_found) { - if (mask_bits.test(s)) { - addra += stride; - mem_addresses[s] = addra; - } else - last_bit1_found = true; - } else - mem_addresses[s] = 0; - } - } - } - // Finish Parsing - // After parsing, fill the inst_t and warp_inst_t params - - // fill active mask - active_mask_t active_mask = mask_bits; - set_active(active_mask); - - // get the opcode - std::istringstream iss(opcode); - std::vector opcode_tokens; - std::string token; - while (std::getline(iss, token, '.')) { - if (!token.empty()) opcode_tokens.push_back(token); - } - - std::string opcode1 = opcode_tokens[0]; - - // fill and initialize common params - m_decoded = true; - pc = (address_type)m_pc; // we will lose the high 32 bits from casting long - // to unsigned, it should be okay! - - isize = - 16; // starting from MAXWELL isize=16 bytes (including the control bytes) - for (unsigned i = 0; i < MAX_OUTPUT_VALUES; i++) { - out[i] = 0; - } - for (unsigned i = 0; i < MAX_INPUT_VALUES; i++) { - in[i] = 0; - } - - is_vectorin = 0; - is_vectorout = 0; - ar1 = 0; - ar2 = 0; - memory_op = no_memory_op; - data_size = 0; - op = ALU_OP; - mem_op = NOT_TEX; - - std::unordered_map::const_iterator it = - OpcodeMap->find(opcode1); - if (it != OpcodeMap->end()) { - m_opcode = it->second.opcode; - op = (op_type)(it->second.opcode_category); - } else { - std::cout << "ERROR: undefined instruction : " << opcode - << " Opcode: " << opcode1 << std::endl; - assert(0 && "undefined instruction"); - } - - // fill regs information - num_regs = reg_srcs_num + reg_dsts_num; - num_operands = num_regs; - outcount = reg_dsts_num; - for (unsigned m = 0; m < reg_dsts_num; ++m) { - out[m] = reg_dest[m] + 1; // Increment by one because GPGPU-sim starts from - // R1, while SASS starts from R0 - arch_reg.dst[m] = reg_dest[m] + 1; - } - - incount = reg_srcs_num; - for (unsigned m = 0; m < reg_srcs_num; ++m) { - in[m] = reg_srcs[m] + 1; // Increment by one because GPGPU-sim starts from - // R1, while SASS starts from R0 - arch_reg.src[m] = reg_srcs[m] + 1; - } - // TO DO: handle: vector, store insts have no output, double inst and hmma, - // and 64 bit address remove redundant registers - - // fill latency and initl - m_tconfig->set_latency(op, latency, initiation_interval); - - // fill addresses - if (mem_width > 0) { - for (unsigned i = 0; i < warp_size(); ++i) set_addr(i, mem_addresses[i]); - } - - // handle special cases and fill memory space - switch (m_opcode) { - case OP_LDG: - case OP_LDL: - assert(mem_width > 0); - // Nvbit reports incorrect data width, and we have to parse the opcode to - // get the correct data width - data_size = get_datawidth_from_opcode(opcode_tokens); - memory_op = memory_load; - cache_op = CACHE_ALL; - if (m_opcode == OP_LDL) - space.set_type(local_space); - else - space.set_type(global_space); - // check the cache scope, if its strong GPU, then bypass L1 - if (check_opcode_contain(opcode_tokens, "STRONG") && - check_opcode_contain(opcode_tokens, "GPU")) { - cache_op = CACHE_GLOBAL; - } - break; - case OP_STG: - case OP_STL: - case OP_ATOMG: - case OP_RED: - case OP_ATOM: - assert(mem_width > 0); - data_size = get_datawidth_from_opcode(opcode_tokens); - memory_op = memory_store; - cache_op = CACHE_ALL; - if (m_opcode == OP_STL) - space.set_type(local_space); - else - space.set_type(global_space); - - if (m_opcode == OP_ATOMG || m_opcode == OP_ATOM || m_opcode == OP_RED) { - m_isatomic = true; - memory_op = memory_load; - op = LOAD_OP; - cache_op = CACHE_GLOBAL; - - // ATOMIC writes to the first operand, we missed that in the trace so we - // fixed it here. TO be fixed in tracer - outcount = reg_dsts_num + 1; - out[0] = in[0]; // Increment by one because GPGPU-sim starts from R1, - // while SASS starts from R0 - arch_reg.dst[0] = reg_srcs[0]; - num_regs = reg_srcs_num + reg_dsts_num + 1; - num_operands = num_regs; - } - - break; - case OP_LDS: - case OP_STS: - case OP_ATOMS: - assert(mem_width > 0); - data_size = mem_width; - space.set_type(shared_space); - if (m_opcode == OP_ATOMS || m_opcode == OP_LDS) { - // m_isatomic = true; - op = LOAD_OP; - memory_op = memory_load; - } - break; - case OP_ST: - case OP_LD: - // TO DO: set generic load based on the address - // right now, we consider all loads are shared. - assert(mem_width > 0); - data_size = get_datawidth_from_opcode(opcode_tokens); - space.set_type(shared_space); - if (m_opcode == OP_LD) - memory_op = memory_load; - else - memory_op = memory_store; - break; - case OP_BAR: - // TO DO: fill this correctly - bar_id = 0; - bar_count = (unsigned)-1; - bar_type = SYNC; - // TO DO - // if bar_type = RED; - // set bar_type - // barrier_type bar_type; - // reduction_type red_type; - break; - case OP_HADD2: - case OP_HADD2_32I: - case OP_HFMA2: - case OP_HFMA2_32I: - case OP_HMUL2_32I: - case OP_HSET2: - case OP_HSETP2: - initiation_interval = - initiation_interval / 2; // FP16 has 2X throughput than FP32 - break; - default: - break; - } - - return true; -} - -trace_config::trace_config() {} - -void trace_config::reg_options(option_parser_t opp) { - option_parser_register(opp, "-trace", OPT_CSTR, &g_traces_filename, - "traces kernel file" - "traces kernel file directory", - "./traces/kernelslist.g"); - - option_parser_register(opp, "-trace_opcode_latency_initiation_int", OPT_CSTR, - &trace_opcode_latency_initiation_int, - "Opcode latencies and initiation for integers in " - "trace driven mode ", - "4,1"); - option_parser_register(opp, "-trace_opcode_latency_initiation_sp", OPT_CSTR, - &trace_opcode_latency_initiation_sp, - "Opcode latencies and initiation for sp in trace " - "driven mode ", - "4,1"); - option_parser_register(opp, "-trace_opcode_latency_initiation_dp", OPT_CSTR, - &trace_opcode_latency_initiation_dp, - "Opcode latencies and initiation for dp in trace " - "driven mode ", - "4,1"); - option_parser_register(opp, "-trace_opcode_latency_initiation_sfu", OPT_CSTR, - &trace_opcode_latency_initiation_sfu, - "Opcode latencies and initiation for sfu in trace " - "driven mode ", - "4,1"); - option_parser_register(opp, "-trace_opcode_latency_initiation_tensor", - OPT_CSTR, &trace_opcode_latency_initiation_tensor, - "Opcode latencies and initiation for tensor in trace " - "driven mode ", - "4,1"); - - for (unsigned j = 0; j < SPECIALIZED_UNIT_NUM; ++j) { - std::stringstream ss; - ss << "-trace_opcode_latency_initiation_spec_op_" << j + 1; - option_parser_register(opp, ss.str().c_str(), OPT_CSTR, - &trace_opcode_latency_initiation_specialized_op[j], - "specialized unit config" - " ", - "4,4"); - } -} - -void trace_config::parse_config() { - sscanf(trace_opcode_latency_initiation_int, "%u,%u", &int_latency, &int_init); - sscanf(trace_opcode_latency_initiation_sp, "%u,%u", &fp_latency, &fp_init); - sscanf(trace_opcode_latency_initiation_dp, "%u,%u", &dp_latency, &dp_init); - sscanf(trace_opcode_latency_initiation_sfu, "%u,%u", &sfu_latency, &sfu_init); - sscanf(trace_opcode_latency_initiation_tensor, "%u,%u", &tensor_latency, - &tensor_init); - - for (unsigned j = 0; j < SPECIALIZED_UNIT_NUM; ++j) { - sscanf(trace_opcode_latency_initiation_specialized_op[j], "%u,%u", - &specialized_unit_latency[j], &specialized_unit_initiation[j]); - } -} -void trace_config::set_latency(unsigned category, unsigned& latency, - unsigned& initiation_interval) { - initiation_interval = latency = 1; - - switch (category) { - case ALU_OP: - case INTP_OP: - case BRANCH_OP: - case CALL_OPS: - case RET_OPS: - latency = int_latency; - initiation_interval = int_init; - break; - case SP_OP: - latency = fp_latency; - initiation_interval = fp_init; - break; - case DP_OP: - latency = dp_latency; - initiation_interval = dp_init; - break; - case SFU_OP: - latency = sfu_latency; - initiation_interval = sfu_init; - break; - case TENSOR_CORE_OP: - latency = tensor_latency; - initiation_interval = tensor_init; - break; - default: - break; - } - // for specialized units - if (category >= SPEC_UNIT_START_ID) { - unsigned spec_id = category - SPEC_UNIT_START_ID; - assert(spec_id >= 0 && spec_id < SPECIALIZED_UNIT_NUM); - latency = specialized_unit_latency[spec_id]; - initiation_interval = specialized_unit_initiation[spec_id]; - } -} - -void trace_gpgpu_sim::createSIMTCluster() { - m_cluster = new simt_core_cluster*[m_shader_config->n_simt_clusters]; - for (unsigned i = 0; i < m_shader_config->n_simt_clusters; i++) - m_cluster[i] = - new trace_simt_core_cluster(this, i, m_shader_config, m_memory_config, - m_shader_stats, m_memory_stats); -} - -void trace_simt_core_cluster::create_shader_core_ctx() { - m_core = new shader_core_ctx*[m_config->n_simt_cores_per_cluster]; - for (unsigned i = 0; i < m_config->n_simt_cores_per_cluster; i++) { - unsigned sid = m_config->cid_to_sid(i, m_cluster_id); - m_core[i] = new trace_shader_core_ctx(m_gpu, this, sid, m_cluster_id, - m_config, m_mem_config, m_stats); - m_core_sim_order.push_back(i); - } -} - -void trace_shader_core_ctx::create_shd_warp() { - m_warp.resize(m_config->max_warps_per_shader); - for (unsigned k = 0; k < m_config->max_warps_per_shader; ++k) { - m_warp[k] = new trace_shd_warp_t(this, m_config->warp_size); - } -} - -void trace_shader_core_ctx::get_pdom_stack_top_info(unsigned warp_id, - const warp_inst_t* pI, - unsigned* pc, - unsigned* rpc) { - // In trace-driven mode, we assume no control hazard - *pc = pI->pc; - *rpc = pI->pc; -} - -const active_mask_t& trace_shader_core_ctx::get_active_mask( - unsigned warp_id, const warp_inst_t* pI) { - // For Trace-driven, the active mask already set in traces, so - // just read it from the inst - return pI->get_active_mask(); -} - -unsigned trace_shader_core_ctx::sim_init_thread( - kernel_info_t& kernel, ptx_thread_info** thread_info, int sid, unsigned tid, - unsigned threads_left, unsigned num_threads, core_t* core, - unsigned hw_cta_id, unsigned hw_warp_id, gpgpu_t* gpu) { - if (kernel.no_more_ctas_to_run()) { - return 0; // finished! - } - - if (kernel.more_threads_in_cta()) { - kernel.increment_thread_id(); - } - - if (!kernel.more_threads_in_cta()) kernel.increment_cta_id(); - - return 1; -} - -void trace_shader_core_ctx::init_warps(unsigned cta_id, unsigned start_thread, - unsigned end_thread, unsigned ctaid, - int cta_size, kernel_info_t& kernel) { - // call base class - shader_core_ctx::init_warps(cta_id, start_thread, end_thread, ctaid, cta_size, - kernel); - - // then init traces - unsigned start_warp = start_thread / m_config->warp_size; - unsigned end_warp = end_thread / m_config->warp_size + - ((end_thread % m_config->warp_size) ? 1 : 0); - - init_traces(start_warp, end_warp, kernel); -} - -const warp_inst_t* trace_shader_core_ctx::get_next_inst(unsigned warp_id, - address_type pc) { - // read the inst from the traces - trace_shd_warp_t* m_trace_warp = - static_cast(m_warp[warp_id]); - return m_trace_warp->get_next_trace_inst(); -} - -void trace_shader_core_ctx::updateSIMTStack(unsigned warpId, - warp_inst_t* inst) { - // No SIMT-stack in trace-driven mode -} - -void trace_shader_core_ctx::init_traces(unsigned start_warp, unsigned end_warp, - kernel_info_t& kernel) { - std::vector*> threadblock_traces; - for (unsigned i = start_warp; i < end_warp; ++i) { - trace_shd_warp_t* m_trace_warp = static_cast(m_warp[i]); - m_trace_warp->clear(); - threadblock_traces.push_back(&(m_trace_warp->warp_traces)); - } - trace_kernel_info_t& trace_kernel = static_cast(kernel); - trace_kernel.get_next_threadblock_traces(threadblock_traces); - - // set the pc from the traces and ignore the functional model - for (unsigned i = start_warp; i < end_warp; ++i) { - trace_shd_warp_t* m_trace_warp = static_cast(m_warp[i]); - m_trace_warp->set_next_pc(m_trace_warp->get_start_trace_pc()); - } -} - -void trace_shader_core_ctx::checkExecutionStatusAndUpdate(warp_inst_t& inst, - unsigned t, - unsigned tid) { - if (inst.isatomic()) m_warp[inst.warp_id()]->inc_n_atomic(); - - if (inst.op == EXIT_OPS) { - m_warp[inst.warp_id()]->set_completed(t); - } -} - -void trace_shader_core_ctx::func_exec_inst(warp_inst_t& inst) { - // here, we generate memory acessess and set the status if thread (done?) - if (inst.is_load() || inst.is_store()) { - inst.generate_mem_accesses(); - } - for (unsigned t = 0; t < m_warp_size; t++) { - if (inst.active(t)) { - unsigned warpId = inst.warp_id(); - unsigned tid = m_warp_size * warpId + t; - - // virtual function - checkExecutionStatusAndUpdate(inst, t, tid); - } - } - trace_shd_warp_t* m_trace_warp = - static_cast(m_warp[inst.warp_id()]); - if (m_trace_warp->trace_done() && m_trace_warp->functional_done()) { - m_trace_warp->ibuffer_flush(); - m_barriers.warp_exit(inst.warp_id()); - } -} diff --git a/src/trace-driven/trace_driven.h b/src/trace-driven/trace_driven.h deleted file mode 100644 index 3af99c3..0000000 --- a/src/trace-driven/trace_driven.h +++ /dev/null @@ -1,210 +0,0 @@ -// developed by Mahmoud Khairy, Purdue Univ - -#include -#include -#include - -#ifndef TRACE_DRIVEN_H -#define TRACE_DRIVEN_H - -#include "../abstract_hardware_model.h" -#include "../gpgpu-sim/shader.h" -#include "ISA_Def/trace_opcode.h" - -class trace_function_info : public function_info { - public: - trace_function_info(const struct gpgpu_ptx_sim_info& info, - gpgpu_context* m_gpgpu_context) - : function_info(0, m_gpgpu_context) { - m_kernel_info = info; - } - - virtual const struct gpgpu_ptx_sim_info* get_kernel_info() const { - return &m_kernel_info; - } - - virtual const void set_kernel_info(const struct gpgpu_ptx_sim_info& info) { - m_kernel_info = info; - } - - virtual ~trace_function_info() {} -}; - -class trace_warp_inst_t : public warp_inst_t { - public: - trace_warp_inst_t() { - m_gpgpu_context = NULL; - m_opcode = 0; - m_tconfig = NULL; - should_do_atomic = false; - } - - trace_warp_inst_t(const class core_config* config, - gpgpu_context* gpgpu_context, class trace_config* tconfig) - : warp_inst_t(config) { - m_gpgpu_context = gpgpu_context; - m_opcode = 0; - m_tconfig = tconfig; - should_do_atomic = false; - } - - bool parse_from_string( - std::string trace, - const std::unordered_map* OpcodeMap); - - private: - gpgpu_context* m_gpgpu_context; - class trace_config* m_tconfig; - unsigned m_opcode; - bool check_opcode_contain(const std::vector& opcode, - std::string param); - unsigned get_datawidth_from_opcode(const std::vector& opcode); -}; - -class trace_kernel_info_t : public kernel_info_t { - public: - trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, - trace_function_info* m_function_info, - std::ifstream* inputstream, gpgpu_sim* gpgpu_sim, - gpgpu_context* gpgpu_context, class trace_config* config); - - bool get_next_threadblock_traces( - std::vector*> threadblock_traces); - - private: - std::ifstream* ifs; - gpgpu_sim* m_gpgpu_sim; - gpgpu_context* m_gpgpu_context; - trace_config* m_tconfig; - unsigned binary_verion; - const std::unordered_map* OpcodeMap; -}; - -class trace_config { - public: - trace_config(); - - void set_latency(unsigned category, unsigned& latency, - unsigned& initiation_interval); - void parse_config(); - void reg_options(option_parser_t opp); - char* get_traces_filename() { return g_traces_filename; } - - private: - unsigned int_latency, fp_latency, dp_latency, sfu_latency, tensor_latency; - unsigned int_init, fp_init, dp_init, sfu_init, tensor_init; - unsigned specialized_unit_latency[SPECIALIZED_UNIT_NUM]; - unsigned specialized_unit_initiation[SPECIALIZED_UNIT_NUM]; - - char* g_traces_filename; - char* trace_opcode_latency_initiation_int; - char* trace_opcode_latency_initiation_sp; - char* trace_opcode_latency_initiation_dp; - char* trace_opcode_latency_initiation_sfu; - char* trace_opcode_latency_initiation_tensor; - char* trace_opcode_latency_initiation_specialized_op[SPECIALIZED_UNIT_NUM]; -}; - -class trace_parser { - public: - trace_parser(const char* kernellist_filepath, gpgpu_sim* m_gpgpu_sim, - gpgpu_context* m_gpgpu_context); - - std::vector parse_kernellist_file(); - trace_kernel_info_t* parse_kernel_info( - const std::string& kerneltraces_filepath, trace_config* config); - void parse_memcpy_info(const std::string& memcpy_command, size_t& add, - size_t& count); - - void kernel_finalizer(trace_kernel_info_t* kernel_info); - - private: - std::string kernellist_filename; - std::ifstream ifs; - gpgpu_sim* m_gpgpu_sim; - gpgpu_context* m_gpgpu_context; -}; - -class trace_shd_warp_t : public shd_warp_t { - public: - trace_shd_warp_t(class shader_core_ctx* shader, unsigned warp_size) - : shd_warp_t(shader, warp_size) { - trace_pc = 0; - } - - std::vector warp_traces; - const trace_warp_inst_t* get_next_trace_inst(); - void clear(); - bool trace_done(); - address_type get_start_trace_pc(); - virtual address_type get_pc(); - - private: - unsigned trace_pc; -}; - -class trace_gpgpu_sim : public gpgpu_sim { - public: - trace_gpgpu_sim(const gpgpu_sim_config& config, gpgpu_context* ctx) - : gpgpu_sim(config, ctx) { - createSIMTCluster(); - } - - virtual void createSIMTCluster(); -}; - -class trace_simt_core_cluster : public simt_core_cluster { - public: - trace_simt_core_cluster(class gpgpu_sim* gpu, unsigned cluster_id, - const shader_core_config* config, - const memory_config* mem_config, - class shader_core_stats* stats, - class memory_stats_t* mstats) - : simt_core_cluster(gpu, cluster_id, config, mem_config, stats, mstats) { - create_shader_core_ctx(); - } - - virtual void create_shader_core_ctx(); -}; - -class trace_shader_core_ctx : public shader_core_ctx { - public: - trace_shader_core_ctx(class gpgpu_sim* gpu, class simt_core_cluster* cluster, - unsigned shader_id, unsigned tpc_id, - const shader_core_config* config, - const memory_config* mem_config, - shader_core_stats* stats) - : shader_core_ctx(gpu, cluster, shader_id, tpc_id, config, mem_config, - stats) { - create_front_pipeline(); - create_shd_warp(); - create_schedulers(); - create_exec_pipeline(); - } - - virtual void checkExecutionStatusAndUpdate(warp_inst_t& inst, unsigned t, - unsigned tid); - virtual void init_warps(unsigned cta_id, unsigned start_thread, - unsigned end_thread, unsigned ctaid, int cta_size, - kernel_info_t& kernel); - virtual void func_exec_inst(warp_inst_t& inst); - virtual unsigned sim_init_thread(kernel_info_t& kernel, - ptx_thread_info** thread_info, int sid, - unsigned tid, unsigned threads_left, - unsigned num_threads, core_t* core, - unsigned hw_cta_id, unsigned hw_warp_id, - gpgpu_t* gpu); - virtual void create_shd_warp(); - virtual const warp_inst_t* get_next_inst(unsigned warp_id, address_type pc); - virtual void updateSIMTStack(unsigned warpId, warp_inst_t* inst); - virtual void get_pdom_stack_top_info(unsigned warp_id, const warp_inst_t* pI, - unsigned* pc, unsigned* rpc); - virtual const active_mask_t& get_active_mask(unsigned warp_id, - const warp_inst_t* pI); - - private: - void init_traces(unsigned start_warp, unsigned end_warp, - kernel_info_t& kernel); -}; - -#endif -- cgit v1.3