From 753bcd50c00dda1481585e2fef1ba314c72e7c57 Mon Sep 17 00:00:00 2001 From: Inderpreet Singh Date: Tue, 3 Jan 2012 19:47:58 -0800 Subject: Fix for Bug 118: Cache line size restrictions Added an assertion that checks to make sure that incoming mem_fetch size is less than or equal to cache's line size. This requires non-decreasing line sizes going down the cache heirarchy. Changed Quadro's texture L2 cache to have 256B lines (because of above restriction and instruction cache having 256B lines; Henry's paper also observed 256B line size for L2). Increased total L2 size to 256KB from 128KB as per Henry's paper. From ISPASS, SDK, and RODINIA benchmarks, only MUM and MGST are affected with a 30% slowdown. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11253] --- configs/QuadroFX5800/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs') diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index 2151183..b5e1f01 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -19,7 +19,7 @@ -gpgpu_cache:il1 4:256:4:L:R:f,A:2:32,4 -gpgpu_tex_cache:l1 8:128:5:L:R:m,F:128:4,128:2 -gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4 --gpgpu_cache:dl2 64:32:8:L:R:m,A:16:4,4 +-gpgpu_cache:dl2 16:256:8:L:R:m,A:16:4,4 -gpgpu_cache:dl2_texture_only 1 -gpgpu_shmem_warp_parts 2 -- cgit v1.3