From 9ceb6f2016a16aa9c877956fc2e8bc43dc697322 Mon Sep 17 00:00:00 2001 From: Tayler Hetherington Date: Sun, 16 Sep 2012 13:38:57 -0800 Subject: Modified the cache hierarchy, reorganized code to eliminate code replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only". Still need to implement Ahmed's sectored cache implementation. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081] --- configs/GTX480/gpgpusim.config | 10 +++++----- configs/QuadroFX5800/gpgpusim.config | 8 ++++---- configs/TeslaC2050/gpgpusim.config | 10 +++++----- 3 files changed, 14 insertions(+), 14 deletions(-) (limited to 'configs') diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index a3450e1..5cda42a 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -39,7 +39,7 @@ # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb # :::::,::, --gpgpu_cache:dl1 32:128:4:L:R:m,A:32:8,8 +-gpgpu_cache:dl1 32:128:4:L:B:m:A:P:N:32:8,8 -gpgpu_shmem_size 49152 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected @@ -47,12 +47,12 @@ #-gpgpu_shmem_size 16384 # 64 sets, each 256 bytes 8-way for each memory partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:256:8:L:R:m,A:32:4,4 +-gpgpu_cache:dl2 64:256:8:L:B:m:A:S:W:32:4:4 -gpgpu_cache:dl2_texture_only 0 --gpgpu_cache:il1 4:128:4:L:R:f,A:2:32,4 --gpgpu_tex_cache:l1 4:128:24:L:R:m,F:128:4,128:2 --gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4 +-gpgpu_cache:il1 4:128:4:L:R:f:A:P:N:2:32:4 +-gpgpu_tex_cache:l1 4:128:24:L:R:m:F:P:N:128:4:128:2 +-gpgpu_const_cache:l1 64:64:2:L:R:f:A:P:N:2:32:4 -gpgpu_num_reg_banks 16 diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index fbe21d7..20cb968 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -31,10 +31,10 @@ -ptx_opcode_initiation_dp 8,8,8,8,130 # memory stage behaviour --gpgpu_cache:il1 4:256:4:L:R:f,A:2:32,4 --gpgpu_tex_cache:l1 8:128:5:L:R:m,F:128:4,128:2 --gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4 --gpgpu_cache:dl2 16:256:8:L:R:m,A:16:4,4 +-gpgpu_cache:il1 4:256:4:L:R:f:A:P:N:2:32,4 +-gpgpu_tex_cache:l1 8:128:5:L:R:m:F:P:N:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2:L:R:f:A:P:N:2:32,4 +-gpgpu_cache:dl2 16:256:8:L:B:m:A:S:W:16:4,4 -gpgpu_cache:dl2_texture_only 1 -gpgpu_shmem_warp_parts 2 diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config index 77a81a2..2407ea9 100644 --- a/configs/TeslaC2050/gpgpusim.config +++ b/configs/TeslaC2050/gpgpusim.config @@ -39,7 +39,7 @@ # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb # :::::,::, --gpgpu_cache:dl1 32:128:4:L:R:m,A:32:8,8 +-gpgpu_cache:dl1 32:128:4:L:B:m:A:P:N:32:8,8 -gpgpu_shmem_size 49152 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected @@ -47,12 +47,12 @@ #-gpgpu_shmem_size 16384 # 64 sets, each 256 bytes 8-way for each memory partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:256:8:L:R:m,A:32:4,4 +-gpgpu_cache:dl2 64:256:8:L:B:m:A:S:W:32:4:4 -gpgpu_cache:dl2_texture_only 0 --gpgpu_cache:il1 4:128:4:L:R:f,A:2:32,4 --gpgpu_tex_cache:l1 4:128:24:L:R:m,F:128:4,128:2 --gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4 +-gpgpu_cache:il1 4:128:4:L:R:f:A:P:N:2:32:4 +-gpgpu_tex_cache:l1 4:128:24:L:R:m:F:P:N:128:4:128:2 +-gpgpu_const_cache:l1 64:64:2:L:R:f:A:P:N:2:32:4 -gpgpu_num_reg_banks 16 -- cgit v1.3