From b0cf792926caf74b393a14e36de676c7afd68164 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Tue, 12 Oct 2010 00:46:24 -0800 Subject: 1. adding simt_core_cluster, which models a TPC or (for fermi) GPC... this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845] --- configs/QuadroFX5800/gpgpusim.config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'configs') diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index e5e29bc..97be091 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -4,7 +4,8 @@ -gpgpu_ptx_force_max_capability 11 # high level architecture configuration --gpgpu_n_shader 30 +-gpgpu_n_clusters 10 +-gpgpu_n_cores_per_cluster 3 -gpgpu_n_mem 8 -gpgpu_clock_domains 325.0:650.0:650.0:800.0 @@ -31,7 +32,6 @@ # interconnection -network_mode 1 -inter_config_file icnt_config_quadro_islip.txt --gpu_concentration 3 # dram model config -gpgpu_dram_scheduler 1 -- cgit v1.3