From b577cbcdf229a2c02d1bf8584c6e82be7a14cb33 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sat, 16 Oct 2010 17:30:52 -0800 Subject: 1. creating cache_config object to encapsulate cache configuration information (and parse it before creating the simulator objects). 2. creating core_config to hold only features of a shader_core that are high level enough either (a) the functional simulator needs to know about them, or (b) they affect memory *access* generation. 3. in config files only (so far) separate out notion of write-{through,back}, from notion of when a line is allocated... will use this to distinguish different types of caches. passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870] --- configs/QuadroFX5800/gpgpusim.config | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'configs') diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index 97be091..f8d27f5 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -19,15 +19,16 @@ # memory stage behaviour -gpgpu_no_dl1 1 -gpgpu_n_cache_bank 1 +-gpgpu_cache:dl1 128:64:4:L:T:m +-gpgpu_tex_cache:l1 8:32:20:L:R:m +-gpgpu_const_cache:l1 64:64:2:L:R:f +-gpgpu_cache:dl2 64:32:8:L:R:m + -gpgpu_shmem_pipe_speedup 2 -gpgpu_shmem_port_per_bank 2 -gpgpu_cache_port_per_bank 2 -gpgpu_const_port_per_bank 2 -gpgpu_interwarp_mshr_merge 6 --gpgpu_cache:dl1 128:64:4:L --gpgpu_tex_cache:l1 8:32:20:L --gpgpu_const_cache:l1 64:64:2:L --gpgpu_cache:dl2 64:32:8:L # interconnection -network_mode 1 -- cgit v1.3