From dc93f319051a9a9936a02cd9c1f7843a382a2da0 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Thu, 21 Oct 2010 07:16:49 -0800 Subject: 1. rewriting memory access generation code (from scratch), why not... passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)... after debugging 1 to get it working with ptxplus, problem is very clear: shared and constant cache accesses not occuring for operations that combine these with ALU operations. TODO: have a "read-operands" stage, which somehow combines operand collector register reading with shared and const memory accesses... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895] --- configs/QuadroFX5800/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs') diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index 6f1c936..3d7d218 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -22,7 +22,7 @@ -gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4 -gpgpu_cache:dl2 64:32:8:L:R:m,A:16:4,4 --gpgpu_shmem_pipe_speedup 2 +-gpgpu_shmem_warp_parts 2 -gpgpu_shmem_port_per_bank 2 # interconnection -- cgit v1.3