From ee5ea34857e4ecc6c63d4971e549076c6a9888ba Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Tue, 19 Oct 2010 23:10:51 -0800 Subject: adding texture cache model with fragment fifo for latency hiding passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886] --- configs/QuadroFX5800/gpgpusim.config | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'configs') diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index f8d27f5..6f1c936 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -17,18 +17,13 @@ -gpgpu_simd_model 1 # memory stage behaviour --gpgpu_no_dl1 1 --gpgpu_n_cache_bank 1 --gpgpu_cache:dl1 128:64:4:L:T:m --gpgpu_tex_cache:l1 8:32:20:L:R:m --gpgpu_const_cache:l1 64:64:2:L:R:f --gpgpu_cache:dl2 64:32:8:L:R:m +-gpgpu_cache:il1 4:256:4:L:R:f,A:2:32,4 +-gpgpu_tex_cache:l1 8:32:20:L:R:m,F:128:4,16:2 +-gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4 +-gpgpu_cache:dl2 64:32:8:L:R:m,A:16:4,4 -gpgpu_shmem_pipe_speedup 2 -gpgpu_shmem_port_per_bank 2 --gpgpu_cache_port_per_bank 2 --gpgpu_const_port_per_bank 2 --gpgpu_interwarp_mshr_merge 6 # interconnection -network_mode 1 -- cgit v1.3