From e177edcdefca06d7d3a7bc7be5f6a759f69b909e Mon Sep 17 00:00:00 2001 From: aamir Date: Fri, 1 Jun 2018 11:18:17 -0700 Subject: remove unwanted files --- cuda-kernels/log | 6328 ------------------------------------------------------ 1 file changed, 6328 deletions(-) delete mode 100644 cuda-kernels/log (limited to 'cuda-kernels/log') diff --git a/cuda-kernels/log b/cuda-kernels/log deleted file mode 100644 index 98df26a..0000000 --- a/cuda-kernels/log +++ /dev/null @@ -1,6328 +0,0 @@ - - - *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-03de5ae03420ba5666d669c6f76faccf2704fa58_modified_17] *** - - -GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: - 1=functional simulation only, 0=detailed performance simulator) -GPGPU-Sim: Configuration options: - --network_mode 1 # Interconnection network mode --inter_config_file config_fermi_islip.icnt # Interconnection network config file --gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries --gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] --gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus --gpgpu_ptx_force_max_capability 70 # Force maximum compute capability --gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file --gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file --gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output --gpgpu_simd_model 1 # 1 = post-dominator --gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} --gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} --gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} --gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) --gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) --n_regfile_gating_group 4 # group of lanes that should be read/written together) --gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations --gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations --gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) --gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) --gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) --gpgpu_n_clusters 40 # number of processing clusters --gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster --gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer --gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer --gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) --gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) --gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check --gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from --gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from --gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) --gpgpu_num_reg_banks 32 # Number of register banks (default = 8) --gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) --gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) --gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) --gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) --gpgpu_num_sched_per_core 2 # Number of warp schedulers per core --gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler --gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) --gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_num_sp_units 4 # Number of SP units (default=1) --gpgpu_num_sfu_units 1 # Number of SF units (default=1) --gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything --gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto --gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) --gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) --gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i --l2_ideal 0 # Use a ideal L2 cache that always hit --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} --gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only --gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu --gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module --gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller --gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs --gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip --gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip --gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) --gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) --dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) --gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --rop_latency 120 # ROP queue latency (default 85) --dram_latency 100 # DRAM latency (default 30) --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} --gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address --gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file --power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) --power_per_cycle_dump 0 # Dump detailed power output each cycle --power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) --power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) --steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) --steady_state_definition 8:4 # allowed deviation:number of samples --gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) --gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} --liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) --gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call --gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call --gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) --gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) --gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} --gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU --gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger --visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) --visualizer_outputfile NULL # Specifies the output log file for visualizer --visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) --trace_enabled 0 # Turn on traces --trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none --trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 --trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) --enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) --ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. --gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 --gpgpu_cdp_enabled 0 # Turn on CDP --save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx --keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs --gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file --ptx_opcode_latency_int 4,13,4,5,145,16,4 # Opcode latencies for integers Default 1,1,19,25,145,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 --ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 --ptx_opcode_initiation_int 1,2,2,2,8,16,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1,1 --ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 --ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 --cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 -DRAM Timing Options: -nbk 16 # number of banks -CCD 2 # column to column delay -RRD 6 # minimal delay between activation of rows in different banks -RCD 12 # row to column delay -RAS 28 # time needed to activate row -RP 12 # time needed to precharge (deactivate) row -RC 40 # row cycle time -CDLR 5 # switching from write to read (changes tWTR) -WR 12 # last data-in to row precharge -CL 12 # CAS latency -WL 4 # Write latency -nbkgrp 1 # number of bank groups -CCDL 0 # column to column delay between accesses to different bank groups -RTPL 0 # read to precharge delay between accesses to different bank groups -Total number of memory sub partition = 22 -addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 -addr_dec_mask[BK] = 0000000000007080 high:15 low:7 -addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 -addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 -addr_dec_mask[BURST] = 000000000000001f high:5 low:0 -sub_partition_id_mask = 0000000000000080 -GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 -GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 -*** Initializing Memory Statistics *** -GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) -GPGPU-Sim uArch: Memory nodes ID start from index: 40 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 50 51 52 53 54 55 -GPGPU-Sim uArch: 56 57 58 59 60 61 -GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) -GPGPU-Sim uArch: Memory nodes start from ID: 40 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 50 51 52 53 54 55 -GPGPU-Sim uArch: 56 57 58 59 60 61 -a9478053306cbb4803bedf0d6ea12100 /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core -GPGPU-Sim uArch: performance model initialization complete. -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default -self exe links to: /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core -Running md5sum using "md5sum /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core " -Parsing file _cuobjdump_complete_output_c7ZC8M -######### cuobjdump parser ######## -## Adding new section PTX -Adding ptx filename: _cuobjdump_1.ptx -Adding arch: sm_70 -Adding identifier: default -Done parsing!!! -GPGPU-Sim PTX: __cudaRegisterFunction _Z17convertFp32ToFp16P6__halfPfi : hostFun 0x0x401dd7, fat_cubin_handle = 1 -WARNING: No guarantee that PTX will be parsed for SM version 70 - _1.ptx:13 => (ptx_parser.cc:175) start_function - _1.ptx:13 => (ptx_parser.cc:144) init_directive_state - _1.ptx:13 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:13 => (ptx_parser.cc:144) init_directive_state - _1.ptx:13 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:13 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" - _1.ptx:13 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B32_TYPE - _1.ptx:14 => (ptx_parser.cc:189) add_function_name vprintf (extern) - _1.ptx:14 => (ptx_parser.cc:381) add_identifier "func_retval0" (0) -GPGPU-Sim PTX: allocating stack frame region for .param "func_retval0" from 0x0 to 0x4 - _1.ptx:14 => (ptx_parser.cc:144) init_directive_state - _1.ptx:15 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:15 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" - _1.ptx:15 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE - _1.ptx:15 => (ptx_parser.cc:381) add_identifier "vprintf_param_0" (1) -GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_0" from 0x4 to 0xc - _1.ptx:15 => (ptx_parser.cc:577) add_function_arg "vprintf_param_0" - _1.ptx:15 => (ptx_parser.cc:219) add_directive - _1.ptx:15 => (ptx_parser.cc:144) init_directive_state - _1.ptx:16 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:16 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" - _1.ptx:16 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE - _1.ptx:17 => (ptx_parser.cc:381) add_identifier "vprintf_param_1" (2) -GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_1" from 0xc to 0x14 - _1.ptx:17 => (ptx_parser.cc:577) add_function_arg "vprintf_param_1" - _1.ptx:17 => (ptx_parser.cc:219) add_directive - _1.ptx:17 => (ptx_parser.cc:144) init_directive_state - _1.ptx:19 => (ptx_parser.cc:605) add_space_spec "global_space" - _1.ptx:19 => (ptx_parser.cc:590) add_alignment_spec - _1.ptx:19 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" - _1.ptx:19 => (ptx_parser.cc:331) set_variable_type space_spec=global_space scalar_type_spec=B8_TYPE - _1.ptx:19 => (ptx_parser.cc:381) add_identifier "$str" (3) -GPGPU-Sim PTX: allocating global region for "$str" from 0x100 to 0x109 (global memory space) - _1.ptx:19 => (ptx_parser.cc:883) add_literal_int - _1.ptx:19 => (ptx_parser.cc:883) add_literal_int - _1.ptx:19 => (ptx_parser.cc:883) add_literal_int - _1.ptx:19 => (ptx_parser.cc:883) add_literal_int - _1.ptx:19 => (ptx_parser.cc:883) add_literal_int - _1.ptx:19 => (ptx_parser.cc:883) add_literal_int - _1.ptx:19 => (ptx_parser.cc:883) add_literal_int - _1.ptx:19 => (ptx_parser.cc:883) add_literal_int - _1.ptx:19 => (ptx_parser.cc:883) add_literal_int - _1.ptx:19 => (ptx_parser.cc:319) add_variables - _1.ptx:19 => (ptx_parser.cc:144) init_directive_state - _1.ptx:21 => (ptx_parser.cc:175) start_function - _1.ptx:21 => (ptx_parser.cc:144) init_directive_state - _1.ptx:21 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:21 => (ptx_parser.cc:144) init_directive_state - _1.ptx:21 => (ptx_parser.cc:189) add_function_name _Z12wmma_exampleP6__halfS0_Pfiiiff (entrypoint) - _1.ptx:22 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:22 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" - _1.ptx:22 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE - _1.ptx:22 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" (4) - _1.ptx:22 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" - _1.ptx:22 => (ptx_parser.cc:219) add_directive - _1.ptx:22 => (ptx_parser.cc:144) init_directive_state - _1.ptx:23 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:23 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" - _1.ptx:23 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE - _1.ptx:23 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" (5) - _1.ptx:23 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" - _1.ptx:23 => (ptx_parser.cc:219) add_directive - _1.ptx:23 => (ptx_parser.cc:144) init_directive_state - _1.ptx:24 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:24 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" - _1.ptx:24 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE - _1.ptx:24 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" (6) - _1.ptx:24 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" - _1.ptx:24 => (ptx_parser.cc:219) add_directive - _1.ptx:24 => (ptx_parser.cc:144) init_directive_state - _1.ptx:25 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:25 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:25 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE - _1.ptx:25 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" (7) - _1.ptx:25 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" - _1.ptx:25 => (ptx_parser.cc:219) add_directive - _1.ptx:25 => (ptx_parser.cc:144) init_directive_state - _1.ptx:26 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:26 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:26 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE - _1.ptx:26 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" (8) - _1.ptx:26 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" - _1.ptx:26 => (ptx_parser.cc:219) add_directive - _1.ptx:26 => (ptx_parser.cc:144) init_directive_state - _1.ptx:27 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:27 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:27 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE - _1.ptx:27 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" (9) - _1.ptx:27 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" - _1.ptx:27 => (ptx_parser.cc:219) add_directive - _1.ptx:27 => (ptx_parser.cc:144) init_directive_state - _1.ptx:28 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:28 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" - _1.ptx:28 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE - _1.ptx:28 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" (10) - _1.ptx:28 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" - _1.ptx:28 => (ptx_parser.cc:219) add_directive - _1.ptx:28 => (ptx_parser.cc:144) init_directive_state - _1.ptx:29 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:29 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" - _1.ptx:29 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE - _1.ptx:30 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" (11) - _1.ptx:30 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" - _1.ptx:30 => (ptx_parser.cc:219) add_directive - _1.ptx:30 => (ptx_parser.cc:144) init_directive_state - _1.ptx:32 => (ptx_parser.cc:605) add_space_spec "local_space" - _1.ptx:32 => (ptx_parser.cc:590) add_alignment_spec - _1.ptx:32 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" - _1.ptx:32 => (ptx_parser.cc:331) set_variable_type space_spec=local_space scalar_type_spec=B8_TYPE - _1.ptx:32 => (ptx_parser.cc:381) add_identifier "__local_depot0" (12) -GPGPU-Sim PTX: allocating stack frame region for .local "__local_depot0" from 0x0 to 0x8 - _1.ptx:32 => (ptx_parser.cc:319) add_variables - _1.ptx:32 => (ptx_parser.cc:144) init_directive_state - _1.ptx:32 => (ptx_parser.cc:219) add_directive - _1.ptx:32 => (ptx_parser.cc:144) init_directive_state - _1.ptx:33 => (ptx_parser.cc:605) add_space_spec "reg_space" - _1.ptx:33 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" - _1.ptx:33 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE - _1.ptx:33 => (ptx_parser.cc:381) add_identifier "%SP" (13) - _1.ptx:33 => (ptx_parser.cc:319) add_variables - _1.ptx:33 => (ptx_parser.cc:144) init_directive_state - _1.ptx:33 => (ptx_parser.cc:219) add_directive - _1.ptx:33 => (ptx_parser.cc:144) init_directive_state - _1.ptx:34 => (ptx_parser.cc:605) add_space_spec "reg_space" - _1.ptx:34 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" - _1.ptx:34 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE - _1.ptx:34 => (ptx_parser.cc:381) add_identifier "%SPL" (14) - _1.ptx:34 => (ptx_parser.cc:319) add_variables - _1.ptx:34 => (ptx_parser.cc:144) init_directive_state - _1.ptx:34 => (ptx_parser.cc:219) add_directive - _1.ptx:34 => (ptx_parser.cc:144) init_directive_state - _1.ptx:35 => (ptx_parser.cc:605) add_space_spec "reg_space" - _1.ptx:35 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" - _1.ptx:35 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=PRED_TYPE - _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p0" (15) - _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p1" (16) - _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p2" (17) - _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p3" (18) - _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p4" (19) - _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p5" (20) - _1.ptx:35 => (ptx_parser.cc:319) add_variables - _1.ptx:35 => (ptx_parser.cc:144) init_directive_state - _1.ptx:35 => (ptx_parser.cc:219) add_directive - _1.ptx:35 => (ptx_parser.cc:144) init_directive_state - _1.ptx:36 => (ptx_parser.cc:605) add_space_spec "reg_space" - _1.ptx:36 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" - _1.ptx:36 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=F32_TYPE - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f0" (21) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f1" (22) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f2" (23) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f3" (24) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f4" (25) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f5" (26) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f6" (27) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f7" (28) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f8" (29) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f9" (30) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f10" (31) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f11" (32) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f12" (33) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f13" (34) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f14" (35) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f15" (36) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f16" (37) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f17" (38) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f18" (39) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f19" (40) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f20" (41) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f21" (42) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f22" (43) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f23" (44) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f24" (45) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f25" (46) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f26" (47) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f27" (48) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f28" (49) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f29" (50) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f30" (51) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f31" (52) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f32" (53) - _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f33" (54) - _1.ptx:36 => (ptx_parser.cc:319) add_variables - _1.ptx:36 => (ptx_parser.cc:144) init_directive_state - _1.ptx:36 => (ptx_parser.cc:219) add_directive - _1.ptx:36 => (ptx_parser.cc:144) init_directive_state - _1.ptx:37 => (ptx_parser.cc:605) add_space_spec "reg_space" - _1.ptx:37 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" - _1.ptx:37 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B32_TYPE - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r0" (55) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r1" (56) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r2" (57) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r3" (58) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r4" (59) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r5" (60) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r6" (61) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r7" (62) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r8" (63) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r9" (64) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r10" (65) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r11" (66) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r12" (67) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r13" (68) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r14" (69) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r15" (70) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r16" (71) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r17" (72) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r18" (73) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r19" (74) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r20" (75) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r21" (76) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r22" (77) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r23" (78) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r24" (79) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r25" (80) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r26" (81) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r27" (82) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r28" (83) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r29" (84) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r30" (85) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r31" (86) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r32" (87) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r33" (88) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r34" (89) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r35" (90) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r36" (91) - _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r37" (92) - _1.ptx:37 => (ptx_parser.cc:319) add_variables - _1.ptx:37 => (ptx_parser.cc:144) init_directive_state - _1.ptx:37 => (ptx_parser.cc:219) add_directive - _1.ptx:37 => (ptx_parser.cc:144) init_directive_state - _1.ptx:38 => (ptx_parser.cc:605) add_space_spec "reg_space" - _1.ptx:38 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" - _1.ptx:38 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd0" (93) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd1" (94) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd2" (95) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd3" (96) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd4" (97) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd5" (98) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd6" (99) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd7" (100) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd8" (101) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd9" (102) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd10" (103) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd11" (104) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd12" (105) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd13" (106) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd14" (107) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd15" (108) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd16" (109) - _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd17" (110) - _1.ptx:38 => (ptx_parser.cc:319) add_variables - _1.ptx:38 => (ptx_parser.cc:144) init_directive_state - _1.ptx:38 => (ptx_parser.cc:219) add_directive - _1.ptx:38 => (ptx_parser.cc:144) init_directive_state - _1.ptx:41 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" - _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:41 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:41 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:41 => (ptx_parser.cc:144) init_directive_state - _1.ptx:42 => (ptx_parser.cc:605) add_space_spec "local_space" - _1.ptx:42 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" - _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:42 => (ptx_parser.cc:295) add_instruction: cvta - _1.ptx:42 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:42 => (ptx_parser.cc:144) init_directive_state - _1.ptx:43 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:43 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" - _1.ptx:43 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:43 => (ptx_parser.cc:929) add_address_operand - _1.ptx:43 => (ptx_parser.cc:766) add_memory_operand - _1.ptx:43 => (ptx_parser.cc:295) add_instruction: ld - _1.ptx:43 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:43 => (ptx_parser.cc:144) init_directive_state - _1.ptx:44 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:44 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" - _1.ptx:44 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:44 => (ptx_parser.cc:929) add_address_operand - _1.ptx:44 => (ptx_parser.cc:766) add_memory_operand - _1.ptx:44 => (ptx_parser.cc:295) add_instruction: ld - _1.ptx:44 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:44 => (ptx_parser.cc:144) init_directive_state - _1.ptx:45 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:45 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" - _1.ptx:45 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:45 => (ptx_parser.cc:929) add_address_operand - _1.ptx:45 => (ptx_parser.cc:766) add_memory_operand - _1.ptx:45 => (ptx_parser.cc:295) add_instruction: ld - _1.ptx:45 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:45 => (ptx_parser.cc:144) init_directive_state - _1.ptx:46 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:46 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:46 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:46 => (ptx_parser.cc:929) add_address_operand - _1.ptx:46 => (ptx_parser.cc:766) add_memory_operand - _1.ptx:46 => (ptx_parser.cc:295) add_instruction: ld - _1.ptx:46 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:46 => (ptx_parser.cc:144) init_directive_state - _1.ptx:47 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:47 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:47 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:47 => (ptx_parser.cc:929) add_address_operand - _1.ptx:47 => (ptx_parser.cc:766) add_memory_operand - _1.ptx:47 => (ptx_parser.cc:295) add_instruction: ld - _1.ptx:47 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:47 => (ptx_parser.cc:144) init_directive_state - _1.ptx:48 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" - _1.ptx:48 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:48 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:48 => (ptx_parser.cc:929) add_address_operand - _1.ptx:48 => (ptx_parser.cc:766) add_memory_operand - _1.ptx:48 => (ptx_parser.cc:295) add_instruction: ld - _1.ptx:48 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:48 => (ptx_parser.cc:144) init_directive_state - _1.ptx:50 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:50 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:50 => (ptx_parser.cc:760) add_builtin_operand - _1.ptx:50 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:50 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:50 => (ptx_parser.cc:144) init_directive_state - _1.ptx:52 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:52 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:52 => (ptx_parser.cc:760) add_builtin_operand - _1.ptx:52 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:52 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:52 => (ptx_parser.cc:144) init_directive_state - _1.ptx:53 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:53 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:53 => (ptx_parser.cc:760) add_builtin_operand - _1.ptx:53 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:53 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:53 => (ptx_parser.cc:144) init_directive_state - _1.ptx:54 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:54 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:54 => (ptx_parser.cc:760) add_builtin_operand - _1.ptx:54 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:54 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:54 => (ptx_parser.cc:144) init_directive_state - _1.ptx:55 => (ptx_parser.cc:672) add_option - _1.ptx:55 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" - _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:55 => (ptx_parser.cc:295) add_instruction: mad - _1.ptx:55 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:55 => (ptx_parser.cc:144) init_directive_state - _1.ptx:56 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:56 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:56 => (ptx_parser.cc:760) add_builtin_operand - _1.ptx:56 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:56 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:56 => (ptx_parser.cc:144) init_directive_state - _1.ptx:57 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:57 => (ptx_parser.cc:295) add_instruction: div - _1.ptx:57 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:57 => (ptx_parser.cc:144) init_directive_state - _1.ptx:58 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:58 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:58 => (ptx_parser.cc:760) add_builtin_operand - _1.ptx:58 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:58 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:58 => (ptx_parser.cc:144) init_directive_state - _1.ptx:59 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:59 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:59 => (ptx_parser.cc:760) add_builtin_operand - _1.ptx:59 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:59 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:59 => (ptx_parser.cc:144) init_directive_state - _1.ptx:60 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" - _1.ptx:60 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:60 => (ptx_parser.cc:760) add_builtin_operand - _1.ptx:60 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:60 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:60 => (ptx_parser.cc:144) init_directive_state - _1.ptx:61 => (ptx_parser.cc:672) add_option - _1.ptx:61 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" - _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:61 => (ptx_parser.cc:295) add_instruction: mad - _1.ptx:61 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:61 => (ptx_parser.cc:144) init_directive_state - _1.ptx:62 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" - _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:62 => (ptx_parser.cc:883) add_literal_int - _1.ptx:62 => (ptx_parser.cc:295) add_instruction: shl - _1.ptx:62 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:62 => (ptx_parser.cc:144) init_directive_state - _1.ptx:63 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" - _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:63 => (ptx_parser.cc:883) add_literal_int - _1.ptx:63 => (ptx_parser.cc:295) add_instruction: shl - _1.ptx:63 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:63 => (ptx_parser.cc:144) init_directive_state - _1.ptx:64 => (ptx_parser.cc:672) add_option - _1.ptx:64 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" - _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:64 => (ptx_parser.cc:295) add_instruction: setp - _1.ptx:64 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:64 => (ptx_parser.cc:144) init_directive_state - _1.ptx:65 => (ptx_parser.cc:672) add_option - _1.ptx:65 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" - _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:65 => (ptx_parser.cc:883) add_literal_int - _1.ptx:65 => (ptx_parser.cc:295) add_instruction: setp - _1.ptx:65 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:65 => (ptx_parser.cc:144) init_directive_state - _1.ptx:66 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" - _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:66 => (ptx_parser.cc:295) add_instruction: and - _1.ptx:66 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:66 => (ptx_parser.cc:144) init_directive_state - _1.ptx:67 => (ptx_parser.cc:672) add_option - _1.ptx:67 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" - _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:67 => (ptx_parser.cc:295) add_instruction: setp - _1.ptx:67 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:67 => (ptx_parser.cc:144) init_directive_state - _1.ptx:68 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" - _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:68 => (ptx_parser.cc:295) add_instruction: and - _1.ptx:68 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:68 => (ptx_parser.cc:144) init_directive_state - _1.ptx:69 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" - _1.ptx:69 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:69 => (ptx_parser.cc:889) add_literal_float - _1.ptx:69 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:69 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:69 => (ptx_parser.cc:144) init_directive_state - _1.ptx:70 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" - _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:70 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:70 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:70 => (ptx_parser.cc:144) init_directive_state - _1.ptx:71 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" - _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:71 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:71 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:71 => (ptx_parser.cc:144) init_directive_state - _1.ptx:72 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" - _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:72 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:72 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:72 => (ptx_parser.cc:144) init_directive_state - _1.ptx:73 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" - _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:73 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:73 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:73 => (ptx_parser.cc:144) init_directive_state - _1.ptx:74 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" - _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:74 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:74 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:74 => (ptx_parser.cc:144) init_directive_state - _1.ptx:75 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" - _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:75 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:75 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:75 => (ptx_parser.cc:144) init_directive_state - _1.ptx:76 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" - _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:76 => (ptx_parser.cc:295) add_instruction: mov - _1.ptx:76 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:76 => (ptx_parser.cc:144) init_directive_state - _1.ptx:77 => (ptx_parser.cc:659) add_pred - _1.ptx:77 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:77 => (ptx_parser.cc:295) add_instruction: bra - _1.ptx:77 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:77 => (ptx_parser.cc:144) init_directive_state - _1.ptx:78 => (ptx_parser.cc:672) add_option - _1.ptx:78 => (ptx_parser.cc:901) add_scalar_operand - _1.ptx:78 => (ptx_parser.cc:295) add_instruction: bra - _1.ptx:78 => (ptx_parser.cc:159) init_instruction_state - _1.ptx:78 => (ptx_parser.cc:144) init_directive_state - _1.ptx:80 => (ptx_parser.cc:643) add_label - _1.ptx:80 => (ptx_parser.cc:295) add_instruction: