From d907c7d848be6ced2b7f2bd2df84b39e57dfbedc Mon Sep 17 00:00:00 2001 From: negargoli Date: Fri, 22 Jun 2018 11:09:18 -0700 Subject: No need to change the config file for adding tensor-core --- cuda-kernels/gpgpusim.config | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'cuda-kernels') diff --git a/cuda-kernels/gpgpusim.config b/cuda-kernels/gpgpusim.config index 69a110f..272ad3d 100755 --- a/cuda-kernels/gpgpusim.config +++ b/cuda-kernels/gpgpusim.config @@ -33,10 +33,9 @@ # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Pascal GP102 has 4 SP SIMD units and 1 SFU unit ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,1,4,1,1,1,,6 +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 1 --gpgpu_num_tensor_core_units 1 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # SFU is 32-width in pascal, then dp units initiation is 1 cycle @@ -72,14 +71,14 @@ ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units -gpgpu_operand_collector_num_units_sp 20 -gpgpu_operand_collector_num_units_sfu 4 --gpgpu_operand_collector_num_units_tensor_core 24 +#-gpgpu_operand_collector_num_units_tensor_core 24 -gpgpu_operand_collector_num_units_mem 8 -gpgpu_operand_collector_num_in_ports_sp 4 -gpgpu_operand_collector_num_out_ports_sp 4 -gpgpu_operand_collector_num_in_ports_sfu 1 -gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_tensor_core 1 --gpgpu_operand_collector_num_out_ports_tensor_core 1 +#-gpgpu_operand_collector_num_in_ports_tensor_core 1 +#-gpgpu_operand_collector_num_out_ports_tensor_core 1 -gpgpu_operand_collector_num_in_ports_mem 1 -gpgpu_operand_collector_num_out_ports_mem 1 # gpgpu_num_reg_banks should be increased to 32, but it gives an error! -- cgit v1.3