From 35cf76f383ec8de6de901bbbcd8fb478f69e46e4 Mon Sep 17 00:00:00 2001 From: sspenst Date: Wed, 6 Jul 2016 13:56:52 -0700 Subject: Added sstarr memory, which works the same as shared memory --- cuobjdump_to_ptxplus/ptx_parser.h | 1 + 1 file changed, 1 insertion(+) (limited to 'cuobjdump_to_ptxplus') diff --git a/cuobjdump_to_ptxplus/ptx_parser.h b/cuobjdump_to_ptxplus/ptx_parser.h index 1c96b46..22377b2 100644 --- a/cuobjdump_to_ptxplus/ptx_parser.h +++ b/cuobjdump_to_ptxplus/ptx_parser.h @@ -58,6 +58,7 @@ enum _memory_space_t { reg_space, local_space, shared_space, + sstarr_space, param_space_unclassified, param_space_kernel, /* global to all threads in a kernel : read-only */ param_space_local, /* local to a thread : read-writable */ -- cgit v1.3 From 968a0510e7d1826fefa7b6688eb662d71d048809 Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Sun, 22 Apr 2018 23:35:05 -0400 Subject: One more instance of where a string should be escaped with %s before being passed to printf. --- cuobjdump_to_ptxplus/cuobjdumpInst.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cuobjdump_to_ptxplus') diff --git a/cuobjdump_to_ptxplus/cuobjdumpInst.cc b/cuobjdump_to_ptxplus/cuobjdumpInst.cc index c74d2d8..392f829 100644 --- a/cuobjdump_to_ptxplus/cuobjdumpInst.cc +++ b/cuobjdump_to_ptxplus/cuobjdumpInst.cc @@ -2083,7 +2083,7 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list labelList, std: else { printf("Unknown Instruction: "); - printf(m_base.c_str()); + printf("%s",m_base.c_str()); printf("\n"); output("Unknown Instruction: "); output(m_base); -- cgit v1.3 From 7dfa2ae2e6f8ccaaf133318265a7ab00de546e82 Mon Sep 17 00:00:00 2001 From: aamir Date: Sun, 27 May 2018 14:18:53 -0700 Subject: added wmma parsing but execution getting aborted --- cuda-kernels/Makefile | 7 + cuda-kernels/_cuobjdump_1.elf | 15 + cuda-kernels/_cuobjdump_1.ptx | 170 ++++ cuda-kernels/_cuobjdump_1.sass | 2 + cuda-kernels/_cuobjdump_2.elf | 494 +++++++++ cuda-kernels/_cuobjdump_2.sass | 348 +++++++ cuda-kernels/_cuobjdump_complete_output_EIGzTK | 1055 ++++++++++++++++++++ cuda-kernels/_cuobjdump_complete_output_rndQyq | 1055 ++++++++++++++++++++ cuda-kernels/config_fermi_islip.icnt | 70 ++ cuda-kernels/gpgpu_inst_stats.txt | 1 + cuda-kernels/gpgpusim.config | 149 +++ ...usim_power_report__Sun-May-27-14-17-34-2018.log | 324 ++++++ ...usim_power_report__Sun-May-27-14-17-47-2018.log | 324 ++++++ cuda-kernels/gpuwattch_gtx1080Ti.xml | 538 ++++++++++ cuda-kernels/tensor_core | Bin 0 -> 48541 bytes cuda-kernels/tensor_core.cu | 250 +++++ cuobjdump_to_ptxplus/ptx_parser.h | 2 + src/cuda-sim/instructions.cc | 8 +- src/cuda-sim/opcodes.def | 2 + src/cuda-sim/opcodes.h | 11 +- src/cuda-sim/ptx.l | 18 +- src/cuda-sim/ptx.y | 10 + src/cuda-sim/ptx_ir.cc | 6 +- src/cuda-sim/ptx_ir.h | 33 + src/cuda-sim/ptx_parser.cc | 33 +- src/cuda-sim/ptx_parser.h | 2 + 26 files changed, 4918 insertions(+), 9 deletions(-) create mode 100755 cuda-kernels/Makefile create mode 100644 cuda-kernels/_cuobjdump_1.elf create mode 100644 cuda-kernels/_cuobjdump_1.ptx create mode 100644 cuda-kernels/_cuobjdump_1.sass create mode 100644 cuda-kernels/_cuobjdump_2.elf create mode 100644 cuda-kernels/_cuobjdump_2.sass create mode 100644 cuda-kernels/_cuobjdump_complete_output_EIGzTK create mode 100644 cuda-kernels/_cuobjdump_complete_output_rndQyq create mode 100755 cuda-kernels/config_fermi_islip.icnt create mode 100755 cuda-kernels/gpgpu_inst_stats.txt create mode 100755 cuda-kernels/gpgpusim.config create mode 100644 cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log create mode 100644 cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log create mode 100755 cuda-kernels/gpuwattch_gtx1080Ti.xml create mode 100755 cuda-kernels/tensor_core create mode 100644 cuda-kernels/tensor_core.cu (limited to 'cuobjdump_to_ptxplus') diff --git a/cuda-kernels/Makefile b/cuda-kernels/Makefile new file mode 100755 index 0000000..51a7760 --- /dev/null +++ b/cuda-kernels/Makefile @@ -0,0 +1,7 @@ +all: tensor_core.cu + nvcc -arch=sm_70 -lcudart -g -o tensor_core tensor_core.cu + +.PHONY: +clean: + rm tensorcore +# nvcc -arch=sm_70 --gpu-architecture=compute_50 --gpu-code=compute_50 -lcudart -g -o tensor_core tensor_core.cu diff --git a/cuda-kernels/_cuobjdump_1.elf b/cuda-kernels/_cuobjdump_1.elf new file mode 100644 index 0000000..672b0f0 --- /dev/null +++ b/cuda-kernels/_cuobjdump_1.elf @@ -0,0 +1,15 @@ +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 32 0 1 STRTAB 0 0 0 .shstrtab + 2 72 32 0 1 STRTAB 0 0 0 .strtab + 3 a8 18 18 8 SYMTAB 0 2 0 .symtab + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + diff --git a/cuda-kernels/_cuobjdump_1.ptx b/cuda-kernels/_cuobjdump_1.ptx new file mode 100644 index 0000000..3453f4a --- /dev/null +++ b/cuda-kernels/_cuobjdump_1.ptx @@ -0,0 +1,170 @@ + + + + + + + +.version 6.0 +.target sm_70 +.address_size 64 + + +.extern .func (.param .b32 func_retval0) vprintf +( +.param .b64 vprintf_param_0, +.param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ +.local .align 8 .b8 __local_depot0[8]; +.reg .b64 %SP; +.reg .b64 %SPL; +.reg .pred %p<6>; +.reg .f32 %f<34>; +.reg .b32 %r<38>; +.reg .b64 %rd<18>; + + +mov.u64 %rd17, __local_depot0; +cvta.local.u64 %SP, %rd17; +ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; +ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; +ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; +ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; +ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; +ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + + mov.u32 %r6, %clock; + + mov.u32 %r8, %ntid.x; +mov.u32 %r9, %ctaid.x; +mov.u32 %r10, %tid.x; +mad.lo.s32 %r11, %r8, %r9, %r10; +mov.u32 %r12, WARP_SZ; +div.u32 %r13, %r11, %r12; +mov.u32 %r14, %ntid.y; +mov.u32 %r15, %ctaid.y; +mov.u32 %r16, %tid.y; +mad.lo.s32 %r17, %r14, %r15, %r16; +shl.b32 %r2, %r13, 4; +shl.b32 %r3, %r17, 4; +setp.lt.s32 %p1, %r2, %r4; +setp.gt.s32 %p2, %r5, 0; +and.pred %p3, %p1, %p2; +setp.lt.s32 %p4, %r3, %r7; +and.pred %p5, %p3, %p4; +mov.f32 %f26, 0f00000000; +mov.f32 %f27, %f26; +mov.f32 %f28, %f26; +mov.f32 %f29, %f26; +mov.f32 %f30, %f26; +mov.f32 %f31, %f26; +mov.f32 %f32, %f26; +mov.f32 %f33, %f26; +@!%p5 bra BB0_2; +bra.uni BB0_1; + +BB0_1: +mul.wide.s32 %rd4, %r2, 2; +add.s64 %rd5, %rd1, %rd4; +wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; +mul.wide.s32 %rd6, %r3, 2; +add.s64 %rd7, %rd2, %rd6; +wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; +mov.f32 %f25, 0f00000000; +wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: +add.u64 %rd8, %SP, 0; +cvta.to.local.u64 %rd9, %rd8; +mul.lo.s32 %r35, %r3, %r4; +cvt.s64.s32 %rd10, %r35; +cvt.s64.s32 %rd11, %r2; +add.s64 %rd12, %rd10, %rd11; +shl.b64 %rd13, %rd12, 2; +add.s64 %rd14, %rd3, %rd13; +wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + + mov.u32 %r34, %clock; + + sub.s32 %r36, %r34, %r6; +st.local.u32 [%rd9], %r36; +mov.u64 %rd15, $str; +cvta.global.u64 %rd16, %rd15; + + { +.reg .b32 temp_param_reg; + + .param .b64 param0; +st.param.b64 [param0+0], %rd16; +.param .b64 param1; +st.param.b64 [param1+0], %rd8; +.param .b32 retval0; +call.uni (retval0), +vprintf, +( +param0, +param1 +); +ld.param.b32 %r37, [retval0+0]; + + + } + ret; +} + + +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, +.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ +.reg .pred %p<2>; +.reg .b16 %rs<2>; +.reg .f32 %f<2>; +.reg .b32 %r<6>; +.reg .b64 %rd<9>; + + +ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; +ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; +ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; +mov.u32 %r3, %ntid.x; +mov.u32 %r4, %ctaid.x; +mov.u32 %r5, %tid.x; +mad.lo.s32 %r1, %r4, %r3, %r5; +setp.ge.s32 %p1, %r1, %r2; +@%p1 bra BB1_2; + +cvta.to.global.u64 %rd3, %rd2; +mul.wide.s32 %rd4, %r1, 4; +add.s64 %rd5, %rd3, %rd4; +ld.global.f32 %f1, [%rd5]; + + { cvt.rn.f16.f32 %rs1, %f1;} + + + cvta.to.global.u64 %rd6, %rd1; +mul.wide.s32 %rd7, %r1, 2; +add.s64 %rd8, %rd6, %rd7; +st.global.u16 [%rd8], %rs1; + +BB1_2: +ret; +} + + diff --git a/cuda-kernels/_cuobjdump_1.sass b/cuda-kernels/_cuobjdump_1.sass new file mode 100644 index 0000000..2aac29a --- /dev/null +++ b/cuda-kernels/_cuobjdump_1.sass @@ -0,0 +1,2 @@ + code for sm_70 + diff --git a/cuda-kernels/_cuobjdump_2.elf b/cuda-kernels/_cuobjdump_2.elf new file mode 100644 index 0000000..c03b06d --- /dev/null +++ b/cuda-kernels/_cuobjdump_2.elf @@ -0,0 +1,494 @@ +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 21b 0 1 STRTAB 0 0 0 .shstrtab + 2 25b 273 0 1 STRTAB 0 0 0 .strtab + 3 4d0 108 18 8 SYMTAB 0 2 7 .symtab + 4 5d8 e0 0 1 PROGBITS 0 0 0 .debug_frame + 5 6b8 48 0 4 CUDA_INFO 0 3 0 .nv.info + 6 700 50 0 4 CUDA_INFO 0 3 d .nv.info._Z17convertFp32ToFp16P6__halfPfi + 7 750 ac 0 4 CUDA_INFO 0 3 e .nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + 8 800 30 10 8 REL 0 3 e .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff + 9 830 30 18 8 RELA 0 3 e .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff + a 860 20 10 8 REL 0 3 4 .rel.debug_frame + b 880 174 0 4 PROGBITS 2 0 d .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + c 9f4 18c 0 4 PROGBITS 2 0 e .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + d b80 100 0 80 PROGBITS 6 3 9000008 .text._Z17convertFp32ToFp16P6__halfPfi + e c80 980 0 80 PROGBITS 6 3 20000009 .text._Z12wmma_exampleP6__halfS0_Pfiiiff + f 1600 9 0 10 PROGBITS 3 0 0 .nv.global.init + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + 1 0 0 3 0 d .text._Z17convertFp32ToFp16P6__halfPfi + 2 0 0 3 0 f .nv.global.init + 3 0 9 1 0 f $str + 4 0 0 3 0 b .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + 5 0 0 3 0 e .text._Z12wmma_exampleP6__halfS0_Pfiiiff + 6 0 0 3 0 c .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + 7 0 0 3 0 4 .debug_frame + 8 0 256 12 10 d _Z17convertFp32ToFp16P6__halfPfi + 9 0 2432 12 10 e _Z12wmma_exampleP6__halfS0_Pfiiiff + 10 0 0 12 0 0 vprintf + + +.nv.constant0._Z17convertFp32ToFp16P6__halfPfi +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 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+0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 + + +.nv.global.init +0x636f6c63 0x64253d6b 0 + + +.nv.info + <0x1> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x9 0x0 + <0x2> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) min stack size: 0x8 + <0x3> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) frame size: 0x8 + <0x4> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x8 0x0 + <0x5> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) min stack size: 0x0 + <0x6> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) frame size: 0x0 + + +.nv.info._Z17convertFp32ToFp16P6__halfPfi + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x4 0x140160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x14 + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x7> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x60 0xe0 + + +.nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x6 0x2c0160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x2c + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x7 Offset : 0x28 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x6 Offset : 0x24 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x5 Offset : 0x20 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x4 Offset : 0x1c Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x7> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x3 Offset : 0x18 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x8> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x9> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x10> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x11> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x12> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x940 + <0x13> + Attribute: EIATTR_EXTERNS + Format: EIFMT_SVAL + Value: externs: vprintf(0xa) + <0x14> + Attribute: EIATTR_CRS_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x0 + + +.text._Z17convertFp32ToFp16P6__halfPfi +bar = 0 reg = 9 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0x00017a02 0x00000a00 0x00000f00 0x000fd000 +0x00047919 0x00000000 0x00002500 0x000e2200 +0x00027919 0x00000000 0x00002100 0x000e2400 +0x04047a24 0x00000000 0x078e0202 0x001fca00 +0x04007a0c 0x00005c00 0x03f062f0 0x000fd800 +0x0000094d 0x00000000 0x03800000 0x000fea00 +0x00027802 0x00000004 0x00000f00 0x000fca00 +0x04027625 0x00005a00 0x078e0202 0x000fd400 +0x02027381 0x00000000 0x001ee900 0x000e2200 +0x00057802 0x00000002 0x00000f00 0x000fca00 +0x04047625 0x00005800 0x078e0205 0x000fe200 +0x00067304 0x00000002 0x00200800 0x001e3200 +0x04007386 0x00000006 0x0010e500 0x0011e200 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 + + + +.text._Z12wmma_exampleP6__halfS0_Pfiiiff +bar = 0 reg = 32 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0xff017624 0x00000a00 0x078e00ff 0x000fd000 +0x01017810 0xfffffff8 0x07ffe0ff 0x000fc800 +0x01027a10 0x00000800 0x07f1e0ff 0x000fca00 +0xff007624 0x00000900 0x000e06ff 0x000fd000 +0x00037805 0x00000000 0x00005000 0x000fd000 +0x00077906 0x00000020 0x00209000 0x000e2400 +0x00077308 0x00000007 0x00001000 0x001e2200 +0x00067919 0x00000000 0x00002500 0x000e6200 +0x00097919 0x00000000 0x00002100 0x000e6200 +0x07087810 0x0ffffffe 0x07ffe0ff 0x001fcc00 +0x00057305 0x00000008 0x0021f000 0x0000a200 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0x06067a24 0x00000000 0x078e0209 0x002fe400 +0x050a7824 0xffffffe0 0x078e00ff 0x004fc800 +0x05047225 0x0000000a 0x078e0004 0x000fd000 +0x05047225 0x00000006 0x078e00ff 0x000fcc00 +0xff047224 0x000000ff 0x078e0a05 0x000fc800 +0x04067824 0x00000020 0x078e0206 0x000fca00 +0x0600780c 0x00000020 0x03f060f0 0x040fe200 +0x001c7919 0x00000000 0x00002600 0x000e2200 +0x00077919 0x00000000 0x00002200 0x000e3400 +0x06060810 0xffffffe0 0x07ffe0ff 0x000fc800 +0x0600780c 0x00000020 0x03f260f0 0x000fe400 +0x05050810 0x00000001 0x07ffe0ff 0x000fe400 +0xff007a0c 0x00006000 0x03f012f0 0x000fd000 +0x05051810 0x00000001 0x07ffe0ff 0x000fe200 +0x1c1c7a24 0x00000100 0x078e0207 0x001fc600 +0x051d7819 0x00000004 0x000006ff 0x000fe200 +0x1c1c7824 0x00000010 0x078e00ff 0x000fc600 +0x1d007a0c 0x00005e00 0x007012f0 0x000fc800 +0x1c007a0c 0x00005f00 0x007012f0 0x000fe200 +0x00007945 0x000003a0 0x03800000 0x000fe200 +0xff077224 0x000000ff 0x078e00ff 0x000fe200 +0x000b7202 0x000000ff 0x00000f00 0x000fe200 +0xff067224 0x000000ff 0x078e00ff 0x000fe400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0xff0a7224 0x000000ff 0x078e00ff 0x000fc400 +0xff097224 0x000000ff 0x078e00ff 0x000fe400 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00008947 0x00000300 0x03800000 0x000fee00 +0x00067919 0x00000000 0x00000000 0x000e2200 +0xff0a7424 0x00000002 0x078e00ff 0x000fc800 +0x1d107625 0x00005800 0x078e020a 0x000fe200 +0xff047819 0x00000002 0x00011606 0x001fc800 +0x04057812 0x00000003 0x078ec0ff 0x000fe400 +0x06047812 0x00000003 0x078ec0ff 0x000fe400 +0x05077812 0x00000001 0x078ec0ff 0x000fe400 +0xff067819 0x00000004 0x00011606 0x000fe400 +0xff057819 0x00000001 0x00011605 0x000fe200 +0x07077824 0x00000008 0x078e0204 0x000fe200 +0x06067812 0x00000001 0x078ec0ff 0x000fc400 +0x05047211 0x00000004 0x078e18ff 0x000fe200 +0x1c0c7625 0x00005a00 0x078e020a 0x000fe400 +0x06077824 0x00000004 0x078e0207 0x040fe400 +0x06047824 0x00000004 0x078e0204 0x000fe400 +0x07077824 0x00000002 0x078e00ff 0x000fe400 +0x04057824 0x00000002 0x078e00ff 0x000fe400 +0x07107a25 0x00005e00 0x078e0010 0x000fc400 +0x050c7a25 0x00006000 0x078e000c 0x000fd000 +0x10187980 0x00000000 0x0010ed00 0x00006400 +0x0c147980 0x00000000 0x0010ed00 0x00046200 +0x10107980 0x00000010 0x0010ed00 0x001e2200 +0x0c0c7980 0x00000010 0x0010ed00 0x004e2200 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00097202 0x000000ff 0x00000f00 0x000fe200 +0xff0a7224 0x000000ff 0x078e00ff 0x000fe400 +0xff0b7224 0x000000ff 0x078e00ff 0x000fe200 +0x00077202 0x000000ff 0x00000f00 0x000fe200 +0xff047224 0x000000ff 0x078e00ff 0x000fc400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff067224 0x000000ff 0x078e00ff 0x000fe200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x18087236 0x00000014 0x00005408 0x0c226400 +0x180a7236 0x00000014 0x0000d40a 0x0c04a400 +0x18047236 0x00000014 0x00015404 0x0c06e400 +0x18067236 0x00000014 0x0001d406 0x00092800 +0x1a087236 0x00000016 0x00005408 0x0c202400 +0x1a0a7236 0x00000016 0x0000d40a 0x0c426400 +0x1a047236 0x00000016 0x00015404 0x0c84a400 +0x1a067236 0x00000016 0x0001d406 0x0106e800 +0x10087236 0x0000000c 0x00005408 0x0c102400 +0x100a7236 0x0000000c 0x0000d40a 0x0c226400 +0x10047236 0x0000000c 0x00015404 0x0c44a400 +0x10067236 0x0000000c 0x0001d406 0x0086e800 +0x12087236 0x0000000e 0x00005408 0x0c102400 +0x120a7236 0x0000000e 0x0000d40a 0x0c202400 +0x12047236 0x0000000e 0x00015404 0x0c402400 +0x12067236 0x0000000e 0x0001d406 0x00803400 +0x00007941 0x00000000 0x03800000 0x001fea00 +0x000c7919 0x00000000 0x00000000 0x000e2200 +0x1c1c7a24 0x00005e00 0x078e02ff 0x000fe200 +0xff0e7819 0x00000004 0x0001160c 0x001fc400 +0xff0d7819 0x00000002 0x0001160c 0x000fe400 +0x0c0c7812 0x00000003 0x078ec0ff 0x000fe400 +0x0e0e7812 0x00000001 0x078ec0ff 0x000fe400 +0x0d0d7812 0x00000003 0x078ec0ff 0x000fc600 +0x0e0c7824 0x00000004 0x078e020c 0x000fe200 +0x0d0f7812 0x00000001 0x078ec0ff 0x000fe400 +0xff107819 0x00000001 0x0001160d 0x000fe400 +0x0c0d7812 0x00000005 0x078ec0ff 0x040fe400 +0x0c0e7812 0x00000002 0x078ec0ff 0x000fc600 +0x0f0c7824 0x00000008 0x078e020d 0x000fe200 +0xff0f7819 0x0000001f 0x0001141d 0x000fe200 +0x100e7824 0x00000008 0x078e020e 0x000fe200 +0x1d117210 0x0000001c 0x07f1e0ff 0x000fe200 +0xff0d7224 0x000000ff 0x078e00ff 0x000fc600 +0x1c0f7211 0x0000000f 0x000f0eff 0x000fe200 +0x0e0c7a25 0x00005e00 0x078e000c 0x000fe200 +0x110e7a11 0x00005c00 0x078010ff 0x000fe200 +0xff127624 0x00005e00 0x078e00ff 0x000fc600 +0x11117a11 0x00005d00 0x000f140f 0x000fe400 +0x0c107211 0x0000000e 0x078010ff 0x000fe400 +0x120e7819 0x00000002 0x000006ff 0x000fe400 +0xff0f7819 0x0000001e 0x00011612 0x000fe400 +0x0c0d7211 0x00000011 0x000f140d 0x000fe400 +0x0e127211 0x00000010 0x078210ff 0x000fc400 +0x0e117210 0x00000010 0x07f1e0ff 0x040fe400 +0x0e137211 0x0000000d 0x008f140f 0x040fe400 +0x0e157210 0x00000012 0x07f3e0ff 0x000fe200 +0x0f147824 0x00000001 0x000e060d 0x040fe400 +0xff0c7224 0x000000ff 0x078e0010 0x000fe400 +0x0f167824 0x00000001 0x008e0613 0x000fe400 +0xff0e7224 0x000000ff 0x078e0011 0x000fc400 +0xff0f7224 0x000000ff 0x078e0014 0x000fe200 +0x00107202 0x00000015 0x00000f00 0x000fe200 +0xff117224 0x000000ff 0x078e0016 0x000fe200 +0x0c007385 0x00000000 0x0010e908 0x0001e200 +0x0c007385 0x00000008 0x0010e90a 0x0003e800 +0x0e007385 0x00000000 0x0010e909 0x0003e200 +0x0e007385 0x00000008 0x0010e90b 0x0003e200 +0x12007385 0x00000000 0x0010e904 0x0003e200 +0x12007385 0x00000008 0x0010e906 0x0003e200 +0x10007385 0x00000000 0x0010e905 0x0003e200 +0x10007385 0x00000008 0x0010e907 0x0003e200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x02087a10 0x80000800 0x07ffe0ff 0x001fd000 +0x00047805 0x00000000 0x00005000 0x002fd000 +0x04037824 0x00000001 0x078e0a03 0x000fd000 +0x08007387 0x00000003 0x00100800 0x0001e200 +0xff067224 0x000000ff 0x078e0002 0x000fe200 +0x00047802 0x00000000 0x00000f00 0x000fe200 +0xff077224 0x000000ff 0x078e0000 0x000fe200 +0x00057802 0x00000000 0x00000f00 0x000fe400 +0x00147802 0x00000000 0x00000f00 0x000fe400 +0x00157802 0x00000000 0x00000f00 0x000fd000 +0x00007943 0x00000000 0x03c00000 0x001fea00 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 + + +.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff REL +2272 $str R_CUDA_ABS32_LO_32 +2304 $str R_CUDA_ABS32_HI_32 +2352 vprintf R_CUDA_ABS47_34 + +.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff RELA +2320 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_LO_32 2368 +2336 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_HI_32 2368 + +.section .debug_frame +decodeDebugFrame, frameBuf 0xffffffff, total_length 224 +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x100 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 0 + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_advance_loc4 delta 52 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x970 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 2 + DW_CFA_def_cfa register R1, offset 8 + DW_CFA_advance_loc4 delta 586 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +.section .rel.debug_frame REL +72 _Z17convertFp32ToFp16P6__halfPfi R_NV_64 +184 _Z12wmma_exampleP6__halfS0_Pfiiiff R_NV_64 + diff --git a/cuda-kernels/_cuobjdump_2.sass b/cuda-kernels/_cuobjdump_2.sass new file mode 100644 index 0000000..1b50ed2 --- /dev/null +++ b/cuda-kernels/_cuobjdump_2.sass @@ -0,0 +1,348 @@ + code for sm_70 + Function : _Z17convertFp32ToFp16P6__halfPfi + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ MOV R1, c[0x0][0x28]; /* 0x00000a0000017a02 */ + /* 0x000fd00000000f00 */ + /*0020*/ S2R R4, SR_CTAID.X; /* 0x0000000000047919 */ + /* 0x000e220000002500 */ + /*0030*/ S2R R2, SR_TID.X; /* 0x0000000000027919 */ + /* 0x000e240000002100 */ + /*0040*/ IMAD R4, R4, c[0x0][0x0], R2; /* 0x0000000004047a24 */ + /* 0x001fca00078e0202 */ + /*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT; /* 0x00005c0004007a0c */ + /* 0x000fd80003f062f0 */ + /*0060*/ @P0 EXIT; /* 0x000000000000094d */ + /* 0x000fea0003800000 */ + /*0070*/ MOV R2, 0x4; /* 0x0000000400027802 */ + /* 0x000fca0000000f00 */ + /*0080*/ IMAD.WIDE R2, R4, R2, c[0x0][0x168]; /* 0x00005a0004027625 */ + /* 0x000fd400078e0202 */ + /*0090*/ LDG.E.SYS R2, [R2]; /* 0x0000000002027381 */ + /* 0x000e2200001ee900 */ + /*00a0*/ MOV R5, 0x2; /* 0x0000000200057802 */ + /* 0x000fca0000000f00 */ + /*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160]; /* 0x0000580004047625 */ + /* 0x000fe200078e0205 */ + /*00c0*/ F2F.F16.F32 R6, R2; /* 0x0000000200067304 */ + /* 0x001e320000200800 */ + /*00d0*/ STG.E.U16.SYS [R4], R6; /* 0x0000000604007386 */ + /* 0x0011e2000010e500 */ + /*00e0*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + ........................................... + + + Function : _Z12wmma_exampleP6__halfS0_Pfiiiff + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ IMAD.U32 R1, RZ, RZ, c[0x0][0x28]; /* 0x00000a00ff017624 */ + /* 0x000fd000078e00ff */ + /*0020*/ IADD3 R1, R1, -0x8, RZ; /* 0xfffffff801017810 */ + /* 0x000fc80007ffe0ff */ + /*0030*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ; /* 0x0000080001027a10 */ + /* 0x000fca0007f1e0ff */ + /*0040*/ IMAD.X R0, RZ, RZ, c[0x0][0x24], P0; /* 0x00000900ff007624 */ + /* 0x000fd000000e06ff */ + /*0050*/ CS2R.32 R3, SR_CLOCKLO; /* 0x0000000000037805 */ + /* 0x000fd00000005000 */ + /*0060*/ I2F.U32.RP R7, 0x20; /* 0x0000002000077906 */ + /* 0x000e240000209000 */ + /*0070*/ MUFU.RCP R7, R7; /* 0x0000000700077308 */ + /* 0x001e220000001000 */ + /*0080*/ S2R R6, SR_CTAID.X; /* 0x0000000000067919 */ + /* 0x000e620000002500 */ + /*0090*/ S2R R9, SR_TID.X; /* 0x0000000000097919 */ + /* 0x000e620000002100 */ + /*00a0*/ IADD3 R8, R7, 0xffffffe, RZ; /* 0x0ffffffe07087810 */ + /* 0x001fcc0007ffe0ff */ + /*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R8; /* 0x0000000800057305 */ + /* 0x0000a2000021f000 */ + /*00c0*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*00d0*/ IMAD R6, R6, c[0x0][0x0], R9; /* 0x0000000006067a24 */ + /* 0x002fe400078e0209 */ + /*00e0*/ IMAD.U32 R10, R5, -0x20, RZ; /* 0xffffffe0050a7824 */ + /* 0x004fc800078e00ff */ + /*00f0*/ IMAD.WIDE.U32 R4, R5, R10, R4; /* 0x0000000a05047225 */ + /* 0x000fd000078e0004 */ + /*0100*/ IMAD.WIDE.U32 R4, R5, R6, RZ; /* 0x0000000605047225 */ + /* 0x000fcc00078e00ff */ + /*0110*/ IMAD R4, RZ, RZ, -R5; /* 0x000000ffff047224 */ + /* 0x000fc800078e0a05 */ + /*0120*/ IMAD R6, R4, 0x20, R6; /* 0x0000002004067824 */ + /* 0x000fca00078e0206 */ + /*0130*/ ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x040fe20003f060f0 */ + /*0140*/ S2R R28, SR_CTAID.Y; /* 0x00000000001c7919 */ + /* 0x000e220000002600 */ + /*0150*/ S2R R7, SR_TID.Y; /* 0x0000000000077919 */ + /* 0x000e340000002200 */ + /*0160*/ @P0 IADD3 R6, R6, -0x20, RZ; /* 0xffffffe006060810 */ + /* 0x000fc80007ffe0ff */ + /*0170*/ ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x000fe40003f260f0 */ + /*0180*/ @P0 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105050810 */ + /* 0x000fe40007ffe0ff */ + /*0190*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT; /* 0x00006000ff007a0c */ + /* 0x000fd00003f012f0 */ + /*01a0*/ @P1 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105051810 */ + /* 0x000fe20007ffe0ff */ + /*01b0*/ IMAD R28, R28, c[0x0][0x4], R7; /* 0x000001001c1c7a24 */ + /* 0x001fc600078e0207 */ + /*01c0*/ SHF.L.U32 R29, R5, 0x4, RZ; /* 0x00000004051d7819 */ + /* 0x000fe200000006ff */ + /*01d0*/ IMAD.U32 R28, R28, 0x10, RZ; /* 0x000000101c1c7824 */ + /* 0x000fc600078e00ff */ + /*01e0*/ ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT; /* 0x00005e001d007a0c */ + /* 0x000fc800007012f0 */ + /*01f0*/ ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT; /* 0x00005f001c007a0c */ + /* 0x000fe200007012f0 */ + /*0200*/ BSSY B0, 0x5b0; /* 0x000003a000007945 */ + /* 0x000fe20003800000 */ + /*0210*/ IMAD.U32 R7, RZ, RZ, RZ; /* 0x000000ffff077224 */ + /* 0x000fe200078e00ff */ + /*0220*/ MOV R11, RZ; /* 0x000000ff000b7202 */ + /* 0x000fe20000000f00 */ + /*0230*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe400078e00ff */ + /*0240*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0250*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*0260*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fc400078e00ff */ + /*0270*/ IMAD.U32 R9, RZ, RZ, RZ; /* 0x000000ffff097224 */ + /* 0x000fe400078e00ff */ + /*0280*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0290*/ @!P0 BRA 0x5a0; /* 0x0000030000008947 */ + /* 0x000fee0003800000 */ + /*02a0*/ S2R R6, SR_LANEID; /* 0x0000000000067919 */ + /* 0x000e220000000000 */ + /*02b0*/ IMAD.U32 R10, RZ, RZ, 0x2; /* 0x00000002ff0a7424 */ + /* 0x000fc800078e00ff */ + /*02c0*/ IMAD.WIDE R16, R29, R10, c[0x0][0x160]; /* 0x000058001d107625 */ + /* 0x000fe200078e020a */ + /*02d0*/ SHF.R.U32.HI R4, RZ, 0x2, R6; /* 0x00000002ff047819 */ + /* 0x001fc80000011606 */ + /*02e0*/ LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT; /* 0x0000000304057812 */ + /* 0x000fe400078ec0ff */ + /*02f0*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT; /* 0x0000000306047812 */ + /* 0x000fe400078ec0ff */ + /*0300*/ LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT; /* 0x0000000105077812 */ + /* 0x000fe400078ec0ff */ + /*0310*/ SHF.R.U32.HI R6, RZ, 0x4, R6; /* 0x00000004ff067819 */ + /* 0x000fe40000011606 */ + /*0320*/ SHF.R.U32.HI R5, RZ, 0x1, R5; /* 0x00000001ff057819 */ + /* 0x000fe20000011605 */ + /*0330*/ IMAD R7, R7, 0x8, R4; /* 0x0000000807077824 */ + /* 0x000fe200078e0204 */ + /*0340*/ LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT; /* 0x0000000106067812 */ + /* 0x000fc400078ec0ff */ + /*0350*/ LEA R4, R5, R4, 0x3; /* 0x0000000405047211 */ + /* 0x000fe200078e18ff */ + /*0360*/ IMAD.WIDE R12, R28, R10, c[0x0][0x168]; /* 0x00005a001c0c7625 */ + /* 0x000fe400078e020a */ + /*0370*/ IMAD R7, R6.reuse, 0x4, R7; /* 0x0000000406077824 */ + /* 0x040fe400078e0207 */ + /*0380*/ IMAD R4, R6, 0x4, R4; /* 0x0000000406047824 */ + /* 0x000fe400078e0204 */ + /*0390*/ IMAD.U32 R7, R7, 0x2, RZ; /* 0x0000000207077824 */ + /* 0x000fe400078e00ff */ + /*03a0*/ IMAD.U32 R5, R4, 0x2, RZ; /* 0x0000000204057824 */ + /* 0x000fe400078e00ff */ + /*03b0*/ IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16; /* 0x00005e0007107a25 */ + /* 0x000fc400078e0010 */ + /*03c0*/ IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12; /* 0x00006000050c7a25 */ + /* 0x000fd000078e000c */ + /*03d0*/ LD.E.128.SYS R24, [R16]; /* 0x0000000010187980 */ + /* 0x000064000010ed00 */ + /*03e0*/ LD.E.128.SYS R20, [R12]; /* 0x000000000c147980 */ + /* 0x000462000010ed00 */ + /*03f0*/ LD.E.128.SYS R16, [R16+0x10]; /* 0x0000001010107980 */ + /* 0x001e22000010ed00 */ + /*0400*/ LD.E.128.SYS R12, [R12+0x10]; /* 0x000000100c0c7980 */ + /* 0x004e22000010ed00 */ + /*0410*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0420*/ MOV R9, RZ; /* 0x000000ff00097202 */ + /* 0x000fe20000000f00 */ + /*0430*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fe400078e00ff */ + /*0440*/ IMAD.U32 R11, RZ, RZ, RZ; /* 0x000000ffff0b7224 */ + /* 0x000fe200078e00ff */ + /*0450*/ MOV R7, RZ; /* 0x000000ff00077202 */ + /* 0x000fe20000000f00 */ + /*0460*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fc400078e00ff */ + /*0470*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0480*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe200078e00ff */ + /*0490*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*04a0*/ HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8; /* 0x0000001418087236 */ + /* 0x0c22640000005408 */ + /*04b0*/ HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10; /* 0x00000014180a7236 */ + /* 0x0c04a4000000d40a */ + /*04c0*/ HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4; /* 0x0000001418047236 */ + /* 0x0c06e40000015404 */ + /*04d0*/ HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6; /* 0x0000001418067236 */ + /* 0x000928000001d406 */ + /*04e0*/ HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8; /* 0x000000161a087236 */ + /* 0x0c20240000005408 */ + /*04f0*/ HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10; /* 0x000000161a0a7236 */ + /* 0x0c4264000000d40a */ + /*0500*/ HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4; /* 0x000000161a047236 */ + /* 0x0c84a40000015404 */ + /*0510*/ HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6; /* 0x000000161a067236 */ + /* 0x0106e8000001d406 */ + /*0520*/ HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8; /* 0x0000000c10087236 */ + /* 0x0c10240000005408 */ + /*0530*/ HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10; /* 0x0000000c100a7236 */ + /* 0x0c2264000000d40a */ + /*0540*/ HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4; /* 0x0000000c10047236 */ + /* 0x0c44a40000015404 */ + /*0550*/ HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6; /* 0x0000000c10067236 */ + /* 0x0086e8000001d406 */ + /*0560*/ HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8; /* 0x0000000e12087236 */ + /* 0x0c10240000005408 */ + /*0570*/ HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10; /* 0x0000000e120a7236 */ + /* 0x0c2024000000d40a */ + /*0580*/ HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4; /* 0x0000000e12047236 */ + /* 0x0c40240000015404 */ + /*0590*/ HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6; /* 0x0000000e12067236 */ + /* 0x008034000001d406 */ + /*05a0*/ BSYNC B0; /* 0x0000000000007941 */ + /* 0x001fea0003800000 */ + /*05b0*/ S2R R12, SR_LANEID; /* 0x00000000000c7919 */ + /* 0x000e220000000000 */ + /*05c0*/ IMAD R28, R28, c[0x0][0x178], RZ; /* 0x00005e001c1c7a24 */ + /* 0x000fe200078e02ff */ + /*05d0*/ SHF.R.U32.HI R14, RZ, 0x4, R12; /* 0x00000004ff0e7819 */ + /* 0x001fc4000001160c */ + /*05e0*/ SHF.R.U32.HI R13, RZ, 0x2, R12; /* 0x00000002ff0d7819 */ + /* 0x000fe4000001160c */ + /*05f0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT; /* 0x000000030c0c7812 */ + /* 0x000fe400078ec0ff */ + /*0600*/ LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT; /* 0x000000010e0e7812 */ + /* 0x000fe400078ec0ff */ + /*0610*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT; /* 0x000000030d0d7812 */ + /* 0x000fc600078ec0ff */ + /*0620*/ IMAD R12, R14, 0x4, R12; /* 0x000000040e0c7824 */ + /* 0x000fe200078e020c */ + /*0630*/ LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT; /* 0x000000010d0f7812 */ + /* 0x000fe400078ec0ff */ + /*0640*/ SHF.R.U32.HI R16, RZ, 0x1, R13; /* 0x00000001ff107819 */ + /* 0x000fe4000001160d */ + /*0650*/ LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT; /* 0x000000050c0d7812 */ + /* 0x040fe400078ec0ff */ + /*0660*/ LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT; /* 0x000000020c0e7812 */ + /* 0x000fc600078ec0ff */ + /*0670*/ IMAD R12, R15, 0x8, R13; /* 0x000000080f0c7824 */ + /* 0x000fe200078e020d */ + /*0680*/ SHF.R.S32.HI R15, RZ, 0x1f, R29; /* 0x0000001fff0f7819 */ + /* 0x000fe2000001141d */ + /*0690*/ IMAD R14, R16, 0x8, R14; /* 0x00000008100e7824 */ + /* 0x000fe200078e020e */ + /*06a0*/ IADD3 R17, P0, R29, R28, RZ; /* 0x0000001c1d117210 */ + /* 0x000fe20007f1e0ff */ + /*06b0*/ IMAD.U32 R13, RZ, RZ, RZ; /* 0x000000ffff0d7224 */ + /* 0x000fc600078e00ff */ + /*06c0*/ LEA.HI.X.SX32 R15, R28, R15, 0x1, P0; /* 0x0000000f1c0f7211 */ + /* 0x000fe200000f0eff */ + /*06d0*/ IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12; /* 0x00005e000e0c7a25 */ + /* 0x000fe200078e000c */ + /*06e0*/ LEA R14, P0, R17, c[0x0][0x170], 0x2; /* 0x00005c00110e7a11 */ + /* 0x000fe200078010ff */ + /*06f0*/ IMAD.U32 R18, RZ, RZ, c[0x0][0x178]; /* 0x00005e00ff127624 */ + /* 0x000fc600078e00ff */ + /*0700*/ LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0; /* 0x00005d0011117a11 */ + /* 0x000fe400000f140f */ + /*0710*/ LEA R16, P0, R12, R14, 0x2; /* 0x0000000e0c107211 */ + /* 0x000fe400078010ff */ + /*0720*/ SHF.L.U32 R14, R18, 0x2, RZ; /* 0x00000002120e7819 */ + /* 0x000fe400000006ff */ + /*0730*/ SHF.R.U32.HI R15, RZ, 0x1e, R18; /* 0x0000001eff0f7819 */ + /* 0x000fe40000011612 */ + /*0740*/ LEA.HI.X R13, R12, R17, R13, 0x2, P0; /* 0x000000110c0d7211 */ + /* 0x000fe400000f140d */ + /*0750*/ LEA R18, P1, R14, R16, 0x2; /* 0x000000100e127211 */ + /* 0x000fc400078210ff */ + /*0760*/ IADD3 R17, P0, R14.reuse, R16, RZ; /* 0x000000100e117210 */ + /* 0x040fe40007f1e0ff */ + /*0770*/ LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1; /* 0x0000000d0e137211 */ + /* 0x040fe400008f140f */ + /*0780*/ IADD3 R21, P1, R14, R18, RZ; /* 0x000000120e157210 */ + /* 0x000fe20007f3e0ff */ + /*0790*/ IMAD.X R20, R15.reuse, 0x1, R13, P0; /* 0x000000010f147824 */ + /* 0x040fe400000e060d */ + /*07a0*/ IMAD.U32 R12, RZ, RZ, R16; /* 0x000000ffff0c7224 */ + /* 0x000fe400078e0010 */ + /*07b0*/ IMAD.X R22, R15, 0x1, R19, P1; /* 0x000000010f167824 */ + /* 0x000fe400008e0613 */ + /*07c0*/ IMAD.U32 R14, RZ, RZ, R17; /* 0x000000ffff0e7224 */ + /* 0x000fc400078e0011 */ + /*07d0*/ IMAD.U32 R15, RZ, RZ, R20; /* 0x000000ffff0f7224 */ + /* 0x000fe200078e0014 */ + /*07e0*/ MOV R16, R21; /* 0x0000001500107202 */ + /* 0x000fe20000000f00 */ + /*07f0*/ IMAD.U32 R17, RZ, RZ, R22; /* 0x000000ffff117224 */ + /* 0x000fe200078e0016 */ + /*0800*/ ST.E.SYS [R12], R8; /* 0x000000000c007385 */ + /* 0x0001e2000010e908 */ + /*0810*/ ST.E.SYS [R12+0x8], R10; /* 0x000000080c007385 */ + /* 0x0003e8000010e90a */ + /*0820*/ ST.E.SYS [R14], R9; /* 0x000000000e007385 */ + /* 0x0003e2000010e909 */ + /*0830*/ ST.E.SYS [R14+0x8], R11; /* 0x000000080e007385 */ + /* 0x0003e2000010e90b */ + /*0840*/ ST.E.SYS [R18], R4; /* 0x0000000012007385 */ + /* 0x0003e2000010e904 */ + /*0850*/ ST.E.SYS [R18+0x8], R6; /* 0x0000000812007385 */ + /* 0x0003e2000010e906 */ + /*0860*/ ST.E.SYS [R16], R5; /* 0x0000000010007385 */ + /* 0x0003e2000010e905 */ + /*0870*/ ST.E.SYS [R16+0x8], R7; /* 0x0000000810007385 */ + /* 0x0003e2000010e907 */ + /*0880*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*0890*/ IADD3 R8, R2, -c[0x0][0x20], RZ; /* 0x8000080002087a10 */ + /* 0x001fd00007ffe0ff */ + /*08a0*/ CS2R.32 R4, SR_CLOCKLO; /* 0x0000000000047805 */ + /* 0x002fd00000005000 */ + /*08b0*/ IMAD R3, R4, 0x1, -R3; /* 0x0000000104037824 */ + /* 0x000fd000078e0a03 */ + /*08c0*/ STL [R8], R3; /* 0x0000000308007387 */ + /* 0x0001e20000100800 */ + /*08d0*/ IMAD.U32 R6, RZ, RZ, R2; /* 0x000000ffff067224 */ + /* 0x000fe200078e0002 */ + /*08e0*/ MOV R4, 0x0; /* 0x0000000000047802 */ + /* 0x000fe20000000f00 */ + /*08f0*/ IMAD.U32 R7, RZ, RZ, R0; /* 0x000000ffff077224 */ + /* 0x000fe200078e0000 */ + /*0900*/ MOV R5, 0x0; /* 0x0000000000057802 */ + /* 0x000fe40000000f00 */ + /*0910*/ MOV R20, 0x0; /* 0x0000000000147802 */ + /* 0x000fe40000000f00 */ + /*0920*/ MOV R21, 0x0; /* 0x0000000000157802 */ + /* 0x000fd00000000f00 */ + /*0930*/ CALL.ABS.NOINC 0x0; /* 0x0000000000007943 */ + /* 0x001fea0003c00000 */ + /*0940*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*0950*/ BRA 0x950; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + /*0960*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + /*0970*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + ............................................. + + + diff --git a/cuda-kernels/_cuobjdump_complete_output_EIGzTK b/cuda-kernels/_cuobjdump_complete_output_EIGzTK new file mode 100644 index 0000000..36999c0 --- /dev/null +++ b/cuda-kernels/_cuobjdump_complete_output_EIGzTK @@ -0,0 +1,1055 @@ + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 32 0 1 STRTAB 0 0 0 .shstrtab + 2 72 32 0 1 STRTAB 0 0 0 .strtab + 3 a8 18 18 8 SYMTAB 0 2 0 .symtab + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + + code for sm_70 + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = cuda +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 21b 0 1 STRTAB 0 0 0 .shstrtab + 2 25b 273 0 1 STRTAB 0 0 0 .strtab + 3 4d0 108 18 8 SYMTAB 0 2 7 .symtab + 4 5d8 e0 0 1 PROGBITS 0 0 0 .debug_frame + 5 6b8 48 0 4 CUDA_INFO 0 3 0 .nv.info + 6 700 50 0 4 CUDA_INFO 0 3 d .nv.info._Z17convertFp32ToFp16P6__halfPfi + 7 750 ac 0 4 CUDA_INFO 0 3 e .nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + 8 800 30 10 8 REL 0 3 e .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff + 9 830 30 18 8 RELA 0 3 e .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff + a 860 20 10 8 REL 0 3 4 .rel.debug_frame + b 880 174 0 4 PROGBITS 2 0 d .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + c 9f4 18c 0 4 PROGBITS 2 0 e .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + d b80 100 0 80 PROGBITS 6 3 9000008 .text._Z17convertFp32ToFp16P6__halfPfi + e c80 980 0 80 PROGBITS 6 3 20000009 .text._Z12wmma_exampleP6__halfS0_Pfiiiff + f 1600 9 0 10 PROGBITS 3 0 0 .nv.global.init + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + 1 0 0 3 0 d .text._Z17convertFp32ToFp16P6__halfPfi + 2 0 0 3 0 f .nv.global.init + 3 0 9 1 0 f $str + 4 0 0 3 0 b .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + 5 0 0 3 0 e .text._Z12wmma_exampleP6__halfS0_Pfiiiff + 6 0 0 3 0 c .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + 7 0 0 3 0 4 .debug_frame + 8 0 256 12 10 d _Z17convertFp32ToFp16P6__halfPfi + 9 0 2432 12 10 e _Z12wmma_exampleP6__halfS0_Pfiiiff + 10 0 0 12 0 0 vprintf + + +.nv.constant0._Z17convertFp32ToFp16P6__halfPfi +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 + + + +.nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 + + +.nv.global.init +0x636f6c63 0x64253d6b 0 + + +.nv.info + <0x1> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x9 0x0 + <0x2> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) min stack size: 0x8 + <0x3> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) frame size: 0x8 + <0x4> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x8 0x0 + <0x5> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) min stack size: 0x0 + <0x6> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) frame size: 0x0 + + +.nv.info._Z17convertFp32ToFp16P6__halfPfi + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x4 0x140160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x14 + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x7> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x60 0xe0 + + +.nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x6 0x2c0160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x2c + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x7 Offset : 0x28 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x6 Offset : 0x24 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x5 Offset : 0x20 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x4 Offset : 0x1c Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x7> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x3 Offset : 0x18 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x8> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x9> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x10> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x11> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x12> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x940 + <0x13> + Attribute: EIATTR_EXTERNS + Format: EIFMT_SVAL + Value: externs: vprintf(0xa) + <0x14> + Attribute: EIATTR_CRS_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x0 + + +.text._Z17convertFp32ToFp16P6__halfPfi +bar = 0 reg = 9 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0x00017a02 0x00000a00 0x00000f00 0x000fd000 +0x00047919 0x00000000 0x00002500 0x000e2200 +0x00027919 0x00000000 0x00002100 0x000e2400 +0x04047a24 0x00000000 0x078e0202 0x001fca00 +0x04007a0c 0x00005c00 0x03f062f0 0x000fd800 +0x0000094d 0x00000000 0x03800000 0x000fea00 +0x00027802 0x00000004 0x00000f00 0x000fca00 +0x04027625 0x00005a00 0x078e0202 0x000fd400 +0x02027381 0x00000000 0x001ee900 0x000e2200 +0x00057802 0x00000002 0x00000f00 0x000fca00 +0x04047625 0x00005800 0x078e0205 0x000fe200 +0x00067304 0x00000002 0x00200800 0x001e3200 +0x04007386 0x00000006 0x0010e500 0x0011e200 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 + + + +.text._Z12wmma_exampleP6__halfS0_Pfiiiff +bar = 0 reg = 32 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0xff017624 0x00000a00 0x078e00ff 0x000fd000 +0x01017810 0xfffffff8 0x07ffe0ff 0x000fc800 +0x01027a10 0x00000800 0x07f1e0ff 0x000fca00 +0xff007624 0x00000900 0x000e06ff 0x000fd000 +0x00037805 0x00000000 0x00005000 0x000fd000 +0x00077906 0x00000020 0x00209000 0x000e2400 +0x00077308 0x00000007 0x00001000 0x001e2200 +0x00067919 0x00000000 0x00002500 0x000e6200 +0x00097919 0x00000000 0x00002100 0x000e6200 +0x07087810 0x0ffffffe 0x07ffe0ff 0x001fcc00 +0x00057305 0x00000008 0x0021f000 0x0000a200 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0x06067a24 0x00000000 0x078e0209 0x002fe400 +0x050a7824 0xffffffe0 0x078e00ff 0x004fc800 +0x05047225 0x0000000a 0x078e0004 0x000fd000 +0x05047225 0x00000006 0x078e00ff 0x000fcc00 +0xff047224 0x000000ff 0x078e0a05 0x000fc800 +0x04067824 0x00000020 0x078e0206 0x000fca00 +0x0600780c 0x00000020 0x03f060f0 0x040fe200 +0x001c7919 0x00000000 0x00002600 0x000e2200 +0x00077919 0x00000000 0x00002200 0x000e3400 +0x06060810 0xffffffe0 0x07ffe0ff 0x000fc800 +0x0600780c 0x00000020 0x03f260f0 0x000fe400 +0x05050810 0x00000001 0x07ffe0ff 0x000fe400 +0xff007a0c 0x00006000 0x03f012f0 0x000fd000 +0x05051810 0x00000001 0x07ffe0ff 0x000fe200 +0x1c1c7a24 0x00000100 0x078e0207 0x001fc600 +0x051d7819 0x00000004 0x000006ff 0x000fe200 +0x1c1c7824 0x00000010 0x078e00ff 0x000fc600 +0x1d007a0c 0x00005e00 0x007012f0 0x000fc800 +0x1c007a0c 0x00005f00 0x007012f0 0x000fe200 +0x00007945 0x000003a0 0x03800000 0x000fe200 +0xff077224 0x000000ff 0x078e00ff 0x000fe200 +0x000b7202 0x000000ff 0x00000f00 0x000fe200 +0xff067224 0x000000ff 0x078e00ff 0x000fe400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0xff0a7224 0x000000ff 0x078e00ff 0x000fc400 +0xff097224 0x000000ff 0x078e00ff 0x000fe400 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00008947 0x00000300 0x03800000 0x000fee00 +0x00067919 0x00000000 0x00000000 0x000e2200 +0xff0a7424 0x00000002 0x078e00ff 0x000fc800 +0x1d107625 0x00005800 0x078e020a 0x000fe200 +0xff047819 0x00000002 0x00011606 0x001fc800 +0x04057812 0x00000003 0x078ec0ff 0x000fe400 +0x06047812 0x00000003 0x078ec0ff 0x000fe400 +0x05077812 0x00000001 0x078ec0ff 0x000fe400 +0xff067819 0x00000004 0x00011606 0x000fe400 +0xff057819 0x00000001 0x00011605 0x000fe200 +0x07077824 0x00000008 0x078e0204 0x000fe200 +0x06067812 0x00000001 0x078ec0ff 0x000fc400 +0x05047211 0x00000004 0x078e18ff 0x000fe200 +0x1c0c7625 0x00005a00 0x078e020a 0x000fe400 +0x06077824 0x00000004 0x078e0207 0x040fe400 +0x06047824 0x00000004 0x078e0204 0x000fe400 +0x07077824 0x00000002 0x078e00ff 0x000fe400 +0x04057824 0x00000002 0x078e00ff 0x000fe400 +0x07107a25 0x00005e00 0x078e0010 0x000fc400 +0x050c7a25 0x00006000 0x078e000c 0x000fd000 +0x10187980 0x00000000 0x0010ed00 0x00006400 +0x0c147980 0x00000000 0x0010ed00 0x00046200 +0x10107980 0x00000010 0x0010ed00 0x001e2200 +0x0c0c7980 0x00000010 0x0010ed00 0x004e2200 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00097202 0x000000ff 0x00000f00 0x000fe200 +0xff0a7224 0x000000ff 0x078e00ff 0x000fe400 +0xff0b7224 0x000000ff 0x078e00ff 0x000fe200 +0x00077202 0x000000ff 0x00000f00 0x000fe200 +0xff047224 0x000000ff 0x078e00ff 0x000fc400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff067224 0x000000ff 0x078e00ff 0x000fe200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x18087236 0x00000014 0x00005408 0x0c226400 +0x180a7236 0x00000014 0x0000d40a 0x0c04a400 +0x18047236 0x00000014 0x00015404 0x0c06e400 +0x18067236 0x00000014 0x0001d406 0x00092800 +0x1a087236 0x00000016 0x00005408 0x0c202400 +0x1a0a7236 0x00000016 0x0000d40a 0x0c426400 +0x1a047236 0x00000016 0x00015404 0x0c84a400 +0x1a067236 0x00000016 0x0001d406 0x0106e800 +0x10087236 0x0000000c 0x00005408 0x0c102400 +0x100a7236 0x0000000c 0x0000d40a 0x0c226400 +0x10047236 0x0000000c 0x00015404 0x0c44a400 +0x10067236 0x0000000c 0x0001d406 0x0086e800 +0x12087236 0x0000000e 0x00005408 0x0c102400 +0x120a7236 0x0000000e 0x0000d40a 0x0c202400 +0x12047236 0x0000000e 0x00015404 0x0c402400 +0x12067236 0x0000000e 0x0001d406 0x00803400 +0x00007941 0x00000000 0x03800000 0x001fea00 +0x000c7919 0x00000000 0x00000000 0x000e2200 +0x1c1c7a24 0x00005e00 0x078e02ff 0x000fe200 +0xff0e7819 0x00000004 0x0001160c 0x001fc400 +0xff0d7819 0x00000002 0x0001160c 0x000fe400 +0x0c0c7812 0x00000003 0x078ec0ff 0x000fe400 +0x0e0e7812 0x00000001 0x078ec0ff 0x000fe400 +0x0d0d7812 0x00000003 0x078ec0ff 0x000fc600 +0x0e0c7824 0x00000004 0x078e020c 0x000fe200 +0x0d0f7812 0x00000001 0x078ec0ff 0x000fe400 +0xff107819 0x00000001 0x0001160d 0x000fe400 +0x0c0d7812 0x00000005 0x078ec0ff 0x040fe400 +0x0c0e7812 0x00000002 0x078ec0ff 0x000fc600 +0x0f0c7824 0x00000008 0x078e020d 0x000fe200 +0xff0f7819 0x0000001f 0x0001141d 0x000fe200 +0x100e7824 0x00000008 0x078e020e 0x000fe200 +0x1d117210 0x0000001c 0x07f1e0ff 0x000fe200 +0xff0d7224 0x000000ff 0x078e00ff 0x000fc600 +0x1c0f7211 0x0000000f 0x000f0eff 0x000fe200 +0x0e0c7a25 0x00005e00 0x078e000c 0x000fe200 +0x110e7a11 0x00005c00 0x078010ff 0x000fe200 +0xff127624 0x00005e00 0x078e00ff 0x000fc600 +0x11117a11 0x00005d00 0x000f140f 0x000fe400 +0x0c107211 0x0000000e 0x078010ff 0x000fe400 +0x120e7819 0x00000002 0x000006ff 0x000fe400 +0xff0f7819 0x0000001e 0x00011612 0x000fe400 +0x0c0d7211 0x00000011 0x000f140d 0x000fe400 +0x0e127211 0x00000010 0x078210ff 0x000fc400 +0x0e117210 0x00000010 0x07f1e0ff 0x040fe400 +0x0e137211 0x0000000d 0x008f140f 0x040fe400 +0x0e157210 0x00000012 0x07f3e0ff 0x000fe200 +0x0f147824 0x00000001 0x000e060d 0x040fe400 +0xff0c7224 0x000000ff 0x078e0010 0x000fe400 +0x0f167824 0x00000001 0x008e0613 0x000fe400 +0xff0e7224 0x000000ff 0x078e0011 0x000fc400 +0xff0f7224 0x000000ff 0x078e0014 0x000fe200 +0x00107202 0x00000015 0x00000f00 0x000fe200 +0xff117224 0x000000ff 0x078e0016 0x000fe200 +0x0c007385 0x00000000 0x0010e908 0x0001e200 +0x0c007385 0x00000008 0x0010e90a 0x0003e800 +0x0e007385 0x00000000 0x0010e909 0x0003e200 +0x0e007385 0x00000008 0x0010e90b 0x0003e200 +0x12007385 0x00000000 0x0010e904 0x0003e200 +0x12007385 0x00000008 0x0010e906 0x0003e200 +0x10007385 0x00000000 0x0010e905 0x0003e200 +0x10007385 0x00000008 0x0010e907 0x0003e200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x02087a10 0x80000800 0x07ffe0ff 0x001fd000 +0x00047805 0x00000000 0x00005000 0x002fd000 +0x04037824 0x00000001 0x078e0a03 0x000fd000 +0x08007387 0x00000003 0x00100800 0x0001e200 +0xff067224 0x000000ff 0x078e0002 0x000fe200 +0x00047802 0x00000000 0x00000f00 0x000fe200 +0xff077224 0x000000ff 0x078e0000 0x000fe200 +0x00057802 0x00000000 0x00000f00 0x000fe400 +0x00147802 0x00000000 0x00000f00 0x000fe400 +0x00157802 0x00000000 0x00000f00 0x000fd000 +0x00007943 0x00000000 0x03c00000 0x001fea00 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 + + +.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff REL +2272 $str R_CUDA_ABS32_LO_32 +2304 $str R_CUDA_ABS32_HI_32 +2352 vprintf R_CUDA_ABS47_34 + +.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff RELA +2320 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_LO_32 2368 +2336 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_HI_32 2368 + +.section .debug_frame +decodeDebugFrame, frameBuf 0xffffffff, total_length 224 +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x100 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 0 + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_advance_loc4 delta 52 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x970 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 2 + DW_CFA_def_cfa register R1, offset 8 + DW_CFA_advance_loc4 delta 586 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +.section .rel.debug_frame REL +72 _Z17convertFp32ToFp16P6__halfPfi R_NV_64 +184 _Z12wmma_exampleP6__halfS0_Pfiiiff R_NV_64 + + code for sm_70 + Function : _Z17convertFp32ToFp16P6__halfPfi + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ MOV R1, c[0x0][0x28]; /* 0x00000a0000017a02 */ + /* 0x000fd00000000f00 */ + /*0020*/ S2R R4, SR_CTAID.X; /* 0x0000000000047919 */ + /* 0x000e220000002500 */ + /*0030*/ S2R R2, SR_TID.X; /* 0x0000000000027919 */ + /* 0x000e240000002100 */ + /*0040*/ IMAD R4, R4, c[0x0][0x0], R2; /* 0x0000000004047a24 */ + /* 0x001fca00078e0202 */ + /*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT; /* 0x00005c0004007a0c */ + /* 0x000fd80003f062f0 */ + /*0060*/ @P0 EXIT; /* 0x000000000000094d */ + /* 0x000fea0003800000 */ + /*0070*/ MOV R2, 0x4; /* 0x0000000400027802 */ + /* 0x000fca0000000f00 */ + /*0080*/ IMAD.WIDE R2, R4, R2, c[0x0][0x168]; /* 0x00005a0004027625 */ + /* 0x000fd400078e0202 */ + /*0090*/ LDG.E.SYS R2, [R2]; /* 0x0000000002027381 */ + /* 0x000e2200001ee900 */ + /*00a0*/ MOV R5, 0x2; /* 0x0000000200057802 */ + /* 0x000fca0000000f00 */ + /*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160]; /* 0x0000580004047625 */ + /* 0x000fe200078e0205 */ + /*00c0*/ F2F.F16.F32 R6, R2; /* 0x0000000200067304 */ + /* 0x001e320000200800 */ + /*00d0*/ STG.E.U16.SYS [R4], R6; /* 0x0000000604007386 */ + /* 0x0011e2000010e500 */ + /*00e0*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + ........................................... + + + Function : _Z12wmma_exampleP6__halfS0_Pfiiiff + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ IMAD.U32 R1, RZ, RZ, c[0x0][0x28]; /* 0x00000a00ff017624 */ + /* 0x000fd000078e00ff */ + /*0020*/ IADD3 R1, R1, -0x8, RZ; /* 0xfffffff801017810 */ + /* 0x000fc80007ffe0ff */ + /*0030*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ; /* 0x0000080001027a10 */ + /* 0x000fca0007f1e0ff */ + /*0040*/ IMAD.X R0, RZ, RZ, c[0x0][0x24], P0; /* 0x00000900ff007624 */ + /* 0x000fd000000e06ff */ + /*0050*/ CS2R.32 R3, SR_CLOCKLO; /* 0x0000000000037805 */ + /* 0x000fd00000005000 */ + /*0060*/ I2F.U32.RP R7, 0x20; /* 0x0000002000077906 */ + /* 0x000e240000209000 */ + /*0070*/ MUFU.RCP R7, R7; /* 0x0000000700077308 */ + /* 0x001e220000001000 */ + /*0080*/ S2R R6, SR_CTAID.X; /* 0x0000000000067919 */ + /* 0x000e620000002500 */ + /*0090*/ S2R R9, SR_TID.X; /* 0x0000000000097919 */ + /* 0x000e620000002100 */ + /*00a0*/ IADD3 R8, R7, 0xffffffe, RZ; /* 0x0ffffffe07087810 */ + /* 0x001fcc0007ffe0ff */ + /*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R8; /* 0x0000000800057305 */ + /* 0x0000a2000021f000 */ + /*00c0*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*00d0*/ IMAD R6, R6, c[0x0][0x0], R9; /* 0x0000000006067a24 */ + /* 0x002fe400078e0209 */ + /*00e0*/ IMAD.U32 R10, R5, -0x20, RZ; /* 0xffffffe0050a7824 */ + /* 0x004fc800078e00ff */ + /*00f0*/ IMAD.WIDE.U32 R4, R5, R10, R4; /* 0x0000000a05047225 */ + /* 0x000fd000078e0004 */ + /*0100*/ IMAD.WIDE.U32 R4, R5, R6, RZ; /* 0x0000000605047225 */ + /* 0x000fcc00078e00ff */ + /*0110*/ IMAD R4, RZ, RZ, -R5; /* 0x000000ffff047224 */ + /* 0x000fc800078e0a05 */ + /*0120*/ IMAD R6, R4, 0x20, R6; /* 0x0000002004067824 */ + /* 0x000fca00078e0206 */ + /*0130*/ ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x040fe20003f060f0 */ + /*0140*/ S2R R28, SR_CTAID.Y; /* 0x00000000001c7919 */ + /* 0x000e220000002600 */ + /*0150*/ S2R R7, SR_TID.Y; /* 0x0000000000077919 */ + /* 0x000e340000002200 */ + /*0160*/ @P0 IADD3 R6, R6, -0x20, RZ; /* 0xffffffe006060810 */ + /* 0x000fc80007ffe0ff */ + /*0170*/ ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x000fe40003f260f0 */ + /*0180*/ @P0 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105050810 */ + /* 0x000fe40007ffe0ff */ + /*0190*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT; /* 0x00006000ff007a0c */ + /* 0x000fd00003f012f0 */ + /*01a0*/ @P1 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105051810 */ + /* 0x000fe20007ffe0ff */ + /*01b0*/ IMAD R28, R28, c[0x0][0x4], R7; /* 0x000001001c1c7a24 */ + /* 0x001fc600078e0207 */ + /*01c0*/ SHF.L.U32 R29, R5, 0x4, RZ; /* 0x00000004051d7819 */ + /* 0x000fe200000006ff */ + /*01d0*/ IMAD.U32 R28, R28, 0x10, RZ; /* 0x000000101c1c7824 */ + /* 0x000fc600078e00ff */ + /*01e0*/ ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT; /* 0x00005e001d007a0c */ + /* 0x000fc800007012f0 */ + /*01f0*/ ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT; /* 0x00005f001c007a0c */ + /* 0x000fe200007012f0 */ + /*0200*/ BSSY B0, 0x5b0; /* 0x000003a000007945 */ + /* 0x000fe20003800000 */ + /*0210*/ IMAD.U32 R7, RZ, RZ, RZ; /* 0x000000ffff077224 */ + /* 0x000fe200078e00ff */ + /*0220*/ MOV R11, RZ; /* 0x000000ff000b7202 */ + /* 0x000fe20000000f00 */ + /*0230*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe400078e00ff */ + /*0240*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0250*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*0260*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fc400078e00ff */ + /*0270*/ IMAD.U32 R9, RZ, RZ, RZ; /* 0x000000ffff097224 */ + /* 0x000fe400078e00ff */ + /*0280*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0290*/ @!P0 BRA 0x5a0; /* 0x0000030000008947 */ + /* 0x000fee0003800000 */ + /*02a0*/ S2R R6, SR_LANEID; /* 0x0000000000067919 */ + /* 0x000e220000000000 */ + /*02b0*/ IMAD.U32 R10, RZ, RZ, 0x2; /* 0x00000002ff0a7424 */ + /* 0x000fc800078e00ff */ + /*02c0*/ IMAD.WIDE R16, R29, R10, c[0x0][0x160]; /* 0x000058001d107625 */ + /* 0x000fe200078e020a */ + /*02d0*/ SHF.R.U32.HI R4, RZ, 0x2, R6; /* 0x00000002ff047819 */ + /* 0x001fc80000011606 */ + /*02e0*/ LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT; /* 0x0000000304057812 */ + /* 0x000fe400078ec0ff */ + /*02f0*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT; /* 0x0000000306047812 */ + /* 0x000fe400078ec0ff */ + /*0300*/ LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT; /* 0x0000000105077812 */ + /* 0x000fe400078ec0ff */ + /*0310*/ SHF.R.U32.HI R6, RZ, 0x4, R6; /* 0x00000004ff067819 */ + /* 0x000fe40000011606 */ + /*0320*/ SHF.R.U32.HI R5, RZ, 0x1, R5; /* 0x00000001ff057819 */ + /* 0x000fe20000011605 */ + /*0330*/ IMAD R7, R7, 0x8, R4; /* 0x0000000807077824 */ + /* 0x000fe200078e0204 */ + /*0340*/ LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT; /* 0x0000000106067812 */ + /* 0x000fc400078ec0ff */ + /*0350*/ LEA R4, R5, R4, 0x3; /* 0x0000000405047211 */ + /* 0x000fe200078e18ff */ + /*0360*/ IMAD.WIDE R12, R28, R10, c[0x0][0x168]; /* 0x00005a001c0c7625 */ + /* 0x000fe400078e020a */ + /*0370*/ IMAD R7, R6.reuse, 0x4, R7; /* 0x0000000406077824 */ + /* 0x040fe400078e0207 */ + /*0380*/ IMAD R4, R6, 0x4, R4; /* 0x0000000406047824 */ + /* 0x000fe400078e0204 */ + /*0390*/ IMAD.U32 R7, R7, 0x2, RZ; /* 0x0000000207077824 */ + /* 0x000fe400078e00ff */ + /*03a0*/ IMAD.U32 R5, R4, 0x2, RZ; /* 0x0000000204057824 */ + /* 0x000fe400078e00ff */ + /*03b0*/ IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16; /* 0x00005e0007107a25 */ + /* 0x000fc400078e0010 */ + /*03c0*/ IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12; /* 0x00006000050c7a25 */ + /* 0x000fd000078e000c */ + /*03d0*/ LD.E.128.SYS R24, [R16]; /* 0x0000000010187980 */ + /* 0x000064000010ed00 */ + /*03e0*/ LD.E.128.SYS R20, [R12]; /* 0x000000000c147980 */ + /* 0x000462000010ed00 */ + /*03f0*/ LD.E.128.SYS R16, [R16+0x10]; /* 0x0000001010107980 */ + /* 0x001e22000010ed00 */ + /*0400*/ LD.E.128.SYS R12, [R12+0x10]; /* 0x000000100c0c7980 */ + /* 0x004e22000010ed00 */ + /*0410*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0420*/ MOV R9, RZ; /* 0x000000ff00097202 */ + /* 0x000fe20000000f00 */ + /*0430*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fe400078e00ff */ + /*0440*/ IMAD.U32 R11, RZ, RZ, RZ; /* 0x000000ffff0b7224 */ + /* 0x000fe200078e00ff */ + /*0450*/ MOV R7, RZ; /* 0x000000ff00077202 */ + /* 0x000fe20000000f00 */ + /*0460*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fc400078e00ff */ + /*0470*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0480*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe200078e00ff */ + /*0490*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*04a0*/ HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8; /* 0x0000001418087236 */ + /* 0x0c22640000005408 */ + /*04b0*/ HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10; /* 0x00000014180a7236 */ + /* 0x0c04a4000000d40a */ + /*04c0*/ HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4; /* 0x0000001418047236 */ + /* 0x0c06e40000015404 */ + /*04d0*/ HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6; /* 0x0000001418067236 */ + /* 0x000928000001d406 */ + /*04e0*/ HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8; /* 0x000000161a087236 */ + /* 0x0c20240000005408 */ + /*04f0*/ HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10; /* 0x000000161a0a7236 */ + /* 0x0c4264000000d40a */ + /*0500*/ HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4; /* 0x000000161a047236 */ + /* 0x0c84a40000015404 */ + /*0510*/ HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6; /* 0x000000161a067236 */ + /* 0x0106e8000001d406 */ + /*0520*/ HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8; /* 0x0000000c10087236 */ + /* 0x0c10240000005408 */ + /*0530*/ HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10; /* 0x0000000c100a7236 */ + /* 0x0c2264000000d40a */ + /*0540*/ HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4; /* 0x0000000c10047236 */ + /* 0x0c44a40000015404 */ + /*0550*/ HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6; /* 0x0000000c10067236 */ + /* 0x0086e8000001d406 */ + /*0560*/ HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8; /* 0x0000000e12087236 */ + /* 0x0c10240000005408 */ + /*0570*/ HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10; /* 0x0000000e120a7236 */ + /* 0x0c2024000000d40a */ + /*0580*/ HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4; /* 0x0000000e12047236 */ + /* 0x0c40240000015404 */ + /*0590*/ HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6; /* 0x0000000e12067236 */ + /* 0x008034000001d406 */ + /*05a0*/ BSYNC B0; /* 0x0000000000007941 */ + /* 0x001fea0003800000 */ + /*05b0*/ S2R R12, SR_LANEID; /* 0x00000000000c7919 */ + /* 0x000e220000000000 */ + /*05c0*/ IMAD R28, R28, c[0x0][0x178], RZ; /* 0x00005e001c1c7a24 */ + /* 0x000fe200078e02ff */ + /*05d0*/ SHF.R.U32.HI R14, RZ, 0x4, R12; /* 0x00000004ff0e7819 */ + /* 0x001fc4000001160c */ + /*05e0*/ SHF.R.U32.HI R13, RZ, 0x2, R12; /* 0x00000002ff0d7819 */ + /* 0x000fe4000001160c */ + /*05f0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT; /* 0x000000030c0c7812 */ + /* 0x000fe400078ec0ff */ + /*0600*/ LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT; /* 0x000000010e0e7812 */ + /* 0x000fe400078ec0ff */ + /*0610*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT; /* 0x000000030d0d7812 */ + /* 0x000fc600078ec0ff */ + /*0620*/ IMAD R12, R14, 0x4, R12; /* 0x000000040e0c7824 */ + /* 0x000fe200078e020c */ + /*0630*/ LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT; /* 0x000000010d0f7812 */ + /* 0x000fe400078ec0ff */ + /*0640*/ SHF.R.U32.HI R16, RZ, 0x1, R13; /* 0x00000001ff107819 */ + /* 0x000fe4000001160d */ + /*0650*/ LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT; /* 0x000000050c0d7812 */ + /* 0x040fe400078ec0ff */ + /*0660*/ LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT; /* 0x000000020c0e7812 */ + /* 0x000fc600078ec0ff */ + /*0670*/ IMAD R12, R15, 0x8, R13; /* 0x000000080f0c7824 */ + /* 0x000fe200078e020d */ + /*0680*/ SHF.R.S32.HI R15, RZ, 0x1f, R29; /* 0x0000001fff0f7819 */ + /* 0x000fe2000001141d */ + /*0690*/ IMAD R14, R16, 0x8, R14; /* 0x00000008100e7824 */ + /* 0x000fe200078e020e */ + /*06a0*/ IADD3 R17, P0, R29, R28, RZ; /* 0x0000001c1d117210 */ + /* 0x000fe20007f1e0ff */ + /*06b0*/ IMAD.U32 R13, RZ, RZ, RZ; /* 0x000000ffff0d7224 */ + /* 0x000fc600078e00ff */ + /*06c0*/ LEA.HI.X.SX32 R15, R28, R15, 0x1, P0; /* 0x0000000f1c0f7211 */ + /* 0x000fe200000f0eff */ + /*06d0*/ IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12; /* 0x00005e000e0c7a25 */ + /* 0x000fe200078e000c */ + /*06e0*/ LEA R14, P0, R17, c[0x0][0x170], 0x2; /* 0x00005c00110e7a11 */ + /* 0x000fe200078010ff */ + /*06f0*/ IMAD.U32 R18, RZ, RZ, c[0x0][0x178]; /* 0x00005e00ff127624 */ + /* 0x000fc600078e00ff */ + /*0700*/ LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0; /* 0x00005d0011117a11 */ + /* 0x000fe400000f140f */ + /*0710*/ LEA R16, P0, R12, R14, 0x2; /* 0x0000000e0c107211 */ + /* 0x000fe400078010ff */ + /*0720*/ SHF.L.U32 R14, R18, 0x2, RZ; /* 0x00000002120e7819 */ + /* 0x000fe400000006ff */ + /*0730*/ SHF.R.U32.HI R15, RZ, 0x1e, R18; /* 0x0000001eff0f7819 */ + /* 0x000fe40000011612 */ + /*0740*/ LEA.HI.X R13, R12, R17, R13, 0x2, P0; /* 0x000000110c0d7211 */ + /* 0x000fe400000f140d */ + /*0750*/ LEA R18, P1, R14, R16, 0x2; /* 0x000000100e127211 */ + /* 0x000fc400078210ff */ + /*0760*/ IADD3 R17, P0, R14.reuse, R16, RZ; /* 0x000000100e117210 */ + /* 0x040fe40007f1e0ff */ + /*0770*/ LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1; /* 0x0000000d0e137211 */ + /* 0x040fe400008f140f */ + /*0780*/ IADD3 R21, P1, R14, R18, RZ; /* 0x000000120e157210 */ + /* 0x000fe20007f3e0ff */ + /*0790*/ IMAD.X R20, R15.reuse, 0x1, R13, P0; /* 0x000000010f147824 */ + /* 0x040fe400000e060d */ + /*07a0*/ IMAD.U32 R12, RZ, RZ, R16; /* 0x000000ffff0c7224 */ + /* 0x000fe400078e0010 */ + /*07b0*/ IMAD.X R22, R15, 0x1, R19, P1; /* 0x000000010f167824 */ + /* 0x000fe400008e0613 */ + /*07c0*/ IMAD.U32 R14, RZ, RZ, R17; /* 0x000000ffff0e7224 */ + /* 0x000fc400078e0011 */ + /*07d0*/ IMAD.U32 R15, RZ, RZ, R20; /* 0x000000ffff0f7224 */ + /* 0x000fe200078e0014 */ + /*07e0*/ MOV R16, R21; /* 0x0000001500107202 */ + /* 0x000fe20000000f00 */ + /*07f0*/ IMAD.U32 R17, RZ, RZ, R22; /* 0x000000ffff117224 */ + /* 0x000fe200078e0016 */ + /*0800*/ ST.E.SYS [R12], R8; /* 0x000000000c007385 */ + /* 0x0001e2000010e908 */ + /*0810*/ ST.E.SYS [R12+0x8], R10; /* 0x000000080c007385 */ + /* 0x0003e8000010e90a */ + /*0820*/ ST.E.SYS [R14], R9; /* 0x000000000e007385 */ + /* 0x0003e2000010e909 */ + /*0830*/ ST.E.SYS [R14+0x8], R11; /* 0x000000080e007385 */ + /* 0x0003e2000010e90b */ + /*0840*/ ST.E.SYS [R18], R4; /* 0x0000000012007385 */ + /* 0x0003e2000010e904 */ + /*0850*/ ST.E.SYS [R18+0x8], R6; /* 0x0000000812007385 */ + /* 0x0003e2000010e906 */ + /*0860*/ ST.E.SYS [R16], R5; /* 0x0000000010007385 */ + /* 0x0003e2000010e905 */ + /*0870*/ ST.E.SYS [R16+0x8], R7; /* 0x0000000810007385 */ + /* 0x0003e2000010e907 */ + /*0880*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*0890*/ IADD3 R8, R2, -c[0x0][0x20], RZ; /* 0x8000080002087a10 */ + /* 0x001fd00007ffe0ff */ + /*08a0*/ CS2R.32 R4, SR_CLOCKLO; /* 0x0000000000047805 */ + /* 0x002fd00000005000 */ + /*08b0*/ IMAD R3, R4, 0x1, -R3; /* 0x0000000104037824 */ + /* 0x000fd000078e0a03 */ + /*08c0*/ STL [R8], R3; /* 0x0000000308007387 */ + /* 0x0001e20000100800 */ + /*08d0*/ IMAD.U32 R6, RZ, RZ, R2; /* 0x000000ffff067224 */ + /* 0x000fe200078e0002 */ + /*08e0*/ MOV R4, 0x0; /* 0x0000000000047802 */ + /* 0x000fe20000000f00 */ + /*08f0*/ IMAD.U32 R7, RZ, RZ, R0; /* 0x000000ffff077224 */ + /* 0x000fe200078e0000 */ + /*0900*/ MOV R5, 0x0; /* 0x0000000000057802 */ + /* 0x000fe40000000f00 */ + /*0910*/ MOV R20, 0x0; /* 0x0000000000147802 */ + /* 0x000fe40000000f00 */ + /*0920*/ MOV R21, 0x0; /* 0x0000000000157802 */ + /* 0x000fd00000000f00 */ + /*0930*/ CALL.ABS.NOINC 0x0; /* 0x0000000000007943 */ + /* 0x001fea0003c00000 */ + /*0940*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*0950*/ BRA 0x950; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + /*0960*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + /*0970*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + ............................................. + + + +Fatbin ptx code: +================ +arch = sm_70 +code version = [6,0] +producer = cuda +host = linux +compile_size = 64bit +compressed + + + + + + + + +.version 6.0 +.target sm_70 +.address_size 64 + + +.extern .func (.param .b32 func_retval0) vprintf +( +.param .b64 vprintf_param_0, +.param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ +.local .align 8 .b8 __local_depot0[8]; +.reg .b64 %SP; +.reg .b64 %SPL; +.reg .pred %p<6>; +.reg .f32 %f<34>; +.reg .b32 %r<38>; +.reg .b64 %rd<18>; + + +mov.u64 %rd17, __local_depot0; +cvta.local.u64 %SP, %rd17; +ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; +ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; +ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; +ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; +ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; +ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + + mov.u32 %r6, %clock; + + mov.u32 %r8, %ntid.x; +mov.u32 %r9, %ctaid.x; +mov.u32 %r10, %tid.x; +mad.lo.s32 %r11, %r8, %r9, %r10; +mov.u32 %r12, WARP_SZ; +div.u32 %r13, %r11, %r12; +mov.u32 %r14, %ntid.y; +mov.u32 %r15, %ctaid.y; +mov.u32 %r16, %tid.y; +mad.lo.s32 %r17, %r14, %r15, %r16; +shl.b32 %r2, %r13, 4; +shl.b32 %r3, %r17, 4; +setp.lt.s32 %p1, %r2, %r4; +setp.gt.s32 %p2, %r5, 0; +and.pred %p3, %p1, %p2; +setp.lt.s32 %p4, %r3, %r7; +and.pred %p5, %p3, %p4; +mov.f32 %f26, 0f00000000; +mov.f32 %f27, %f26; +mov.f32 %f28, %f26; +mov.f32 %f29, %f26; +mov.f32 %f30, %f26; +mov.f32 %f31, %f26; +mov.f32 %f32, %f26; +mov.f32 %f33, %f26; +@!%p5 bra BB0_2; +bra.uni BB0_1; + +BB0_1: +mul.wide.s32 %rd4, %r2, 2; +add.s64 %rd5, %rd1, %rd4; +wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; +mul.wide.s32 %rd6, %r3, 2; +add.s64 %rd7, %rd2, %rd6; +wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; +mov.f32 %f25, 0f00000000; +wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: +add.u64 %rd8, %SP, 0; +cvta.to.local.u64 %rd9, %rd8; +mul.lo.s32 %r35, %r3, %r4; +cvt.s64.s32 %rd10, %r35; +cvt.s64.s32 %rd11, %r2; +add.s64 %rd12, %rd10, %rd11; +shl.b64 %rd13, %rd12, 2; +add.s64 %rd14, %rd3, %rd13; +wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + + mov.u32 %r34, %clock; + + sub.s32 %r36, %r34, %r6; +st.local.u32 [%rd9], %r36; +mov.u64 %rd15, $str; +cvta.global.u64 %rd16, %rd15; + + { +.reg .b32 temp_param_reg; + + .param .b64 param0; +st.param.b64 [param0+0], %rd16; +.param .b64 param1; +st.param.b64 [param1+0], %rd8; +.param .b32 retval0; +call.uni (retval0), +vprintf, +( +param0, +param1 +); +ld.param.b32 %r37, [retval0+0]; + + + } + ret; +} + + +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, +.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ +.reg .pred %p<2>; +.reg .b16 %rs<2>; +.reg .f32 %f<2>; +.reg .b32 %r<6>; +.reg .b64 %rd<9>; + + +ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; +ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; +ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; +mov.u32 %r3, %ntid.x; +mov.u32 %r4, %ctaid.x; +mov.u32 %r5, %tid.x; +mad.lo.s32 %r1, %r4, %r3, %r5; +setp.ge.s32 %p1, %r1, %r2; +@%p1 bra BB1_2; + +cvta.to.global.u64 %rd3, %rd2; +mul.wide.s32 %rd4, %r1, 4; +add.s64 %rd5, %rd3, %rd4; +ld.global.f32 %f1, [%rd5]; + + { cvt.rn.f16.f32 %rs1, %f1;} + + + cvta.to.global.u64 %rd6, %rd1; +mul.wide.s32 %rd7, %r1, 2; +add.s64 %rd8, %rd6, %rd7; +st.global.u16 [%rd8], %rs1; + +BB1_2: +ret; +} + + diff --git a/cuda-kernels/_cuobjdump_complete_output_rndQyq b/cuda-kernels/_cuobjdump_complete_output_rndQyq new file mode 100644 index 0000000..36999c0 --- /dev/null +++ b/cuda-kernels/_cuobjdump_complete_output_rndQyq @@ -0,0 +1,1055 @@ + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 32 0 1 STRTAB 0 0 0 .shstrtab + 2 72 32 0 1 STRTAB 0 0 0 .strtab + 3 a8 18 18 8 SYMTAB 0 2 0 .symtab + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + + code for sm_70 + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = cuda +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 21b 0 1 STRTAB 0 0 0 .shstrtab + 2 25b 273 0 1 STRTAB 0 0 0 .strtab + 3 4d0 108 18 8 SYMTAB 0 2 7 .symtab + 4 5d8 e0 0 1 PROGBITS 0 0 0 .debug_frame + 5 6b8 48 0 4 CUDA_INFO 0 3 0 .nv.info + 6 700 50 0 4 CUDA_INFO 0 3 d .nv.info._Z17convertFp32ToFp16P6__halfPfi + 7 750 ac 0 4 CUDA_INFO 0 3 e .nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + 8 800 30 10 8 REL 0 3 e .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff + 9 830 30 18 8 RELA 0 3 e .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff + a 860 20 10 8 REL 0 3 4 .rel.debug_frame + b 880 174 0 4 PROGBITS 2 0 d .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + c 9f4 18c 0 4 PROGBITS 2 0 e .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + d b80 100 0 80 PROGBITS 6 3 9000008 .text._Z17convertFp32ToFp16P6__halfPfi + e c80 980 0 80 PROGBITS 6 3 20000009 .text._Z12wmma_exampleP6__halfS0_Pfiiiff + f 1600 9 0 10 PROGBITS 3 0 0 .nv.global.init + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + 1 0 0 3 0 d .text._Z17convertFp32ToFp16P6__halfPfi + 2 0 0 3 0 f .nv.global.init + 3 0 9 1 0 f $str + 4 0 0 3 0 b .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + 5 0 0 3 0 e .text._Z12wmma_exampleP6__halfS0_Pfiiiff + 6 0 0 3 0 c .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + 7 0 0 3 0 4 .debug_frame + 8 0 256 12 10 d _Z17convertFp32ToFp16P6__halfPfi + 9 0 2432 12 10 e _Z12wmma_exampleP6__halfS0_Pfiiiff + 10 0 0 12 0 0 vprintf + + +.nv.constant0._Z17convertFp32ToFp16P6__halfPfi +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 + + + +.nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 + + +.nv.global.init +0x636f6c63 0x64253d6b 0 + + +.nv.info + <0x1> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x9 0x0 + <0x2> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) min stack size: 0x8 + <0x3> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) frame size: 0x8 + <0x4> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x8 0x0 + <0x5> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) min stack size: 0x0 + <0x6> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) frame size: 0x0 + + +.nv.info._Z17convertFp32ToFp16P6__halfPfi + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x4 0x140160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x14 + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x7> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x60 0xe0 + + +.nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x6 0x2c0160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x2c + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x7 Offset : 0x28 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x6 Offset : 0x24 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x5 Offset : 0x20 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x4 Offset : 0x1c Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x7> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x3 Offset : 0x18 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x8> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x9> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x10> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x11> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x12> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x940 + <0x13> + Attribute: EIATTR_EXTERNS + Format: EIFMT_SVAL + Value: externs: vprintf(0xa) + <0x14> + Attribute: EIATTR_CRS_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x0 + + +.text._Z17convertFp32ToFp16P6__halfPfi +bar = 0 reg = 9 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0x00017a02 0x00000a00 0x00000f00 0x000fd000 +0x00047919 0x00000000 0x00002500 0x000e2200 +0x00027919 0x00000000 0x00002100 0x000e2400 +0x04047a24 0x00000000 0x078e0202 0x001fca00 +0x04007a0c 0x00005c00 0x03f062f0 0x000fd800 +0x0000094d 0x00000000 0x03800000 0x000fea00 +0x00027802 0x00000004 0x00000f00 0x000fca00 +0x04027625 0x00005a00 0x078e0202 0x000fd400 +0x02027381 0x00000000 0x001ee900 0x000e2200 +0x00057802 0x00000002 0x00000f00 0x000fca00 +0x04047625 0x00005800 0x078e0205 0x000fe200 +0x00067304 0x00000002 0x00200800 0x001e3200 +0x04007386 0x00000006 0x0010e500 0x0011e200 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 + + + +.text._Z12wmma_exampleP6__halfS0_Pfiiiff +bar = 0 reg = 32 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0xff017624 0x00000a00 0x078e00ff 0x000fd000 +0x01017810 0xfffffff8 0x07ffe0ff 0x000fc800 +0x01027a10 0x00000800 0x07f1e0ff 0x000fca00 +0xff007624 0x00000900 0x000e06ff 0x000fd000 +0x00037805 0x00000000 0x00005000 0x000fd000 +0x00077906 0x00000020 0x00209000 0x000e2400 +0x00077308 0x00000007 0x00001000 0x001e2200 +0x00067919 0x00000000 0x00002500 0x000e6200 +0x00097919 0x00000000 0x00002100 0x000e6200 +0x07087810 0x0ffffffe 0x07ffe0ff 0x001fcc00 +0x00057305 0x00000008 0x0021f000 0x0000a200 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0x06067a24 0x00000000 0x078e0209 0x002fe400 +0x050a7824 0xffffffe0 0x078e00ff 0x004fc800 +0x05047225 0x0000000a 0x078e0004 0x000fd000 +0x05047225 0x00000006 0x078e00ff 0x000fcc00 +0xff047224 0x000000ff 0x078e0a05 0x000fc800 +0x04067824 0x00000020 0x078e0206 0x000fca00 +0x0600780c 0x00000020 0x03f060f0 0x040fe200 +0x001c7919 0x00000000 0x00002600 0x000e2200 +0x00077919 0x00000000 0x00002200 0x000e3400 +0x06060810 0xffffffe0 0x07ffe0ff 0x000fc800 +0x0600780c 0x00000020 0x03f260f0 0x000fe400 +0x05050810 0x00000001 0x07ffe0ff 0x000fe400 +0xff007a0c 0x00006000 0x03f012f0 0x000fd000 +0x05051810 0x00000001 0x07ffe0ff 0x000fe200 +0x1c1c7a24 0x00000100 0x078e0207 0x001fc600 +0x051d7819 0x00000004 0x000006ff 0x000fe200 +0x1c1c7824 0x00000010 0x078e00ff 0x000fc600 +0x1d007a0c 0x00005e00 0x007012f0 0x000fc800 +0x1c007a0c 0x00005f00 0x007012f0 0x000fe200 +0x00007945 0x000003a0 0x03800000 0x000fe200 +0xff077224 0x000000ff 0x078e00ff 0x000fe200 +0x000b7202 0x000000ff 0x00000f00 0x000fe200 +0xff067224 0x000000ff 0x078e00ff 0x000fe400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0xff0a7224 0x000000ff 0x078e00ff 0x000fc400 +0xff097224 0x000000ff 0x078e00ff 0x000fe400 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00008947 0x00000300 0x03800000 0x000fee00 +0x00067919 0x00000000 0x00000000 0x000e2200 +0xff0a7424 0x00000002 0x078e00ff 0x000fc800 +0x1d107625 0x00005800 0x078e020a 0x000fe200 +0xff047819 0x00000002 0x00011606 0x001fc800 +0x04057812 0x00000003 0x078ec0ff 0x000fe400 +0x06047812 0x00000003 0x078ec0ff 0x000fe400 +0x05077812 0x00000001 0x078ec0ff 0x000fe400 +0xff067819 0x00000004 0x00011606 0x000fe400 +0xff057819 0x00000001 0x00011605 0x000fe200 +0x07077824 0x00000008 0x078e0204 0x000fe200 +0x06067812 0x00000001 0x078ec0ff 0x000fc400 +0x05047211 0x00000004 0x078e18ff 0x000fe200 +0x1c0c7625 0x00005a00 0x078e020a 0x000fe400 +0x06077824 0x00000004 0x078e0207 0x040fe400 +0x06047824 0x00000004 0x078e0204 0x000fe400 +0x07077824 0x00000002 0x078e00ff 0x000fe400 +0x04057824 0x00000002 0x078e00ff 0x000fe400 +0x07107a25 0x00005e00 0x078e0010 0x000fc400 +0x050c7a25 0x00006000 0x078e000c 0x000fd000 +0x10187980 0x00000000 0x0010ed00 0x00006400 +0x0c147980 0x00000000 0x0010ed00 0x00046200 +0x10107980 0x00000010 0x0010ed00 0x001e2200 +0x0c0c7980 0x00000010 0x0010ed00 0x004e2200 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00097202 0x000000ff 0x00000f00 0x000fe200 +0xff0a7224 0x000000ff 0x078e00ff 0x000fe400 +0xff0b7224 0x000000ff 0x078e00ff 0x000fe200 +0x00077202 0x000000ff 0x00000f00 0x000fe200 +0xff047224 0x000000ff 0x078e00ff 0x000fc400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff067224 0x000000ff 0x078e00ff 0x000fe200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x18087236 0x00000014 0x00005408 0x0c226400 +0x180a7236 0x00000014 0x0000d40a 0x0c04a400 +0x18047236 0x00000014 0x00015404 0x0c06e400 +0x18067236 0x00000014 0x0001d406 0x00092800 +0x1a087236 0x00000016 0x00005408 0x0c202400 +0x1a0a7236 0x00000016 0x0000d40a 0x0c426400 +0x1a047236 0x00000016 0x00015404 0x0c84a400 +0x1a067236 0x00000016 0x0001d406 0x0106e800 +0x10087236 0x0000000c 0x00005408 0x0c102400 +0x100a7236 0x0000000c 0x0000d40a 0x0c226400 +0x10047236 0x0000000c 0x00015404 0x0c44a400 +0x10067236 0x0000000c 0x0001d406 0x0086e800 +0x12087236 0x0000000e 0x00005408 0x0c102400 +0x120a7236 0x0000000e 0x0000d40a 0x0c202400 +0x12047236 0x0000000e 0x00015404 0x0c402400 +0x12067236 0x0000000e 0x0001d406 0x00803400 +0x00007941 0x00000000 0x03800000 0x001fea00 +0x000c7919 0x00000000 0x00000000 0x000e2200 +0x1c1c7a24 0x00005e00 0x078e02ff 0x000fe200 +0xff0e7819 0x00000004 0x0001160c 0x001fc400 +0xff0d7819 0x00000002 0x0001160c 0x000fe400 +0x0c0c7812 0x00000003 0x078ec0ff 0x000fe400 +0x0e0e7812 0x00000001 0x078ec0ff 0x000fe400 +0x0d0d7812 0x00000003 0x078ec0ff 0x000fc600 +0x0e0c7824 0x00000004 0x078e020c 0x000fe200 +0x0d0f7812 0x00000001 0x078ec0ff 0x000fe400 +0xff107819 0x00000001 0x0001160d 0x000fe400 +0x0c0d7812 0x00000005 0x078ec0ff 0x040fe400 +0x0c0e7812 0x00000002 0x078ec0ff 0x000fc600 +0x0f0c7824 0x00000008 0x078e020d 0x000fe200 +0xff0f7819 0x0000001f 0x0001141d 0x000fe200 +0x100e7824 0x00000008 0x078e020e 0x000fe200 +0x1d117210 0x0000001c 0x07f1e0ff 0x000fe200 +0xff0d7224 0x000000ff 0x078e00ff 0x000fc600 +0x1c0f7211 0x0000000f 0x000f0eff 0x000fe200 +0x0e0c7a25 0x00005e00 0x078e000c 0x000fe200 +0x110e7a11 0x00005c00 0x078010ff 0x000fe200 +0xff127624 0x00005e00 0x078e00ff 0x000fc600 +0x11117a11 0x00005d00 0x000f140f 0x000fe400 +0x0c107211 0x0000000e 0x078010ff 0x000fe400 +0x120e7819 0x00000002 0x000006ff 0x000fe400 +0xff0f7819 0x0000001e 0x00011612 0x000fe400 +0x0c0d7211 0x00000011 0x000f140d 0x000fe400 +0x0e127211 0x00000010 0x078210ff 0x000fc400 +0x0e117210 0x00000010 0x07f1e0ff 0x040fe400 +0x0e137211 0x0000000d 0x008f140f 0x040fe400 +0x0e157210 0x00000012 0x07f3e0ff 0x000fe200 +0x0f147824 0x00000001 0x000e060d 0x040fe400 +0xff0c7224 0x000000ff 0x078e0010 0x000fe400 +0x0f167824 0x00000001 0x008e0613 0x000fe400 +0xff0e7224 0x000000ff 0x078e0011 0x000fc400 +0xff0f7224 0x000000ff 0x078e0014 0x000fe200 +0x00107202 0x00000015 0x00000f00 0x000fe200 +0xff117224 0x000000ff 0x078e0016 0x000fe200 +0x0c007385 0x00000000 0x0010e908 0x0001e200 +0x0c007385 0x00000008 0x0010e90a 0x0003e800 +0x0e007385 0x00000000 0x0010e909 0x0003e200 +0x0e007385 0x00000008 0x0010e90b 0x0003e200 +0x12007385 0x00000000 0x0010e904 0x0003e200 +0x12007385 0x00000008 0x0010e906 0x0003e200 +0x10007385 0x00000000 0x0010e905 0x0003e200 +0x10007385 0x00000008 0x0010e907 0x0003e200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x02087a10 0x80000800 0x07ffe0ff 0x001fd000 +0x00047805 0x00000000 0x00005000 0x002fd000 +0x04037824 0x00000001 0x078e0a03 0x000fd000 +0x08007387 0x00000003 0x00100800 0x0001e200 +0xff067224 0x000000ff 0x078e0002 0x000fe200 +0x00047802 0x00000000 0x00000f00 0x000fe200 +0xff077224 0x000000ff 0x078e0000 0x000fe200 +0x00057802 0x00000000 0x00000f00 0x000fe400 +0x00147802 0x00000000 0x00000f00 0x000fe400 +0x00157802 0x00000000 0x00000f00 0x000fd000 +0x00007943 0x00000000 0x03c00000 0x001fea00 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 + + +.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff REL +2272 $str R_CUDA_ABS32_LO_32 +2304 $str R_CUDA_ABS32_HI_32 +2352 vprintf R_CUDA_ABS47_34 + +.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff RELA +2320 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_LO_32 2368 +2336 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_HI_32 2368 + +.section .debug_frame +decodeDebugFrame, frameBuf 0xffffffff, total_length 224 +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x100 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 0 + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_advance_loc4 delta 52 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x970 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 2 + DW_CFA_def_cfa register R1, offset 8 + DW_CFA_advance_loc4 delta 586 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +.section .rel.debug_frame REL +72 _Z17convertFp32ToFp16P6__halfPfi R_NV_64 +184 _Z12wmma_exampleP6__halfS0_Pfiiiff R_NV_64 + + code for sm_70 + Function : _Z17convertFp32ToFp16P6__halfPfi + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ MOV R1, c[0x0][0x28]; /* 0x00000a0000017a02 */ + /* 0x000fd00000000f00 */ + /*0020*/ S2R R4, SR_CTAID.X; /* 0x0000000000047919 */ + /* 0x000e220000002500 */ + /*0030*/ S2R R2, SR_TID.X; /* 0x0000000000027919 */ + /* 0x000e240000002100 */ + /*0040*/ IMAD R4, R4, c[0x0][0x0], R2; /* 0x0000000004047a24 */ + /* 0x001fca00078e0202 */ + /*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT; /* 0x00005c0004007a0c */ + /* 0x000fd80003f062f0 */ + /*0060*/ @P0 EXIT; /* 0x000000000000094d */ + /* 0x000fea0003800000 */ + /*0070*/ MOV R2, 0x4; /* 0x0000000400027802 */ + /* 0x000fca0000000f00 */ + /*0080*/ IMAD.WIDE R2, R4, R2, c[0x0][0x168]; /* 0x00005a0004027625 */ + /* 0x000fd400078e0202 */ + /*0090*/ LDG.E.SYS R2, [R2]; /* 0x0000000002027381 */ + /* 0x000e2200001ee900 */ + /*00a0*/ MOV R5, 0x2; /* 0x0000000200057802 */ + /* 0x000fca0000000f00 */ + /*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160]; /* 0x0000580004047625 */ + /* 0x000fe200078e0205 */ + /*00c0*/ F2F.F16.F32 R6, R2; /* 0x0000000200067304 */ + /* 0x001e320000200800 */ + /*00d0*/ STG.E.U16.SYS [R4], R6; /* 0x0000000604007386 */ + /* 0x0011e2000010e500 */ + /*00e0*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + ........................................... + + + Function : _Z12wmma_exampleP6__halfS0_Pfiiiff + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ IMAD.U32 R1, RZ, RZ, c[0x0][0x28]; /* 0x00000a00ff017624 */ + /* 0x000fd000078e00ff */ + /*0020*/ IADD3 R1, R1, -0x8, RZ; /* 0xfffffff801017810 */ + /* 0x000fc80007ffe0ff */ + /*0030*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ; /* 0x0000080001027a10 */ + /* 0x000fca0007f1e0ff */ + /*0040*/ IMAD.X R0, RZ, RZ, c[0x0][0x24], P0; /* 0x00000900ff007624 */ + /* 0x000fd000000e06ff */ + /*0050*/ CS2R.32 R3, SR_CLOCKLO; /* 0x0000000000037805 */ + /* 0x000fd00000005000 */ + /*0060*/ I2F.U32.RP R7, 0x20; /* 0x0000002000077906 */ + /* 0x000e240000209000 */ + /*0070*/ MUFU.RCP R7, R7; /* 0x0000000700077308 */ + /* 0x001e220000001000 */ + /*0080*/ S2R R6, SR_CTAID.X; /* 0x0000000000067919 */ + /* 0x000e620000002500 */ + /*0090*/ S2R R9, SR_TID.X; /* 0x0000000000097919 */ + /* 0x000e620000002100 */ + /*00a0*/ IADD3 R8, R7, 0xffffffe, RZ; /* 0x0ffffffe07087810 */ + /* 0x001fcc0007ffe0ff */ + /*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R8; /* 0x0000000800057305 */ + /* 0x0000a2000021f000 */ + /*00c0*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*00d0*/ IMAD R6, R6, c[0x0][0x0], R9; /* 0x0000000006067a24 */ + /* 0x002fe400078e0209 */ + /*00e0*/ IMAD.U32 R10, R5, -0x20, RZ; /* 0xffffffe0050a7824 */ + /* 0x004fc800078e00ff */ + /*00f0*/ IMAD.WIDE.U32 R4, R5, R10, R4; /* 0x0000000a05047225 */ + /* 0x000fd000078e0004 */ + /*0100*/ IMAD.WIDE.U32 R4, R5, R6, RZ; /* 0x0000000605047225 */ + /* 0x000fcc00078e00ff */ + /*0110*/ IMAD R4, RZ, RZ, -R5; /* 0x000000ffff047224 */ + /* 0x000fc800078e0a05 */ + /*0120*/ IMAD R6, R4, 0x20, R6; /* 0x0000002004067824 */ + /* 0x000fca00078e0206 */ + /*0130*/ ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x040fe20003f060f0 */ + /*0140*/ S2R R28, SR_CTAID.Y; /* 0x00000000001c7919 */ + /* 0x000e220000002600 */ + /*0150*/ S2R R7, SR_TID.Y; /* 0x0000000000077919 */ + /* 0x000e340000002200 */ + /*0160*/ @P0 IADD3 R6, R6, -0x20, RZ; /* 0xffffffe006060810 */ + /* 0x000fc80007ffe0ff */ + /*0170*/ ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x000fe40003f260f0 */ + /*0180*/ @P0 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105050810 */ + /* 0x000fe40007ffe0ff */ + /*0190*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT; /* 0x00006000ff007a0c */ + /* 0x000fd00003f012f0 */ + /*01a0*/ @P1 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105051810 */ + /* 0x000fe20007ffe0ff */ + /*01b0*/ IMAD R28, R28, c[0x0][0x4], R7; /* 0x000001001c1c7a24 */ + /* 0x001fc600078e0207 */ + /*01c0*/ SHF.L.U32 R29, R5, 0x4, RZ; /* 0x00000004051d7819 */ + /* 0x000fe200000006ff */ + /*01d0*/ IMAD.U32 R28, R28, 0x10, RZ; /* 0x000000101c1c7824 */ + /* 0x000fc600078e00ff */ + /*01e0*/ ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT; /* 0x00005e001d007a0c */ + /* 0x000fc800007012f0 */ + /*01f0*/ ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT; /* 0x00005f001c007a0c */ + /* 0x000fe200007012f0 */ + /*0200*/ BSSY B0, 0x5b0; /* 0x000003a000007945 */ + /* 0x000fe20003800000 */ + /*0210*/ IMAD.U32 R7, RZ, RZ, RZ; /* 0x000000ffff077224 */ + /* 0x000fe200078e00ff */ + /*0220*/ MOV R11, RZ; /* 0x000000ff000b7202 */ + /* 0x000fe20000000f00 */ + /*0230*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe400078e00ff */ + /*0240*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0250*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*0260*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fc400078e00ff */ + /*0270*/ IMAD.U32 R9, RZ, RZ, RZ; /* 0x000000ffff097224 */ + /* 0x000fe400078e00ff */ + /*0280*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0290*/ @!P0 BRA 0x5a0; /* 0x0000030000008947 */ + /* 0x000fee0003800000 */ + /*02a0*/ S2R R6, SR_LANEID; /* 0x0000000000067919 */ + /* 0x000e220000000000 */ + /*02b0*/ IMAD.U32 R10, RZ, RZ, 0x2; /* 0x00000002ff0a7424 */ + /* 0x000fc800078e00ff */ + /*02c0*/ IMAD.WIDE R16, R29, R10, c[0x0][0x160]; /* 0x000058001d107625 */ + /* 0x000fe200078e020a */ + /*02d0*/ SHF.R.U32.HI R4, RZ, 0x2, R6; /* 0x00000002ff047819 */ + /* 0x001fc80000011606 */ + /*02e0*/ LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT; /* 0x0000000304057812 */ + /* 0x000fe400078ec0ff */ + /*02f0*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT; /* 0x0000000306047812 */ + /* 0x000fe400078ec0ff */ + /*0300*/ LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT; /* 0x0000000105077812 */ + /* 0x000fe400078ec0ff */ + /*0310*/ SHF.R.U32.HI R6, RZ, 0x4, R6; /* 0x00000004ff067819 */ + /* 0x000fe40000011606 */ + /*0320*/ SHF.R.U32.HI R5, RZ, 0x1, R5; /* 0x00000001ff057819 */ + /* 0x000fe20000011605 */ + /*0330*/ IMAD R7, R7, 0x8, R4; /* 0x0000000807077824 */ + /* 0x000fe200078e0204 */ + /*0340*/ LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT; /* 0x0000000106067812 */ + /* 0x000fc400078ec0ff */ + /*0350*/ LEA R4, R5, R4, 0x3; /* 0x0000000405047211 */ + /* 0x000fe200078e18ff */ + /*0360*/ IMAD.WIDE R12, R28, R10, c[0x0][0x168]; /* 0x00005a001c0c7625 */ + /* 0x000fe400078e020a */ + /*0370*/ IMAD R7, R6.reuse, 0x4, R7; /* 0x0000000406077824 */ + /* 0x040fe400078e0207 */ + /*0380*/ IMAD R4, R6, 0x4, R4; /* 0x0000000406047824 */ + /* 0x000fe400078e0204 */ + /*0390*/ IMAD.U32 R7, R7, 0x2, RZ; /* 0x0000000207077824 */ + /* 0x000fe400078e00ff */ + /*03a0*/ IMAD.U32 R5, R4, 0x2, RZ; /* 0x0000000204057824 */ + /* 0x000fe400078e00ff */ + /*03b0*/ IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16; /* 0x00005e0007107a25 */ + /* 0x000fc400078e0010 */ + /*03c0*/ IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12; /* 0x00006000050c7a25 */ + /* 0x000fd000078e000c */ + /*03d0*/ LD.E.128.SYS R24, [R16]; /* 0x0000000010187980 */ + /* 0x000064000010ed00 */ + /*03e0*/ LD.E.128.SYS R20, [R12]; /* 0x000000000c147980 */ + /* 0x000462000010ed00 */ + /*03f0*/ LD.E.128.SYS R16, [R16+0x10]; /* 0x0000001010107980 */ + /* 0x001e22000010ed00 */ + /*0400*/ LD.E.128.SYS R12, [R12+0x10]; /* 0x000000100c0c7980 */ + /* 0x004e22000010ed00 */ + /*0410*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0420*/ MOV R9, RZ; /* 0x000000ff00097202 */ + /* 0x000fe20000000f00 */ + /*0430*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fe400078e00ff */ + /*0440*/ IMAD.U32 R11, RZ, RZ, RZ; /* 0x000000ffff0b7224 */ + /* 0x000fe200078e00ff */ + /*0450*/ MOV R7, RZ; /* 0x000000ff00077202 */ + /* 0x000fe20000000f00 */ + /*0460*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fc400078e00ff */ + /*0470*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0480*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe200078e00ff */ + /*0490*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*04a0*/ HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8; /* 0x0000001418087236 */ + /* 0x0c22640000005408 */ + /*04b0*/ HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10; /* 0x00000014180a7236 */ + /* 0x0c04a4000000d40a */ + /*04c0*/ HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4; /* 0x0000001418047236 */ + /* 0x0c06e40000015404 */ + /*04d0*/ HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6; /* 0x0000001418067236 */ + /* 0x000928000001d406 */ + /*04e0*/ HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8; /* 0x000000161a087236 */ + /* 0x0c20240000005408 */ + /*04f0*/ HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10; /* 0x000000161a0a7236 */ + /* 0x0c4264000000d40a */ + /*0500*/ HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4; /* 0x000000161a047236 */ + /* 0x0c84a40000015404 */ + /*0510*/ HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6; /* 0x000000161a067236 */ + /* 0x0106e8000001d406 */ + /*0520*/ HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8; /* 0x0000000c10087236 */ + /* 0x0c10240000005408 */ + /*0530*/ HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10; /* 0x0000000c100a7236 */ + /* 0x0c2264000000d40a */ + /*0540*/ HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4; /* 0x0000000c10047236 */ + /* 0x0c44a40000015404 */ + /*0550*/ HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6; /* 0x0000000c10067236 */ + /* 0x0086e8000001d406 */ + /*0560*/ HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8; /* 0x0000000e12087236 */ + /* 0x0c10240000005408 */ + /*0570*/ HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10; /* 0x0000000e120a7236 */ + /* 0x0c2024000000d40a */ + /*0580*/ HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4; /* 0x0000000e12047236 */ + /* 0x0c40240000015404 */ + /*0590*/ HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6; /* 0x0000000e12067236 */ + /* 0x008034000001d406 */ + /*05a0*/ BSYNC B0; /* 0x0000000000007941 */ + /* 0x001fea0003800000 */ + /*05b0*/ S2R R12, SR_LANEID; /* 0x00000000000c7919 */ + /* 0x000e220000000000 */ + /*05c0*/ IMAD R28, R28, c[0x0][0x178], RZ; /* 0x00005e001c1c7a24 */ + /* 0x000fe200078e02ff */ + /*05d0*/ SHF.R.U32.HI R14, RZ, 0x4, R12; /* 0x00000004ff0e7819 */ + /* 0x001fc4000001160c */ + /*05e0*/ SHF.R.U32.HI R13, RZ, 0x2, R12; /* 0x00000002ff0d7819 */ + /* 0x000fe4000001160c */ + /*05f0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT; /* 0x000000030c0c7812 */ + /* 0x000fe400078ec0ff */ + /*0600*/ LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT; /* 0x000000010e0e7812 */ + /* 0x000fe400078ec0ff */ + /*0610*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT; /* 0x000000030d0d7812 */ + /* 0x000fc600078ec0ff */ + /*0620*/ IMAD R12, R14, 0x4, R12; /* 0x000000040e0c7824 */ + /* 0x000fe200078e020c */ + /*0630*/ LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT; /* 0x000000010d0f7812 */ + /* 0x000fe400078ec0ff */ + /*0640*/ SHF.R.U32.HI R16, RZ, 0x1, R13; /* 0x00000001ff107819 */ + /* 0x000fe4000001160d */ + /*0650*/ LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT; /* 0x000000050c0d7812 */ + /* 0x040fe400078ec0ff */ + /*0660*/ LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT; /* 0x000000020c0e7812 */ + /* 0x000fc600078ec0ff */ + /*0670*/ IMAD R12, R15, 0x8, R13; /* 0x000000080f0c7824 */ + /* 0x000fe200078e020d */ + /*0680*/ SHF.R.S32.HI R15, RZ, 0x1f, R29; /* 0x0000001fff0f7819 */ + /* 0x000fe2000001141d */ + /*0690*/ IMAD R14, R16, 0x8, R14; /* 0x00000008100e7824 */ + /* 0x000fe200078e020e */ + /*06a0*/ IADD3 R17, P0, R29, R28, RZ; /* 0x0000001c1d117210 */ + /* 0x000fe20007f1e0ff */ + /*06b0*/ IMAD.U32 R13, RZ, RZ, RZ; /* 0x000000ffff0d7224 */ + /* 0x000fc600078e00ff */ + /*06c0*/ LEA.HI.X.SX32 R15, R28, R15, 0x1, P0; /* 0x0000000f1c0f7211 */ + /* 0x000fe200000f0eff */ + /*06d0*/ IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12; /* 0x00005e000e0c7a25 */ + /* 0x000fe200078e000c */ + /*06e0*/ LEA R14, P0, R17, c[0x0][0x170], 0x2; /* 0x00005c00110e7a11 */ + /* 0x000fe200078010ff */ + /*06f0*/ IMAD.U32 R18, RZ, RZ, c[0x0][0x178]; /* 0x00005e00ff127624 */ + /* 0x000fc600078e00ff */ + /*0700*/ LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0; /* 0x00005d0011117a11 */ + /* 0x000fe400000f140f */ + /*0710*/ LEA R16, P0, R12, R14, 0x2; /* 0x0000000e0c107211 */ + /* 0x000fe400078010ff */ + /*0720*/ SHF.L.U32 R14, R18, 0x2, RZ; /* 0x00000002120e7819 */ + /* 0x000fe400000006ff */ + /*0730*/ SHF.R.U32.HI R15, RZ, 0x1e, R18; /* 0x0000001eff0f7819 */ + /* 0x000fe40000011612 */ + /*0740*/ LEA.HI.X R13, R12, R17, R13, 0x2, P0; /* 0x000000110c0d7211 */ + /* 0x000fe400000f140d */ + /*0750*/ LEA R18, P1, R14, R16, 0x2; /* 0x000000100e127211 */ + /* 0x000fc400078210ff */ + /*0760*/ IADD3 R17, P0, R14.reuse, R16, RZ; /* 0x000000100e117210 */ + /* 0x040fe40007f1e0ff */ + /*0770*/ LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1; /* 0x0000000d0e137211 */ + /* 0x040fe400008f140f */ + /*0780*/ IADD3 R21, P1, R14, R18, RZ; /* 0x000000120e157210 */ + /* 0x000fe20007f3e0ff */ + /*0790*/ IMAD.X R20, R15.reuse, 0x1, R13, P0; /* 0x000000010f147824 */ + /* 0x040fe400000e060d */ + /*07a0*/ IMAD.U32 R12, RZ, RZ, R16; /* 0x000000ffff0c7224 */ + /* 0x000fe400078e0010 */ + /*07b0*/ IMAD.X R22, R15, 0x1, R19, P1; /* 0x000000010f167824 */ + /* 0x000fe400008e0613 */ + /*07c0*/ IMAD.U32 R14, RZ, RZ, R17; /* 0x000000ffff0e7224 */ + /* 0x000fc400078e0011 */ + /*07d0*/ IMAD.U32 R15, RZ, RZ, R20; /* 0x000000ffff0f7224 */ + /* 0x000fe200078e0014 */ + /*07e0*/ MOV R16, R21; /* 0x0000001500107202 */ + /* 0x000fe20000000f00 */ + /*07f0*/ IMAD.U32 R17, RZ, RZ, R22; /* 0x000000ffff117224 */ + /* 0x000fe200078e0016 */ + /*0800*/ ST.E.SYS [R12], R8; /* 0x000000000c007385 */ + /* 0x0001e2000010e908 */ + /*0810*/ ST.E.SYS [R12+0x8], R10; /* 0x000000080c007385 */ + /* 0x0003e8000010e90a */ + /*0820*/ ST.E.SYS [R14], R9; /* 0x000000000e007385 */ + /* 0x0003e2000010e909 */ + /*0830*/ ST.E.SYS [R14+0x8], R11; /* 0x000000080e007385 */ + /* 0x0003e2000010e90b */ + /*0840*/ ST.E.SYS [R18], R4; /* 0x0000000012007385 */ + /* 0x0003e2000010e904 */ + /*0850*/ ST.E.SYS [R18+0x8], R6; /* 0x0000000812007385 */ + /* 0x0003e2000010e906 */ + /*0860*/ ST.E.SYS [R16], R5; /* 0x0000000010007385 */ + /* 0x0003e2000010e905 */ + /*0870*/ ST.E.SYS [R16+0x8], R7; /* 0x0000000810007385 */ + /* 0x0003e2000010e907 */ + /*0880*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*0890*/ IADD3 R8, R2, -c[0x0][0x20], RZ; /* 0x8000080002087a10 */ + /* 0x001fd00007ffe0ff */ + /*08a0*/ CS2R.32 R4, SR_CLOCKLO; /* 0x0000000000047805 */ + /* 0x002fd00000005000 */ + /*08b0*/ IMAD R3, R4, 0x1, -R3; /* 0x0000000104037824 */ + /* 0x000fd000078e0a03 */ + /*08c0*/ STL [R8], R3; /* 0x0000000308007387 */ + /* 0x0001e20000100800 */ + /*08d0*/ IMAD.U32 R6, RZ, RZ, R2; /* 0x000000ffff067224 */ + /* 0x000fe200078e0002 */ + /*08e0*/ MOV R4, 0x0; /* 0x0000000000047802 */ + /* 0x000fe20000000f00 */ + /*08f0*/ IMAD.U32 R7, RZ, RZ, R0; /* 0x000000ffff077224 */ + /* 0x000fe200078e0000 */ + /*0900*/ MOV R5, 0x0; /* 0x0000000000057802 */ + /* 0x000fe40000000f00 */ + /*0910*/ MOV R20, 0x0; /* 0x0000000000147802 */ + /* 0x000fe40000000f00 */ + /*0920*/ MOV R21, 0x0; /* 0x0000000000157802 */ + /* 0x000fd00000000f00 */ + /*0930*/ CALL.ABS.NOINC 0x0; /* 0x0000000000007943 */ + /* 0x001fea0003c00000 */ + /*0940*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*0950*/ BRA 0x950; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + /*0960*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + /*0970*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + ............................................. + + + +Fatbin ptx code: +================ +arch = sm_70 +code version = [6,0] +producer = cuda +host = linux +compile_size = 64bit +compressed + + + + + + + + +.version 6.0 +.target sm_70 +.address_size 64 + + +.extern .func (.param .b32 func_retval0) vprintf +( +.param .b64 vprintf_param_0, +.param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ +.local .align 8 .b8 __local_depot0[8]; +.reg .b64 %SP; +.reg .b64 %SPL; +.reg .pred %p<6>; +.reg .f32 %f<34>; +.reg .b32 %r<38>; +.reg .b64 %rd<18>; + + +mov.u64 %rd17, __local_depot0; +cvta.local.u64 %SP, %rd17; +ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; +ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; +ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; +ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; +ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; +ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + + mov.u32 %r6, %clock; + + mov.u32 %r8, %ntid.x; +mov.u32 %r9, %ctaid.x; +mov.u32 %r10, %tid.x; +mad.lo.s32 %r11, %r8, %r9, %r10; +mov.u32 %r12, WARP_SZ; +div.u32 %r13, %r11, %r12; +mov.u32 %r14, %ntid.y; +mov.u32 %r15, %ctaid.y; +mov.u32 %r16, %tid.y; +mad.lo.s32 %r17, %r14, %r15, %r16; +shl.b32 %r2, %r13, 4; +shl.b32 %r3, %r17, 4; +setp.lt.s32 %p1, %r2, %r4; +setp.gt.s32 %p2, %r5, 0; +and.pred %p3, %p1, %p2; +setp.lt.s32 %p4, %r3, %r7; +and.pred %p5, %p3, %p4; +mov.f32 %f26, 0f00000000; +mov.f32 %f27, %f26; +mov.f32 %f28, %f26; +mov.f32 %f29, %f26; +mov.f32 %f30, %f26; +mov.f32 %f31, %f26; +mov.f32 %f32, %f26; +mov.f32 %f33, %f26; +@!%p5 bra BB0_2; +bra.uni BB0_1; + +BB0_1: +mul.wide.s32 %rd4, %r2, 2; +add.s64 %rd5, %rd1, %rd4; +wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; +mul.wide.s32 %rd6, %r3, 2; +add.s64 %rd7, %rd2, %rd6; +wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; +mov.f32 %f25, 0f00000000; +wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: +add.u64 %rd8, %SP, 0; +cvta.to.local.u64 %rd9, %rd8; +mul.lo.s32 %r35, %r3, %r4; +cvt.s64.s32 %rd10, %r35; +cvt.s64.s32 %rd11, %r2; +add.s64 %rd12, %rd10, %rd11; +shl.b64 %rd13, %rd12, 2; +add.s64 %rd14, %rd3, %rd13; +wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + + mov.u32 %r34, %clock; + + sub.s32 %r36, %r34, %r6; +st.local.u32 [%rd9], %r36; +mov.u64 %rd15, $str; +cvta.global.u64 %rd16, %rd15; + + { +.reg .b32 temp_param_reg; + + .param .b64 param0; +st.param.b64 [param0+0], %rd16; +.param .b64 param1; +st.param.b64 [param1+0], %rd8; +.param .b32 retval0; +call.uni (retval0), +vprintf, +( +param0, +param1 +); +ld.param.b32 %r37, [retval0+0]; + + + } + ret; +} + + +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, +.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ +.reg .pred %p<2>; +.reg .b16 %rs<2>; +.reg .f32 %f<2>; +.reg .b32 %r<6>; +.reg .b64 %rd<9>; + + +ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; +ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; +ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; +mov.u32 %r3, %ntid.x; +mov.u32 %r4, %ctaid.x; +mov.u32 %r5, %tid.x; +mad.lo.s32 %r1, %r4, %r3, %r5; +setp.ge.s32 %p1, %r1, %r2; +@%p1 bra BB1_2; + +cvta.to.global.u64 %rd3, %rd2; +mul.wide.s32 %rd4, %r1, 4; +add.s64 %rd5, %rd3, %rd4; +ld.global.f32 %f1, [%rd5]; + + { cvt.rn.f16.f32 %rs1, %f1;} + + + cvta.to.global.u64 %rd6, %rd1; +mul.wide.s32 %rd7, %r1, 2; +add.s64 %rd8, %rd6, %rd7; +st.global.u16 [%rd8], %rs1; + +BB1_2: +ret; +} + + diff --git a/cuda-kernels/config_fermi_islip.icnt b/cuda-kernels/config_fermi_islip.icnt new file mode 100755 index 0000000..a788090 --- /dev/null +++ b/cuda-kernels/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 62; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/cuda-kernels/gpgpu_inst_stats.txt b/cuda-kernels/gpgpu_inst_stats.txt new file mode 100755 index 0000000..acb1839 --- /dev/null +++ b/cuda-kernels/gpgpu_inst_stats.txt @@ -0,0 +1 @@ +kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence diff --git a/cuda-kernels/gpgpusim.config b/cuda-kernels/gpgpusim.config new file mode 100755 index 0000000..306d7f9 --- /dev/null +++ b/cuda-kernels/gpgpusim.config @@ -0,0 +1,149 @@ +# This config models the Pascal GP102 (GeForceGTX 1080Ti) + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 40 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 11 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145,16,4 +-ptx_opcode_initiation_int 1,2,2,2,8,16,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 1,2,1,1,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The default is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) +# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log new file mode 100644 index 0000000..f754f0c --- /dev/null +++ b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log @@ -0,0 +1,324 @@ +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + diff --git a/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log new file mode 100644 index 0000000..f754f0c --- /dev/null +++ b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log @@ -0,0 +1,324 @@ +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + diff --git a/cuda-kernels/gpuwattch_gtx1080Ti.xml b/cuda-kernels/gpuwattch_gtx1080Ti.xml new file mode 100755 index 0000000..02619ff --- /dev/null +++ b/cuda-kernels/gpuwattch_gtx1080Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cuda-kernels/tensor_core b/cuda-kernels/tensor_core new file mode 100755 index 0000000..b25f3d9 Binary files /dev/null and b/cuda-kernels/tensor_core differ diff --git a/cuda-kernels/tensor_core.cu b/cuda-kernels/tensor_core.cu new file mode 100644 index 0000000..483a42b --- /dev/null +++ b/cuda-kernels/tensor_core.cu @@ -0,0 +1,250 @@ +/* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of NVIDIA CORPORATION nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +// Define some error checking macros. +#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } +void cudaErrCheck_(cudaError_t stat, const char *file, int line) { + if (stat != cudaSuccess) { + fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); + } +} + + + + +#include +using namespace nvcuda; + +// Must be multiples of 16 for wmma code to work +#define MATRIX_M (16) +#define MATRIX_N (16) +#define MATRIX_K (16) + + + +// The only dimensions currently supported by WMMA +const int WMMA_M = 16; +const int WMMA_N = 16; +const int WMMA_K = 16; + + +// Performs an MxNxK GEMM (C=alpha*A*B + beta*C) assuming: +// 1) Matrices are packed in memory. +// 2) M, N and K are multiples of 16. +// 3) Neither A nor B are transposed. +// Note: This is NOT a high performance example but is for demonstration purposes only +// For a high performance code please use the GEMM provided in cuBLAS. +__global__ void wmma_example(half *a, half *b, float *c, int M, int N, int K, float alpha, float beta) { + unsigned int start_time=0,end_time=0; + // Leading dimensions. Packed with no transpositions. + start_time=clock(); + int lda = M; + int ldb = K; + int ldc = M; + + // Tile using a 2D grid/ + int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize; + int warpN = (blockIdx.y * blockDim.y + threadIdx.y); + + // Declare the fragments + wmma::fragment a_frag; + wmma::fragment b_frag; + wmma::fragment acc_frag; + wmma::fragment c_frag; + + wmma::fill_fragment(c_frag, 0.0f); + + int i=0; + int aRow = warpM * WMMA_M; + int bCol = warpN * WMMA_N; + int aCol = i; + int bRow = i; + + + // Bounds checking + if (aRow < M && aCol < K && bRow < K && bCol < N) { + wmma::load_matrix_sync(a_frag, a+aRow+aCol*lda, lda); + wmma::load_matrix_sync(b_frag, b+bRow*ldb+bCol, ldb); + wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); + //wmma::mma_sync(acc_frag, a_frag, b_frag, acc_frag); + } + int cRow = warpM * WMMA_M; + int cCol = warpN * WMMA_N; + wmma::store_matrix_sync(c + cRow + cCol * ldc, c_frag, ldc, wmma::mem_col_major); + end_time=clock(); + printf("clock=%d",end_time-start_time); +} + +__global__ void convertFp32ToFp16 (half *out, float *in, int n) { + int idx = blockDim.x * blockIdx.x + threadIdx.x; + if (idx < n) { + out[idx] = in[idx]; + } +} + +int main(int argc, char* argv[]) { + float *a_fp32; + float *b_fp32; + half *a_fp16; + half *b_fp16; + + float *c; + float *c_cublas; + float *c_wmma; + + float *c_host_cublas; + float *c_host_wmma; + float *a_host_wmma; + float *b_host_wmma; + float *c_init_host_wmma; + + + cudaEvent_t startWMMA; + cudaEvent_t stopWMMA; + + + cudaErrCheck(cudaEventCreate(&startWMMA)); + cudaErrCheck(cudaEventCreate(&stopWMMA)); + + + + + // Use tensor cores + + + cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); + cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); + cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); + cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); + + cudaErrCheck(cudaMalloc((void**)&c, MATRIX_M * MATRIX_N * sizeof(float))); + cudaErrCheck(cudaMalloc((void**)&c_wmma, MATRIX_M * MATRIX_N * sizeof(float))); + + c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); + c_init_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); + a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); + b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); + + + +// printf("a_fp32\n"); + for(int m=0;m>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); + convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); + + for(int m=0;m>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); + // wmma_example <<< gridDim, blockDim >>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); + cudaErrCheck(cudaEventRecord(stopWMMA)); + + + + + // Error checking + printf("\nChecking results...\n"); + cudaErrCheck(cudaMemcpy(c_host_wmma, c_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); + // printf("c_host\n"); + // for(int m=0;m{ +\.a\.sync TC; ptx_lval.int_value = LOAD_A; return WMMA_DIRECTIVE; +\.b\.sync TC; ptx_lval.int_value = LOAD_B; return WMMA_DIRECTIVE; +\.c\.sync TC; ptx_lval.int_value = LOAD_C; return WMMA_DIRECTIVE; +\.d\.sync TC; ptx_lval.int_value = STORE_D; return WMMA_DIRECTIVE; +\.sync TC;ptx_lval.int_value=MMA; return WMMA_DIRECTIVE; +\.row TC; ptx_lval.int_value = ROW; return LAYOUT; +\.col TC; ptx_lval.int_value = COL; return LAYOUT; +\.m16n16k16 TC; ptx_lval.int_value = M16N16K16; return CONFIGURATION; + \.align TC; return ALIGN_DIRECTIVE; \.branchtargets TC; return BRANCHTARGETS_DIRECTIVE; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 3360c55..737657c 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -37,6 +37,9 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token STRING %token OPCODE +%token WMMA_DIRECTIVE +%token LAYOUT +%token CONFIGURATION %token ALIGN_DIRECTIVE %token BRANCHTARGETS_DIRECTIVE %token BYTE_DIRECTIVE @@ -428,6 +431,7 @@ option: type_spec | compare_spec | addressable_spec | rounding_mode + | wmma_spec | SYNC_OPTION { add_option(SYNC_OPTION); } | ARRIVE_OPTION { add_option(ARRIVE_OPTION); } | RED_OPTION { add_option(RED_OPTION); } @@ -483,6 +487,7 @@ atomic_operation_spec: ATOMIC_AND { add_option(ATOMIC_AND); } rounding_mode: floating_point_rounding_mode | integer_rounding_mode; + floating_point_rounding_mode: RN_OPTION { add_option(RN_OPTION); } | RZ_OPTION { add_option(RZ_OPTION); } | RM_OPTION { add_option(RM_OPTION); } @@ -515,6 +520,10 @@ compare_spec:EQ_OPTION { add_option(EQ_OPTION); } | NAN_OPTION { add_option(NAN_OPTION); } ; +wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);} + | WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + ; + operand_list: operand | operand COMMA operand_list; @@ -543,6 +552,7 @@ operand: IDENTIFIER { add_scalar_operand( $1 ); } vector_operand: LEFT_BRACE IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_2vector_operand($2,$4); } | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_3vector_operand($2,$4,$6); } | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_4vector_operand($2,$4,$6,$8); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_8vector_operand($2,$4,$6,$8,$10,$12,$14,$16); } | LEFT_BRACE IDENTIFIER RIGHT_BRACE { add_1vector_operand($2); } ; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 8ebdcf8..9a4d8d3 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -995,7 +995,7 @@ static std::list check_operands( int opcode, const std::list &operands ) { static int g_warn_literal_operands_two_type_inst; - if( (opcode == CVT_OP) || (opcode == SET_OP) || (opcode == SLCT_OP) || (opcode == TEX_OP) ) { + if( (opcode == CVT_OP) || (opcode == SET_OP) || (opcode == SLCT_OP) || (opcode == TEX_OP) || (opcode==MMA_OP)) { // just make sure these do not have have const operands... if( !g_warn_literal_operands_two_type_inst ) { std::list::const_iterator o; @@ -1043,6 +1043,7 @@ ptx_instruction::ptx_instruction( int opcode, const std::list &operands, const operand_info &return_var, const std::list &options, + const std::list &wmma_options, const std::list &scalar_type, memory_space_t space_spec, const char *file, @@ -1061,6 +1062,7 @@ ptx_instruction::ptx_instruction( int opcode, m_operands.insert(m_operands.begin(), checked_operands.begin(), checked_operands.end() ); m_return_var = return_var; m_options = options; + m_wmma_options = wmma_options; m_wide = false; m_hi = false; m_lo = false; @@ -1078,7 +1080,7 @@ ptx_instruction::ptx_instruction( int opcode, m_atomic_spec = 0; m_membar_level = 0; m_inst_size = 8; // bytes - + int rr=0; std::list::const_iterator i; unsigned n=1; for ( i=options.begin(); i!= options.end(); i++, n++ ) { diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 0601b97..ff24a66 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -582,6 +582,34 @@ public: m_is_return_var = false; m_immediate_address=false; } + operand_info( const symbol *s1, const symbol *s2, const symbol *s3, const symbol *s4 ,const symbol *s5,const symbol *s6,const symbol *s7, const symbol *s8) + { + init(); + m_is_non_arch_reg = false; + m_addr_space = undefined_space; + m_operand_lohi = 0; + m_double_operand_type = 0; + m_operand_neg = false; + m_const_mem_offset = 0; + m_uid = get_uid(); + m_valid = true; + m_vector = true; + m_type = vector_t; + m_value.m_vector_symbolic = new const symbol*[8]; + m_value.m_vector_symbolic[0] = s1; + m_value.m_vector_symbolic[1] = s2; + m_value.m_vector_symbolic[2] = s3; + m_value.m_vector_symbolic[3] = s4; + m_value.m_vector_symbolic[4] = s5; + m_value.m_vector_symbolic[5] = s6; + m_value.m_vector_symbolic[6] = s7; + m_value.m_vector_symbolic[7] = s8; + m_addr_offset = 0; + m_neg_pred = false; + m_is_return_var = false; + m_immediate_address=false; + } + void init() { m_uid=(unsigned)-1; @@ -866,6 +894,7 @@ public: const std::list &operands, const operand_info &return_var, const std::list &options, + const std::list &wmma_options, const std::list &scalar_type, memory_space_t space_spec, const char *file, @@ -1087,6 +1116,7 @@ private: operand_info m_return_var; std::list m_options; + std::list m_wmma_options; bool m_wide; bool m_hi; bool m_lo; @@ -1096,6 +1126,9 @@ private: bool m_uni; //if branch instruction, this evaluates to true for uniform branches (ie jumps) bool m_to_option; unsigned m_cache_option; + unsigned m_wmma_type; + unsigned m_wmma_layout[2]; + unsigned m_wmma_configuration; unsigned m_rounding_mode; unsigned m_compare_op; unsigned m_saturation_mode; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 7fc54e9..6757091 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -72,6 +72,7 @@ symbol *g_label; int g_opcode = -1; std::list g_operands; std::list g_options; +std::list g_wmma_options; std::list g_scalar_type; #define PTX_PARSE_DPRINTF(...) \ @@ -162,6 +163,7 @@ void init_instruction_state() g_label = NULL; g_opcode = -1; g_options.clear(); + g_wmma_options.clear(); g_return_var = operand_info(); init_directive_state(); } @@ -300,6 +302,7 @@ void add_instruction() g_operands, g_return_var, g_options, + g_wmma_options, g_scalar_type, g_space_spec, g_filename, @@ -629,7 +632,7 @@ void add_scalar_type_spec( int type_spec ) g_scalar_type.push_back( type_spec ); if ( g_scalar_type.size() > 1 ) { parse_assert( (g_opcode == -1) || (g_opcode == CVT_OP) || (g_opcode == SET_OP) || (g_opcode == SLCT_OP) - || (g_opcode == TEX_OP), + || (g_opcode == TEX_OP)|| (g_opcode==MMA_OP), "only cvt, set, slct, and tex can have more than one type specifier."); } g_scalar_type_spec = type_spec; @@ -669,7 +672,11 @@ void add_option( int option ) PTX_PARSE_DPRINTF("add_option"); g_options.push_back( option ); } - +void add_wmma_option( int option ) +{ + PTX_PARSE_DPRINTF("add_option"); + g_wmma_options.push_back( option ); +} void add_double_operand( const char *d1, const char *d2 ) { //operands that access two variables. @@ -725,6 +732,28 @@ void add_4vector_operand( const char *d1, const char *d2, const char *d3, const if ( s4 == null_op ) s4 = NULL; g_operands.push_back( operand_info(s1,s2,s3,s4) ); } +void add_8vector_operand( const char *d1, const char *d2, const char *d3, const char *d4,const char *d5,const char *d6,const char *d7,const char *d8 ) +{ + PTX_PARSE_DPRINTF("add_8vector_operand"); + const symbol *s1 = g_current_symbol_table->lookup(d1); + const symbol *s2 = g_current_symbol_table->lookup(d2); + const symbol *s3 = g_current_symbol_table->lookup(d3); + const symbol *s4 = g_current_symbol_table->lookup(d4); + const symbol *s5 = g_current_symbol_table->lookup(d5); + const symbol *s6 = g_current_symbol_table->lookup(d6); + const symbol *s7 = g_current_symbol_table->lookup(d7); + const symbol *s8 = g_current_symbol_table->lookup(d8); + parse_assert( s1 != NULL && s2 != NULL && s3 != NULL && s4 != NULL && s5 !=NULL && s6 !=NULL && s7 !=NULL && s8 !=NULL, "v4 component(s) missing declarations."); + const symbol *null_op = g_current_symbol_table->lookup("_"); + if ( s2 == null_op ) s2 = NULL; + if ( s3 == null_op ) s3 = NULL; + if ( s4 == null_op ) s4 = NULL; + if ( s5 == null_op ) s5 = NULL; + if ( s6 == null_op ) s6 = NULL; + if ( s7 == null_op ) s7 = NULL; + if ( s8 == null_op ) s8 = NULL; + g_operands.push_back( operand_info(s1,s2,s3,s4,s5,s6,s7,s8) ); +} void add_builtin_operand( int builtin, int dim_modifier ) { diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h index 32f3903..8094b43 100644 --- a/src/cuda-sim/ptx_parser.h +++ b/src/cuda-sim/ptx_parser.h @@ -57,7 +57,9 @@ void add_1vector_operand( const char *d1 ); void add_2vector_operand( const char *d1, const char *d2 ); void add_3vector_operand( const char *d1, const char *d2, const char *d3 ); void add_4vector_operand( const char *d1, const char *d2, const char *d3, const char *d4 ); +void add_8vector_operand( const char *d1, const char *d2, const char *d3, const char *d4 ,const char *d5,const char *d6,const char *d7,const char *d8); void add_option(int option ); +void add_wmma_option(int option ); void add_builtin_operand( int builtin, int dim_modifier ); void add_memory_operand( ); void add_literal_int( int value ); -- cgit v1.3 From eae030c9d1d607d1c14e4ade99cb5caea6403efd Mon Sep 17 00:00:00 2001 From: aamir Date: Sat, 3 Nov 2018 17:03:58 -0700 Subject: merged with memory subsytem. Regression is passing but tensorcore kernel is stuck in deadlock --- .gitignore | 1 + .travis.yml | 31 +- CHANGES | 30 + Jenkinsfile | 126 ++++ README | 10 +- aerialvision/organizedata.py | 2 +- configs/GTX480/config_fermi_islip.icnt | 70 -- configs/GTX480/gpgpusim.config | 134 ---- configs/GTX480/gpuwattch_gtx480.xml | 538 -------------- configs/GeForceGTX1080Ti/config_fermi_islip.icnt | 70 -- configs/GeForceGTX1080Ti/gpgpusim.config | 150 ---- configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml | 538 -------------- configs/GeForceGTX750Ti/config_fermi_islip.icnt | 70 -- configs/GeForceGTX750Ti/gpgpusim.config | 131 ---- configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml | 539 -------------- configs/Pascal_TITANX/config_fermi_islip.icnt | 70 -- configs/Pascal_TITANX/gpgpusim.config | 156 ---- configs/QuadroFX5600/gpgpusim.config | 99 --- configs/QuadroFX5600/gpuwattch_quadrofx5600.xml | 538 -------------- configs/QuadroFX5600/icnt_config_islip.icnt | 70 -- configs/QuadroFX5800/config_quadro_islip.icnt | 69 -- configs/QuadroFX5800/gpgpusim.config | 88 --- configs/TeslaC2050/config_fermi_islip.icnt | 70 -- configs/TeslaC2050/gpgpusim.config | 133 ---- .../deprecated-cfgs/GTX480/config_fermi_islip.icnt | 70 ++ configs/deprecated-cfgs/GTX480/gpgpusim.config | 134 ++++ .../deprecated-cfgs/GTX480/gpuwattch_gtx480.xml | 538 ++++++++++++++ .../GeForceGTX750Ti/config_fermi_islip.icnt | 70 ++ .../GeForceGTX750Ti/gpgpusim.config | 131 ++++ .../GeForceGTX750Ti/gpuwattch_gtx750Ti.xml | 539 ++++++++++++++ .../deprecated-cfgs/QuadroFX5600/gpgpusim.config | 99 +++ .../QuadroFX5600/gpuwattch_quadrofx5600.xml | 538 ++++++++++++++ .../QuadroFX5600/icnt_config_islip.icnt | 70 ++ .../QuadroFX5800/config_quadro_islip.icnt | 69 ++ .../deprecated-cfgs/QuadroFX5800/gpgpusim.config | 88 +++ .../SM6_GTX1080/config_fermi_islip.icnt | 70 ++ .../deprecated-cfgs/SM6_GTX1080/gpgpusim.config | 150 ++++ .../SM6_GTX1080/gpuwattch_gtx1080Ti.xml | 538 ++++++++++++++ .../SM6_P100/config_fermi_islip.icnt | 70 ++ configs/deprecated-cfgs/SM6_P100/gpgpusim.config | 156 ++++ .../deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml | 538 ++++++++++++++ .../SM6_TITANX/config_fermi_islip.icnt | 70 ++ configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config | 157 +++++ .../SM6_TITANX/gpuwattch_gtx480.xml | 538 ++++++++++++++ .../SM7_TITANV/config_fermi_islip.icnt | 70 ++ configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config | 165 +++++ .../TeslaC2050/config_fermi_islip.icnt | 70 ++ configs/deprecated-cfgs/TeslaC2050/gpgpusim.config | 133 ++++ .../tested-cfgs/SM2_GTX480/config_fermi_islip.icnt | 70 ++ configs/tested-cfgs/SM2_GTX480/gpgpusim.config | 153 ++++ .../tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml | 538 ++++++++++++++ .../tested-cfgs/SM6_TITANX/config_fermi_islip.icnt | 73 ++ configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 185 +++++ .../tested-cfgs/SM7_TITANV/config_fermi_islip.icnt | 74 ++ configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 191 +++++ cuobjdump_to_ptxplus/ptx_parser.h | 4 + libcuda/cuda_runtime_api.cc | 49 +- nightly.jenkinsfile | 75 ++ setup_environment | 2 +- src/abstract_hardware_model.cc | 49 +- src/abstract_hardware_model.h | 33 +- src/cuda-sim/cuda-sim.cc | 47 +- src/cuda-sim/instructions.cc | 1 + src/cuda-sim/ptx.y | 3 +- src/cuda-sim/ptx_ir.cc | 7 +- src/cuda-sim/ptx_ir.h | 7 + src/cuda-sim/ptx_parser.cc | 4 + src/cuda-sim/ptx_parser.h | 1 + src/gpgpu-sim/addrdec.cc | 71 ++ src/gpgpu-sim/addrdec.h | 9 + src/gpgpu-sim/delayqueue.h | 1 + src/gpgpu-sim/dram.cc | 637 +++++++++++++---- src/gpgpu-sim/dram.h | 77 +- src/gpgpu-sim/dram_sched.cc | 121 +++- src/gpgpu-sim/dram_sched.h | 12 + src/gpgpu-sim/gpu-cache.cc | 782 +++++++++++++++++---- src/gpgpu-sim/gpu-cache.h | 644 +++++++++++++++-- src/gpgpu-sim/gpu-sim.cc | 125 +++- src/gpgpu-sim/gpu-sim.h | 57 +- src/gpgpu-sim/l2cache.cc | 166 ++++- src/gpgpu-sim/l2cache.h | 18 + src/gpgpu-sim/l2cache_trace.h | 16 + src/gpgpu-sim/mem_fetch.cc | 7 +- src/gpgpu-sim/mem_fetch.h | 13 +- src/gpgpu-sim/mem_latency_stat.cc | 19 +- src/gpgpu-sim/mem_latency_stat.h | 4 + src/gpgpu-sim/shader.cc | 431 ++++++++++-- src/gpgpu-sim/shader.h | 93 ++- src/gpgpusim_entrypoint.cc | 1 + src/gpuwattch/makefile | 4 +- src/intersim2/Makefile | 2 +- src/intersim2/interconnect_interface.cpp | 9 +- src/trace_streams.tup | 2 + version | 2 +- 94 files changed, 9589 insertions(+), 4104 deletions(-) create mode 100644 Jenkinsfile delete mode 100644 configs/GTX480/config_fermi_islip.icnt delete mode 100644 configs/GTX480/gpgpusim.config delete mode 100755 configs/GTX480/gpuwattch_gtx480.xml delete mode 100644 configs/GeForceGTX1080Ti/config_fermi_islip.icnt delete mode 100644 configs/GeForceGTX1080Ti/gpgpusim.config delete mode 100755 configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml delete mode 100644 configs/GeForceGTX750Ti/config_fermi_islip.icnt delete mode 100644 configs/GeForceGTX750Ti/gpgpusim.config delete mode 100755 configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml delete mode 100644 configs/Pascal_TITANX/config_fermi_islip.icnt delete mode 100644 configs/Pascal_TITANX/gpgpusim.config delete mode 100644 configs/QuadroFX5600/gpgpusim.config delete mode 100644 configs/QuadroFX5600/gpuwattch_quadrofx5600.xml delete mode 100644 configs/QuadroFX5600/icnt_config_islip.icnt delete mode 100644 configs/QuadroFX5800/config_quadro_islip.icnt delete mode 100644 configs/QuadroFX5800/gpgpusim.config delete mode 100644 configs/TeslaC2050/config_fermi_islip.icnt delete mode 100644 configs/TeslaC2050/gpgpusim.config create mode 100644 configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt create mode 100644 configs/deprecated-cfgs/GTX480/gpgpusim.config create mode 100755 configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml create mode 100644 configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt create mode 100644 configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config create mode 100755 configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml create mode 100644 configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config create mode 100644 configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml create mode 100644 configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt create mode 100644 configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt create mode 100644 configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config create mode 100644 configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt create mode 100644 configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config create mode 100755 configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml create mode 100644 configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt create mode 100644 configs/deprecated-cfgs/SM6_P100/gpgpusim.config create mode 100755 configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml create mode 100644 configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt create mode 100644 configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config create mode 100755 configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml create mode 100644 configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt create mode 100644 configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config create mode 100644 configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt create mode 100644 configs/deprecated-cfgs/TeslaC2050/gpgpusim.config create mode 100644 configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt create mode 100644 configs/tested-cfgs/SM2_GTX480/gpgpusim.config create mode 100755 configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml create mode 100644 configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt create mode 100644 configs/tested-cfgs/SM6_TITANX/gpgpusim.config create mode 100644 configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt create mode 100644 configs/tested-cfgs/SM7_TITANV/gpgpusim.config create mode 100644 nightly.jenkinsfile (limited to 'cuobjdump_to_ptxplus') diff --git a/.gitignore b/.gitignore index d21cc8f..6c6ed5f 100644 --- a/.gitignore +++ b/.gitignore @@ -32,4 +32,5 @@ cuobjdump_to_ptxplus/sass_parser.hh cuobjdump_to_ptxplus/sass_parser.output build/* +tags *.swp diff --git a/.travis.yml b/.travis.yml index 7a12a1c..b38f468 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,7 +1,7 @@ sudo: required before_install: - - docker pull tgrogers/gpgpu-sim_regress:latest + - docker pull tgrogers/gpgpu-sim_regress:volta_update language: cpp @@ -10,34 +10,13 @@ matrix: include: - services: docker env: - - CONFIG=configs.gtx480.yml + - CONFIG=GTX480 - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ -# This config is just taking far too long... -# - services: docker -# env: -# - CONFIG=configs.gtx750ti.yml -# - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ -# - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - services: docker env: - - CONFIG=configs.quadro5600.yml - - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - - services: docker - env: - - CONFIG=configs.quadro5800.yml - - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - - services: docker - env: - - CONFIG=configs.teslac2050.yml - - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - - services: docker - env: - - CONFIG=configs.gtx1080ti.yml - - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ + - CONFIG=TITANV + - CUDA_INSTALL_PATH=/usr/local/cuda-9.1/ - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-9.1/ -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'export CUDA_INSTALL_PATH=$CUDA_INSTALL_PATH && export PTXAS_CUDA_INSTALL_PATH=$PTXAS_CUDA_INSTALL_PATH && source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:volta_update /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'export CUDA_INSTALL_PATH=$CUDA_INSTALL_PATH && export PTXAS_CUDA_INSTALL_PATH=$PTXAS_CUDA_INSTALL_PATH && source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -C $CONFIG -B rodinia_2.0-ft -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" diff --git a/CHANGES b/CHANGES index dbf5b39..60be885 100644 --- a/CHANGES +++ b/CHANGES @@ -1,4 +1,34 @@ LOG: +Version 4.0.0 (development branch) versus 3.2.3 +-Front-End: +1- Support .nc cache modifier and __ldg function to access the read-only L1D cache +2- Partially-support some SASS_60 in the PTXP_PLUS (not completed yet) +-GPU Core: +1- Fermi/Pascal coalescer: coalescing on 32-bytes sectors. +2- Adding separate dp unit pipeline. +3- diff dual issue: allow scheduler to issue diff insts at a time +4- Fair memory issue from multiple schedulers. +-Cache System: +1- Sector L1/L2 cache +2- Fetch-on-write and lazy-fetch-on-read write allocation policy. +3- Improving the L1 cache throughput (streaming L1 cache) +4- Performance model for CUDA memory copy. +5- Support memory partition indexing to reduce partition camping (POLY, XOR and PAE (ISCA’18) Indexing) +6- Adaptive cache configuration +-Memory: +1- Performance Model for HBM (mainly the dual-bus interface) +2- Separate Read/Write buffers. +3- Advanced bank indexing function. +-Statistics: +1- Adding more detailed cache statistics to define and analyze cache bottlenecks. +2- Adding more detailed memory statistics (BLP, RBL, etc) to define and analyze memory bottlenecks. +3- Addig new system stats: gpu occupancy, L2BW, etc +-Configs: +Adding the Pascal and Volta config files that has been correlated against real hardware. +See the correlation website here: +https://engineering.purdue.edu/tgrogers/group/correlator.html + + Version 3.2.3+edits (development branch) versus 3.2.3 - Support for running regression tests using Travis - Support added for CUDA dynamic parallelism (courtesy of Jin Wang from Georgia Tech) diff --git a/Jenkinsfile b/Jenkinsfile new file mode 100644 index 0000000..1969aea --- /dev/null +++ b/Jenkinsfile @@ -0,0 +1,126 @@ +pipeline { + agent { + label "purdue-cluster" + } + + options { + disableConcurrentBuilds() + } + + stages { + stage('simulator-build') { + steps { + parallel "4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + }, "9.1" : { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + } + } + } + stage('simulations-build'){ + steps{ + sh 'rm -rf gpgpu-sim_simulations' + sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + cd gpgpu-sim_simulations && \ + git checkout purdue-cluster && \ + git pull && \ + ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src rodinia_2.0-ft sdk-4.2 && \ + make -C ./benchmarks/src data' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src/ rodinia_2.0-ft sdk-4.2 && \ + make -C ./benchmarks/src data' + } + } + stage('regress'){ + steps { + parallel "4.2-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS -N regress-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-per-app-4.2.csv && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-per-app-4.2.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR ' + }, "9.1-functest": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft,sdk-4.2 -C TITANX,TITANX-L1ON -N regress-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-per-app-9.1.csv -N regress-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-per-app-9.1.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + } + } + } + stage('4.2-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + PLOTDIR="jenkins/${JOB_NAME}" &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS > stats-per-kernel-4.2.csv &&\ + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh stats-per-kernel-4.2.csv $PLOTDIR ${BUILD_NUMBER}' + } + } + stage('9.1-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + PLOTDIR="jenkins/${JOB_NAME}" &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft,sdk-4.2 -C TITANX,TITANX-L1ON > stats-per-kernel-9.1.csv &&\ + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh stats-per-kernel-9.1.csv $PLOTDIR ${BUILD_NUMBER}' + } + } + stage('archive-and-delta') { + steps { + sh 'rm -rf gpgpu-sim-results-repo' + sh 'git clone git@github.com:purdue-aalp/gpgpu-sim-results-repo.git' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480-PTXPLUS > stats-per-kernel-4.2-ptxplus.csv &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480 > stats-per-kernel-4.2-ptx.csv' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft,sdk-4.2 -C TITANX > stats-per-kernel-9.1-titanx.csv' + sh './gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/jenkins/quick-regress/AALP/gpgpu-sim_distribution/dev-purdue-integration/stats-per-app-4.2.csv,./stats-per-app-4.2.csv -R > per-app-merge-4.2.csv' + sh './gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/jenkins/quick-regress/AALP/gpgpu-sim_distribution/dev-purdue-integration/stats-per-app-9.1.csv,./stats-per-app-9.1.csv -R > per-app-merge-9.1.csv' + sh 'PLOTDIR="jenkins/${JOB_NAME}" &&\ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c per-app-merge-4.2.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR/deltas -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR/deltas &&\ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c per-app-merge-9.1.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR/deltas -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR/deltas -n $PLOTDIR/deltas &&\ + ./gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/jenkins/quick-regress/AALP/gpgpu-sim_distribution/dev-purdue-integration/stats-per-kernel-4.2-ptx.csv,./stats-per-kernel-4.2-ptx.csv -R > per-kernel-merge-4.2-ptx.csv &&\ + ./gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/jenkins/quick-regress/AALP/gpgpu-sim_distribution/dev-purdue-integration/stats-per-kernel-4.2-ptxplus.csv,./stats-per-kernel-4.2-ptxplus.csv -R > per-kernel-merge-4.2-ptxplus.csv &&\ + ./gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/jenkins/quick-regress/AALP/gpgpu-sim_distribution/dev-purdue-integration/stats-per-kernel-9.1-titanx.csv,./stats-per-kernel-9.1-titanx.csv -R > per-kernel-merge-9.1-titanx.csv &&\ + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh per-kernel-merge-4.2-ptx.csv $PLOTDIR ${BUILD_NUMBER} &&\ + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh per-kernel-merge-4.2-ptxplus.csv $PLOTDIR ${BUILD_NUMBER} &&\ + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh per-kernel-merge-9.1-titanx.csv $PLOTDIR ${BUILD_NUMBER} &&\ + mkdir -p ./jenkins/quick-regress/${JOB_NAME}/ && cp stats-per-*.csv ./jenkins/quick-regress/${JOB_NAME}/ &&\ + cd ./gpgpu-sim-results-repo &&\ + git diff --quiet && git diff --staged --quiet || git commit -am "Jenkins automated checkin ${BUILD_NUMBER}" &&\ + git push' + } + } + } + post { + success { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!", + to: 'tgrogers@purdue.edu' + } + failure { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}", + to: 'tgrogers@purdue.edu' + } + } +} diff --git a/README b/README index 6e2d734..7eaae5d 100644 --- a/README +++ b/README @@ -5,8 +5,8 @@ AerialVision and a configurable and extensible energy model called GPUWattch. GPGPU-Sim and GPUWattch have been rigorously validated with performance and power measurements of real hardware GPUs. -This version of GPGPU-Sim has been tested with CUDA version 2.3, 3.1, 4.0, -5.0, 5.5, 6.0 and 7.5. +This version of GPGPU-Sim has been tested with CUDA version 4.2, +5.0, 5.5, 6.0 and 7.5, 8.0, 9.0, 9.1 Please see the copyright notice in the file COPYRIGHT distributed with this release in the same directory as this file. @@ -18,6 +18,12 @@ Analyzing CUDA Workloads Using a Detailed GPU Simulator, in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Boston, MA, April 19-21, 2009. +If you use the memory system in GPGPU-Sim, or the Volta/Pascal models, +please cite: +Mahmoud Khairy, Jain Akshay, Tor Aamodt, Timothy G Rogers, +Exploring Modern GPU Memory System Design Challenges through Accurate Modeling, arXiv:1810.07269, +https://arxiv.org/abs/1810.07269 + If you use the GPUWattch energy model in your research, please cite: Jingwen Leng, Tayler Hetherington, Ahmed ElTantawy, Syed Gilani, Nam Sung Kim, diff --git a/aerialvision/organizedata.py b/aerialvision/organizedata.py index 090b90f..ea947cd 100644 --- a/aerialvision/organizedata.py +++ b/aerialvision/organizedata.py @@ -97,7 +97,7 @@ def organizedata(fileVars): 'sparse':OrganizeSparse, # Vector data with 2D index (used by DRAM access stats) 'custom':0 } - data_type_char = {int:'I', float:'f'} + data_type_char = {int:'L', float:'d'} print "Organizing data into internal format..." diff --git a/configs/GTX480/config_fermi_islip.icnt b/configs/GTX480/config_fermi_islip.icnt deleted file mode 100644 index 7820e4e..0000000 --- a/configs/GTX480/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 27; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config deleted file mode 100644 index ee90c12..0000000 --- a/configs/GTX480/gpgpusim.config +++ /dev/null @@ -1,134 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 - - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 15 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 6 --gpgpu_n_sub_partition_per_mchannel 2 - -# Fermi clock domains -#-gpgpu_clock_domains ::: -# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided -# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 700.0:700.0:700.0:924.0 - -# shader core pipeline config --gpgpu_shader_registers 32768 --gpgpu_occupancy_sm_number 20 - -# This implies a maximum of 48 warps/SM --gpgpu_shader_core_pipeline 1536:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 2,1,1,2,1,1,2 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,16,8,8,130 - - -# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. --gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 49152 - -# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 -#-gpgpu_shmem_size 16384 - -# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 --gpgpu_cache:dl2_texture_only 0 - --gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_num_reg_banks 16 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - --gpgpu_max_insn_issue_per_warp 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 116 - -# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5 is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS - -# GDDR5 timing from hynix H5GQ1H24AFR -# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/GTX480/gpuwattch_gtx480.xml b/configs/GTX480/gpuwattch_gtx480.xml deleted file mode 100755 index 304e0fd..0000000 --- a/configs/GTX480/gpuwattch_gtx480.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/GeForceGTX1080Ti/config_fermi_islip.icnt b/configs/GeForceGTX1080Ti/config_fermi_islip.icnt deleted file mode 100644 index 2a69ddd..0000000 --- a/configs/GeForceGTX1080Ti/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 50; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config deleted file mode 100644 index fb044c6..0000000 --- a/configs/GeForceGTX1080Ti/gpgpusim.config +++ /dev/null @@ -1,150 +0,0 @@ -# This config models the Pascal GP102 (GeForceGTX 1080Ti) - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 60 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 11 --gpgpu_n_sub_partition_per_mchannel 2 - -# Pascal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA TITAN X clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 --gpgpu_occupancy_sm_number 60 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 1 SFU unit -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,4,1,1,6 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# SFU is 32-width in pascal, then dp units initiation is 1 cycle --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,2,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 1,2,1,1,130 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory -# Pascal GP102 has 64KB L1 cache -# The default is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 --gpgpu_shmem_size 98304 --gmem_skip_L1D 1 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 --gpgpu_cache:dl2_texture_only 0 - -# 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 - -# enable operand collector -## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 20 --gpgpu_operand_collector_num_units_sfu 4 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 -# gpgpu_num_reg_banks should be increased to 32, but it gives an error! --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) -# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition -# the atom size of GDDR5X (the smallest read request) is 32 bytes --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5X is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing from hynix H5GQ1H24AFR -# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" - -# Pascal has four schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml b/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml deleted file mode 100755 index 02619ff..0000000 --- a/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/GeForceGTX750Ti/config_fermi_islip.icnt deleted file mode 100644 index 069ca02..0000000 --- a/configs/GeForceGTX750Ti/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 7; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config deleted file mode 100644 index c675aab..0000000 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ /dev/null @@ -1,131 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 52 - - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 5 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 2 --gpgpu_n_sub_partition_per_mchannel 1 - -# Maxwell clock domains -#-gpgpu_clock_domains ::: -# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number. --gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 --gpgpu_occupancy_sm_number 52 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 2,1,1,2,1,1,2 --gpgpu_num_sp_units 8 --gpgpu_num_sfu_units 32 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 6,12,13,13,210 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 6,12,6,6,374 --ptx_opcode_initiation_fp 1,1,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,16,8,8,130 - --gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 --gmem_skip_L1D 1 --gpgpu_shmem_size 65536 - -# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 -#-gpgpu_shmem_size 16384 - -# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache --gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32 --gpgpu_cache:dl2_texture_only 0 - --gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_num_reg_banks 16 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 150 --dram_latency 130 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 300 - -# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 32 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5 is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS - -# GDDR5 timing from hynix H5GQ1H24AFR -# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" - -# Maxwell has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs -# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy. -# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present. --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx750Ti.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml deleted file mode 100755 index e2b2324..0000000 --- a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml +++ /dev/null @@ -1,539 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/Pascal_TITANX/config_fermi_islip.icnt b/configs/Pascal_TITANX/config_fermi_islip.icnt deleted file mode 100644 index 602daee..0000000 --- a/configs/Pascal_TITANX/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 52; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/Pascal_TITANX/gpgpusim.config b/configs/Pascal_TITANX/gpgpusim.config deleted file mode 100644 index f78bd02..0000000 --- a/configs/Pascal_TITANX/gpgpusim.config +++ /dev/null @@ -1,156 +0,0 @@ -# This config models the Pascal GP102 (NVIDIA TITAN X) -# For more info about this card, see Nvidia White paper -# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 61 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 12 --gpgpu_n_sub_partition_per_mchannel 2 - -# Pascal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA TITAN X clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 1 SFU unit -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,4,1,1,6 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# SFU is 32-width in pascal, then dp units initiation is 1 cycle --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,8,4,4,130 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory -# Pascal GP102 has 64KB L1 cache -# The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_shmem_size 98304 --gpgpu_shmem_size_PrefL1 98304 --gpgpu_shmem_size_PrefShared 98304 --gmem_skip_L1D 1 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 32:32:32:32 - -# 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 - -# enable operand collector -## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 20 --gpgpu_operand_collector_num_units_sfu 4 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 -# gpgpu_num_reg_banks should be increased to 32 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) -# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition -# the atom size of GDDR5X (the smallest read request) is 32 bytes --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5X is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing from hynix H5GQ1H24AFR -# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config deleted file mode 100644 index 6f836ee..0000000 --- a/configs/QuadroFX5600/gpgpusim.config +++ /dev/null @@ -1,99 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 12 - -# high level architecture configuration --gpgpu_n_clusters 8 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 6 --gpgpu_clock_domains 337.5:600.0:600.0:800.0 - -# shader core pipeline config --gpgpu_shader_registers 16384 --gpgpu_occupancy_sm_number 12 - --gpgpu_occupancy_sm_number 12 -#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though) --gpgpu_shader_core_pipeline 768:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 1,1,1,1,1,1,1 --gpgpu_num_sp_units 1 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 1,1,19,25,145 --ptx_opcode_initiation_int 1,1,4,4,32 --ptx_opcode_latency_fp 1,1,1,1,30 --ptx_opcode_initiation_fp 1,1,1,1,5 --ptx_opcode_latency_dp 8,8,8,8,335 --ptx_opcode_initiation_dp 8,8,8,8,130 - -# memory stage behaviour --gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 --gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4 --gpgpu_cache:dl2_texture_only 1 - -# TLB parameters -#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8 -#-gpgpu_tlbl2_latency 45 - - --gpgpu_shmem_warp_parts 2 - -# interconnection --network_mode 1 --inter_config_file icnt_config_islip.icnt - -# dram scheduler config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (30 core cycles). I.e. -# Total buffer space required = 30 x 800MHz / 337.5MHz = 71 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 55 - -# dram model config --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 4 --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS -# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz -# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 - - - -# Using cuobjdump to extract ptx/SASS --gpgpu_ptx_use_cuobjdump 1 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 - --visualizer_enabled 0 --power_trace_enabled 0 --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_quadrofx5600.xml - --steady_power_levels_enabled 1 --steady_state_definition 8,4 diff --git a/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml deleted file mode 100644 index 2c5a6fc..0000000 --- a/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/QuadroFX5600/icnt_config_islip.icnt b/configs/QuadroFX5600/icnt_config_islip.icnt deleted file mode 100644 index de3bcc8..0000000 --- a/configs/QuadroFX5600/icnt_config_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//14*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we donot use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 14; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/QuadroFX5800/config_quadro_islip.icnt b/configs/QuadroFX5800/config_quadro_islip.icnt deleted file mode 100644 index cfe9cac..0000000 --- a/configs/QuadroFX5800/config_quadro_islip.icnt +++ /dev/null @@ -1,69 +0,0 @@ -//18*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we donot use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 18; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config deleted file mode 100644 index fef1110..0000000 --- a/configs/QuadroFX5800/gpgpusim.config +++ /dev/null @@ -1,88 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 13 - -# high level architecture configuration --gpgpu_n_clusters 10 --gpgpu_n_cores_per_cluster 3 --gpgpu_n_mem 8 --gpgpu_clock_domains 325.0:650.0:650.0:800.0 - -# shader core pipeline config --gpgpu_shader_registers 16384 --gpgpu_occupancy_sm_number 13 - --gpgpu_shader_core_pipeline 1024:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 1,1,1,1,1,1,1 --gpgpu_num_sp_units 1 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 1,1,19,25,145 --ptx_opcode_initiation_int 1,1,4,4,32 --ptx_opcode_latency_fp 1,1,1,1,30 --ptx_opcode_initiation_fp 1,1,1,1,5 --ptx_opcode_latency_dp 8,8,8,8,335 --ptx_opcode_initiation_dp 8,8,8,8,130 - -# memory stage behaviour -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo --gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 --gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4 --gpgpu_cache:dl2_texture_only 1 - --gpgpu_shmem_warp_parts 2 - -# interconnection --network_mode 1 --inter_config_file config_quadro_islip.icnt - -# dram scheduler config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (30 core cycles). I.e. -# Total buffer space required = 30 x 800MHz / 325MHz = 74 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 58 - -# dram model config --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 4 --dram_data_command_freq_ratio 2 # GDDR3 is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS -# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz --gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 - --visualizer_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/TeslaC2050/config_fermi_islip.icnt b/configs/TeslaC2050/config_fermi_islip.icnt deleted file mode 100644 index a11bd8e..0000000 --- a/configs/TeslaC2050/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//20*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we donot use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 26; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config deleted file mode 100644 index 6ac2c12..0000000 --- a/configs/TeslaC2050/gpgpusim.config +++ /dev/null @@ -1,133 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 - -# Using cuobjdump to extract ptx/SASS -#-gpgpu_ptx_use_cuobjdump 1 # use default - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - - -# high level architecture configuration --gpgpu_n_clusters 14 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 6 --gpgpu_n_sub_partition_per_mchannel 2 - -# Fermi clock domains -#-gpgpu_clock_domains ::: -# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided -# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 575.0:575.0:575.0:750.0 - -# shader core pipeline config --gpgpu_shader_registers 32768 --gpgpu_occupancy_sm_number 20 - -# This implies a maximum of 48 warps/SM --gpgpu_shader_core_pipeline 1536:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 2,1,1,2,1,1,2 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,16,8,8,130 - - -# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. --gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 49152 - -# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 -#-gpgpu_shmem_size 16384 - -# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 --gpgpu_cache:dl2_texture_only 0 - --gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_num_reg_banks 16 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - --gpgpu_max_insn_issue_per_warp 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 750MHz / 575MHz = 130 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 114 - -# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5 is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS - -# GDDR5 timing from hynix H5GQ1H24AFR -# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt b/configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt new file mode 100644 index 0000000..7820e4e --- /dev/null +++ b/configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 27; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/deprecated-cfgs/GTX480/gpgpusim.config b/configs/deprecated-cfgs/GTX480/gpgpusim.config new file mode 100644 index 0000000..ee90c12 --- /dev/null +++ b/configs/deprecated-cfgs/GTX480/gpgpusim.config @@ -0,0 +1,134 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 15 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Fermi clock domains +#-gpgpu_clock_domains ::: +# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided +# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +-gpgpu_clock_domains 700.0:700.0:700.0:924.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 +-gpgpu_occupancy_sm_number 20 + +# This implies a maximum of 48 warps/SM +-gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,1,1,2,1,1,2 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,1,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + + +# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_shmem_size 49152 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 116 + +# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt new file mode 100644 index 0000000..069ca02 --- /dev/null +++ b/configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 7; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config b/configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config new file mode 100644 index 0000000..c675aab --- /dev/null +++ b/configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config @@ -0,0 +1,131 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 52 + + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 5 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 2 +-gpgpu_n_sub_partition_per_mchannel 1 + +# Maxwell clock domains +#-gpgpu_clock_domains ::: +# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number. +-gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 +-gpgpu_occupancy_sm_number 52 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,1,1,2,1,1,2 +-gpgpu_num_sp_units 8 +-gpgpu_num_sfu_units 32 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 6,12,13,13,210 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 6,12,6,6,374 +-ptx_opcode_initiation_fp 1,1,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + +-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gmem_skip_L1D 1 +-gpgpu_shmem_size 65536 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache +-gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 150 +-dram_latency 130 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 300 + +# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 32 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Maxwell has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy. +# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present. +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx750Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml new file mode 100755 index 0000000..e2b2324 --- /dev/null +++ b/configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml @@ -0,0 +1,539 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config b/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config new file mode 100644 index 0000000..6f836ee --- /dev/null +++ b/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config @@ -0,0 +1,99 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 12 + +# high level architecture configuration +-gpgpu_n_clusters 8 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 6 +-gpgpu_clock_domains 337.5:600.0:600.0:800.0 + +# shader core pipeline config +-gpgpu_shader_registers 16384 +-gpgpu_occupancy_sm_number 12 + +-gpgpu_occupancy_sm_number 12 +#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though) +-gpgpu_shader_core_pipeline 768:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,1,1,1,1,1,1 +-gpgpu_num_sp_units 1 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 1,1,19,25,145 +-ptx_opcode_initiation_int 1,1,4,4,32 +-ptx_opcode_latency_fp 1,1,1,1,30 +-ptx_opcode_initiation_fp 1,1,1,1,5 +-ptx_opcode_latency_dp 8,8,8,8,335 +-ptx_opcode_initiation_dp 8,8,8,8,130 + +# memory stage behaviour +-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 +-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4 +-gpgpu_cache:dl2_texture_only 1 + +# TLB parameters +#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8 +#-gpgpu_tlbl2_latency 45 + + +-gpgpu_shmem_warp_parts 2 + +# interconnection +-network_mode 1 +-inter_config_file icnt_config_islip.icnt + +# dram scheduler config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (30 core cycles). I.e. +# Total buffer space required = 30 x 800MHz / 337.5MHz = 71 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 55 + +# dram model config +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 4 +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS +# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz +# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 + + + +# Using cuobjdump to extract ptx/SASS +-gpgpu_ptx_use_cuobjdump 1 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 + +-visualizer_enabled 0 +-power_trace_enabled 0 +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_quadrofx5600.xml + +-steady_power_levels_enabled 1 +-steady_state_definition 8,4 diff --git a/configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml new file mode 100644 index 0000000..2c5a6fc --- /dev/null +++ b/configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt b/configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt new file mode 100644 index 0000000..de3bcc8 --- /dev/null +++ b/configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt @@ -0,0 +1,70 @@ +//14*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we donot use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 14; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt b/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt new file mode 100644 index 0000000..cfe9cac --- /dev/null +++ b/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt @@ -0,0 +1,69 @@ +//18*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we donot use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 18; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config b/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config new file mode 100644 index 0000000..fef1110 --- /dev/null +++ b/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config @@ -0,0 +1,88 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 13 + +# high level architecture configuration +-gpgpu_n_clusters 10 +-gpgpu_n_cores_per_cluster 3 +-gpgpu_n_mem 8 +-gpgpu_clock_domains 325.0:650.0:650.0:800.0 + +# shader core pipeline config +-gpgpu_shader_registers 16384 +-gpgpu_occupancy_sm_number 13 + +-gpgpu_shader_core_pipeline 1024:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,1,1,1,1,1,1 +-gpgpu_num_sp_units 1 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 1,1,19,25,145 +-ptx_opcode_initiation_int 1,1,4,4,32 +-ptx_opcode_latency_fp 1,1,1,1,30 +-ptx_opcode_initiation_fp 1,1,1,1,5 +-ptx_opcode_latency_dp 8,8,8,8,335 +-ptx_opcode_initiation_dp 8,8,8,8,130 + +# memory stage behaviour +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 +-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4 +-gpgpu_cache:dl2_texture_only 1 + +-gpgpu_shmem_warp_parts 2 + +# interconnection +-network_mode 1 +-inter_config_file config_quadro_islip.icnt + +# dram scheduler config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (30 core cycles). I.e. +# Total buffer space required = 30 x 800MHz / 325MHz = 74 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 58 + +# dram model config +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 4 +-dram_data_command_freq_ratio 2 # GDDR3 is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS +# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz +-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 + +-visualizer_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt new file mode 100644 index 0000000..2a69ddd --- /dev/null +++ b/configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 50; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config new file mode 100644 index 0000000..fb044c6 --- /dev/null +++ b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config @@ -0,0 +1,150 @@ +# This config models the Pascal GP102 (GeForceGTX 1080Ti) + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 60 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 11 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 +-gpgpu_occupancy_sm_number 60 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 1,2,1,1,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The default is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) +# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml b/configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml new file mode 100755 index 0000000..02619ff --- /dev/null +++ b/configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt new file mode 100644 index 0000000..d26c8d9 --- /dev/null +++ b/configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 60; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/deprecated-cfgs/SM6_P100/gpgpusim.config b/configs/deprecated-cfgs/SM6_P100/gpgpusim.config new file mode 100644 index 0000000..a5e6736 --- /dev/null +++ b/configs/deprecated-cfgs/SM6_P100/gpgpusim.config @@ -0,0 +1,156 @@ +# This config models the Pascal GP100 +# For more info about this card, see Nvidia White paper +# https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 60 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 32 +-gpgpu_n_sub_partition_per_mchannel 1 + +# Pscal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Nvidia_Tesla +-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 2,2,1,2,2,1,4 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 2,2,2,2,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +# Pascal GP100 has 48KB L1 cache +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 65536 +-gpgpu_shmem_size_PrefShared 65536 +-gmem_skip_L1D 0 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 14 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_units_mem 10 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt new file mode 100644 index 0000000..602daee --- /dev/null +++ b/configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config b/configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config new file mode 100644 index 0000000..28912a3 --- /dev/null +++ b/configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config @@ -0,0 +1,157 @@ +# This config models the Pascal GP102 (NVIDIA TITAN X) +# For more info about this card, see Nvidia White paper +# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 61 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 +-gpgpu_occupancy_sm_number 61 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,8,4,4,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The defulat is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_shmem_size 98304 +-gpgpu_shmem_size_PrefL1 98304 +-gpgpu_shmem_size_PrefShared 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt new file mode 100644 index 0000000..fac792a --- /dev/null +++ b/configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 64; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config b/configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config new file mode 100644 index 0000000..aefb04a --- /dev/null +++ b/configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config @@ -0,0 +1,165 @@ +# This config models the Volta Titan X +# For more info about this card: +# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf +# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf +# https://devblogs.nvidia.com/inside-volta/ +# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 40 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 24 +-gpgpu_n_sub_partition_per_mchannel 1 + +# volta clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0 +# boost mode +# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,4,1,4,4,1,9 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Volta GV100 has 64KB Shared memory +-gpgpu_cache:dl1 64:128:8,L:L:m:N:H,A:256:8,16:0 +-gpgpu_cache:dl1PrefL1 64:128:16,L:L:m:N:H,A:256:8,16:0 +-gpgpu_cache:dl1PrefShared 32:128:6,L:L:m:N:H,A:256:8,16:0 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 1 +-gpgpu_shmem_size_PrefShared 98304 +-gmem_skip_L1D 0 + +# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache +-gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 + +# 128 KB Inst. +-gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 14 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_units_mem 10 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt b/configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt new file mode 100644 index 0000000..a11bd8e --- /dev/null +++ b/configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//20*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we donot use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 26; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; diff --git a/configs/deprecated-cfgs/TeslaC2050/gpgpusim.config b/configs/deprecated-cfgs/TeslaC2050/gpgpusim.config new file mode 100644 index 0000000..6ac2c12 --- /dev/null +++ b/configs/deprecated-cfgs/TeslaC2050/gpgpusim.config @@ -0,0 +1,133 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + +# Using cuobjdump to extract ptx/SASS +#-gpgpu_ptx_use_cuobjdump 1 # use default + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + + +# high level architecture configuration +-gpgpu_n_clusters 14 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Fermi clock domains +#-gpgpu_clock_domains ::: +# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided +# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +-gpgpu_clock_domains 575.0:575.0:575.0:750.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 +-gpgpu_occupancy_sm_number 20 + +# This implies a maximum of 48 warps/SM +-gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,1,1,2,1,1,2 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,1,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + + +# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_shmem_size 49152 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 750MHz / 575MHz = 130 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 114 + +# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt b/configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt new file mode 100644 index 0000000..c399db9 --- /dev/null +++ b/configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 27; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 64; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config new file mode 100644 index 0000000..4096b09 --- /dev/null +++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config @@ -0,0 +1,153 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 15 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Fermi clock domains +#-gpgpu_clock_domains ::: +# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided +# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +-gpgpu_clock_domains 700.0:700.0:700.0:924.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 +-gpgpu_occupancy_sm_number 20 + +# This implies a maximum of 48 warps/SM +-gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +#For Fermi, DP unit =0, DP inst is executed on SFU +-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,1,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + + +# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,S:64:8,8 +-gpgpu_shmem_size 49152 +-icnt_flit_size 40 +-gmem_skip_L1D 0 +-gpgpu_n_cluster_ejection_buffer_size 32 +-l1_latency 35 +-smem_latency 26 +-gpgpu_flush_l1_cache 1 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,S:64:8,8 +#-gpgpu_shmem_size 16384 + +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 S:64:128:8,L:B:m:L:L,A:256:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-perf_sim_memcpy 1 +-memory_partition_indexing 0 + +-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4 +-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,T:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,S:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 20 + +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml b/configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt new file mode 100644 index 0000000..dec4789 --- /dev/null +++ b/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt @@ -0,0 +1,73 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 64; +input_buffer_size = 256; +ejection_buffer_size = 64; +boundary_buffer_size = 64; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config new file mode 100644 index 0000000..3842508 --- /dev/null +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -0,0 +1,185 @@ +# This config models the Pascal GP102 (NVIDIA TITAN X) +# For more info about this card, see Nvidia White paper +# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 61 +-gpgpu_ignore_resources_limitation 1 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +# P102 has two semi-indp scheds per core, and two cores per cluster +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 +-gpgpu_occupancy_sm_number 62 + +# This implies a maximum of 32 warps/SM +-gpgpu_shader_core_pipeline 1024:32 +-gpgpu_shader_cta 16 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 4 SFU units +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 2 +-gpgpu_num_dp_units 1 + + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,8,8,8,130 +-ptx_opcode_initiation_sfu 4 +-ptx_opcode_latency_sfu 8 + + +# latencies and cache configs are adopted from: +# https://arxiv.org/pdf/1804.06826.pdf +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB +# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache +# The defulat is to disable the L1 cache, unless cache modifieres are used +-gpgpu_cache:dl1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_shmem_size 49152 +-gpgpu_shmem_size_PrefL1 49152 +-gpgpu_shmem_size_PrefShared 49152 +# By default, L1 cache is disabled in Pascal P102. +# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1 +-gmem_skip_L1D 1 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 +-l1_latency 82 +-smem_latency 24 +-gpgpu_flush_l1_cache 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 +-perf_sim_memcpy 1 + +# 4 KB Inst. +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_operand_collector_num_in_ports_sfu 2 +-gpgpu_operand_collector_num_out_ports_sfu 2 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +# Use Pascal Coalsce arhitetecture +-gpgpu_coalesce_arch 61 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 240 + +# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" + +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Pascal 102 has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 102 +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt new file mode 100644 index 0000000..2f25889 --- /dev/null +++ b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt @@ -0,0 +1,74 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 64; +n = 1; + +// Routing + +routing_function = dest_tag; + + +// Flow control + +num_vcs = 1; +vc_buf_size = 256; +input_buffer_size = 256; +ejection_buffer_size = 256; +boundary_buffer_size = 256; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config new file mode 100644 index 0000000..c8351da --- /dev/null +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -0,0 +1,191 @@ +# This config models the Volta Titan X +# For more info about this card: +# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf +# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf +# https://devblogs.nvidia.com/inside-volta/ +# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 40 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 24 +-gpgpu_n_sub_partition_per_mchannel 1 + +# volta clock domains +#-gpgpu_clock_domains ::: +# Volta NVIDIA GV100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +-gpgpu_clock_domains 1200.0:2000.0:1200.0:850.0 +# boost mode +# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 +-gpgpu_occupancy_sm_number 70 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 +-gpgpu_num_dp_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 +-ptx_opcode_latency_sfu 100 +-ptx_opcode_initiation_sfu 8 + + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Defualt config is 32KB DL1 and 96KB shared memory +# In Volta, we assign the remaining shared memory to L1 cache +# if the assigned shd mem = 0, then L1 cache = 128KB +# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x +# disable this mode in case of multi kernels/apps execution +-adpative_volta_cache_config 1 +-gpgpu_cache:dl1 S:4:128:64,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 0 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 +-l1_latency 28 +-smem_latency 19 +-gpgpu_flush_l1_cache 1 + +# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache +-gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-perf_sim_memcpy 1 + +# 128 KB Inst. +-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 192 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# HBM has dual bus interface, in which it can issue two col and row commands at a time +-dual_bus_interface 1 +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Pascal has two schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 100 +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/cuobjdump_to_ptxplus/ptx_parser.h b/cuobjdump_to_ptxplus/ptx_parser.h index a534e92..ee7a942 100644 --- a/cuobjdump_to_ptxplus/ptx_parser.h +++ b/cuobjdump_to_ptxplus/ptx_parser.h @@ -376,4 +376,8 @@ void func_header_info_int(const char* s, int i) g_headerList->getListEnd().addOperand(buff); } } + +void maxnt_id(int x, int y, int z) { + +} #endif //_PTX_PARSER_H_ diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index d67fd85..61af0ee 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -338,10 +338,19 @@ struct _cuda_device_id *GPGPUSim_Init() prop->minor = 2; prop->totalGlobalMem = 0x80000000 /* 2 GB */; prop->memPitch = 0; - prop->maxThreadsPerBlock = 512; - prop->maxThreadsDim[0] = 512; - prop->maxThreadsDim[1] = 512; - prop->maxThreadsDim[2] = 512; + if(prop->major >= 2) { + prop->maxThreadsPerBlock = 1024; + prop->maxThreadsDim[0] = 1024; + prop->maxThreadsDim[1] = 1024; + } + else + { + prop->maxThreadsPerBlock = 512; + prop->maxThreadsDim[0] = 512; + prop->maxThreadsDim[1] = 512; + } + + prop->maxThreadsDim[2] = 64; prop->maxGridSize[0] = 0x40000000; prop->maxGridSize[1] = 0x40000000; prop->maxGridSize[2] = 0x40000000; @@ -353,6 +362,9 @@ struct _cuda_device_id *GPGPUSim_Init() prop->clockRate = the_gpu->shader_clock(); #if (CUDART_VERSION >= 2010) prop->multiProcessorCount = the_gpu->get_config().num_shader(); +#endif +#if (CUDART_VERSION >= 4000) + prop->maxThreadsPerMultiProcessor = the_gpu->threads_per_core(); #endif the_gpu->set_prop(prop); the_device = new _cuda_device_id(the_gpu); @@ -2167,8 +2179,28 @@ cudaError_t CUDARTAPI cudaSetValidDevices(int *device_arr, int len) cudaError_t CUDARTAPI cudaSetDeviceFlags( int flags ) { - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; + // This flag is implicitly always on (unless you are using the driver API). It is safe for GPGPU-Sim to + // just ignore it. + if ( cudaDeviceMapHost == flags ) { + return g_last_cudaError = cudaSuccess; + } else { + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; + } +} + +size_t getMaxThreadsPerBlock(struct cudaFuncAttributes *attr) { + _cuda_device_id *dev = GPGPUSim_Init(); + struct cudaDeviceProp prop; + + prop = *dev->get_prop(); + + size_t max = prop.maxThreadsPerBlock; + + if ((prop.regsPerBlock / attr->numRegs) < max) + max = prop.regsPerBlock / attr->numRegs; + + return max; } cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, const char *hostFun ) @@ -2181,7 +2213,10 @@ cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, con attr->constSizeBytes = kinfo->cmem; attr->localSizeBytes = kinfo->lmem; attr->numRegs = kinfo->regs; - attr->maxThreadsPerBlock = 0; // from pragmas? + if(kinfo->maxthreads > 0) + attr->maxThreadsPerBlock = kinfo->maxthreads; + else + attr->maxThreadsPerBlock = getMaxThreadsPerBlock(attr); #if CUDART_VERSION >= 3000 attr->ptxVersion = kinfo->ptx_version; attr->binaryVersion = kinfo->sm_target; diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile new file mode 100644 index 0000000..5221b3b --- /dev/null +++ b/nightly.jenkinsfile @@ -0,0 +1,75 @@ +pipeline { + agent { + label "purdue-cluster" + } + + options { + disableConcurrentBuilds() + overrideIndexTriggers(true) + } + + triggers { + pollSCM('0 1 * * *') + } + + stages { + stage('nightly-simulator-build') { + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + } + } + stage('nightly-simulations-build'){ + steps{ + sh 'rm -rf gpgpu-sim_simulations' + sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + cd gpgpu-sim_simulations && \ + git checkout purdue-cluster && \ + git pull && \ + ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -i -j -C ./benchmarks/src/ all && \ + make -C ./benchmarks/src data' + } + } + stage('nightly-2B-insn-run'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C TITANX-2B,TITANX-L1ON-2B,P100-2B,TITANV-2B -N nightly-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/getstats" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -I -S 1800 -v -s stats-$$.csv -N nightly-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + } + } + stage('nightly-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + PLOTDIR="jenkins/${JOB_NAME}" &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C TITANX-2B,TITANX-L1ON-2B,P100-2B,TITANV-2B > nightly-stats-per-kernel-9.1.csv &&\ + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh nightly-stats-per-kernel-9.1.csv $PLOTDIR ${BUILD_NUMBER}' + } + } + } + post { + success { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!", + to: 'tgrogers@purdue.edu' + } + failure { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}", + to: 'tgrogers@purdue.edu' + } + } +} diff --git a/setup_environment b/setup_environment index f1af978..9578942 100644 --- a/setup_environment +++ b/setup_environment @@ -1,6 +1,6 @@ # see README before running this -ps -p $$ | awk '/bash/ || / sh/ || /zsh/ {exit 1;}' && echo "ERROR ** source setup_environment must be run in a bash, zsh or sh shell; see README" && exit +ps -p $$ | awk '/bash/ || / sh/ || /zsh/ {exit 1;}' && echo "WARNING ** source setup_environment must be run in a bash, zsh or sh shell; see README" export GPGPUSIM_SETUP_ENVIRONMENT_WAS_RUN= export GPGPUSIM_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )" diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index f7f1016..acb376a 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -316,12 +316,12 @@ void warp_inst_t::generate_mem_accesses() break; case global_space: case local_space: case param_space_local: - if( m_config->gpgpu_coalesce_arch == 13 ) { - if(isatomic()) - memory_coalescing_arch_13_atomic(is_write, access_type); - else - memory_coalescing_arch_13(is_write, access_type); - } else abort(); + if( m_config->gpgpu_coalesce_arch >= 13 && m_config->gpgpu_coalesce_arch <= 62) { + if(isatomic()) + memory_coalescing_arch_atomic(is_write, access_type); + else + memory_coalescing_arch(is_write, access_type); + } else abort(); break; @@ -345,7 +345,7 @@ void warp_inst_t::generate_mem_accesses() byte_mask.set(idx+i); } for( a=accesses.begin(); a != accesses.end(); ++a ) - m_accessq.push_back( mem_access_t(access_type,a->first,cache_block_size,is_write,a->second,byte_mask) ); + m_accessq.push_back( mem_access_t(access_type,a->first,cache_block_size,is_write,a->second, byte_mask, mem_access_sector_mask_t())); } if ( space.get_type() == global_space ) { @@ -354,15 +354,32 @@ void warp_inst_t::generate_mem_accesses() m_mem_accesses_created=true; } -void warp_inst_t::memory_coalescing_arch_13( bool is_write, mem_access_type access_type ) +void warp_inst_t::memory_coalescing_arch( bool is_write, mem_access_type access_type ) { // see the CUDA manual where it discusses coalescing rules before reading this unsigned segment_size = 0; unsigned warp_parts = m_config->mem_warp_parts; + bool sector_segment_size = false; + + if(m_config->gpgpu_coalesce_arch >= 20 && m_config->gpgpu_coalesce_arch < 39) + { + //Fermi and Kepler, L1 is normal and L2 is sector + if(m_config->gmem_skip_L1D || cache_op == CACHE_GLOBAL) + sector_segment_size = true; + else + sector_segment_size = false; + } + else if(m_config->gpgpu_coalesce_arch >= 40) + { + //Maxwell and Pascal, L1 and L2 are sectors + //all requests should be 32 bytes + sector_segment_size = true; + } + switch( data_size ) { case 1: segment_size = 32; break; - case 2: segment_size = 64; break; - case 4: case 8: case 16: segment_size = 128; break; + case 2: segment_size = sector_segment_size? 32 : 64; break; + case 4: case 8: case 16: segment_size = sector_segment_size? 32 : 128; break; } unsigned subwarp_size = m_config->warp_size / warp_parts; @@ -413,13 +430,13 @@ void warp_inst_t::memory_coalescing_arch_13( bool is_write, mem_access_type acce new_addr_type addr = t->first; const transaction_info &info = t->second; - memory_coalescing_arch_13_reduce_and_send(is_write, access_type, info, addr, segment_size); + memory_coalescing_arch_reduce_and_send(is_write, access_type, info, addr, segment_size); } } } -void warp_inst_t::memory_coalescing_arch_13_atomic( bool is_write, mem_access_type access_type ) +void warp_inst_t::memory_coalescing_arch_atomic( bool is_write, mem_access_type access_type ) { assert(space.get_type() == global_space); // Atomics allowed only for global memory @@ -488,13 +505,13 @@ void warp_inst_t::memory_coalescing_arch_13_atomic( bool is_write, mem_access_ty for(t=transaction_list.begin(); t!=transaction_list.end(); t++) { // For each transaction const transaction_info &info = *t; - memory_coalescing_arch_13_reduce_and_send(is_write, access_type, info, addr, segment_size); + memory_coalescing_arch_reduce_and_send(is_write, access_type, info, addr, segment_size); } } } } -void warp_inst_t::memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size ) +void warp_inst_t::memory_coalescing_arch_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size ) { assert( (addr & (segment_size-1)) == 0 ); @@ -543,7 +560,7 @@ void warp_inst_t::memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_ assert(lower_half_used && upper_half_used); } } - m_accessq.push_back( mem_access_t(access_type,addr,size,is_write,info.active,info.bytes) ); + m_accessq.push_back( mem_access_t(access_type,addr,size,is_write,info.active,info.bytes, info.chunks) ); } void warp_inst_t::completed( unsigned long long cycle ) const @@ -577,6 +594,8 @@ kernel_info_t::kernel_info_t( dim3 gridDim, dim3 blockDim, class function_info * //Jin: launch latency management m_launch_latency = g_kernel_launch_latency; + + volta_cache_config_set=false; } kernel_info_t::~kernel_info_t() diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 71d3d89..a612bac 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -82,6 +82,7 @@ enum uarch_op_t { ALU_OP=1, SFU_OP, TENSOR_CORE_OP, + DP_OP, ALU_SFU_OP, LOAD_OP, TENSOR_CORE_LOAD_OP, @@ -139,6 +140,7 @@ typedef enum special_operations_t special_ops; // Required to identify for the p enum operation_pipeline_t { UNKOWN_OP, SP__OP, + DP__OP, SFU__OP, TENSOR_CORE__OP, MEM__OP @@ -308,6 +310,8 @@ public: unsigned long long start_cycle; unsigned long long end_cycle; unsigned m_launch_latency; + + mutable bool volta_cache_config_set; }; struct core_config { @@ -347,6 +351,7 @@ struct core_config { unsigned gpgpu_cache_constl1_linesize; unsigned gpgpu_max_insn_issue_per_warp; + bool gmem_skip_L1D; // on = global memory access always skip the L1 cache }; // bounded stack that implements simt reconvergence using pdom mechanism from MICRO'07 paper @@ -398,6 +403,7 @@ protected: #define LOCAL_MEM_SIZE_MAX (8*1024) #define MAX_STREAMING_MULTIPROCESSORS 64 #define MAX_THREAD_PER_SM 2048 +#define MAX_WARP_PER_SM 64 #define TOTAL_LOCAL_MEM_PER_SM (MAX_THREAD_PER_SM*LOCAL_MEM_SIZE_MAX) #define TOTAL_SHARED_MEM (MAX_STREAMING_MULTIPROCESSORS*SHARED_MEM_SIZE_MAX) #define TOTAL_LOCAL_MEM (MAX_STREAMING_MULTIPROCESSORS*MAX_THREAD_PER_SM*LOCAL_MEM_SIZE_MAX) @@ -523,7 +529,14 @@ public: const struct textureReference* get_texref(const std::string &texname) const { std::map::const_iterator t=m_NameToTextureRef.find(texname); - assert( t != m_NameToTextureRef.end() ); + if( t == m_NameToTextureRef.end() ) { + // search for :: prefixed names + std::string temp("::" + texname); + t=m_NameToTextureRef.find(temp); + } + + assert(t != m_NameToTextureRef.end()); + return t->second; } const struct cudaArray* get_texarray( const struct textureReference *texref ) const @@ -574,6 +587,7 @@ struct gpgpu_ptx_sim_info int cmem; int gmem; int regs; + unsigned maxthreads; unsigned ptx_version; unsigned sm_target; }; @@ -625,6 +639,9 @@ private: const unsigned MAX_MEMORY_ACCESS_SIZE = 128; typedef std::bitset mem_access_byte_mask_t; +const unsigned SECTOR_CHUNCK_SIZE = 4; //four sectors +const unsigned SECTOR_SIZE = 32 ; //sector is 32 bytes width +typedef std::bitset mem_access_sector_mask_t; #define NO_PARTIAL_WRITE (mem_access_byte_mask_t()) #define MEM_ACCESS_TYPE_TUP_DEF \ @@ -660,6 +677,7 @@ enum cache_operator_type { CACHE_ALL, // .ca CACHE_LAST_USE, // .lu CACHE_VOLATILE, // .cv + CACHE_L1, // .nc // loads and stores CACHE_STREAMING, // .cs @@ -689,8 +707,9 @@ public: unsigned size, bool wr, const active_mask_t &active_mask, - const mem_access_byte_mask_t &byte_mask ) - : m_warp_mask(active_mask), m_byte_mask(byte_mask) + const mem_access_byte_mask_t &byte_mask, + const mem_access_sector_mask_t §or_mask) + : m_warp_mask(active_mask), m_byte_mask(byte_mask), m_sector_mask(sector_mask) { init(); m_type = type; @@ -706,6 +725,7 @@ public: bool is_write() const { return m_write; } enum mem_access_type get_type() const { return m_type; } mem_access_byte_mask_t get_byte_mask() const { return m_byte_mask; } + mem_access_sector_mask_t get_sector_mask() const { return m_sector_mask; } void print(FILE *fp) const { @@ -739,6 +759,7 @@ private: mem_access_type m_type; active_mask_t m_warp_mask; mem_access_byte_mask_t m_byte_mask; + mem_access_sector_mask_t m_sector_mask; static unsigned sm_next_access_uid; }; @@ -961,9 +982,9 @@ public: }; void generate_mem_accesses(); - void memory_coalescing_arch_13( bool is_write, mem_access_type access_type ); - void memory_coalescing_arch_13_atomic( bool is_write, mem_access_type access_type ); - void memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size ); + void memory_coalescing_arch( bool is_write, mem_access_type access_type ); + void memory_coalescing_arch_atomic( bool is_write, mem_access_type access_type ); + void memory_coalescing_arch_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size ); void add_callback( unsigned lane_id, void (*function)(const class inst_t*, class ptx_thread_info*), diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index d5c5c3d..87a0b9c 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -62,8 +62,8 @@ addr_t g_debug_pc = 0xBEEF1518; unsigned g_ptx_sim_num_insn = 0; unsigned gpgpu_param_num_shaders = 0; -char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp; -char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; +char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp,*opcode_latency_sfu; +char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp,*opcode_initiation_sfu; char *cdp_latency_str; unsigned cdp_latency[5]; @@ -80,6 +80,10 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Opcode latencies for double precision floating points " "Default 8,8,8,8,335", "8,8,8,8,335"); + option_parser_register(opp, "-ptx_opcode_latency_sfu", OPT_CSTR, &opcode_latency_sfu, + "Opcode latencies for SFU instructions" + "Default 8", + "8"); option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, "Opcode initiation intervals for integers " "Default 1,1,4,4,32", @@ -92,6 +96,10 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Opcode initiation intervals for double precision floating points " "Default 8,8,8,8,130", "8,8,8,8,130"); + option_parser_register(opp, "-ptx_opcode_initiation_sfu", OPT_CSTR, &opcode_initiation_sfu, + "Opcode initiation intervals for sfu instructions" + "Default 8", + "8"); option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str, "CDP API latency write(dst_start_addr+n,1, src_data+n,NULL,NULL); + + // Copy into the performance model. + extern gpgpu_sim* g_the_gpu; + g_the_gpu->perf_memcpy_to_gpu(dst_start_addr, count); if(g_debug_execution >= 3) { printf( " done.\n"); fflush(stdout); @@ -408,6 +420,10 @@ void gpgpu_t::memcpy_from_gpu( void *dst, size_t src_start_addr, size_t count ) unsigned char *dst_data = (unsigned char*)dst; for (unsigned n=0; n < count; n ++ ) m_global_mem->read(src_start_addr+n,1,dst_data+n); + + // Copy into the performance model. + extern gpgpu_sim* g_the_gpu; + g_the_gpu->perf_memcpy_to_gpu(src_start_addr, count); if(g_debug_execution >= 3) { printf( " done.\n"); fflush(stdout); @@ -592,9 +608,11 @@ void ptx_instruction::set_opcode_and_latency() unsigned int_latency[5]; unsigned fp_latency[5]; unsigned dp_latency[5]; + unsigned sfu_latency; unsigned int_init[5]; unsigned fp_init[5]; unsigned dp_init[5]; + unsigned sfu_init; /* * [0] ADD,SUB * [1] MAX,Min @@ -611,7 +629,9 @@ void ptx_instruction::set_opcode_and_latency() sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", &dp_latency[0],&dp_latency[1],&dp_latency[2], &dp_latency[3],&dp_latency[4]); - sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u, %u", + sscanf(opcode_latency_sfu, "%u", + &sfu_latency); + sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u", &int_init[0],&int_init[1],&int_init[2], &int_init[3],&int_init[4]); sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", @@ -620,8 +640,10 @@ void ptx_instruction::set_opcode_and_latency() sscanf(opcode_initiation_dp, "%u,%u,%u,%u,%u", &dp_init[0],&dp_init[1],&dp_init[2], &dp_init[3],&dp_init[4]); + sscanf(opcode_initiation_sfu, "%u", + &sfu_init); sscanf(cdp_latency_str, "%u,%u,%u,%u,%u", - &cdp_latency[0],&cdp_latency[1],&cdp_latency[2], + &cdp_latency[0],&cdp_latency[1],&cdp_latency[2], &cdp_latency[3],&cdp_latency[4]); if(!m_operands.empty()){ @@ -684,6 +706,7 @@ void ptx_instruction::set_opcode_and_latency() case FF64_TYPE: latency = dp_latency[0]; initiation_interval = dp_init[0]; + op = DP_OP; break; case B32_TYPE: case U32_TYPE: @@ -705,6 +728,7 @@ void ptx_instruction::set_opcode_and_latency() case FF64_TYPE: latency = dp_latency[1]; initiation_interval = dp_init[1]; + op = DP_OP; break; case B32_TYPE: case U32_TYPE: @@ -721,13 +745,12 @@ void ptx_instruction::set_opcode_and_latency() case F32_TYPE: latency = fp_latency[2]; initiation_interval = fp_init[2]; - op = ALU_SFU_OP; break; case F64_TYPE: case FF64_TYPE: latency = dp_latency[2]; initiation_interval = dp_init[2]; - op = ALU_SFU_OP; + op = DP_OP; break; case B32_TYPE: case U32_TYPE: @@ -750,6 +773,7 @@ void ptx_instruction::set_opcode_and_latency() case FF64_TYPE: latency = dp_latency[3]; initiation_interval = dp_init[3]; + op = DP_OP; break; case B32_TYPE: case U32_TYPE: @@ -785,8 +809,8 @@ void ptx_instruction::set_opcode_and_latency() break; case SQRT_OP: case SIN_OP: case COS_OP: case EX2_OP: case LG2_OP: case RSQRT_OP: case RCP_OP: //Using double to approximate those - latency = dp_latency[2]; - initiation_interval = dp_init[2]; + latency = sfu_latency; + initiation_interval = sfu_init; op = SFU_OP; break; case MMA_OP: @@ -796,7 +820,7 @@ void ptx_instruction::set_opcode_and_latency() break; case SHFL_OP: latency = 32; - initiation_interval = 15; + initiation_interval = 4; break; default: break; @@ -889,6 +913,7 @@ void ptx_instruction::pre_decode() switch( m_cache_option ) { case CA_OPTION: cache_op = CACHE_ALL; break; + case NC_OPTION: cache_op = CACHE_L1; break; case CG_OPTION: cache_op = CACHE_GLOBAL; break; case CS_OPTION: cache_op = CACHE_STREAMING; break; case LU_OPTION: cache_op = CACHE_LAST_USE; break; @@ -1169,13 +1194,13 @@ void function_info::finalize( memory_space *param_mem ) // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over //Jin: copy parameter using aligned rules const size_t word_size = 4; - param_address = (param_address + size - 1) / size * size; //aligned with size + //param_address = (param_address + size - 1) / size * size; //aligned with size TODO: align not correct for (size_t idx = 0; idx < size; idx += word_size) { const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); } unsigned offset = p.get_offset(); - assert(offset == param_address); + //assert(offset == param_address); param->set_address(param_address); param_address += size; } diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 4614f25..973eeab 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -33,6 +33,7 @@ #include "ptx.tab.h" #include #include +#include #include #include "cuda-math.h" #include "../abstract_hardware_model.h" diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 8b901a3..45392fb 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -237,7 +237,8 @@ function_defn: function_decl { set_symtab($1); func_header(".skip"); } statement block_spec: MAXNTID_DIRECTIVE INT_OPERAND COMMA INT_OPERAND COMMA INT_OPERAND {func_header_info_int(".maxntid", $2); func_header_info_int(",", $4); - func_header_info_int(",", $6); } + func_header_info_int(",", $6); + maxnt_id($2, $4, $6);} | MINNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".minnctapersm", $2); printf("GPGPU-Sim: Warning: .minnctapersm ignored. \n"); } | MAXNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".maxnctapersm", $2); printf("GPGPU-Sim: Warning: .maxnctapersm ignored. \n"); } ; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index d12c741..1813f8c 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -222,6 +222,7 @@ bool symbol_table::add_function_decl( const char *name, int entry_point, functio } else { *func_info = new function_info(entry_point); (*func_info)->set_name(name); + (*func_info)->set_maxnt_id(0); m_function_info_lookup[key] = *func_info; } @@ -1234,16 +1235,16 @@ ptx_instruction::ptx_instruction( int opcode, m_inst_size = 4; // bytes break; case EXTP_OPTION: - break; + break; case NC_OPTION: - break; + m_cache_option = last_ptx_inst_option; + break; case UP_OPTION: case DOWN_OPTION: case BFLY_OPTION: case IDX_OPTION: m_shfl_op = last_ptx_inst_option; break; - case PRMT_F4E_MODE: case PRMT_B4E_MODE: case PRMT_RC8_MODE: diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 0767379..4c36cfc 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1333,6 +1333,7 @@ public: const struct gpgpu_ptx_sim_info* get_kernel_info () const { + assert (m_kernel_info.maxthreads == maxnt_id); return &m_kernel_info; } @@ -1340,6 +1341,8 @@ public: m_kernel_info = info; m_kernel_info.ptx_version = 10*get_ptx_version().ver(); m_kernel_info.sm_target = get_ptx_version().target(); + // THIS DEPENDS ON ptxas being called after the PTX is parsed. + m_kernel_info.maxthreads = maxnt_id; } symbol_table *get_symtab() { @@ -1363,7 +1366,11 @@ public: } bool is_entry_point() const { return m_entry_point; } + void set_maxnt_id(unsigned maxthreads) { maxnt_id = maxthreads;} + unsigned get_maxnt_id() { return maxnt_id;} + private: + unsigned maxnt_id; unsigned m_uid; unsigned m_local_mem_framesize; bool m_entry_point; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 9671ab7..cf40365 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -1012,6 +1012,10 @@ void target_header3(char* a, char* b, char* c) g_global_symbol_table->set_sm_target(a,b,c); } +void maxnt_id(int x, int y, int z) { + g_func_info->set_maxnt_id(x * y * z); +} + void func_header(const char* a) {} //intentional dummy function void func_header_info(const char* a) {} //intentional dummy function void func_header_info_int(const char* a, int b) {} //intentional dummy function diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h index 8094b43..7b6e3a2 100644 --- a/src/cuda-sim/ptx_parser.h +++ b/src/cuda-sim/ptx_parser.h @@ -95,6 +95,7 @@ void change_double_operand_type( int addr_type ); void change_operand_neg( ); void set_immediate_operand_type( ); void version_header(double a); +void maxnt_id(int x, int y, int z); //Jin: handle instructino group for cdp void start_inst_group(); diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc index 422576d..8651869 100644 --- a/src/gpgpu-sim/addrdec.cc +++ b/src/gpgpu-sim/addrdec.cc @@ -62,6 +62,9 @@ void linear_to_raw_address_translation::addrdec_setoption(option_parser_t opp) option_parser_register(opp, "-gpgpu_mem_address_mask", OPT_INT32, &gpgpu_mem_address_mask, "0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits", "0"); + option_parser_register(opp, "-memory_partition_indexing", OPT_UINT32, &memory_partition_indexing, + "0 = no indexing, 1 = bitwise xoring, 2 = IPoly, 3 = custom indexing", + "0"); } new_addr_type linear_to_raw_address_translation::partition_address( new_addr_type addr ) const @@ -103,6 +106,74 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_ tlx->burst= addrdec_packbits(addrdec_mask[BURST], rest_of_addr, addrdec_mkhigh[BURST], addrdec_mklow[BURST]); } + switch(memory_partition_indexing){ + case CONSECUTIVE: + //Do nothing + break; + case BITWISE_PERMUTATION: + { + assert(!gap); + tlx->chip = (tlx->chip) ^ (tlx->row & (m_n_channel-1)); + assert(tlx->chip < m_n_channel); + break; + } + case IPOLY: + { + /* + * Set Indexing function from "Pseudo-randomly interleaved memory." + * Rau, B. R et al. + * ISCA 1991 + * + * equations are adopted from: + * "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu cache management scheme." + * Khairy et al. + * IEEE TPDS 2017. + */ + if(m_n_channel == 32) { + std::bitset<64> a(tlx->row); + std::bitset<5> chip(tlx->chip); + chip[0] = a[13]^a[12]^a[11]^a[10]^a[9]^a[6]^a[5]^a[3]^a[0]^chip[0]; + chip[1] = a[14]^a[13]^a[12]^a[11]^a[10]^a[7]^a[6]^a[4]^a[1]^chip[1]; + chip[2] = a[14]^a[10]^a[9]^a[8]^a[7]^a[6]^a[3]^a[2]^a[0]^chip[2]; + chip[3] = a[11]^a[10]^a[9]^a[8]^a[7]^a[4]^a[3]^a[1]^chip[3]; + chip[4] = a[12]^a[11]^a[10]^a[9]^a[8]^a[5]^a[4]^a[2]^chip[4]; + tlx->chip = chip.to_ulong(); + + } + else{ /* Else incorrect number of channels for the hashing function */ + assert("\nGPGPU-Sim memory_partition_indexing error: The number of channels should be " + "32 for the hashing IPOLY index function.\n" && 0); + } + assert(tlx->chip < m_n_channel); + break; + } + case PAE: + { + //Page Address Entropy + //random selected bits from the page and bank bits + //similar to + //Liu, Yuxi, et al. "Get Out of the Valley: Power-Efficient Address Mapping for GPUs." ISCA 2018 + std::bitset<64> a(tlx->row); + std::bitset<5> chip(tlx->chip); + std::bitset<4> b(tlx->bk); + chip[0] = a[13]^a[10]^a[9]^a[5]^a[0]^b[3]^b[0]^chip[0]; + chip[1] = a[12]^a[11]^a[6]^a[1]^b[3]^b[2]^b[1]^chip[1]; + chip[2] = a[14]^a[9]^a[8]^a[7]^a[2]^b[1]^chip[2]; + chip[3] = a[11]^a[10]^a[8]^a[3]^b[2]^b[3]^chip[3]; + chip[4] = a[12]^a[9]^a[8]^a[5]^a[4]^b[1]^b[0]^chip[4]; + tlx->chip = chip.to_ulong(); + assert(tlx->chip < m_n_channel); + break; + } + case CUSTOM: + /* No custom set function implemented */ + //Do you custom index here + break; + default: + assert("\nUndefined set index function.\n" && 0); + break; + } + // combine the chip address and the lower bits of DRAM bank address to form the subpartition ID unsigned sub_partition_addr_mask = m_n_sub_partition_in_channel - 1; tlx->sub_partition = tlx->chip * m_n_sub_partition_in_channel diff --git a/src/gpgpu-sim/addrdec.h b/src/gpgpu-sim/addrdec.h index fd9af8d..bdc5fec 100644 --- a/src/gpgpu-sim/addrdec.h +++ b/src/gpgpu-sim/addrdec.h @@ -35,6 +35,14 @@ #include "../abstract_hardware_model.h" +enum partition_index_function{ + CONSECUTIVE = 0, + BITWISE_PERMUTATION, + IPOLY, + PAE, + CUSTOM +}; + struct addrdec_t { void print( FILE *fp ) const; @@ -72,6 +80,7 @@ private: const char *addrdec_option; int gpgpu_mem_address_mask; + partition_index_function memory_partition_indexing; bool run_test; int ADDR_CHIP_S; diff --git a/src/gpgpu-sim/delayqueue.h b/src/gpgpu-sim/delayqueue.h index b25f143..0caa5d4 100644 --- a/src/gpgpu-sim/delayqueue.h +++ b/src/gpgpu-sim/delayqueue.h @@ -161,6 +161,7 @@ public: } bool full() const { return (m_max_len && m_length >= m_max_len); } + bool is_avilable_size(unsigned size) const { return (m_max_len && m_length+size-1 >= m_max_len); } bool empty() const { return m_head == NULL; } unsigned get_n_element() const { return m_n_element; } unsigned get_length() const { return m_length; } diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index a0e024b..6c11b43 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -49,11 +49,45 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m m_stats = stats; m_config = config; + //rowblp + access_num=0; + hits_num=0; + read_num=0; + write_num=0; + hits_read_num=0; + hits_write_num=0; + banks_1time=0; + banks_acess_total=0; + banks_acess_total_after=0; + banks_time_ready=0; + banks_access_ready_total=0; + issued_two=0; + issued_total=0; + issued_total_row=0; + issued_total_col=0; + CCDc = 0; RRDc = 0; RTWc = 0; WTRc = 0; + wasted_bw_row=0; + wasted_bw_col=0; + util_bw=0; + idle_bw=0; + RCDc_limit=0; + CCDLc_limit=0; + CCDLc_limit_alone=0; + CCDc_limit=0; + WTRc_limit=0; + WTRc_limit_alone=0; + RCDWRc_limit=0; + RTWc_limit=0; + RTWc_limit_alone=0; + rwq_limit=0; + write_to_read_ratio_blp_rw_average=0; + bkgrp_parallsim_rw=0; + rw = READ; //read mode is default bkgrp = (bankgrp_t**) calloc(sizeof(bankgrp_t*), m_config->nbkgrp); @@ -74,12 +108,13 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m bk[i]->state = BANK_IDLE; bk[i]->bkgrpindex = i/(m_config->nbk/m_config->nbkgrp); } - prio = 0; + prio = 0; + rwq = new fifo_pipeline("rwq",m_config->CL,m_config->CL+1); mrqq = new fifo_pipeline("mrqq",0,2); returnq = new fifo_pipeline("dramreturnq",0,m_config->gpgpu_dram_return_queue_size==0?1024:m_config->gpgpu_dram_return_queue_size); m_frfcfs_scheduler = NULL; - if ( m_config->scheduler_type == DRAM_FRFCFS ) + if ( m_config->scheduler_type == DRAM_FRFCFS) m_frfcfs_scheduler = new frfcfs_scheduler(m_config,this,stats); n_cmd = 0; n_activity = 0; @@ -88,6 +123,8 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m n_pre = 0; n_rd = 0; n_wr = 0; + n_wr_WB=0; + n_rd_L2_A=0; n_req = 0; max_mrqs_temp = 0; bwutil = 0; @@ -113,13 +150,21 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m mrqq_Dist = StatCreate("mrqq_length",1, queue_limit()); else //queue length is unlimited; mrqq_Dist = StatCreate("mrqq_length",1,64); //track up to 64 entries + } -bool dram_t::full() const +bool dram_t::full(bool is_write) const { - if(m_config->scheduler_type == DRAM_FRFCFS ){ + if(m_config->scheduler_type == DRAM_FRFCFS){ if(m_config->gpgpu_frfcfs_dram_sched_queue_size == 0 ) return false; - return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_frfcfs_dram_sched_queue_size; + if(m_config->seperate_write_queue_enabled){ + if(is_write) + return m_frfcfs_scheduler->num_write_pending() >= m_config->gpgpu_frfcfs_dram_write_queue_size; + else + return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_frfcfs_dram_sched_queue_size; + } + else + return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_frfcfs_dram_sched_queue_size; } else return mrqq->full(); } @@ -127,7 +172,7 @@ bool dram_t::full() const unsigned dram_t::que_length() const { unsigned nreqs = 0; - if (m_config->scheduler_type == DRAM_FRFCFS ) { + if (m_config->scheduler_type == DRAM_FRFCFS) { nreqs = m_frfcfs_scheduler->num_pending(); } else { nreqs = mrqq->get_length(); @@ -146,7 +191,7 @@ unsigned int dram_t::queue_limit() const } -dram_req_t::dram_req_t( class mem_fetch *mf ) +dram_req_t::dram_req_t( class mem_fetch *mf, unsigned banks, unsigned dram_bnk_indexing_policy) { txbytes = 0; dqbytes = 0; @@ -154,7 +199,29 @@ dram_req_t::dram_req_t( class mem_fetch *mf ) const addrdec_t &tlx = mf->get_tlx_addr(); - bk = tlx.bk; + switch(dram_bnk_indexing_policy){ + case LINEAR_BK_INDEX: + { + bk = tlx.bk; + break; + } + case BITWISE_XORING_BK_INDEX: + { + //xoring bank bits with lower bits of the page + int lbank = log2(banks); + bk = tlx.bk ^ (tlx.row & ((1<get_data_size(); @@ -169,14 +236,15 @@ void dram_t::push( class mem_fetch *data ) { assert(id == data->get_tlx_addr().chip); // Ensure request is in correct memory partition - dram_req_t *mrq = new dram_req_t(data); + dram_req_t *mrq = new dram_req_t(data,m_config->nbk,m_config->dram_bnk_indexing_policy); + data->set_status(IN_PARTITION_MC_INTERFACE_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); - mrqq->push(mrq); + mrqq->push(mrq); // stats... n_req += 1; n_req_partial += 1; - if ( m_config->scheduler_type == DRAM_FRFCFS ) { + if ( m_config->scheduler_type == DRAM_FRFCFS) { unsigned nreqs = m_frfcfs_scheduler->num_pending(); if ( nreqs > max_mrqs_temp) max_mrqs_temp = nreqs; @@ -212,6 +280,7 @@ void dram_t::cycle() printf("\tDQ: BK%d Row:%03x Col:%03x", cmd->bk, cmd->row, cmd->col + cmd->dqbytes); #endif cmd->dqbytes += m_config->dram_atom_size; + if (cmd->dqbytes >= cmd->nbytes) { mem_fetch *data = cmd->data; data->set_status(IN_PARTITION_MC_RETURNQ,gpu_sim_cycle+gpu_tot_sim_cycle); @@ -240,7 +309,7 @@ void dram_t::cycle() printf("Error: Unknown DRAM scheduler type\n"); assert(0); } - if ( m_config->scheduler_type == DRAM_FRFCFS ) { + if ( m_config->scheduler_type == DRAM_FRFCFS) { unsigned nreqs = m_frfcfs_scheduler->num_pending(); if ( nreqs > max_mrqs) { max_mrqs = nreqs; @@ -258,130 +327,123 @@ void dram_t::cycle() unsigned k=m_config->nbk; bool issued = false; - // check if any bank is ready to issue a new read + //collect row buffer locality, BLP and other statistics + ///////////////////////////////////////////////////////////////////////// + unsigned int memory_pending=0; for (unsigned i=0;inbk;i++) { - unsigned j = (i + prio) % m_config->nbk; - unsigned grp = j>>m_config->bk_tag_length; - if (bk[j]->mrq) { //if currently servicing a memory request - bk[j]->mrq->data->set_status(IN_PARTITION_DRAM,gpu_sim_cycle+gpu_tot_sim_cycle); - // correct row activated for a READ - if ( !issued && !CCDc && !bk[j]->RCDc && - !(bkgrp[grp]->CCDLc) && - (bk[j]->curr_row == bk[j]->mrq->row) && - (bk[j]->mrq->rw == READ) && (WTRc == 0 ) && - (bk[j]->state == BANK_ACTIVE) && - !rwq->full() ) { - if (rw==WRITE) { - rw=READ; - rwq->set_min_length(m_config->CL); - } - rwq->push(bk[j]->mrq); - bk[j]->mrq->txbytes += m_config->dram_atom_size; - CCDc = m_config->tCCD; - bkgrp[grp]->CCDLc = m_config->tCCDL; - RTWc = m_config->tRTW; - bk[j]->RTPc = m_config->BL/m_config->data_command_freq_ratio; - bkgrp[grp]->RTPLc = m_config->tRTPL; - issued = true; - n_rd++; - bwutil += m_config->BL/m_config->data_command_freq_ratio; - bwutil_partial += m_config->BL/m_config->data_command_freq_ratio; - bk[j]->n_access++; -#ifdef DRAM_VERIFY - PRINT_CYCLE=1; - printf("\tRD Bk:%d Row:%03x Col:%03x \n", - j, bk[j]->curr_row, - bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); -#endif - // transfer done - if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) { - bk[j]->mrq = NULL; - } - } else - // correct row activated for a WRITE - if ( !issued && !CCDc && !bk[j]->RCDWRc && - !(bkgrp[grp]->CCDLc) && - (bk[j]->curr_row == bk[j]->mrq->row) && - (bk[j]->mrq->rw == WRITE) && (RTWc == 0 ) && - (bk[j]->state == BANK_ACTIVE) && - !rwq->full() ) { - if (rw==READ) { - rw=WRITE; - rwq->set_min_length(m_config->WL); - } - rwq->push(bk[j]->mrq); - - bk[j]->mrq->txbytes += m_config->dram_atom_size; - CCDc = m_config->tCCD; - bkgrp[grp]->CCDLc = m_config->tCCDL; - WTRc = m_config->tWTR; - bk[j]->WTPc = m_config->tWTP; - issued = true; - n_wr++; - bwutil += m_config->BL/m_config->data_command_freq_ratio; - bwutil_partial += m_config->BL/m_config->data_command_freq_ratio; -#ifdef DRAM_VERIFY - PRINT_CYCLE=1; - printf("\tWR Bk:%d Row:%03x Col:%03x \n", - j, bk[j]->curr_row, - bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); -#endif - // transfer done - if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) { - bk[j]->mrq = NULL; - } - } - - else - // bank is idle - if ( !issued && !RRDc && - (bk[j]->state == BANK_IDLE) && - !bk[j]->RPc && !bk[j]->RCc ) { -#ifdef DRAM_VERIFY - PRINT_CYCLE=1; - printf("\tACT BK:%d NewRow:%03x From:%03x \n", - j,bk[j]->mrq->row,bk[j]->curr_row); -#endif - // activate the row with current memory request - bk[j]->curr_row = bk[j]->mrq->row; - bk[j]->state = BANK_ACTIVE; - RRDc = m_config->tRRD; - bk[j]->RCDc = m_config->tRCD; - bk[j]->RCDWRc = m_config->tRCDWR; - bk[j]->RASc = m_config->tRAS; - bk[j]->RCc = m_config->tRC; - prio = (j + 1) % m_config->nbk; - issued = true; - n_act_partial++; - n_act++; - } - - else - // different row activated - if ( (!issued) && - (bk[j]->curr_row != bk[j]->mrq->row) && - (bk[j]->state == BANK_ACTIVE) && - (!bk[j]->RASc && !bk[j]->WTPc && - !bk[j]->RTPc && - !bkgrp[grp]->RTPLc) ) { - // make the bank idle again - bk[j]->state = BANK_IDLE; - bk[j]->RPc = m_config->tRP; - prio = (j + 1) % m_config->nbk; - issued = true; - n_pre++; - n_pre_partial++; -#ifdef DRAM_VERIFY - PRINT_CYCLE=1; - printf("\tPRE BK:%d Row:%03x \n", j,bk[j]->curr_row); -#endif - } - } else { - if (!CCDc && !RRDc && !RTWc && !WTRc && !bk[j]->RCDc && !bk[j]->RASc - && !bk[j]->RCc && !bk[j]->RPc && !bk[j]->RCDWRc) k--; - bk[j]->n_idle++; - } + if (bk[i]->mrq) + memory_pending++; } + banks_1time += memory_pending; + if(memory_pending >0) + banks_acess_total++; + + unsigned int memory_pending_rw=0; + unsigned read_blp_rw=0; + unsigned write_blp_rw=0; + std::bitset<8> bnkgrp_rw_found; //assume max we have 8 bank groups + + for (unsigned j=0;jnbk;j++) { + unsigned grp = get_bankgrp_number(j); + if (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == READ) && + (bk[j]->state == BANK_ACTIVE)))) + { + memory_pending_rw++; + read_blp_rw++; + bnkgrp_rw_found.set(grp); + } + else if + (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == WRITE) && + (bk[j]->state == BANK_ACTIVE)))) + { + memory_pending_rw++; + write_blp_rw++; + bnkgrp_rw_found.set(grp); + } + } + banks_time_rw += memory_pending_rw; + bkgrp_parallsim_rw += bnkgrp_rw_found.count(); + if(memory_pending_rw >0) + { + write_to_read_ratio_blp_rw_average += (double)write_blp_rw/(write_blp_rw+read_blp_rw); + banks_access_rw_total++; + } + + unsigned int memory_Pending_ready=0; + for (unsigned j=0;jnbk;j++) { + unsigned grp = get_bankgrp_number(j); + if (bk[j]->mrq && ((!CCDc && !bk[j]->RCDc && + !(bkgrp[grp]->CCDLc) && + (bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == READ) && (WTRc == 0 ) && + (bk[j]->state == BANK_ACTIVE) && + !rwq->full()) + || + (!CCDc && !bk[j]->RCDWRc && + !(bkgrp[grp]->CCDLc) && + (bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == WRITE) && (RTWc == 0 ) && + (bk[j]->state == BANK_ACTIVE) && + !rwq->full()))) + { + memory_Pending_ready++; + } + } + banks_time_ready += memory_Pending_ready; + if(memory_Pending_ready >0) + banks_access_ready_total++; + /////////////////////////////////////////////////////////////////////////////////// + + bool issued_col_cmd = false; + bool issued_row_cmd = false; + + if(m_config->dual_bus_interface) + { + //dual bus interface + //issue one row command and one column command + for (unsigned i=0;inbk;i++) { + unsigned j = (i + prio) % m_config->nbk; + issued_col_cmd = issue_col_command(j); + if(issued_col_cmd) break; + } + for (unsigned i=0;inbk;i++) { + unsigned j = (i + prio) % m_config->nbk; + issued_row_cmd = issue_row_command(j); + if(issued_row_cmd) break; + } + for (unsigned i=0;inbk;i++) { + unsigned j = (i + prio) % m_config->nbk; + if(!bk[j]->mrq) { + if (!CCDc && !RRDc && !RTWc && !WTRc && !bk[j]->RCDc && !bk[j]->RASc + && !bk[j]->RCc && !bk[j]->RPc && !bk[j]->RCDWRc) k--; + bk[j]->n_idle++; + } + } + } + else + { + //single bus interface + //issue only one row/column command + for (unsigned i=0;inbk;i++) { + unsigned j = (i + prio) % m_config->nbk; + if(!issued_col_cmd) + issued_col_cmd = issue_col_command(j); + + if(!issued_col_cmd && !issued_row_cmd) + issued_row_cmd = issue_row_command(j); + + if(!bk[j]->mrq) { + if (!CCDc && !RRDc && !RTWc && !WTRc && !bk[j]->RCDc && !bk[j]->RASc + && !bk[j]->RCc && !bk[j]->RPc && !bk[j]->RCDWRc) k--; + bk[j]->n_idle++; + } + + } + } + + issued = issued_row_cmd || issued_col_cmd; if (!issued) { n_nop++; n_nop_partial++; @@ -395,6 +457,85 @@ void dram_t::cycle() } n_cmd++; n_cmd_partial++; + if(issued) + { + issued_total++; + if(issued_col_cmd && issued_row_cmd) + issued_two++; + } + if(issued_col_cmd) issued_total_col++; + if(issued_row_cmd) issued_total_row++; + + + //Collect some statistics + //check the limitation, see where BW is wasted? + ///////////////////////////////////////////////////////// + unsigned int memory_pending_found=0; + for (unsigned i=0;inbk;i++) { + if (bk[i]->mrq) + memory_pending_found++; + } + if(memory_pending_found>0) + banks_acess_total_after++; + + bool memory_pending_rw_found=false; + for (unsigned j=0;jnbk;j++) { + unsigned grp = get_bankgrp_number(j); + if (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == READ) && + (bk[j]->state == BANK_ACTIVE)) + || + ( + (bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == WRITE) && + (bk[j]->state == BANK_ACTIVE)))) + memory_pending_rw_found=true; + } + + + if(issued_col_cmd || CCDc) + util_bw++; + else if (memory_pending_rw_found) + { + wasted_bw_col++; + for (unsigned j=0;jnbk;j++) { + unsigned grp = get_bankgrp_number(j); + //read + if (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == READ) && + (bk[j]->state == BANK_ACTIVE)))) + { + if(bk[j]->RCDc) RCDc_limit++; + if(bkgrp[grp]->CCDLc) CCDLc_limit++; + if(WTRc) WTRc_limit++; + if(CCDc) CCDc_limit++; + if(rwq->full()) rwq_limit++; + if(bkgrp[grp]->CCDLc && !WTRc) CCDLc_limit_alone++; + if(!bkgrp[grp]->CCDLc && WTRc) WTRc_limit_alone++; + } + //write + else if (bk[j]->mrq && ((bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == WRITE) && + (bk[j]->state == BANK_ACTIVE))) + { + if(bk[j]->RCDWRc) RCDWRc_limit++; + if(bkgrp[grp]->CCDLc) CCDLc_limit++; + if(RTWc) RTWc_limit++; + if(CCDc) CCDc_limit++; + if(rwq->full()) rwq_limit++; + if(bkgrp[grp]->CCDLc && !RTWc) CCDLc_limit_alone++; + if(!bkgrp[grp]->CCDLc && RTWc) RTWc_limit_alone++; + } + } + } + else if (memory_pending_found) + wasted_bw_row++; + else if (!memory_pending_found) + idle_bw++; + else + assert(1); + + ///////////////////////////////////////////////////////// // decrements counters once for each time dram_issueCMD is called DEC2ZERO(RRDc); @@ -420,39 +561,237 @@ void dram_t::cycle() #endif } +bool dram_t::issue_col_command(int j) +{ + bool issued = false; + unsigned grp = get_bankgrp_number(j); + if (bk[j]->mrq) { //if currently servicing a memory request + bk[j]->mrq->data->set_status(IN_PARTITION_DRAM,gpu_sim_cycle+gpu_tot_sim_cycle); + // correct row activated for a READ + if ( !issued && !CCDc && !bk[j]->RCDc && + !(bkgrp[grp]->CCDLc) && + (bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == READ) && (WTRc == 0 ) && + (bk[j]->state == BANK_ACTIVE) && + !rwq->full() ) { + if (rw==WRITE) { + rw=READ; + rwq->set_min_length(m_config->CL); + } + rwq->push(bk[j]->mrq); + bk[j]->mrq->txbytes += m_config->dram_atom_size; + CCDc = m_config->tCCD; + bkgrp[grp]->CCDLc = m_config->tCCDL; + RTWc = m_config->tRTW; + bk[j]->RTPc = m_config->BL/m_config->data_command_freq_ratio; + bkgrp[grp]->RTPLc = m_config->tRTPL; + issued = true; + if(bk[j]->mrq->data->get_access_type() == L2_WR_ALLOC_R) + n_rd_L2_A++; + else + n_rd++; + + bwutil += m_config->BL/m_config->data_command_freq_ratio; + bwutil_partial += m_config->BL/m_config->data_command_freq_ratio; + bk[j]->n_access++; + +#ifdef DRAM_VERIFY + PRINT_CYCLE=1; + printf("\tRD Bk:%d Row:%03x Col:%03x \n", + j, bk[j]->curr_row, + bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); +#endif + // transfer done + if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) { + bk[j]->mrq = NULL; + } + } else + // correct row activated for a WRITE + if ( !issued && !CCDc && !bk[j]->RCDWRc && + !(bkgrp[grp]->CCDLc) && + (bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == WRITE) && (RTWc == 0 ) && + (bk[j]->state == BANK_ACTIVE) && + !rwq->full() ) { + if (rw==READ) { + rw=WRITE; + rwq->set_min_length(m_config->WL); + } + rwq->push(bk[j]->mrq); + + bk[j]->mrq->txbytes += m_config->dram_atom_size; + CCDc = m_config->tCCD; + bkgrp[grp]->CCDLc = m_config->tCCDL; + WTRc = m_config->tWTR; + bk[j]->WTPc = m_config->tWTP; + issued = true; + + if(bk[j]->mrq->data->get_access_type() == L2_WRBK_ACC) + n_wr_WB++; + else + n_wr++; + bwutil += m_config->BL/m_config->data_command_freq_ratio; + bwutil_partial += m_config->BL/m_config->data_command_freq_ratio; +#ifdef DRAM_VERIFY + PRINT_CYCLE=1; + printf("\tWR Bk:%d Row:%03x Col:%03x \n", + j, bk[j]->curr_row, + bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); +#endif + // transfer done + if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) { + bk[j]->mrq = NULL; + } + } + + } + + return issued; +} + +bool dram_t::issue_row_command(int j) +{ + bool issued = false; + unsigned grp = get_bankgrp_number(j); + if (bk[j]->mrq) { //if currently servicing a memory request + bk[j]->mrq->data->set_status(IN_PARTITION_DRAM,gpu_sim_cycle+gpu_tot_sim_cycle); + // bank is idle + //else + if ( !issued && !RRDc && + (bk[j]->state == BANK_IDLE) && + !bk[j]->RPc && !bk[j]->RCc) { // +#ifdef DRAM_VERIFY + PRINT_CYCLE=1; + printf("\tACT BK:%d NewRow:%03x From:%03x \n", + j,bk[j]->mrq->row,bk[j]->curr_row); +#endif + // activate the row with current memory request + bk[j]->curr_row = bk[j]->mrq->row; + bk[j]->state = BANK_ACTIVE; + RRDc = m_config->tRRD; + bk[j]->RCDc = m_config->tRCD; + bk[j]->RCDWRc = m_config->tRCDWR; + bk[j]->RASc = m_config->tRAS; + bk[j]->RCc = m_config->tRC; + prio = (j + 1) % m_config->nbk; + issued = true; + n_act_partial++; + n_act++; + } + + else + // different row activated + if ( (!issued) && + (bk[j]->curr_row != bk[j]->mrq->row) && + (bk[j]->state == BANK_ACTIVE) && + (!bk[j]->RASc && !bk[j]->WTPc && + !bk[j]->RTPc && + !bkgrp[grp]->RTPLc) ) { + // make the bank idle again + bk[j]->state = BANK_IDLE; + bk[j]->RPc = m_config->tRP; + prio = (j + 1) % m_config->nbk; + issued = true; + n_pre++; + n_pre_partial++; +#ifdef DRAM_VERIFY + PRINT_CYCLE=1; + printf("\tPRE BK:%d Row:%03x \n", j,bk[j]->curr_row); +#endif + } + } + return issued; +} + + //if mrq is being serviced by dram, gets popped after CL latency fulfilled -class mem_fetch* dram_t::return_queue_pop() +class mem_fetch* dram_t::return_queue_pop() { return returnq->pop(); } -class mem_fetch* dram_t::return_queue_top() +class mem_fetch* dram_t::return_queue_top() { return returnq->top(); } + void dram_t::print( FILE* simFile) const { unsigned i; fprintf(simFile,"DRAM[%d]: %d bks, busW=%d BL=%d CL=%d, ", id, m_config->nbk, m_config->busW, m_config->BL, m_config->CL ); fprintf(simFile,"tRRD=%d tCCD=%d, tRCD=%d tRAS=%d tRP=%d tRC=%d\n", - m_config->tCCD, m_config->tRRD, m_config->tRCD, m_config->tRAS, m_config->tRP, m_config->tRC ); - fprintf(simFile,"n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_req=%d n_rd=%d n_write=%d bw_util=%.4g\n", - n_cmd, n_nop, n_act, n_pre, n_req, n_rd, n_wr, + m_config->tRRD, m_config->tCCD, m_config->tRCD, m_config->tRAS, m_config->tRP, m_config->tRC ); + fprintf(simFile,"n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_ref_event=%d n_req=%d n_rd=%d n_rd_L2_A=%d n_write=%d n_wr_bk=%d bw_util=%.4g\n", + n_cmd, n_nop, n_act, n_pre, n_ref, n_req, n_rd, n_rd_L2_A, n_wr, n_wr_WB, (float)bwutil/n_cmd); fprintf(simFile,"n_activity=%d dram_eff=%.4g\n", n_activity, (float)bwutil/n_activity); for (i=0;inbk;i++) { fprintf(simFile, "bk%d: %da %di ",i,bk[i]->n_access,bk[i]->n_idle); } + fprintf(simFile, "\n"); + fprintf(simFile, "\n------------------------------------------------------------------------\n"); + + printf("\nRow_Buffer_Locality = %.6f", (float)hits_num / access_num); + printf("\nRow_Buffer_Locality_read = %.6f", (float)hits_read_num / read_num); + printf("\nRow_Buffer_Locality_write = %.6f", (float)hits_write_num / write_num); + printf("\nBank_Level_Parallism = %.6f", (float)banks_1time / banks_acess_total); + printf("\nBank_Level_Parallism_Col = %.6f", (float)banks_time_rw / banks_access_rw_total); + printf("\nBank_Level_Parallism_Ready = %.6f", (float)banks_time_ready /banks_access_ready_total); + printf("\nwrite_to_read_ratio_blp_rw_average = %.6f", write_to_read_ratio_blp_rw_average /banks_access_rw_total); + printf("\nGrpLevelPara = %.6f \n", (float)bkgrp_parallsim_rw /banks_access_rw_total); + + printf("\nBW Util details:\n"); + printf("bwutil = %.6f \n", (float)bwutil/n_cmd); + printf("total_CMD = %d \n", n_cmd); + printf("util_bw = %d \n", util_bw); + printf("Wasted_Col = %d \n", wasted_bw_col); + printf("Wasted_Row = %d \n", wasted_bw_row); + printf("Idle = %d \n", idle_bw); + + printf("\nBW Util Bottlenecks: \n"); + printf("RCDc_limit = %d \n", RCDc_limit); + printf("RCDWRc_limit = %d \n", RCDWRc_limit); + printf("WTRc_limit = %d \n", WTRc_limit); + printf("RTWc_limit = %d \n", RTWc_limit); + printf("CCDLc_limit = %d \n", CCDLc_limit); + printf("rwq = %d \n", rwq_limit); + printf("CCDLc_limit_alone = %d \n", CCDLc_limit_alone); + printf("WTRc_limit_alone = %d \n", WTRc_limit_alone); + printf("RTWc_limit_alone = %d \n", RTWc_limit_alone); + + printf("\nCommands details: \n"); + printf("total_CMD = %d \n", n_cmd); + printf("n_nop = %d \n", n_nop); + printf("Read = %d \n", n_rd); + printf("Write = %d \n",n_wr); + printf("L2_Alloc = %d \n", n_rd_L2_A); + printf("L2_WB = %d \n", n_wr_WB); + printf("n_act = %d \n", n_act); + printf("n_pre = %d \n", n_pre); + printf("n_ref = %d \n", n_ref); + printf("n_req = %d \n", n_req ); + printf("total_req = %d \n", n_rd+n_wr+n_rd_L2_A+n_wr_WB); + + printf("\nDual Bus Interface Util: \n"); + printf("issued_total_row = %lu \n", issued_total_row); + printf("issued_total_col = %lu \n", issued_total_col); + printf("Row_Bus_Util = %.6f \n", (float)issued_total_row / n_cmd); + printf("CoL_Bus_Util = %.6f \n", (float)issued_total_col / n_cmd); + printf("Either_Row_CoL_Bus_Util = %.6f \n", (float)issued_total / n_cmd); + printf("Issued_on_Two_Bus_Simul_Util = %.6f \n", (float)issued_two /n_cmd); + printf("issued_two_Eff = %.6f \n", (float)issued_two /issued_total); + printf("queue_avg = %.6f \n\n", (float)ave_mrqs/n_cmd ); + fprintf(simFile, "\n"); fprintf(simFile, "dram_util_bins:"); for (i=0;i<10;i++) fprintf(simFile, " %d", dram_util_bins[i]); fprintf(simFile, "\ndram_eff_bins:"); for (i=0;i<10;i++) fprintf(simFile, " %d", dram_eff_bins[i]); fprintf(simFile, "\n"); - if(m_config->scheduler_type== DRAM_FRFCFS) + if(m_config->scheduler_type== DRAM_FRFCFS) fprintf(simFile, "mrqq: max=%d avg=%g\n", max_mrqs, (float)ave_mrqs/n_cmd); } @@ -476,8 +815,8 @@ void dram_t::visualize() const void dram_t::print_stat( FILE* simFile ) { - fprintf(simFile,"DRAM (%d): n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_req=%d n_rd=%d n_write=%d bw_util=%.4g ", - id, n_cmd, n_nop, n_act, n_pre, n_req, n_rd, n_wr, + fprintf(simFile,"DRAM (%d): n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_ref=%d n_req=%d n_rd=%d n_write=%d bw_util=%.4g ", + id, n_cmd, n_nop, n_act, n_pre, n_ref, n_req, n_rd, n_wr, (float)bwutil/n_cmd); fprintf(simFile, "mrqq: %d %.4g mrqsmax=%d ", max_mrqs, (float)ave_mrqs/n_cmd, max_mrqs_temp); fprintf(simFile, "\n"); @@ -516,6 +855,7 @@ void dram_t::visualizer_print( gzFile visualizer_file ) n_pre_partial = 0; n_req_partial = 0; + // dram access type classification for (unsigned j = 0; j < m_config->nbk; j++) { gzprintf(visualizer_file,"dramglobal_acc_r: %u %u %u\n", id, j, @@ -553,3 +893,16 @@ void dram_t::set_dram_power_stats( unsigned &cmd, wr = n_wr; req = n_req; } + +unsigned dram_t::get_bankgrp_number(unsigned i) +{ + if(m_config->dram_bnkgrp_indexing_policy == HIGHER_BITS) { //higher bits + return i>>m_config->bk_tag_length; + } + else if (m_config->dram_bnkgrp_indexing_policy == LOWER_BITS) { //lower bits + return i&((m_config->nbkgrp-1)); + } + else { + assert(1); + } +} diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index 15c63e7..bee5b7b 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -31,9 +31,15 @@ #include "delayqueue.h" #include +#include +#include +#include +#include +#include #include #include #include +#include #define READ 'R' //define read and write states #define WRITE 'W' @@ -42,7 +48,7 @@ class dram_req_t { public: - dram_req_t( class mem_fetch *data ); + dram_req_t( class mem_fetch *data , unsigned banks, unsigned dram_bnk_indexing_policy); unsigned int row; unsigned int col; @@ -87,6 +93,17 @@ struct bank_t unsigned int bkgrpindex; }; +enum bank_index_function{ + LINEAR_BK_INDEX = 0, + BITWISE_XORING_BK_INDEX, + CUSTOM_BK_INDEX +}; + +enum bank_grp_bits_position{ + HIGHER_BITS = 0, + LOWER_BITS +}; + class mem_fetch; class dram_t @@ -95,7 +112,7 @@ public: dram_t( unsigned int parition_id, const struct memory_config *config, class memory_stats_t *stats, class memory_partition_unit *mp ); - bool full() const; + bool full(bool is_write) const; void print( FILE* simFile ) const; void visualize() const; void print_stat( FILE* simFile ); @@ -106,6 +123,7 @@ public: class mem_fetch* return_queue_pop(); class mem_fetch* return_queue_top(); + void push( class mem_fetch *data ); void cycle(); void dram_log (int task); @@ -123,17 +141,24 @@ public: unsigned &wr, unsigned &req) const; -private: - void scheduler_fifo(); - void scheduler_frfcfs(); + const struct memory_config *m_config; +private: bankgrp_t **bkgrp; bank_t **bk; unsigned int prio; + unsigned get_bankgrp_number(unsigned i); + + void scheduler_fifo(); + void scheduler_frfcfs(); + + bool issue_col_command(int j); + bool issue_row_command(int j); + unsigned int RRDc; unsigned int CCDc; unsigned int RTWc; //read to write penalty applies across banks @@ -146,7 +171,7 @@ private: fifo_pipeline *rwq; fifo_pipeline *mrqq; //buffer to hold packets when DRAM processing is over - //should be filled with dram clock and popped with l2or icnt clock + //should be filled with dram clock and popped with l2or icnt clock fifo_pipeline *returnq; unsigned int dram_util_bins[10]; @@ -158,11 +183,51 @@ private: unsigned int n_nop; unsigned int n_act; unsigned int n_pre; + unsigned int n_ref; unsigned int n_rd; + unsigned int n_rd_L2_A; unsigned int n_wr; + unsigned int n_wr_WB; unsigned int n_req; unsigned int max_mrqs_temp; + //some statistics to collect to see where BW is wasted? + unsigned wasted_bw_row; + unsigned wasted_bw_col; + unsigned util_bw; + unsigned idle_bw; + unsigned RCDc_limit; + unsigned CCDLc_limit; + unsigned CCDLc_limit_alone; + unsigned CCDc_limit; + unsigned WTRc_limit; + unsigned WTRc_limit_alone; + unsigned RCDWRc_limit; + unsigned RTWc_limit; + unsigned RTWc_limit_alone; + unsigned rwq_limit; + + //row locality, BLP and other statistics + unsigned long access_num; + unsigned long read_num; + unsigned long write_num; + unsigned long long hits_num; + unsigned long long hits_read_num; + unsigned long long hits_write_num; + unsigned long long banks_1time; + unsigned long long banks_acess_total; + unsigned long long banks_acess_total_after; + unsigned long long banks_time_rw; + unsigned long long banks_access_rw_total; + unsigned long long banks_time_ready; + unsigned long long banks_access_ready_total; + unsigned long long issued_two; + unsigned long long issued_total; + unsigned long long issued_total_row; + unsigned long long issued_total_col; + double write_to_read_ratio_blp_rw_average; + unsigned long long bkgrp_parallsim_rw; + unsigned int bwutil; unsigned int max_mrqs; unsigned int ave_mrqs; diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc index 8303e86..ff50050 100644 --- a/src/gpgpu-sim/dram_sched.cc +++ b/src/gpgpu-sim/dram_sched.cc @@ -36,6 +36,7 @@ frfcfs_scheduler::frfcfs_scheduler( const memory_config *config, dram_t *dm, mem m_config = config; m_stats = stats; m_num_pending = 0; + m_num_write_pending = 0; m_dram = dm; m_queue = new std::list[m_config->nbk]; m_bins = new std::map::iterator> >[ m_config->nbk ]; @@ -49,15 +50,36 @@ frfcfs_scheduler::frfcfs_scheduler( const memory_config *config, dram_t *dm, mem curr_row_service_time[i] = 0; row_service_timestamp[i] = 0; } + if(m_config->seperate_write_queue_enabled) { + m_write_queue = new std::list[m_config->nbk]; + m_write_bins = new std::map::iterator> >[ m_config->nbk ]; + m_last_write_row = new std::list::iterator>*[ m_config->nbk ]; + + for ( unsigned i=0; i < m_config->nbk; i++ ) { + m_write_queue[i].clear(); + m_write_bins[i].clear(); + m_last_write_row[i] = NULL; + } + } + m_mode = READ_MODE; } void frfcfs_scheduler::add_req( dram_req_t *req ) { - m_num_pending++; - m_queue[req->bk].push_front(req); - std::list::iterator ptr = m_queue[req->bk].begin(); - m_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front + if(m_config->seperate_write_queue_enabled && req->data->is_write()) { + assert(m_num_write_pending < m_config->gpgpu_frfcfs_dram_write_queue_size); + m_num_write_pending++; + m_write_queue[req->bk].push_front(req); + std::list::iterator ptr = m_write_queue[req->bk].begin(); + m_write_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front + } else { + assert(m_num_pending < m_config->gpgpu_frfcfs_dram_sched_queue_size); + m_num_pending++; + m_queue[req->bk].push_front(req); + std::list::iterator ptr = m_queue[req->bk].begin(); + m_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front + } } void frfcfs_scheduler::data_collection(unsigned int bank) @@ -78,41 +100,92 @@ void frfcfs_scheduler::data_collection(unsigned int bank) dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row ) { - if ( m_last_row[bank] == NULL ) { - if ( m_queue[bank].empty() ) + //row + bool rowhit = true; + std::list *m_current_queue = m_queue; + std::map::iterator> > *m_current_bins = m_bins ; + std::list::iterator> **m_current_last_row = m_last_row; + + if(m_config->seperate_write_queue_enabled) { + if(m_mode == READ_MODE && + ((m_num_write_pending >= m_config->write_high_watermark ) + // || (m_queue[bank].empty() && !m_write_queue[bank].empty()) + )) { + m_mode = WRITE_MODE; + } + else if(m_mode == WRITE_MODE && + (( m_num_write_pending < m_config->write_low_watermark ) + // || (!m_queue[bank].empty() && m_write_queue[bank].empty()) + )){ + m_mode = READ_MODE; + } + } + + if(m_mode == WRITE_MODE) { + m_current_queue = m_write_queue; + m_current_bins = m_write_bins ; + m_current_last_row = m_last_write_row; + } + + if ( m_current_last_row[bank] == NULL ) { + if ( m_current_queue[bank].empty() ) return NULL; - std::map::iterator> >::iterator bin_ptr = m_bins[bank].find( curr_row ); - if ( bin_ptr == m_bins[bank].end()) { - dram_req_t *req = m_queue[bank].back(); - bin_ptr = m_bins[bank].find( req->row ); - assert( bin_ptr != m_bins[bank].end() ); // where did the request go??? - m_last_row[bank] = &(bin_ptr->second); + std::map::iterator> >::iterator bin_ptr = m_current_bins[bank].find( curr_row ); + if ( bin_ptr == m_current_bins[bank].end()) { + dram_req_t *req = m_current_queue[bank].back(); + bin_ptr = m_current_bins[bank].find( req->row ); + assert( bin_ptr != m_current_bins[bank].end() ); // where did the request go??? + m_current_last_row[bank] = &(bin_ptr->second); data_collection(bank); + rowhit = false; } else { - m_last_row[bank] = &(bin_ptr->second); - + m_current_last_row[bank] = &(bin_ptr->second); + rowhit = true; } } - std::list::iterator next = m_last_row[bank]->back(); + std::list::iterator next = m_current_last_row[bank]->back(); dram_req_t *req = (*next); + //rowblp stats + m_dram->access_num++; + bool is_write = req->data->is_write(); + if(is_write) + m_dram->write_num++; + else + m_dram->read_num++; + + if(rowhit) { + m_dram->hits_num++; + if(is_write) + m_dram->hits_write_num++; + else + m_dram->hits_read_num++; + } + m_stats->concurrent_row_access[m_dram->id][bank]++; m_stats->row_access[m_dram->id][bank]++; - m_last_row[bank]->pop_back(); + m_current_last_row[bank]->pop_back(); - m_queue[bank].erase(next); - if ( m_last_row[bank]->empty() ) { - m_bins[bank].erase( req->row ); - m_last_row[bank] = NULL; + m_current_queue[bank].erase(next); + if ( m_current_last_row[bank]->empty() ) { + m_current_bins[bank].erase( req->row ); + m_current_last_row[bank] = NULL; } #ifdef DEBUG_FAST_IDEAL_SCHED if ( req ) printf("%08u : DRAM(%u) scheduling memory request to bank=%u, row=%u\n", (unsigned)gpu_sim_cycle, m_dram->id, req->bk, req->row ); #endif - assert( req != NULL && m_num_pending != 0 ); - m_num_pending--; + + if(m_config->seperate_write_queue_enabled && req->data->is_write()) { + assert( req != NULL && m_num_write_pending != 0 ); + m_num_write_pending--; + } + else { + assert( req != NULL && m_num_pending != 0 ); + m_num_pending--; + } return req; } @@ -129,7 +202,7 @@ void dram_t::scheduler_frfcfs() { unsigned mrq_latency; frfcfs_scheduler *sched = m_frfcfs_scheduler; - while ( !mrqq->empty() && (!m_config->gpgpu_frfcfs_dram_sched_queue_size || sched->num_pending() < m_config->gpgpu_frfcfs_dram_sched_queue_size)) { + while ( !mrqq->empty() ) { dram_req_t *req = mrqq->pop(); // Power stats @@ -160,6 +233,8 @@ void dram_t::scheduler_frfcfs() bk[b]->mrq = req; if (m_config->gpgpu_memlatency_stat) { mrq_latency = gpu_sim_cycle + gpu_tot_sim_cycle - bk[b]->mrq->timestamp; + m_stats->tot_mrq_latency += mrq_latency; + m_stats->tot_mrq_num++; bk[b]->mrq->timestamp = gpu_tot_sim_cycle + gpu_sim_cycle; m_stats->mrq_lat_table[LOGB2(mrq_latency)]++; if (mrq_latency > m_stats->max_mrq_latency) { diff --git a/src/gpgpu-sim/dram_sched.h b/src/gpgpu-sim/dram_sched.h index 3860f5b..63f5831 100644 --- a/src/gpgpu-sim/dram_sched.h +++ b/src/gpgpu-sim/dram_sched.h @@ -35,6 +35,11 @@ #include #include +enum memory_mode { + READ_MODE = 0, + WRITE_MODE +}; + class frfcfs_scheduler { public: frfcfs_scheduler( const memory_config *config, dram_t *dm, memory_stats_t *stats ); @@ -43,17 +48,24 @@ public: dram_req_t *schedule( unsigned bank, unsigned curr_row ); void print( FILE *fp ); unsigned num_pending() const { return m_num_pending;} + unsigned num_write_pending() const { return m_num_write_pending;} private: const memory_config *m_config; dram_t *m_dram; unsigned m_num_pending; + unsigned m_num_write_pending; std::list *m_queue; std::map::iterator> > *m_bins; std::list::iterator> **m_last_row; unsigned *curr_row_service_time; //one set of variables for each bank. unsigned *row_service_timestamp; //tracks when scheduler began servicing current row + std::list *m_write_queue; + std::map::iterator> > *m_write_bins; + std::list::iterator> **m_last_write_row; + + enum memory_mode m_mode; memory_stats_t *m_stats; }; diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 8886398..ba81440 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -29,7 +29,6 @@ #include "stat-tool.h" #include -#define MAX_DEFAULT_CACHE_SIZE_MULTIBLIER 4 // used to allocate memory that is large enough to adapt the changes in cache size across kernels const char * cache_request_status_str(enum cache_request_status status) @@ -38,7 +37,8 @@ const char * cache_request_status_str(enum cache_request_status status) "HIT", "HIT_RESERVED", "MISS", - "RESERVATION_FAIL" + "RESERVATION_FAIL", + "SECTOR_MISS" }; assert(sizeof(static_cache_request_status_str) / sizeof(const char*) == NUM_CACHE_REQUEST_STATUS); @@ -47,6 +47,22 @@ const char * cache_request_status_str(enum cache_request_status status) return static_cache_request_status_str[status]; } +const char * cache_fail_status_str(enum cache_reservation_fail_reason status) +{ + static const char * static_cache_reservation_fail_reason_str[] = { + "LINE_ALLOC_FAIL", + "MISS_QUEUE_FULL", + "MSHR_ENRTY_FAIL", + "MSHR_MERGE_ENRTY_FAIL", + "MSHR_RW_PENDING" + }; + + assert(sizeof(static_cache_reservation_fail_reason_str) / sizeof(const char*) == NUM_CACHE_RESERVATION_FAIL_STATUS); + assert(status < NUM_CACHE_RESERVATION_FAIL_STATUS); + + return static_cache_reservation_fail_reason_str[status]; +} + unsigned l1d_cache_config::set_index(new_addr_type addr) const{ unsigned set_index = m_nset; // Default to linear set index function unsigned lower_xor = 0; @@ -54,10 +70,11 @@ unsigned l1d_cache_config::set_index(new_addr_type addr) const{ switch(m_set_index_function){ case FERMI_HASH_SET_FUNCTION: + case BITWISE_XORING_FUNCTION: /* * Set Indexing function from "A Detailed GPU Cache Model Based on Reuse Distance Theory" * Cedric Nugteren et al. - * ISCA 2014 + * HPCA 2014 */ if(m_nset == 32 || m_nset == 64){ // Lower xor value is bits 7-11 @@ -80,6 +97,36 @@ unsigned l1d_cache_config::set_index(new_addr_type addr) const{ } break; + case HASH_IPOLY_FUNCTION: + /* + * Set Indexing function from "Pseudo-randomly interleaved memory." + * Rau, B. R et al. + * ISCA 1991 + * + * "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu cache management scheme." + * Khairy et al. + * IEEE TPDS 2017. + */ + if(m_nset == 32 || m_nset == 64){ + std::bitset<64> a(addr); + std::bitset<6> index; + index[0] = a[25]^a[24]^a[23]^a[22]^a[21]^a[18]^a[17]^a[15]^a[12]^a[7]; //10 + index[1] = a[26]^a[25]^a[24]^a[23]^a[22]^a[19]^a[18]^a[16]^a[13]^a[8]; //10 + index[2] = a[26]^a[22]^a[21]^a[20]^a[19]^a[18]^a[15]^a[14]^a[12]^a[9]; //10 + index[3] = a[23]^a[22]^a[21]^a[20]^a[19]^a[16]^a[15]^a[13]^a[10]; //9 + index[4] = a[24]^a[23]^a[22]^a[21]^a[20]^a[17]^a[16]^a[14]^a[11]; //9 + + if(m_nset == 64) + index[5] = a[12]; + + set_index = index.to_ulong(); + + }else{ /* Else incorrect number of sets for the hashing function */ + assert("\nGPGPU-Sim cache configuration error: The number of sets should be " + "32 or 64 for the hashing set index function.\n" && 0); + } + break; + case CUSTOM_SET_FUNCTION: /* No custom set function implemented */ break; @@ -87,6 +134,10 @@ unsigned l1d_cache_config::set_index(new_addr_type addr) const{ case LINEAR_SET_FUNCTION: set_index = (addr >> m_line_sz_log2) & (m_nset-1); break; + + default: + assert("\nUndefined set index function.\n" && 0); + break; } // Linear function selected or custom set index function not implemented @@ -113,13 +164,16 @@ unsigned l2_cache_config::set_index(new_addr_type addr) const{ tag_array::~tag_array() { + unsigned cache_lines_num = m_config.get_max_num_lines(); + for(unsigned i=0; iget_addr()); + line_table::const_iterator i = pending_lines.find(addr); + if ( i == pending_lines.end() ) { + pending_lines[addr] = mf->get_inst().get_uid(); + } +} + +void tag_array::remove_pending_line(mem_fetch *mf){ + assert(mf); + new_addr_type addr = m_config.block_addr(mf->get_addr()); + line_table::const_iterator i = pending_lines.find(addr); + if ( i != pending_lines.end() ) { + pending_lines.erase(addr); + } } -enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx ) const { +enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx, mem_fetch* mf, bool probe_mode) const { + mem_access_sector_mask_t mask = mf->get_access_sector_mask(); + return probe(addr, idx, mask, probe_mode, mf); +} + + +enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx, mem_access_sector_mask_t mask, bool probe_mode, mem_fetch* mf) const { //assert( m_config.m_write_policy == READ_ONLY ); unsigned set_index = m_config.set_index(addr); new_addr_type tag = m_config.tag(addr); @@ -169,35 +263,45 @@ enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx ) // check for hit or pending hit for (unsigned way=0; waym_tag == tag) { - if ( line->m_status == RESERVED ) { + if ( line->get_status(mask) == RESERVED ) { idx = index; return HIT_RESERVED; - } else if ( line->m_status == VALID ) { + } else if ( line->get_status(mask) == VALID ) { idx = index; return HIT; - } else if ( line->m_status == MODIFIED ) { + } else if ( line->get_status(mask) == MODIFIED) { + if(line->is_readable(mask)) { + idx = index; + return HIT; + } + else { + idx = index; + return SECTOR_MISS; + } + + } else if ( line->is_valid_line() && line->get_status(mask) == INVALID ) { idx = index; - return HIT; - } else { - assert( line->m_status == INVALID ); + return SECTOR_MISS; + }else { + assert( line->get_status(mask) == INVALID ); } } - if (line->m_status != RESERVED) { + if (!line->is_reserved_line()) { all_reserved = false; - if (line->m_status == INVALID) { + if (line->is_invalid_line()) { invalid_line = index; } else { // valid line : keep track of most appropriate replacement candidate if ( m_config.m_replacement_policy == LRU ) { - if ( line->m_last_access_time < valid_timestamp ) { - valid_timestamp = line->m_last_access_time; + if ( line->get_last_access_time() < valid_timestamp ) { + valid_timestamp = line->get_last_access_time(); valid_line = index; } } else if ( m_config.m_replacement_policy == FIFO ) { - if ( line->m_alloc_time < valid_timestamp ) { - valid_timestamp = line->m_alloc_time; + if ( line->get_alloc_time() < valid_timestamp ) { + valid_timestamp = line->get_alloc_time(); valid_line = index; } } @@ -215,40 +319,59 @@ enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx ) idx = valid_line; } else abort(); // if an unreserved block exists, it is either invalid or replaceable + + if(probe_mode && m_config.is_streaming()){ + line_table::const_iterator i = pending_lines.find(m_config.block_addr(addr)); + assert(mf); + if ( !mf->is_write() && i != pending_lines.end() ) { + if(i->second != mf->get_inst().get_uid()) + return SECTOR_MISS; + } + } + return MISS; } -enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, unsigned &idx ) +enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, unsigned &idx, mem_fetch* mf) { bool wb=false; - cache_block_t evicted; - enum cache_request_status result = access(addr,time,idx,wb,evicted); + evicted_block_info evicted; + enum cache_request_status result = access(addr,time,idx,wb,evicted,mf); assert(!wb); return result; } -enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, unsigned &idx, bool &wb, cache_block_t &evicted ) +enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, unsigned &idx, bool &wb, evicted_block_info &evicted, mem_fetch* mf ) { m_access++; + is_used = true; shader_cache_access_log(m_core_id, m_type_id, 0); // log accesses to cache - enum cache_request_status status = probe(addr,idx); + enum cache_request_status status = probe(addr,idx,mf); switch (status) { case HIT_RESERVED: m_pending_hit++; case HIT: - m_lines[idx].m_last_access_time=time; + m_lines[idx]->set_last_access_time(time, mf->get_access_sector_mask()); break; case MISS: m_miss++; shader_cache_access_log(m_core_id, m_type_id, 1); // log cache misses if ( m_config.m_alloc_policy == ON_MISS ) { - if( m_lines[idx].m_status == MODIFIED ) { + if( m_lines[idx]->is_modified_line()) { wb = true; - evicted = m_lines[idx]; + evicted.set_info(m_lines[idx]->m_block_addr, m_lines[idx]->get_modified_size()); } - m_lines[idx].allocate( m_config.tag(addr), m_config.block_addr(addr), time ); + m_lines[idx]->allocate( m_config.tag(addr), m_config.block_addr(addr), time, mf->get_access_sector_mask()); } break; + case SECTOR_MISS: + assert(m_config.m_cache_type == SECTOR); + m_sector_miss++; + shader_cache_access_log(m_core_id, m_type_id, 1); // log cache misses + if ( m_config.m_alloc_policy == ON_MISS ) { + ((sector_cache_block*)m_lines[idx])->allocate_sector( time, mf->get_access_sector_mask() ); + } + break; case RESERVATION_FAIL: m_res_fail++; shader_cache_access_log(m_core_id, m_type_id, 1); // log cache misses @@ -261,37 +384,70 @@ enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, return status; } -void tag_array::fill( new_addr_type addr, unsigned time ) +void tag_array::fill( new_addr_type addr, unsigned time, mem_fetch* mf) +{ + fill(addr, time, mf->get_access_sector_mask()); +} + +void tag_array::fill( new_addr_type addr, unsigned time, mem_access_sector_mask_t mask ) { - assert( m_config.m_alloc_policy == ON_FILL ); + //assert( m_config.m_alloc_policy == ON_FILL ); unsigned idx; - enum cache_request_status status = probe(addr,idx); - assert(status==MISS); // MSHR should have prevented redundant memory request - m_lines[idx].allocate( m_config.tag(addr), m_config.block_addr(addr), time ); - m_lines[idx].fill(time); + enum cache_request_status status = probe(addr,idx,mask); + //assert(status==MISS||status==SECTOR_MISS); // MSHR should have prevented redundant memory request + if(status==MISS) + m_lines[idx]->allocate( m_config.tag(addr), m_config.block_addr(addr), time, mask ); + else if (status==SECTOR_MISS) { + assert(m_config.m_cache_type == SECTOR); + ((sector_cache_block*)m_lines[idx])->allocate_sector( time, mask ); + } + + m_lines[idx]->fill(time, mask); } -void tag_array::fill( unsigned index, unsigned time ) +void tag_array::fill( unsigned index, unsigned time, mem_fetch* mf) { assert( m_config.m_alloc_policy == ON_MISS ); - m_lines[index].fill(time); + m_lines[index]->fill(time, mf->get_access_sector_mask()); } + +//TODO: we need write back the flushed data to the upper level void tag_array::flush() { + if(!is_used) + return; + for (unsigned i=0; i < m_config.get_num_lines(); i++) - m_lines[i].m_status = INVALID; + if(m_lines[i]->is_modified_line()) { + for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++) + m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ; + } + + is_used = false; +} + +void tag_array::invalidate() +{ + if(!is_used) + return; + + for (unsigned i=0; i < m_config.get_num_lines(); i++) + for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++) + m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ; + + is_used = false; } float tag_array::windowed_miss_rate( ) const { unsigned n_access = m_access - m_prev_snapshot_access; - unsigned n_miss = m_miss - m_prev_snapshot_miss; + unsigned n_miss = (m_miss+m_sector_miss) - m_prev_snapshot_miss; // unsigned n_pending_hit = m_pending_hit - m_prev_snapshot_pending_hit; float missrate = 0.0f; if (n_access != 0) - missrate = (float) n_miss / n_access; + missrate = (float) (n_miss+m_sector_miss) / n_access; return missrate; } @@ -299,23 +455,24 @@ void tag_array::new_window() { m_prev_snapshot_access = m_access; m_prev_snapshot_miss = m_miss; + m_prev_snapshot_miss = m_miss + m_sector_miss; m_prev_snapshot_pending_hit = m_pending_hit; } void tag_array::print( FILE *stream, unsigned &total_access, unsigned &total_misses ) const { m_config.print(stream); - fprintf( stream, "\t\tAccess = %d, Miss = %d (%.3g), PendingHit = %d (%.3g)\n", - m_access, m_miss, (float) m_miss / m_access, + fprintf( stream, "\t\tAccess = %d, Miss = %d, Sector_Miss = %d, Total_Miss = %d (%.3g), PendingHit = %d (%.3g)\n", + m_access, m_miss, m_sector_miss, (m_miss+m_sector_miss), (float) (m_miss+m_sector_miss) / m_access, m_pending_hit, (float) m_pending_hit / m_access); - total_misses+=m_miss; + total_misses+=(m_miss+m_sector_miss); total_access+=m_access; } void tag_array::get_stats(unsigned &total_access, unsigned &total_misses, unsigned &total_hit_res, unsigned &total_res_fail) const{ // Update statistics from the tag array total_access = m_access; - total_misses = m_miss; + total_misses = (m_miss+m_sector_miss); total_hit_res = m_pending_hit; total_res_fail = m_res_fail; } @@ -324,16 +481,17 @@ void tag_array::get_stats(unsigned &total_access, unsigned &total_misses, unsign bool was_write_sent( const std::list &events ) { for( std::list::const_iterator e=events.begin(); e!=events.end(); e++ ) { - if( *e == WRITE_REQUEST_SENT ) + if( (*e).m_cache_event_type == WRITE_REQUEST_SENT ) return true; } return false; } -bool was_writeback_sent( const std::list &events ) +bool was_writeback_sent( const std::list &events, cache_event& wb_event) { for( std::list::const_iterator e=events.begin(); e!=events.end(); e++ ) { - if( *e == WRITE_BACK_REQUEST_SENT ) + if( (*e).m_cache_event_type == WRITE_BACK_REQUEST_SENT ) + wb_event = *e; return true; } return false; @@ -342,7 +500,16 @@ bool was_writeback_sent( const std::list &events ) bool was_read_sent( const std::list &events ) { for( std::list::const_iterator e=events.begin(); e!=events.end(); e++ ) { - if( *e == READ_REQUEST_SENT ) + if( (*e).m_cache_event_type == READ_REQUEST_SENT ) + return true; + } + return false; +} + +bool was_writeallocate_sent( const std::list &events ) +{ + for( std::list::const_iterator e=events.begin(); e!=events.end(); e++ ) { + if( (*e).m_cache_event_type == WRITE_ALLOCATE_SENT ) return true; } return false; @@ -375,11 +542,27 @@ void mshr_table::add( new_addr_type block_addr, mem_fetch *mf ){ } } +/// check is_read_after_write_pending +bool mshr_table::is_read_after_write_pending( new_addr_type block_addr){ + std::list my_list = m_data[block_addr].m_list; + bool write_found = false; + for (std::list::iterator it=my_list.begin(); it != my_list.end(); ++it) + { + if((*it)->is_write()) //Pending Write Request + write_found = true; + else if(write_found) //Pending Read Request and we found previous Write + return true; + } + + return false; + +} + /// Accept a new cache fill response: mark entry ready for processing void mshr_table::mark_ready( new_addr_type block_addr, bool &has_atomic ){ assert( !busy() ); table::iterator a = m_data.find(block_addr); - assert( a != m_data.end() ); // don't remove same request twice + assert( a != m_data.end() ); m_current_response.push_back( block_addr ); has_atomic = a->second.m_has_atomic; assert( m_current_response.size() <= m_data.size() ); @@ -417,9 +600,11 @@ void mshr_table::display( FILE *fp ) const{ /***************************************************************** Caches *****************************************************************/ cache_stats::cache_stats(){ m_stats.resize(NUM_MEM_ACCESS_TYPE); + m_fail_stats.resize(NUM_MEM_ACCESS_TYPE); for(unsigned i=0; i 0) - fprintf(fout, "\t%s[%s][%s] = %u\n", - m_cache_name.c_str(), - mem_access_type_str((enum mem_access_type)type), - "TOTAL_ACCESS", - total_access[type]); + if(total_access[type] > 0) + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + "TOTAL_ACCESS", + total_access[type]); } } +void cache_stats::print_fail_stats(FILE *fout, const char *cache_name) const{ + std::string m_cache_name = cache_name; + for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { + for (unsigned fail = 0; fail < NUM_CACHE_RESERVATION_FAIL_STATUS; ++fail) { + if(m_fail_stats[type][fail] > 0){ + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + cache_fail_status_str((enum cache_reservation_fail_reason)fail), + m_fail_stats[type][fail]); + } + } + } +} + void cache_sub_stats::print_port_stats(FILE *fout, const char *cache_name) const { float data_port_util = 0.0f; @@ -580,10 +813,10 @@ void cache_stats::get_sub_stats(struct cache_sub_stats &css) const{ for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { for (unsigned status = 0; status < NUM_CACHE_REQUEST_STATUS; ++status) { - if(status == HIT || status == MISS || status == HIT_RESERVED) + if(status == HIT || status == MISS || status == SECTOR_MISS || status == HIT_RESERVED) t_css.accesses += m_stats[type][status]; - if(status == MISS) + if(status == MISS || status == SECTOR_MISS) t_css.misses += m_stats[type][status]; if(status == HIT_RESERVED) @@ -611,6 +844,16 @@ bool cache_stats::check_valid(int type, int status) const{ return false; } +bool cache_stats::check_fail_valid(int type, int fail) const{ + /// + /// Verify a valid access_type/access_status + /// + if((type >= 0) && (type < NUM_MEM_ACCESS_TYPE) && (fail >= 0) && (fail < NUM_CACHE_RESERVATION_FAIL_STATUS)) + return true; + else + return false; +} + void cache_stats::sample_cache_port_utility(bool data_port_busy, bool fill_port_busy) { m_cache_port_available_cycles += 1; @@ -639,15 +882,18 @@ void baseline_cache::bandwidth_management::use_data_port(mem_fetch *mf, enum cac unsigned data_cycles = data_size / port_width + ((data_size % port_width > 0)? 1 : 0); m_data_port_occupied_cycles += data_cycles; } break; - case HIT_RESERVED: + case HIT_RESERVED: case MISS: { // the data array is accessed to read out the entire line for write-back - if (was_writeback_sent(events)) { - unsigned data_cycles = m_config.m_line_sz / port_width; + // in case of sector cache we need to write bank only the modified sectors + cache_event ev(WRITE_BACK_REQUEST_SENT); + if (was_writeback_sent(events, ev)) { + unsigned data_cycles = ev.m_evicted_block.m_modified_size / port_width; m_data_port_occupied_cycles += data_cycles; } } break; - case RESERVATION_FAIL: + case SECTOR_MISS: + case RESERVATION_FAIL: // Does not consume any port bandwidth break; default: @@ -660,7 +906,7 @@ void baseline_cache::bandwidth_management::use_data_port(mem_fetch *mf, enum cac void baseline_cache::bandwidth_management::use_fill_port(mem_fetch *mf) { // assume filling the entire line with the returned request - unsigned fill_cycles = m_config.m_line_sz / m_config.m_data_port_width; + unsigned fill_cycles = m_config.get_atom_sz() / m_config.m_data_port_width; m_fill_port_occupied_cycles += fill_cycles; } @@ -707,21 +953,43 @@ void baseline_cache::cycle(){ /// Interface for response from lower memory level (model bandwidth restictions in caller) void baseline_cache::fill(mem_fetch *mf, unsigned time){ + + if(m_config.m_mshr_type == SECTOR_ASSOC) { + assert(mf->get_original_mf()); + extra_mf_fields_lookup::iterator e = m_extra_mf_fields.find(mf->get_original_mf()); + assert( e != m_extra_mf_fields.end() ); + e->second.pending_read--; + + if(e->second.pending_read > 0) { + //wait for the other requests to come back + delete mf; + return; + } else { + mem_fetch *temp = mf; + mf = mf->get_original_mf(); + delete temp; + } + } + extra_mf_fields_lookup::iterator e = m_extra_mf_fields.find(mf); assert( e != m_extra_mf_fields.end() ); assert( e->second.m_valid ); mf->set_data_size( e->second.m_data_size ); + mf->set_addr( e->second.m_addr ); if ( m_config.m_alloc_policy == ON_MISS ) - m_tag_array->fill(e->second.m_cache_index,time); - else if ( m_config.m_alloc_policy == ON_FILL ) - m_tag_array->fill(e->second.m_block_addr,time); + m_tag_array->fill(e->second.m_cache_index,time,mf); + else if ( m_config.m_alloc_policy == ON_FILL ) { + m_tag_array->fill(e->second.m_block_addr,time,mf); + if(m_config.is_streaming()) + m_tag_array->remove_pending_line(mf); + } else abort(); bool has_atomic = false; m_mshrs.mark_ready(e->second.m_block_addr, has_atomic); if (has_atomic) { assert(m_config.m_alloc_policy == ON_MISS); - cache_block_t &block = m_tag_array->get_block(e->second.m_cache_index); - block.m_status = MODIFIED; // mark line as dirty for atomic operation + cache_block_t* block = m_tag_array->get_block(e->second.m_cache_index); + block->set_status(MODIFIED, mf->get_access_sector_mask()); // mark line as dirty for atomic operation } m_extra_mf_fields.erase(mf); m_bandwidth_management.use_fill_port(mf); @@ -749,45 +1017,59 @@ void baseline_cache::send_read_request(new_addr_type addr, new_addr_type block_a unsigned time, bool &do_miss, std::list &events, bool read_only, bool wa){ bool wb=false; - cache_block_t e; + evicted_block_info e; send_read_request(addr, block_addr, cache_index, mf, time, do_miss, wb, e, events, read_only, wa); } /// Read miss handler. Check MSHR hit or MSHR available void baseline_cache::send_read_request(new_addr_type addr, new_addr_type block_addr, unsigned cache_index, mem_fetch *mf, - unsigned time, bool &do_miss, bool &wb, cache_block_t &evicted, std::list &events, bool read_only, bool wa){ + unsigned time, bool &do_miss, bool &wb, evicted_block_info &evicted, std::list &events, bool read_only, bool wa){ - bool mshr_hit = m_mshrs.probe(block_addr); - bool mshr_avail = !m_mshrs.full(block_addr); + new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr()); + bool mshr_hit = m_mshrs.probe(mshr_addr); + bool mshr_avail = !m_mshrs.full(mshr_addr); if ( mshr_hit && mshr_avail ) { if(read_only) - m_tag_array->access(block_addr,time,cache_index); + m_tag_array->access(block_addr,time,cache_index,mf); else - m_tag_array->access(block_addr,time,cache_index,wb,evicted); + m_tag_array->access(block_addr,time,cache_index,wb,evicted,mf); - m_mshrs.add(block_addr,mf); + m_mshrs.add(mshr_addr,mf); do_miss = true; + } else if ( !mshr_hit && mshr_avail && (m_miss_queue.size() < m_config.m_miss_queue_size) ) { if(read_only) - m_tag_array->access(block_addr,time,cache_index); + m_tag_array->access(block_addr,time,cache_index,mf); else - m_tag_array->access(block_addr,time,cache_index,wb,evicted); - - m_mshrs.add(block_addr,mf); - m_extra_mf_fields[mf] = extra_mf_fields(block_addr,cache_index, mf->get_data_size()); - mf->set_data_size( m_config.get_line_sz() ); + m_tag_array->access(block_addr,time,cache_index,wb,evicted,mf); + + m_mshrs.add(mshr_addr,mf); + if(m_config.is_streaming() && m_config.m_cache_type == SECTOR){ + m_tag_array->add_pending_line(mf); + } + m_extra_mf_fields[mf] = extra_mf_fields(mshr_addr,mf->get_addr(),cache_index, mf->get_data_size(), m_config); + mf->set_data_size( m_config.get_atom_sz() ); + mf->set_addr( mshr_addr ); m_miss_queue.push_back(mf); mf->set_status(m_miss_queue_status,time); if(!wa) - events.push_back(READ_REQUEST_SENT); + events.push_back(cache_event(READ_REQUEST_SENT)); + do_miss = true; } + else if(mshr_hit && !mshr_avail) + m_stats.inc_fail_stats(mf->get_access_type(), MSHR_MERGE_ENRTY_FAIL); + else if (!mshr_hit && !mshr_avail) + m_stats.inc_fail_stats(mf->get_access_type(), MSHR_ENRTY_FAIL); + else + assert(0); } /// Sends write request to lower level memory (write or writeback) void data_cache::send_write_request(mem_fetch *mf, cache_event request, unsigned time, std::list &events){ - events.push_back(request); + + events.push_back(request); m_miss_queue.push_back(mf); mf->set_status(m_miss_queue_status,time); } @@ -798,40 +1080,44 @@ void data_cache::send_write_request(mem_fetch *mf, cache_event request, unsigned /// Write-back hit: Mark block as modified cache_request_status data_cache::wr_hit_wb(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list &events, enum cache_request_status status ){ new_addr_type block_addr = m_config.block_addr(addr); - m_tag_array->access(block_addr,time,cache_index); // update LRU state - cache_block_t &block = m_tag_array->get_block(cache_index); - block.m_status = MODIFIED; + m_tag_array->access(block_addr,time,cache_index,mf); // update LRU state + cache_block_t* block = m_tag_array->get_block(cache_index); + block->set_status(MODIFIED, mf->get_access_sector_mask()); return HIT; } /// Write-through hit: Directly send request to lower level memory cache_request_status data_cache::wr_hit_wt(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list &events, enum cache_request_status status ){ - if(miss_queue_full(0)) + if(miss_queue_full(0)) { + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); return RESERVATION_FAIL; // cannot handle request this cycle + } new_addr_type block_addr = m_config.block_addr(addr); - m_tag_array->access(block_addr,time,cache_index); // update LRU state - cache_block_t &block = m_tag_array->get_block(cache_index); - block.m_status = MODIFIED; + m_tag_array->access(block_addr,time,cache_index,mf); // update LRU state + cache_block_t* block = m_tag_array->get_block(cache_index); + block->set_status(MODIFIED, mf->get_access_sector_mask()); // generate a write-through - send_write_request(mf, WRITE_REQUEST_SENT, time, events); + send_write_request(mf, cache_event(WRITE_REQUEST_SENT), time, events); return HIT; } /// Write-evict hit: Send request to lower level memory and invalidate corresponding block cache_request_status data_cache::wr_hit_we(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list &events, enum cache_request_status status ){ - if(miss_queue_full(0)) + if(miss_queue_full(0)) { + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); return RESERVATION_FAIL; // cannot handle request this cycle + } // generate a write-through/evict - cache_block_t &block = m_tag_array->get_block(cache_index); - send_write_request(mf, WRITE_REQUEST_SENT, time, events); + cache_block_t* block = m_tag_array->get_block(cache_index); + send_write_request(mf, cache_event(WRITE_REQUEST_SENT), time, events); // Invalidate block - block.m_status = INVALID; + block->set_status(INVALID, mf->get_access_sector_mask()); return HIT; } @@ -850,34 +1136,46 @@ enum cache_request_status data_cache::wr_hit_global_we_local_wb(new_addr_type ad /// Write-allocate miss: Send write request to lower level memory // and send a read request for the same block enum cache_request_status -data_cache::wr_miss_wa( new_addr_type addr, +data_cache::wr_miss_wa_naive( new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list &events, enum cache_request_status status ) { new_addr_type block_addr = m_config.block_addr(addr); + new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr()); // Write allocate, maximum 3 requests (write miss, read request, write back request) // Conservatively ensure the worst-case request can be handled this cycle - bool mshr_hit = m_mshrs.probe(block_addr); - bool mshr_avail = !m_mshrs.full(block_addr); + bool mshr_hit = m_mshrs.probe(mshr_addr); + bool mshr_avail = !m_mshrs.full(mshr_addr); if(miss_queue_full(2) || (!(mshr_hit && mshr_avail) - && !(!mshr_hit && mshr_avail - && (m_miss_queue.size() < m_config.m_miss_queue_size)))) + && !(!mshr_hit && mshr_avail && (m_miss_queue.size() < m_config.m_miss_queue_size)))) { + //check what is the exactly the failure reason + if(miss_queue_full(2) ) + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); + else if(mshr_hit && !mshr_avail) + m_stats.inc_fail_stats(mf->get_access_type(), MSHR_MERGE_ENRTY_FAIL); + else if (!mshr_hit && !mshr_avail) + m_stats.inc_fail_stats(mf->get_access_type(), MSHR_ENRTY_FAIL); + else + assert(0); + return RESERVATION_FAIL; + } - send_write_request(mf, WRITE_REQUEST_SENT, time, events); + send_write_request(mf, cache_event(WRITE_REQUEST_SENT), time, events); // Tries to send write allocate request, returns true on success and false on failure //if(!send_write_allocate(mf, addr, block_addr, cache_index, time, events)) // return RESERVATION_FAIL; const mem_access_t *ma = new mem_access_t( m_wr_alloc_type, mf->get_addr(), - mf->get_data_size(), + m_config.get_atom_sz(), false, // Now performing a read mf->get_access_warp_mask(), - mf->get_access_byte_mask() ); + mf->get_access_byte_mask(), + mf->get_access_sector_mask()); mem_fetch *n_mf = new mem_fetch( *ma, NULL, @@ -889,20 +1187,22 @@ data_cache::wr_miss_wa( new_addr_type addr, bool do_miss = false; bool wb = false; - cache_block_t evicted; + evicted_block_info evicted; // Send read request resulting from write miss send_read_request(addr, block_addr, cache_index, n_mf, time, do_miss, wb, evicted, events, false, true); + events.push_back(cache_event(WRITE_ALLOCATE_SENT)); + if( do_miss ){ // If evicted block is modified and not a write-through // (already modified lower level) if( wb && (m_config.m_write_policy != WRITE_THROUGH) ) { + assert(status == MISS); //SECTOR_MISS and HIT_RESERVED should not send write back mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr, - m_wrbk_type,m_config.get_line_sz(),true); - m_miss_queue.push_back(wb); - wb->set_status(m_miss_queue_status,time); + m_wrbk_type,evicted.m_modified_size,true); + send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } return MISS; } @@ -910,6 +1210,177 @@ data_cache::wr_miss_wa( new_addr_type addr, return RESERVATION_FAIL; } + +enum cache_request_status +data_cache::wr_miss_wa_fetch_on_write( new_addr_type addr, + unsigned cache_index, mem_fetch *mf, + unsigned time, std::list &events, + enum cache_request_status status ) +{ + new_addr_type block_addr = m_config.block_addr(addr); + new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr()); + + if(mf->get_access_byte_mask().count() == m_config.get_atom_sz()) + { + //if the request writes to the whole cache line/sector, then, write and set cache line Modified. + //and no need to send read request to memory or reserve mshr + + if(miss_queue_full(0)) { + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); + return RESERVATION_FAIL; // cannot handle request this cycle + } + + bool wb = false; + evicted_block_info evicted; + + cache_request_status status = m_tag_array->access(block_addr,time,cache_index,wb,evicted,mf); + assert(status != HIT); + cache_block_t* block = m_tag_array->get_block(cache_index); + block->set_status(MODIFIED, mf->get_access_sector_mask()); + if(status == HIT_RESERVED) + block->set_ignore_on_fill(true, mf->get_access_sector_mask()); + + if( status != RESERVATION_FAIL ){ + // If evicted block is modified and not a write-through + // (already modified lower level) + if( wb && (m_config.m_write_policy != WRITE_THROUGH) ) { + mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr, + m_wrbk_type,evicted.m_modified_size,true); + send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); + } + return MISS; + } + return RESERVATION_FAIL; + } + else + { + bool mshr_hit = m_mshrs.probe(mshr_addr); + bool mshr_avail = !m_mshrs.full(mshr_addr); + if(miss_queue_full(1) + || (!(mshr_hit && mshr_avail) + && !(!mshr_hit && mshr_avail && (m_miss_queue.size() < m_config.m_miss_queue_size)))) { + //check what is the exactly the failure reason + if(miss_queue_full(1) ) + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); + else if(mshr_hit && !mshr_avail) + m_stats.inc_fail_stats(mf->get_access_type(), MSHR_MERGE_ENRTY_FAIL); + else if (!mshr_hit && !mshr_avail) + m_stats.inc_fail_stats(mf->get_access_type(), MSHR_ENRTY_FAIL); + else + assert(0); + + return RESERVATION_FAIL; + } + + + //prevent Write - Read - Write in pending mshr + //allowing another write will override the value of the first write, and the pending read request will read incorrect result from the second write + if(m_mshrs.probe(mshr_addr) && m_mshrs.is_read_after_write_pending(mshr_addr) && mf->is_write()) + { + //assert(0); + m_stats.inc_fail_stats(mf->get_access_type(), MSHR_RW_PENDING); + return RESERVATION_FAIL; + } + + const mem_access_t *ma = new mem_access_t( m_wr_alloc_type, + mf->get_addr(), + m_config.get_atom_sz(), + false, // Now performing a read + mf->get_access_warp_mask(), + mf->get_access_byte_mask(), + mf->get_access_sector_mask()); + + mem_fetch *n_mf = new mem_fetch( *ma, + NULL, + mf->get_ctrl_size(), + mf->get_wid(), + mf->get_sid(), + mf->get_tpc(), + mf->get_mem_config(), + NULL, + mf); + + + new_addr_type block_addr = m_config.block_addr(addr); + bool do_miss = false; + bool wb = false; + evicted_block_info evicted; + send_read_request( addr, + block_addr, + cache_index, + n_mf, time, do_miss, wb, evicted, events, false, true); + + cache_block_t* block = m_tag_array->get_block(cache_index); + block->set_modified_on_fill(true, mf->get_access_sector_mask()); + + events.push_back(cache_event(WRITE_ALLOCATE_SENT)); + + if( do_miss ){ + // If evicted block is modified and not a write-through + // (already modified lower level) + if(wb && (m_config.m_write_policy != WRITE_THROUGH) ){ + mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr, + m_wrbk_type,evicted.m_modified_size,true); + send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); + } + return MISS; + } + return RESERVATION_FAIL; + } +} + +enum cache_request_status +data_cache::wr_miss_wa_lazy_fetch_on_read( new_addr_type addr, + unsigned cache_index, mem_fetch *mf, + unsigned time, std::list &events, + enum cache_request_status status ) +{ + + new_addr_type block_addr = m_config.block_addr(addr); + new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr()); + + + //if the request writes to the whole cache line/sector, then, write and set cache line Modified. + //and no need to send read request to memory or reserve mshr + + if(miss_queue_full(0)) { + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); + return RESERVATION_FAIL; // cannot handle request this cycle + } + + bool wb = false; + evicted_block_info evicted; + + cache_request_status m_status = m_tag_array->access(block_addr,time,cache_index,wb,evicted,mf); + assert(m_status != HIT); + cache_block_t* block = m_tag_array->get_block(cache_index); + block->set_status(MODIFIED, mf->get_access_sector_mask()); + if(m_status == HIT_RESERVED) { + block->set_ignore_on_fill(true, mf->get_access_sector_mask()); + block->set_modified_on_fill(true, mf->get_access_sector_mask()); + } + + if(mf->get_access_byte_mask().count() == m_config.get_atom_sz()) + { + block->set_m_readable(true, mf->get_access_sector_mask()); + } else + { + block->set_m_readable(false, mf->get_access_sector_mask()); + } + + if( m_status != RESERVATION_FAIL ){ + // If evicted block is modified and not a write-through + // (already modified lower level) + if( wb && (m_config.m_write_policy != WRITE_THROUGH) ) { + mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr, + m_wrbk_type,evicted.m_modified_size,true); + send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); + } + return MISS; + } + return RESERVATION_FAIL; +} + /// No write-allocate miss: Simply send write request to lower level memory enum cache_request_status data_cache::wr_miss_no_wa( new_addr_type addr, @@ -919,11 +1390,14 @@ data_cache::wr_miss_no_wa( new_addr_type addr, std::list &events, enum cache_request_status status ) { - if(miss_queue_full(0)) - return RESERVATION_FAIL; // cannot handle request this cycle + if(miss_queue_full(0)) { + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); + return RESERVATION_FAIL; // cannot handle request this cycle + } + // on miss, generate write through (no write buffering -- too many threads for that) - send_write_request(mf, WRITE_REQUEST_SENT, time, events); + send_write_request(mf, cache_event(WRITE_REQUEST_SENT), time, events); return MISS; } @@ -941,13 +1415,13 @@ data_cache::rd_hit_base( new_addr_type addr, enum cache_request_status status ) { new_addr_type block_addr = m_config.block_addr(addr); - m_tag_array->access(block_addr,time,cache_index); + m_tag_array->access(block_addr,time,cache_index,mf); // Atomics treated as global read/write requests - Perform read, mark line as // MODIFIED if(mf->isatomic()){ assert(mf->get_access_type() == GLOBAL_ACC_R); - cache_block_t &block = m_tag_array->get_block(cache_index); - block.m_status = MODIFIED; // mark line as dirty + cache_block_t* block = m_tag_array->get_block(cache_index); + block->set_status(MODIFIED, mf->get_access_sector_mask()) ; // mark line as dirty } return HIT; } @@ -963,15 +1437,17 @@ data_cache::rd_miss_base( new_addr_type addr, unsigned time, std::list &events, enum cache_request_status status ){ - if(miss_queue_full(1)) + if(miss_queue_full(1)) { // cannot handle request this cycle // (might need to generate two requests) + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); return RESERVATION_FAIL; + } new_addr_type block_addr = m_config.block_addr(addr); bool do_miss = false; bool wb = false; - cache_block_t evicted; + evicted_block_info evicted; send_read_request( addr, block_addr, cache_index, @@ -982,12 +1458,12 @@ data_cache::rd_miss_base( new_addr_type addr, // (already modified lower level) if(wb && (m_config.m_write_policy != WRITE_THROUGH) ){ mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr, - m_wrbk_type,m_config.get_line_sz(),true); + m_wrbk_type,evicted.m_modified_size,true); send_write_request(wb, WRITE_BACK_REQUEST_SENT, time, events); } return MISS; } - return RESERVATION_FAIL; + return RESERVATION_FAIL; } /// Access cache for read_only_cache: returns RESERVATION_FAIL if @@ -998,16 +1474,16 @@ read_only_cache::access( new_addr_type addr, unsigned time, std::list &events ) { - assert( mf->get_data_size() <= m_config.get_line_sz()); + assert( mf->get_data_size() <= m_config.get_atom_sz()); assert(m_config.m_write_policy == READ_ONLY); assert(!mf->get_is_write()); new_addr_type block_addr = m_config.block_addr(addr); unsigned cache_index = (unsigned)-1; - enum cache_request_status status = m_tag_array->probe(block_addr,cache_index); + enum cache_request_status status = m_tag_array->probe(block_addr,cache_index,mf); enum cache_request_status cache_status = RESERVATION_FAIL; if ( status == HIT ) { - cache_status = m_tag_array->access(block_addr,time,cache_index); // update LRU state + cache_status = m_tag_array->access(block_addr,time,cache_index,mf); // update LRU state }else if ( status != RESERVATION_FAIL ) { if(!miss_queue_full(0)){ bool do_miss=false; @@ -1018,7 +1494,10 @@ read_only_cache::access( new_addr_type addr, cache_status = RESERVATION_FAIL; }else{ cache_status = RESERVATION_FAIL; + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); } + }else { + m_stats.inc_fail_stats(mf->get_access_type(), LINE_ALLOC_FAIL); } m_stats.inc_stats(mf->get_access_type(), m_stats.select_stats_status(status, cache_status)); @@ -1047,10 +1526,13 @@ data_cache::process_tag_probe( bool wr, access_status = (this->*m_wr_hit)( addr, cache_index, mf, time, events, probe_status ); - }else if ( probe_status != RESERVATION_FAIL ) { + }else if ( (probe_status != RESERVATION_FAIL) || (probe_status == RESERVATION_FAIL && m_config.m_write_alloc_policy == NO_WRITE_ALLOCATE) ) { access_status = (this->*m_wr_miss)( addr, cache_index, mf, time, events, probe_status ); + }else { + //the only reason for reservation fail here is LINE_ALLOC_FAIL (i.e all lines are reserved) + m_stats.inc_fail_stats(mf->get_access_type(), LINE_ALLOC_FAIL); } }else{ // Read if(probe_status == HIT){ @@ -1061,6 +1543,9 @@ data_cache::process_tag_probe( bool wr, access_status = (this->*m_rd_miss)( addr, cache_index, mf, time, events, probe_status ); + }else { + //the only reason for reservation fail here is LINE_ALLOC_FAIL (i.e all lines are reserved) + m_stats.inc_fail_stats(mf->get_access_type(), LINE_ALLOC_FAIL); } } @@ -1080,12 +1565,12 @@ data_cache::access( new_addr_type addr, std::list &events ) { - assert( mf->get_data_size() <= m_config.get_line_sz()); + assert( mf->get_data_size() <= m_config.get_atom_sz()); bool wr = mf->get_is_write(); new_addr_type block_addr = m_config.block_addr(addr); unsigned cache_index = (unsigned)-1; enum cache_request_status probe_status - = m_tag_array->probe( block_addr, cache_index ); + = m_tag_array->probe( block_addr, cache_index, mf, true); enum cache_request_status access_status = process_tag_probe( wr, probe_status, addr, cache_index, mf, time, events ); m_stats.inc_stats(mf->get_access_type(), @@ -1134,7 +1619,7 @@ enum cache_request_status tex_cache::access( new_addr_type addr, mem_fetch *mf, // at this point, we will accept the request : access tags and immediately allocate line new_addr_type block_addr = m_config.block_addr(addr); unsigned cache_index = (unsigned)-1; - enum cache_request_status status = m_tags.access(block_addr,time,cache_index); + enum cache_request_status status = m_tags.access(block_addr,time,cache_index,mf); enum cache_request_status cache_status = RESERVATION_FAIL; assert( status != RESERVATION_FAIL ); assert( status != HIT_RESERVED ); // as far as tags are concerned: HIT or MISS @@ -1142,12 +1627,12 @@ enum cache_request_status tex_cache::access( new_addr_type addr, mem_fetch *mf, if ( status == MISS ) { // we need to send a memory request... unsigned rob_index = m_rob.push( rob_entry(cache_index, mf, block_addr) ); - m_extra_mf_fields[mf] = extra_mf_fields(rob_index); + m_extra_mf_fields[mf] = extra_mf_fields(rob_index, m_config); mf->set_data_size(m_config.get_line_sz()); - m_tags.fill(cache_index,time); // mark block as valid + m_tags.fill(cache_index,time,mf); // mark block as valid m_request_fifo.push(mf); mf->set_status(m_request_queue_status,time); - events.push_back(READ_REQUEST_SENT); + events.push_back(cache_event(READ_REQUEST_SENT)); cache_status = MISS; } else { // the value *will* *be* in the cache already @@ -1174,7 +1659,7 @@ void tex_cache::cycle(){ unsigned rob_index = m_rob.next_pop_index(); const rob_entry &r = m_rob.peek(rob_index); assert( r.m_request == e.m_request ); - assert( r.m_block_addr == m_config.block_addr(e.m_request->get_addr()) ); + //assert( r.m_block_addr == m_config.block_addr(e.m_request->get_addr()) ); if ( r.m_ready ) { assert( r.m_index == e.m_cache_index ); m_cache[r.m_index].m_valid = true; @@ -1197,6 +1682,23 @@ void tex_cache::cycle(){ /// Place returning cache block into reorder buffer void tex_cache::fill( mem_fetch *mf, unsigned time ) { + if(m_config.m_mshr_type == SECTOR_TEX_FIFO) { + assert(mf->get_original_mf()); + extra_mf_fields_lookup::iterator e = m_extra_mf_fields.find(mf->get_original_mf()); + assert( e != m_extra_mf_fields.end() ); + e->second.pending_read--; + + if(e->second.pending_read > 0) { + //wait for the other requests to come back + delete mf; + return; + } else { + mem_fetch *temp = mf; + mf = mf->get_original_mf(); + delete temp; + } + } + extra_mf_fields_lookup::iterator e = m_extra_mf_fields.find(mf); assert( e != m_extra_mf_fields.end() ); assert( e->second.m_valid ); diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 7535a1d..e663cf6 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -36,9 +36,12 @@ #include "../tr1_hash_map.h" #include "addrdec.h" +#include + +#define MAX_DEFAULT_CACHE_SIZE_MULTIBLIER 4 enum cache_block_state { - INVALID, + INVALID=0, RESERVED, VALID, MODIFIED @@ -49,13 +52,51 @@ enum cache_request_status { HIT_RESERVED, MISS, RESERVATION_FAIL, + SECTOR_MISS, NUM_CACHE_REQUEST_STATUS }; -enum cache_event { +enum cache_reservation_fail_reason { + LINE_ALLOC_FAIL= 0,// all line are reserved + MISS_QUEUE_FULL, // MISS queue (i.e. interconnect or DRAM) is full + MSHR_ENRTY_FAIL, + MSHR_MERGE_ENRTY_FAIL, + MSHR_RW_PENDING, + NUM_CACHE_RESERVATION_FAIL_STATUS +}; + +enum cache_event_type { WRITE_BACK_REQUEST_SENT, READ_REQUEST_SENT, - WRITE_REQUEST_SENT + WRITE_REQUEST_SENT, + WRITE_ALLOCATE_SENT +}; + +struct evicted_block_info { + new_addr_type m_block_addr; + unsigned m_modified_size; + evicted_block_info() { + m_block_addr = 0; + m_modified_size = 0; + } + void set_info(new_addr_type block_addr, unsigned modified_size){ + m_block_addr = block_addr; + m_modified_size = modified_size; + } +}; + +struct cache_event { + enum cache_event_type m_cache_event_type; + evicted_block_info m_evicted_block; //if it was write_back event, fill the the evicted block info + + cache_event(enum cache_event_type m_cache_event){ + m_cache_event_type = m_cache_event; + } + + cache_event(enum cache_event_type cache_event, evicted_block_info evicted_block){ + m_cache_event_type = cache_event; + m_evicted_block = evicted_block; + } }; const char * cache_request_status_str(enum cache_request_status status); @@ -65,33 +106,340 @@ struct cache_block_t { { m_tag=0; m_block_addr=0; - m_alloc_time=0; - m_fill_time=0; - m_last_access_time=0; - m_status=INVALID; } - void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time ) + + virtual void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask) = 0; + virtual void fill( unsigned time, mem_access_sector_mask_t sector_mask) = 0; + + virtual bool is_invalid_line() = 0; + virtual bool is_valid_line() = 0; + virtual bool is_reserved_line() = 0; + virtual bool is_modified_line() = 0; + + virtual enum cache_block_state get_status( mem_access_sector_mask_t sector_mask) = 0; + virtual void set_status(enum cache_block_state m_status, mem_access_sector_mask_t sector_mask) = 0; + + virtual unsigned get_last_access_time() = 0; + virtual void set_last_access_time(unsigned time, mem_access_sector_mask_t sector_mask) = 0; + virtual unsigned get_alloc_time() = 0; + virtual void set_ignore_on_fill(bool m_ignore, mem_access_sector_mask_t sector_mask) = 0; + virtual void set_modified_on_fill(bool m_modified, mem_access_sector_mask_t sector_mask) = 0; + virtual unsigned get_modified_size() = 0; + virtual void set_m_readable(bool readable, mem_access_sector_mask_t sector_mask)=0; + virtual bool is_readable(mem_access_sector_mask_t sector_mask)=0; + virtual void print_status()=0; + virtual ~cache_block_t() {} + + + new_addr_type m_tag; + new_addr_type m_block_addr; + +}; + +struct line_cache_block: public cache_block_t { + line_cache_block() + { + m_alloc_time=0; + m_fill_time=0; + m_last_access_time=0; + m_status=INVALID; + m_ignore_on_fill_status = false; + m_set_modified_on_fill = false; + m_readable = true; + } + void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask) + { + m_tag=tag; + m_block_addr=block_addr; + m_alloc_time=time; + m_last_access_time=time; + m_fill_time=0; + m_status=RESERVED; + m_ignore_on_fill_status = false; + m_set_modified_on_fill = false; + } + void fill( unsigned time, mem_access_sector_mask_t sector_mask ) + { + //if(!m_ignore_on_fill_status) + // assert( m_status == RESERVED ); + + m_status = m_set_modified_on_fill? MODIFIED : VALID; + + m_fill_time=time; + } + virtual bool is_invalid_line() + { + return m_status == INVALID; + } + virtual bool is_valid_line() + { + return m_status == VALID; + } + virtual bool is_reserved_line() + { + return m_status == RESERVED; + } + virtual bool is_modified_line() + { + return m_status == MODIFIED; + } + + virtual enum cache_block_state get_status(mem_access_sector_mask_t sector_mask) + { + return m_status; + } + virtual void set_status(enum cache_block_state status, mem_access_sector_mask_t sector_mask) + { + m_status = status; + } + virtual unsigned get_last_access_time() + { + return m_last_access_time; + } + virtual void set_last_access_time(unsigned time, mem_access_sector_mask_t sector_mask) + { + m_last_access_time = time; + } + virtual unsigned get_alloc_time() + { + return m_alloc_time; + } + virtual void set_ignore_on_fill(bool m_ignore, mem_access_sector_mask_t sector_mask) + { + m_ignore_on_fill_status = m_ignore; + } + virtual void set_modified_on_fill(bool m_modified, mem_access_sector_mask_t sector_mask) + { + m_set_modified_on_fill = m_modified; + } + virtual unsigned get_modified_size() + { + return SECTOR_CHUNCK_SIZE * SECTOR_SIZE; //i.e. cache line size + } + virtual void set_m_readable(bool readable, mem_access_sector_mask_t sector_mask) + { + m_readable = readable; + } + virtual bool is_readable(mem_access_sector_mask_t sector_mask) { + return m_readable; + } + virtual void print_status() { + printf("m_block_addr is %llu, status = %u\n", m_block_addr, m_status); + } + + +private: + unsigned m_alloc_time; + unsigned m_last_access_time; + unsigned m_fill_time; + cache_block_state m_status; + bool m_ignore_on_fill_status; + bool m_set_modified_on_fill; + bool m_readable; +}; + +struct sector_cache_block : public cache_block_t { + sector_cache_block() { - m_tag=tag; - m_block_addr=block_addr; - m_alloc_time=time; - m_last_access_time=time; - m_fill_time=0; - m_status=RESERVED; + init(); } - void fill( unsigned time ) + + void init() { + for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) { + m_sector_alloc_time[i]= 0; + m_sector_fill_time[i]= 0; + m_last_sector_access_time[i]= 0; + m_status[i]= INVALID; + m_ignore_on_fill_status[i] = false; + m_set_modified_on_fill[i] = false; + m_readable[i] = true; + } + m_line_alloc_time=0; + m_line_last_access_time=0; + m_line_fill_time=0; + } + + virtual void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask ) { - assert( m_status == RESERVED ); - m_status=VALID; - m_fill_time=time; + allocate_line( tag, block_addr, time, sector_mask ); } - new_addr_type m_tag; - new_addr_type m_block_addr; - unsigned m_alloc_time; - unsigned m_last_access_time; - unsigned m_fill_time; - cache_block_state m_status; + void allocate_line( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask ) + { + //allocate a new line + //assert(m_block_addr != 0 && m_block_addr != block_addr); + init(); + m_tag=tag; + m_block_addr=block_addr; + + unsigned sidx = get_sector_index(sector_mask); + + //set sector stats + m_sector_alloc_time[sidx]=time; + m_last_sector_access_time[sidx]=time; + m_sector_fill_time[sidx]=0; + m_status[sidx]=RESERVED; + m_ignore_on_fill_status[sidx] = false; + m_set_modified_on_fill[sidx] = false; + + //set line stats + m_line_alloc_time=time; //only set this for the first allocated sector + m_line_last_access_time=time; + m_line_fill_time=0; + } + + void allocate_sector(unsigned time, mem_access_sector_mask_t sector_mask ) + { + //allocate invalid sector of this allocated valid line + assert(is_valid_line()); + unsigned sidx = get_sector_index(sector_mask); + + //set sector stats + m_sector_alloc_time[sidx]=time; + m_last_sector_access_time[sidx]=time; + m_sector_fill_time[sidx]=0; + if(m_status[sidx]==MODIFIED) //this should be the case only for fetch-on-write policy //TO DO + m_set_modified_on_fill[sidx] = true; + else + m_set_modified_on_fill[sidx] = false; + + m_status[sidx]=RESERVED; + m_ignore_on_fill_status[sidx] = false; + //m_set_modified_on_fill[sidx] = false; + m_readable[sidx] = true; + + //set line stats + m_line_last_access_time=time; + m_line_fill_time=0; + } + + virtual void fill( unsigned time, mem_access_sector_mask_t sector_mask) + { + unsigned sidx = get_sector_index(sector_mask); + + // if(!m_ignore_on_fill_status[sidx]) + // assert( m_status[sidx] == RESERVED ); + + m_status[sidx] = m_set_modified_on_fill[sidx]? MODIFIED : VALID; + + m_sector_fill_time[sidx]=time; + m_line_fill_time=time; + } + virtual bool is_invalid_line() { + //all the sectors should be invalid + for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) { + if (m_status[i] != INVALID) + return false; + } + return true; + } + virtual bool is_valid_line() { return !(is_invalid_line()); } + virtual bool is_reserved_line() { + //if any of the sector is reserved, then the line is reserved + for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) { + if (m_status[i] == RESERVED) + return true; + } + return false; + } + virtual bool is_modified_line() { + //if any of the sector is modified, then the line is modified + for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) { + if (m_status[i] == MODIFIED) + return true; + } + return false; + } + + virtual enum cache_block_state get_status(mem_access_sector_mask_t sector_mask) + { + unsigned sidx = get_sector_index(sector_mask); + + return m_status[sidx]; + } + + virtual void set_status(enum cache_block_state status, mem_access_sector_mask_t sector_mask) + { + unsigned sidx = get_sector_index(sector_mask); + m_status[sidx] = status; + } + + virtual unsigned get_last_access_time() + { + return m_line_last_access_time; + } + + virtual void set_last_access_time(unsigned time, mem_access_sector_mask_t sector_mask) + { + unsigned sidx = get_sector_index(sector_mask); + + m_last_sector_access_time[sidx] = time; + m_line_last_access_time = time; + } + + virtual unsigned get_alloc_time() + { + return m_line_alloc_time; + } + + virtual void set_ignore_on_fill(bool m_ignore, mem_access_sector_mask_t sector_mask) + { + unsigned sidx = get_sector_index(sector_mask); + m_ignore_on_fill_status[sidx] = m_ignore; + } + + virtual void set_modified_on_fill(bool m_modified, mem_access_sector_mask_t sector_mask) + { + unsigned sidx = get_sector_index(sector_mask); + m_set_modified_on_fill[sidx] = m_modified; + } + + virtual void set_m_readable(bool readable, mem_access_sector_mask_t sector_mask) + { + unsigned sidx = get_sector_index(sector_mask); + m_readable[sidx] = readable; + } + + virtual bool is_readable(mem_access_sector_mask_t sector_mask) { + unsigned sidx = get_sector_index(sector_mask); + return m_readable[sidx]; + } + + virtual unsigned get_modified_size() + { + unsigned modified=0; + for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) { + if (m_status[i] == MODIFIED) + modified++; + } + return modified * SECTOR_SIZE; + } + + virtual void print_status() { + printf("m_block_addr is %llu, status = %u %u %u %u\n", m_block_addr, m_status[0], m_status[1], m_status[2], m_status[3]); + } + + +private: + unsigned m_sector_alloc_time[SECTOR_CHUNCK_SIZE]; + unsigned m_last_sector_access_time[SECTOR_CHUNCK_SIZE]; + unsigned m_sector_fill_time[SECTOR_CHUNCK_SIZE]; + unsigned m_line_alloc_time; + unsigned m_line_last_access_time; + unsigned m_line_fill_time; + cache_block_state m_status[SECTOR_CHUNCK_SIZE]; + bool m_ignore_on_fill_status[SECTOR_CHUNCK_SIZE]; + bool m_set_modified_on_fill[SECTOR_CHUNCK_SIZE]; + bool m_readable[SECTOR_CHUNCK_SIZE]; + + unsigned get_sector_index(mem_access_sector_mask_t sector_mask) + { + assert(sector_mask.count() == 1); + for(unsigned i =0; i< SECTOR_CHUNCK_SIZE; ++i) { + if(sector_mask.to_ulong() & (1< line_table; + line_table pending_lines; }; class mshr_table { public: - mshr_table( unsigned num_entries, unsigned max_merged ) + mshr_table( unsigned num_entries, unsigned max_merged) : m_num_entries(num_entries), m_max_merged(max_merged) #if (tr1_hash_map_ismap == 0) @@ -414,6 +879,8 @@ public: /// Returns next ready access mem_fetch *next_access(); void display( FILE *fp ) const; + // Returns true if there is a pending read after write + bool is_read_after_write_pending(new_addr_type block_addr); void check_mshr_parameters( unsigned num_entries, unsigned max_merged ) { @@ -433,7 +900,9 @@ private: mshr_entry() : m_has_atomic(false) { } }; typedef tr1_hash_map table; + typedef tr1_hash_map line_table; table m_data; + line_table pending_lines; // it may take several cycles to process the merged requests bool m_current_response_ready; @@ -510,12 +979,14 @@ public: cache_stats(); void clear(); void inc_stats(int access_type, int access_outcome); + void inc_fail_stats(int access_type, int fail_outcome); enum cache_request_status select_stats_status(enum cache_request_status probe, enum cache_request_status access) const; - unsigned &operator()(int access_type, int access_outcome); - unsigned operator()(int access_type, int access_outcome) const; + unsigned &operator()(int access_type, int access_outcome, bool fail_outcome); + unsigned operator()(int access_type, int access_outcome, bool fail_outcome) const; cache_stats operator+(const cache_stats &cs); cache_stats &operator+=(const cache_stats &cs); void print_stats(FILE *fout, const char *cache_name = "Cache_stats") const; + void print_fail_stats(FILE *fout, const char *cache_name = "Cache_fail_stats") const; unsigned get_stats(enum mem_access_type *access_type, unsigned num_access_type, enum cache_request_status *access_status, unsigned num_access_status) const; void get_sub_stats(struct cache_sub_stats &css) const; @@ -523,8 +994,10 @@ public: void sample_cache_port_utility(bool data_port_busy, bool fill_port_busy); private: bool check_valid(int type, int status) const; + bool check_fail_valid(int type, int fail) const; std::vector< std::vector > m_stats; + std::vector< std::vector > m_fail_stats; unsigned long long m_cache_port_available_cycles; unsigned long long m_cache_data_port_busy_cycles; @@ -543,6 +1016,7 @@ public: bool was_write_sent( const std::list &events ); bool was_read_sent( const std::list &events ); +bool was_writeallocate_sent( const std::list &events ); /// Baseline cache /// Implements common functions for read_only_cache and data_cache @@ -552,7 +1026,7 @@ public: baseline_cache( const char *name, cache_config &config, int core_id, int type_id, mem_fetch_interface *memport, enum mem_fetch_status status ) : m_config(config), m_tag_array(new tag_array(config,core_id,type_id)), - m_mshrs(config.m_mshr_entries,config.m_mshr_max_merge), + m_mshrs(config.m_mshr_entries,config.m_mshr_max_merge), m_bandwidth_management(config) { init( name, config, memport, status ); @@ -564,7 +1038,7 @@ public: enum mem_fetch_status status ) { m_name = name; - assert(config.m_mshr_type == ASSOC); + assert(config.m_mshr_type == ASSOC || config.m_mshr_type == SECTOR_ASSOC); m_memport=memport; m_miss_queue_status = status; } @@ -594,6 +1068,7 @@ public: mem_fetch *next_access(){return m_mshrs.next_access();} // flash invalidate all entries in cache void flush(){m_tag_array->flush();} + void invalidate(){m_tag_array->invalidate();} void print(FILE *fp, unsigned &accesses, unsigned &misses) const; void display_state( FILE *fp ) const; @@ -612,6 +1087,15 @@ public: bool data_port_free() const { return m_bandwidth_management.data_port_free(); } bool fill_port_free() const { return m_bandwidth_management.fill_port_free(); } + // This is a gapping hole we are poking in the system to quickly handle + // filling the cache on cudamemcopies. We don't care about anything other than + // L2 state after the memcopy - so just force the tag array to act as though + // something is read or written without doing anything else. + void force_tag_access( new_addr_type addr, unsigned time, mem_access_sector_mask_t mask ) + { + m_tag_array->fill( addr, time, mask ); + } + protected: // Constructor that can be used by derived classes with custom tag arrays baseline_cache( const char *name, @@ -633,24 +1117,31 @@ protected: std::string m_name; cache_config &m_config; tag_array* m_tag_array; - mshr_table m_mshrs; + mshr_table m_mshrs; std::list m_miss_queue; enum mem_fetch_status m_miss_queue_status; mem_fetch_interface *m_memport; struct extra_mf_fields { extra_mf_fields() { m_valid = false;} - extra_mf_fields( new_addr_type a, unsigned i, unsigned d ) + extra_mf_fields( new_addr_type a, new_addr_type ad, unsigned i, unsigned d, const cache_config& m_config) { m_valid = true; m_block_addr = a; + m_addr = ad; m_cache_index = i; m_data_size = d; + pending_read = m_config.m_mshr_type == SECTOR_ASSOC? m_config.m_line_sz/SECTOR_SIZE : 0; + } bool m_valid; new_addr_type m_block_addr; + new_addr_type m_addr; unsigned m_cache_index; unsigned m_data_size; + //this variable is used when a load request generates multiple load transactions + //For example, a read request from non-sector L1 request sends a request to sector L2 + unsigned pending_read; }; typedef std::map extra_mf_fields_lookup; @@ -668,7 +1159,7 @@ protected: unsigned time, bool &do_miss, std::list &events, bool read_only, bool wa); /// Read miss handler. Check MSHR hit or MSHR available void send_read_request(new_addr_type addr, new_addr_type block_addr, unsigned cache_index, mem_fetch *mf, - unsigned time, bool &do_miss, bool &wb, cache_block_t &evicted, std::list &events, bool read_only, bool wa); + unsigned time, bool &do_miss, bool &wb, evicted_block_info &evicted, std::list &events, bool read_only, bool wa); /// Sub-class containing all metadata for port bandwidth management class bandwidth_management @@ -760,8 +1251,10 @@ public: // Set write miss function switch(m_config.m_write_alloc_policy){ - case WRITE_ALLOCATE: m_wr_miss = &data_cache::wr_miss_wa; break; case NO_WRITE_ALLOCATE: m_wr_miss = &data_cache::wr_miss_no_wa; break; + case WRITE_ALLOCATE: m_wr_miss = &data_cache::wr_miss_wa_naive; break; + case FETCH_ON_WRITE: m_wr_miss = &data_cache::wr_miss_wa_fetch_on_write; break; + case LAZY_FETCH_ON_READ: m_wr_miss = &data_cache::wr_miss_wa_lazy_fetch_on_read; break; default: assert(0 && "Error: Must set valid cache write miss policy\n"); break; // Need to set a write miss function @@ -870,12 +1363,33 @@ protected: /// Sends read request, and possible write-back request, // to lower level memory for a write miss with write-allocate enum cache_request_status - wr_miss_wa( new_addr_type addr, - unsigned cache_index, - mem_fetch *mf, - unsigned time, - std::list &events, - enum cache_request_status status ); // write-allocate + wr_miss_wa_naive( new_addr_type addr, + unsigned cache_index, + mem_fetch *mf, + unsigned time, + std::list &events, + enum cache_request_status status ); // write-allocate-send-write-and-read-request + enum cache_request_status + wr_miss_wa_fetch_on_write( new_addr_type addr, + unsigned cache_index, + mem_fetch *mf, + unsigned time, + std::list &events, + enum cache_request_status status ); // write-allocate with fetch-on-every-write + enum cache_request_status + wr_miss_wa_lazy_fetch_on_read( new_addr_type addr, + unsigned cache_index, + mem_fetch *mf, + unsigned time, + std::list &events, + enum cache_request_status status ); // write-allocate with read-fetch-only + enum cache_request_status + wr_miss_wa_write_validate( new_addr_type addr, + unsigned cache_index, + mem_fetch *mf, + unsigned time, + std::list &events, + enum cache_request_status status ); // write-allocate that writes with no read fetch enum cache_request_status wr_miss_no_wa( new_addr_type addr, unsigned cache_index, @@ -991,7 +1505,7 @@ public: m_result_fifo(config.m_result_fifo_entries) { m_name = name; - assert(config.m_mshr_type == TEX_FIFO); + assert(config.m_mshr_type == TEX_FIFO || config.m_mshr_type == SECTOR_TEX_FIFO ); assert(config.m_write_policy == READ_ONLY); assert(config.m_alloc_policy == ON_MISS); m_memport=memport; @@ -1144,13 +1658,15 @@ private: struct extra_mf_fields { extra_mf_fields() { m_valid = false;} - extra_mf_fields( unsigned i ) + extra_mf_fields( unsigned i, const cache_config &m_config ) { m_valid = true; m_rob_index = i; + pending_read = m_config.m_mshr_type == SECTOR_TEX_FIFO? m_config.m_line_sz/SECTOR_SIZE : 0; } bool m_valid; unsigned m_rob_index; + unsigned pending_read; }; cache_stats m_stats; diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 63ba759..a8be4d2 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -150,6 +150,8 @@ void power_config::reg_options(class OptionParser * opp) void memory_config::reg_options(class OptionParser * opp) { + option_parser_register(opp, "-perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, + "Fill the L2 cache on memcpy", "1"); option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, &scheduler_type, "0 = fifo, 1 = FR-FCFS (defaul)", "1"); option_parser_register(opp, "-gpgpu_dram_partition_queues", OPT_CSTR, &gpgpu_L2_queue_config, @@ -202,7 +204,27 @@ void memory_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-dram_latency", OPT_UINT32, &dram_latency, "DRAM latency (default 30)", "30"); - + option_parser_register(opp, "-dual_bus_interface", OPT_UINT32, &dual_bus_interface, + "dual_bus_interface (default = 0) ", + "0"); + option_parser_register(opp, "-dram_bnk_indexing_policy", OPT_UINT32, &dram_bnk_indexing_policy, + "dram_bnk_indexing_policy (0 = normal indexing, 1 = Xoring with the higher bits) (Default = 0)", + "0"); + option_parser_register(opp, "-dram_bnkgrp_indexing_policy", OPT_UINT32, &dram_bnkgrp_indexing_policy, + "dram_bnkgrp_indexing_policy (0 = take higher bits, 1 = take lower bits) (Default = 0)", + "0"); + option_parser_register(opp, "-Seperate_Write_Queue_Enable", OPT_BOOL, &seperate_write_queue_enabled, + "Seperate_Write_Queue_Enable", + "0"); + option_parser_register(opp, "-Write_Queue_Size", OPT_CSTR, &write_queue_size_opt, + "Write_Queue_Size", + "32:28:16"); + option_parser_register(opp, "-Elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround, + "elimnate_rw_turnaround i.e set tWTR and tRTW = 0", + "0"); + option_parser_register(opp, "-icnt_flit_size", OPT_UINT32, &icnt_flit_size, + "icnt_flit_size", + "32"); m_address_mapping.addrdec_setoption(opp); } @@ -229,6 +251,12 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); + option_parser_register(opp, "-l1_latency", OPT_UINT32, &m_L1D_config.l1_latency, + "L1 Hit Latency", + "0"); + option_parser_register(opp, "-smem_latency", OPT_UINT32, &smem_latency, + "smem Latency", + "3"); option_parser_register(opp, "-gpgpu_cache:dl1PrefL1", OPT_CSTR, &m_L1D_config.m_config_stringPrefL1, "per-shader L1 data cache config " " {::,:::,::, | none}", @@ -256,6 +284,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shader_registers", OPT_UINT32, &gpgpu_shader_registers, "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); + option_parser_register(opp, "-gpgpu_ignore_resources_limitation", OPT_BOOL, &gpgpu_ignore_resources_limitation, + "gpgpu_ignore_resources_limitation (default 0)", + "0"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", "8"); @@ -277,6 +308,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); + option_parser_register(opp, "-adpative_volta_cache_config", OPT_BOOL, &adpative_volta_cache_config, + "adpative_volta_cache_config", + "0"); option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_sizeDefault, "Size of shared memory per shader core (default 16kB)", "16384"); @@ -295,6 +329,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts, "Number of portions a warp is divided into for shared memory bank conflict check ", "2"); + option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts, + "Number of portions a warp is divided into for shared memory bank conflict check ", + "2"); option_parser_register(opp, "-gpgpu_warpdistro_shader", OPT_INT32, &gpgpu_warpdistro_shader, "Specify which shader core to collect the warp size distribution from", "-1"); @@ -303,7 +340,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "0"); option_parser_register(opp, "-gpgpu_local_mem_map", OPT_BOOL, &gpgpu_local_mem_map, "Mapping from local memory space address to simulated GPU physical address space (default = enabled)", - "1"); + "1"); option_parser_register(opp, "-gpgpu_num_reg_banks", OPT_INT32, &gpgpu_num_reg_banks, "Number of register banks (default = 8)", "8"); @@ -313,6 +350,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_units_sp", OPT_INT32, &gpgpu_operand_collector_num_units_sp, "number of collector units (default = 4)", "4"); + option_parser_register(opp, "-gpgpu_operand_collector_num_units_dp", OPT_INT32, &gpgpu_operand_collector_num_units_dp, + "number of collector units (default = 0)", + "0"); option_parser_register(opp, "-gpgpu_operand_collector_num_units_sfu", OPT_INT32, &gpgpu_operand_collector_num_units_sfu, "number of collector units (default = 4)", "4"); @@ -328,6 +368,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_sp", OPT_INT32, &gpgpu_operand_collector_num_in_ports_sp, "number of collector unit in ports (default = 1)", "1"); + option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_dp", OPT_INT32, &gpgpu_operand_collector_num_in_ports_dp, + "number of collector unit in ports (default = 0)", + "0"); option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_sfu", OPT_INT32, &gpgpu_operand_collector_num_in_ports_sfu, "number of collector unit in ports (default = 1)", "1"); @@ -343,6 +386,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_sp", OPT_INT32, &gpgpu_operand_collector_num_out_ports_sp, "number of collector unit in ports (default = 1)", "1"); + option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_dp", OPT_INT32, &gpgpu_operand_collector_num_out_ports_dp, + "number of collector unit in ports (default = 0)", + "0"); option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_sfu", OPT_INT32, &gpgpu_operand_collector_num_out_ports_sfu, "number of collector unit in ports (default = 1)", "1"); @@ -356,27 +402,33 @@ void shader_core_config::reg_options(class OptionParser * opp) "number of collector unit in ports (default = 0)", "0"); option_parser_register(opp, "-gpgpu_coalesce_arch", OPT_INT32, &gpgpu_coalesce_arch, - "Coalescing arch (default = 13, anything else is off for now)", + "Coalescing arch (GT200 = 13, Fermi = 20)", "13"); option_parser_register(opp, "-gpgpu_num_sched_per_core", OPT_INT32, &gpgpu_num_sched_per_core, "Number of warp schedulers per core", "1"); option_parser_register(opp, "-gpgpu_max_insn_issue_per_warp", OPT_INT32, &gpgpu_max_insn_issue_per_warp, - "Max number of instructions that can be issued per warp in one cycle by scheduler", - "2"); + "Max number of instructions that can be issued per warp in one cycle by scheduler (either 1 or 2)", + "2"); + option_parser_register(opp, "-gpgpu_dual_issue_diff_exec_units", OPT_BOOL, &gpgpu_dual_issue_diff_exec_units, + "should dual issue use two different execution unit resources (Default = 1)", + "1"); option_parser_register(opp, "-gpgpu_simt_core_sim_order", OPT_INT32, &simt_core_sim_order, "Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)", "1"); option_parser_register(opp, "-gpgpu_pipeline_widths", OPT_CSTR, &pipeline_widths_string, "Pipeline widths " - "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB", - "1,1,1,1,1,1,1,1,1,1" ); + "ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE", + "1,1,1,1,1,1,1,1,1,1,1" ); option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_INT32, &gpgpu_tensor_core_avail, "Tensor Core Available (default=0)", "0"); option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32, &gpgpu_num_sp_units, "Number of SP units (default=1)", "1"); + option_parser_register(opp, "-gpgpu_num_dp_units", OPT_INT32, &gpgpu_num_dp_units, + "Number of DP units (default=0)", + "0"); option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_INT32, &gpgpu_num_sfu_units, "Number of SF units (default=1)", "1"); @@ -425,7 +477,6 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) option_parser_register(opp, "-gpgpu_flush_l2_cache", OPT_BOOL, &gpgpu_flush_l2_cache, "Flush L2 cache at the end of each kernel call", "0"); - option_parser_register(opp, "-gpgpu_deadlock_detect", OPT_BOOL, &gpu_deadlock_detect, "Stop the simulation at deadlock (1=on (default), 0=off)", "1"); @@ -669,7 +720,7 @@ gpgpu_sim::gpgpu_sim( const gpgpu_sim_config &config ) m_running_kernels.resize( config.max_concurrent_kernel, NULL ); m_last_issued_kernel = 0; - m_last_cluster_issue = 0; + m_last_cluster_issue = m_shader_config->n_simt_clusters-1; // this causes first launch to use simt cluster 0 *average_pipeline_duty_cycle=0; *active_sms=0; @@ -813,6 +864,7 @@ void gpgpu_sim::update_stats() { partiton_replys_in_parallel_total += partiton_replys_in_parallel; partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util; gpu_tot_sim_cycle_parition_util += gpu_sim_cycle_parition_util ; + gpu_tot_occupancy += gpu_occupancy; gpu_sim_cycle = 0; partiton_reqs_in_parallel = 0; @@ -821,6 +873,7 @@ void gpgpu_sim::update_stats() { gpu_sim_cycle_parition_util = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; + gpu_occupancy = occupancy_stats(); } void gpgpu_sim::print_stats() @@ -994,6 +1047,9 @@ void gpgpu_sim::gpu_print_stat() printf("gpu_tot_sim_insn = %lld\n", gpu_tot_sim_insn+gpu_sim_insn); printf("gpu_tot_ipc = %12.4f\n", (float)(gpu_tot_sim_insn+gpu_sim_insn) / (gpu_tot_sim_cycle+gpu_sim_cycle)); printf("gpu_tot_issued_cta = %lld\n", gpu_tot_issued_cta + m_total_cta_launched); + printf("gpu_occupancy = %.4f\% \n", gpu_occupancy.get_occ_fraction() * 100); + printf("gpu_tot_occupancy = %.4f\% \n", (gpu_occupancy + gpu_tot_occupancy).get_occ_fraction() * 100); + extern unsigned long long g_max_total_param_size; fprintf(statfout, "max_total_param_size = %llu\n", g_max_total_param_size); @@ -1032,6 +1088,8 @@ void gpgpu_sim::gpu_print_stat() } printf("\nTotal_core_cache_stats:\n"); core_cache_stats.print_stats(stdout, "Total_core_cache_stats_breakdown"); + printf("\nTotal_core_cache_fail_stats:\n"); + core_cache_stats.print_fail_stats(stdout, "Total_core_cache_fail_stats_breakdown"); shader_print_scheduler_stat( stdout, false ); m_shader_stats->print(stdout); @@ -1076,6 +1134,8 @@ void gpgpu_sim::gpu_print_stat() printf("L2_total_cache_reservation_fails = %u\n", total_l2_css.res_fails); printf("L2_total_cache_breakdown:\n"); l2_stats.print_stats(stdout, "L2_cache_stats_breakdown"); + printf("L2_total_cache_reservation_fail_breakdown:\n"); + l2_stats.print_fail_stats(stdout, "L2_cache_stats_fail_breakdown"); total_l2_css.print_port_stats(stdout, "L2_cache"); } } @@ -1429,7 +1489,7 @@ void gpgpu_sim::cycle() if (mf) { unsigned response_size = mf->get_is_write()?mf->get_ctrl_size():mf->size(); if ( ::icnt_has_buffer( m_shader_config->mem2device(i), response_size ) ) { - if (!mf->get_is_write()) + //if (!mf->get_is_write()) mf->set_return_timestamp(gpu_sim_cycle+gpu_tot_sim_cycle); mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle); ::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size ); @@ -1462,12 +1522,14 @@ void gpgpu_sim::cycle() for (unsigned i=0;im_n_mem_sub_partition;i++) { //move memory request from interconnect into memory partition (if not backed up) //Note:This needs to be called in DRAM clock domain if there is no L2 cache in the system - if ( m_memory_sub_partition[i]->full() ) { + //In the worst case, we may need to push SECTOR_CHUNCK_SIZE requests, so ensure you have enough buffer for them + if ( m_memory_sub_partition[i]->full(SECTOR_CHUNCK_SIZE) ) { gpu_stall_dramfull++; } else { mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) ); m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle ); - partiton_reqs_in_parallel_per_cycle++; + if(mf) + partiton_reqs_in_parallel_per_cycle++; } m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle); m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]); @@ -1494,6 +1556,8 @@ void gpgpu_sim::cycle() // Update core icnt/cache stats for GPUWattch m_cluster[i]->get_icnt_stats(m_power_stats->pwr_mem_stat->n_simt_to_mem[CURRENT_STAT_IDX][i], m_power_stats->pwr_mem_stat->n_mem_to_simt[CURRENT_STAT_IDX][i]); m_cluster[i]->get_cache_stats(m_power_stats->pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX]); + m_cluster[i]->get_current_occupancy(gpu_occupancy.aggregate_warp_slot_filled, gpu_occupancy.aggregate_theoretical_warp_slots); + } float temp=0; for (unsigned i=0;inum_shader();i++){ @@ -1521,12 +1585,12 @@ void gpgpu_sim::cycle() issue_block2core(); - // Depending on configuration, flush the caches once all of threads are completed. + // Depending on configuration, invalidate the caches once all of threads are completed. int all_threads_complete = 1; if (m_config.gpgpu_flush_l1_cache) { for (unsigned i=0;in_simt_clusters;i++) { if (m_cluster[i]->get_not_completed() == 0) - m_cluster[i]->cache_flush(); + m_cluster[i]->cache_invalidate(); else all_threads_complete = 0 ; } @@ -1548,7 +1612,7 @@ void gpgpu_sim::cycle() int dlc = 0; for (unsigned i=0;im_n_mem;i++) { dlc = m_memory_sub_partition[i]->flushL2(); - assert (dlc == 0); // need to model actual writes to DRAM here + assert (dlc == 0); // TODO: need to model actual writes to DRAM here printf("Dirty lines flushed from L2 %d is %d\n", i, dlc ); } } @@ -1560,15 +1624,20 @@ void gpgpu_sim::cycle() time_t curr_time; time(&curr_time); unsigned long long elapsed_time = MAX(curr_time - g_simulation_starttime, 1); - if ( (elapsed_time - last_liveness_message_time) >= m_config.liveness_message_freq ) { + if ( (elapsed_time - last_liveness_message_time) >= m_config.liveness_message_freq && DTRACE(LIVENESS) ) { days = elapsed_time/(3600*24); hrs = elapsed_time/3600 - 24*days; minutes = elapsed_time/60 - 60*(hrs + 24*days); sec = elapsed_time - 60*(minutes + 60*(hrs + 24*days)); - - DPRINTF(LIVENESS, "GPGPU-Sim uArch: cycles simulated: %lld inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", - gpu_tot_sim_cycle + gpu_sim_cycle, gpu_tot_sim_insn + gpu_sim_insn, + + unsigned long long active = 0, total = 0; + for (unsigned i=0;in_simt_clusters;i++) { + m_cluster[i]->get_current_occupancy(active, total); + } + DPRINTF(LIVENESS, "uArch: inst.: %lld (ipc=%4.1f, occ=%0.4f\% [%llu / %llu]) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", + gpu_tot_sim_insn + gpu_sim_insn, (double)gpu_sim_insn/(double)gpu_sim_cycle, + float(active)/float(total) * 100, active, total, (unsigned)((gpu_tot_sim_insn+gpu_sim_insn) / elapsed_time), (unsigned)days,(unsigned)hrs,(unsigned)minutes,(unsigned)sec, ctime(&curr_time)); @@ -1620,6 +1689,24 @@ void shader_core_ctx::dump_warp_state( FILE *fout ) const m_warp[w].print(fout); } + +void gpgpu_sim::perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ) +{ + if (m_memory_config->m_perf_sim_memcpy) { + assert (dst_start_addr % 32 == 0); + + for ( unsigned counter = 0; counter < count; counter += 32 ) { + const unsigned wr_addr = dst_start_addr + counter; + addrdec_t raw_addr; + mem_access_sector_mask_t mask; + mask.set(wr_addr % 128 / 32); + m_memory_config->m_address_mapping.addrdec_tlx( wr_addr, &raw_addr ); + const unsigned partition_id = raw_addr.sub_partition / m_memory_config->m_n_sub_partition_per_memory_channel; + m_memory_partition_unit[ partition_id ]->handle_memcpy_to_gpu( wr_addr, raw_addr.sub_partition, mask ); + } + } +} + void gpgpu_sim::dump_pipeline( int mask, int s, int m ) const { /* diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 7d92c66..1bae1fa 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -198,8 +198,14 @@ struct memory_config { bk_tag_length = i-1; assert(nbkgrp>0 && "Number of bank groups cannot be zero"); tRCDWR = tRCD-(WL+1); + if(elimnate_rw_turnaround) + { + tRTW = 0; + tWTR = 0; + } else { tRTW = (CL+(BL/data_command_freq_ratio)+2-WL); - tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR); + tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR); + } tWTP = (WL+(BL/data_command_freq_ratio)+tWR); dram_atom_size = BL * busW * gpu_n_mem_per_ctrlr; // burst length x bus width x # chips per partition @@ -213,7 +219,9 @@ struct memory_config { m_L2_config.init(&m_address_mapping); m_valid = true; - icnt_flit_size = 32; // Default 32 + + sscanf(write_queue_size_opt,"%d:%d:%d", + &gpgpu_frfcfs_dram_write_queue_size,&write_high_watermark,&write_low_watermark); } void reg_options(class OptionParser * opp); @@ -264,12 +272,25 @@ struct memory_config { unsigned nbk; + bool elimnate_rw_turnaround; + unsigned data_command_freq_ratio; // frequency ratio between DRAM data bus and command bus (2 for GDDR3, 4 for GDDR5) unsigned dram_atom_size; // number of bytes transferred per read or write command linear_to_raw_address_translation m_address_mapping; unsigned icnt_flit_size; + + unsigned dram_bnk_indexing_policy; + unsigned dram_bnkgrp_indexing_policy; + bool dual_bus_interface; + + bool seperate_write_queue_enabled; + char *write_queue_size_opt; + unsigned gpgpu_frfcfs_dram_write_queue_size; + unsigned write_high_watermark; + unsigned write_low_watermark; + bool m_perf_sim_memcpy; }; // global counters and flags (please try not to add to this list!!!) @@ -362,6 +383,32 @@ private: friend class gpgpu_sim; }; +struct occupancy_stats { + occupancy_stats() : aggregate_warp_slot_filled(0), aggregate_theoretical_warp_slots(0){} + occupancy_stats( unsigned long long wsf, unsigned long long tws ) + : aggregate_warp_slot_filled(wsf), aggregate_theoretical_warp_slots(tws){} + + unsigned long long aggregate_warp_slot_filled; + unsigned long long aggregate_theoretical_warp_slots; + + float get_occ_fraction() const { + return float(aggregate_warp_slot_filled) / float(aggregate_theoretical_warp_slots); + } + + occupancy_stats& operator+=(const occupancy_stats& rhs) { + aggregate_warp_slot_filled += rhs.aggregate_warp_slot_filled; + aggregate_theoretical_warp_slots += rhs.aggregate_theoretical_warp_slots; + return *this; + } + + occupancy_stats operator+(const occupancy_stats& rhs) const{ + return occupancy_stats( aggregate_warp_slot_filled + rhs.aggregate_warp_slot_filled, + aggregate_theoretical_warp_slots + rhs.aggregate_theoretical_warp_slots + ); + } +}; + + class gpgpu_sim : public gpgpu_t { public: gpgpu_sim( const gpgpu_sim_config &config ); @@ -405,6 +452,8 @@ public: void gpu_print_stat(); void dump_pipeline( int mask, int s, int m ) const; + void perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ); + //The next three functions added to be used by the functional simulation function //! Get shader core configuration @@ -498,6 +547,9 @@ public: unsigned long long gpu_tot_sim_insn; unsigned long long gpu_sim_insn_last_update; unsigned gpu_sim_insn_last_update_sid; + occupancy_stats gpu_occupancy; + occupancy_stats gpu_tot_occupancy; + FuncCache get_cache_config(std::string kernel_name); void set_cache_config(std::string kernel_name, FuncCache cacheConfig ); @@ -526,4 +578,5 @@ public: } }; + #endif diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index c5fc44e..25da107 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -74,6 +74,15 @@ memory_partition_unit::memory_partition_unit( unsigned partition_id, } } +void memory_partition_unit::handle_memcpy_to_gpu( size_t addr, unsigned global_subpart_id, mem_access_sector_mask_t mask ) +{ + unsigned p = global_sub_partition_id_to_local_id(global_subpart_id); + std::string mystring = + mask.to_string(); + MEMPART_DPRINTF("Copy Engine Request Received For Address=%llx, local_subpart=%u, global_subpart=%u, sector_mask=%s \n", addr, p, global_subpart_id, mystring.c_str()); + m_sub_partition[p]->force_l2_tag_update(addr,gpu_sim_cycle+gpu_tot_sim_cycle, mask); +} + memory_partition_unit::~memory_partition_unit() { delete m_dram; @@ -93,7 +102,9 @@ memory_partition_unit::arbitration_metadata::arbitration_metadata(const struct m m_private_credit_limit = 1; m_shared_credit_limit = config->gpgpu_frfcfs_dram_sched_queue_size + config->gpgpu_dram_return_queue_size - - (config->m_n_sub_partition_per_memory_channel - 1); + - (config->m_n_sub_partition_per_memory_channel - 1); + if(config->seperate_write_queue_enabled ) + m_shared_credit_limit += config->gpgpu_frfcfs_dram_write_queue_size; if (config->gpgpu_frfcfs_dram_sched_queue_size == 0 or config->gpgpu_dram_return_queue_size == 0) { @@ -220,7 +231,8 @@ void memory_partition_unit::dram_cycle() m_dram->cycle(); m_dram->dram_log(SAMPLELOG); - if( !m_dram->full() ) { + // mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top(); + //if( !m_dram->full(mf->is_write()) ) { // L2->DRAM queue to DRAM latency queue // Arbitrate among multiple L2 subpartitions int last_issued_partition = m_arbitration_metadata.last_borrower(); @@ -228,6 +240,9 @@ void memory_partition_unit::dram_cycle() int spid = (p + last_issued_partition + 1) % m_config->m_n_sub_partition_per_memory_channel; if (!m_sub_partition[spid]->L2_dram_queue_empty() && can_issue_to_dram(spid)) { mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top(); + if(m_dram->full(mf->is_write()) ) + break; + m_sub_partition[spid]->L2_dram_queue_pop(); MEMPART_DPRINTF("Issue mem_fetch request %p from sub partition %d to dram\n", mf, spid); dram_delay_t d; @@ -239,12 +254,13 @@ void memory_partition_unit::dram_cycle() break; // the DRAM should only accept one request per cycle } } - } + //} // DRAM latency queue - if( !m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle ) && !m_dram->full() ) { - mem_fetch* mf = m_dram_latency_queue.front().req; - m_dram_latency_queue.pop_front(); + + if( !m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle ) && !m_dram->full(m_dram_latency_queue.front().req->is_write()) ) { + mem_fetch* mf = m_dram_latency_queue.front().req; + m_dram_latency_queue.pop_front(); m_dram->push(mf); } } @@ -299,6 +315,7 @@ memory_sub_partition::memory_sub_partition( unsigned sub_partition_id, m_id = sub_partition_id; m_config=config; m_stats=stats; + m_memcpy_cycle_offset = 0; assert(m_id < m_config->m_n_mem_sub_partition); @@ -343,6 +360,14 @@ void memory_sub_partition::cache_cycle( unsigned cycle ) mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); m_L2_icnt_queue->push(mf); }else{ + if(m_config->m_L2_config.m_write_alloc_policy == FETCH_ON_WRITE) + { + mem_fetch* original_wr_mf = mf->get_original_wr_mf(); + assert(original_wr_mf); + original_wr_mf->set_reply(); + original_wr_mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + m_L2_icnt_queue->push(original_wr_mf); + } m_request_tracker.erase(mf); delete mf; } @@ -355,10 +380,11 @@ void memory_sub_partition::cache_cycle( unsigned cycle ) if ( !m_config->m_L2_config.disabled() && m_L2cache->waiting_for_fill(mf) ) { if (m_L2cache->fill_port_free()) { mf->set_status(IN_PARTITION_L2_FILL_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); - m_L2cache->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle); + m_L2cache->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle+m_memcpy_cycle_offset); m_dram_L2_queue->pop(); } } else if ( !m_L2_icnt_queue->full() ) { + if(mf->is_write() && mf->get_type() == WRITE_ACK) mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); m_L2_icnt_queue->push(mf); m_dram_L2_queue->pop(); @@ -380,9 +406,10 @@ void memory_sub_partition::cache_cycle( unsigned cycle ) bool port_free = m_L2cache->data_port_free(); if ( !output_full && port_free ) { std::list events; - enum cache_request_status status = m_L2cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle,events); + enum cache_request_status status = m_L2cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle+m_memcpy_cycle_offset,events); bool write_sent = was_write_sent(events); bool read_sent = was_read_sent(events); + MEM_SUBPART_DPRINTF("Probing L2 cache Address=%llx, status=%u\n", mf->get_addr(), status); if ( status == HIT ) { if( !write_sent ) { @@ -402,6 +429,11 @@ void memory_sub_partition::cache_cycle( unsigned cycle ) m_icnt_L2_queue->pop(); } } else if ( status != RESERVATION_FAIL ) { + if(mf->is_write() && (m_config->m_L2_config.m_write_alloc_policy == FETCH_ON_WRITE || m_config->m_L2_config.m_write_alloc_policy == LAZY_FETCH_ON_READ) && !was_writeallocate_sent(events)) { + mf->set_reply(); + mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + m_L2_icnt_queue->push(mf); + } // L2 cache accepted request m_icnt_L2_queue->pop(); } else { @@ -432,6 +464,11 @@ bool memory_sub_partition::full() const return m_icnt_L2_queue->full(); } +bool memory_sub_partition::full(unsigned size) const +{ + return m_icnt_L2_queue->is_avilable_size(size); +} + bool memory_sub_partition::L2_dram_queue_empty() const { return m_L2_dram_queue->empty(); @@ -532,7 +569,15 @@ unsigned memory_sub_partition::flushL2() if (!m_config->m_L2_config.disabled()) { m_L2cache->flush(); } - return 0; // L2 is read only in this version + return 0; //TODO: write the flushed data to the main memory +} + +unsigned memory_sub_partition::invalidateL2() +{ + if (!m_config->m_L2_config.disabled()) { + m_L2cache->invalidate(); + } + return 0; } bool memory_sub_partition::busy() const @@ -540,21 +585,94 @@ bool memory_sub_partition::busy() const return !m_request_tracker.empty(); } -void memory_sub_partition::push( mem_fetch* req, unsigned long long cycle ) -{ - if (req) { - m_request_tracker.insert(req); - m_stats->memlatstat_icnt2mem_pop(req); - if( req->istexture() ) { - m_icnt_L2_queue->push(req); - req->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); - } else { - rop_delay_t r; - r.req = req; - r.ready_cycle = cycle + m_config->rop_latency; - m_rop.push(r); - req->set_status(IN_PARTITION_ROP_DELAY,gpu_sim_cycle+gpu_tot_sim_cycle); - } +std::vector memory_sub_partition::breakdown_request_to_sector_requests(mem_fetch* mf) +{ + std::vector result; + + if(mf->get_data_size() == SECTOR_SIZE && mf->get_access_sector_mask().count() == 1) { + result.push_back(mf); + } else if (mf->get_data_size() == 128 || mf->get_data_size() == 64) { + //We only accept 32, 64 and 128 bytes reqs + unsigned start=0, end=0; + if(mf->get_data_size() == 128) { + start=0; end=3; + } else if (mf->get_data_size() == 64 && mf->get_access_sector_mask().to_string() == "1100") { + start=2; end=3; + } else if (mf->get_data_size() == 64 && mf->get_access_sector_mask().to_string() == "0011") { + start=0; end=1; + } else if (mf->get_data_size() == 64 && (mf->get_access_sector_mask().to_string() == "1111" || mf->get_access_sector_mask().to_string() == "0000")) { + if(mf->get_addr() % 128 == 0) { + start=0; end=1; + } else { + start=2; end=3; + } + } else + { + printf("Invalid sector received, address = 0x%06x, sector mask = %s, data size = %d", + mf->get_addr(), mf->get_access_sector_mask(), mf->get_data_size()); + assert(0 && "Undefined sector mask is received"); + } + + std::bitset byte_sector_mask; + byte_sector_mask.reset(); + for(unsigned k=start*SECTOR_SIZE; k< SECTOR_SIZE; ++k) + byte_sector_mask.set(k); + + for(unsigned j=start, i=0; j<= end ; ++j, ++i){ + + const mem_access_t *ma = new mem_access_t( mf->get_access_type(), + mf->get_addr() + SECTOR_SIZE*i, + SECTOR_SIZE, + mf->is_write(), + mf->get_access_warp_mask(), + mf->get_access_byte_mask() & byte_sector_mask, + std::bitset().set(j)); + + mem_fetch *n_mf = new mem_fetch( *ma, + NULL, + mf->get_ctrl_size(), + mf->get_wid(), + mf->get_sid(), + mf->get_tpc(), + mf->get_mem_config(), + mf); + + result.push_back(n_mf); + byte_sector_mask <<= SECTOR_SIZE; + } + } else { + printf("Invalid sector received, address = 0x%06x, sector mask = %d, byte mask = , data size = %d", + mf->get_addr(), mf->get_access_sector_mask().count(), mf->get_data_size()); + assert(0 && "Undefined data size is received"); + } + + return result; +} + +void memory_sub_partition::push( mem_fetch* m_req, unsigned long long cycle ) +{ + if (m_req) { + m_stats->memlatstat_icnt2mem_pop(m_req); + std::vector reqs; + if(m_config->m_L2_config.m_cache_type == SECTOR) + reqs = breakdown_request_to_sector_requests(m_req); + else + reqs.push_back(m_req); + + for(unsigned i=0; iistexture() ) { + m_icnt_L2_queue->push(req); + req->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + } else { + rop_delay_t r; + r.req = req; + r.ready_cycle = cycle + m_config->rop_latency; + m_rop.push(r); + req->set_status(IN_PARTITION_ROP_DELAY,gpu_sim_cycle+gpu_tot_sim_cycle); + } + } } } diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 3df54b1..18c0a8b 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -72,6 +72,7 @@ public: void print_stat( FILE *fp ) { m_dram->print_stat(fp); } void visualize() const { m_dram->visualize(); } void print( FILE *fp ) const; + void handle_memcpy_to_gpu( size_t dst_start_addr, unsigned subpart_id, mem_access_sector_mask_t mask ); class memory_sub_partition * get_sub_partition(int sub_partition_id) { @@ -154,12 +155,14 @@ public: void cache_cycle( unsigned cycle ); bool full() const; + bool full(unsigned size) const; void push( class mem_fetch* mf, unsigned long long clock_cycle ); class mem_fetch* pop(); class mem_fetch* top(); void set_done( mem_fetch *mf ); unsigned flushL2(); + unsigned invalidateL2(); // interface to L2_dram_queue bool L2_dram_queue_empty() const; @@ -177,6 +180,12 @@ public: void accumulate_L2cache_stats(class cache_stats &l2_stats) const; void get_L2cache_sub_stats(struct cache_sub_stats &css) const; + void force_l2_tag_update(new_addr_type addr, unsigned time, mem_access_sector_mask_t mask) + { + m_L2cache->force_tag_access( addr, m_memcpy_cycle_offset + time, mask ); + m_memcpy_cycle_offset += 1; + } + private: // data unsigned m_id; //< the global sub partition ID @@ -207,6 +216,15 @@ private: std::set m_request_tracker; friend class L2interface; + + std::vector breakdown_request_to_sector_requests(mem_fetch* mf); + + // This is a cycle offset that has to be applied to the l2 accesses to account for + // the cudamemcpy read/writes. We want GPGPU-Sim to only count cycles for kernel execution + // but we want cudamemcpy to go through the L2. Everytime an access is made from cudamemcpy + // this counter is incremented, and when the l2 is accessed (in both cudamemcpyies and otherwise) + // this value is added to the gpgpu-sim cycle counters. + unsigned m_memcpy_cycle_offset; }; class L2interface : public mem_fetch_interface { diff --git a/src/gpgpu-sim/l2cache_trace.h b/src/gpgpu-sim/l2cache_trace.h index 3dac87d..2235cdc 100644 --- a/src/gpgpu-sim/l2cache_trace.h +++ b/src/gpgpu-sim/l2cache_trace.h @@ -34,6 +34,9 @@ #define MEMPART_PRINT_STR SIM_PRINT_STR " %d - " #define MEMPART_DTRACE(x) ( DTRACE(x) && (Trace::sampling_memory_partition == -1 || Trace::sampling_memory_partition == (int)get_mpid()) ) +#define MEM_SUBPART_PRINT_STR SIM_PRINT_STR " %d - " +#define MEM_SUBPART_DTRACE(x) ( DTRACE(x) && (Trace::sampling_memory_partition == -1 || Trace::sampling_memory_partition == (int)m_id) ) + // Intended to be called from inside components of a memory partition // Depends on a get_mpid() function #define MEMPART_DPRINTF(...) do {\ @@ -46,10 +49,23 @@ }\ } while (0) +#define MEM_SUBPART_DPRINTF(...) do {\ + if (MEM_SUBPART_DTRACE(MEMORY_PARTITION_UNIT)) {\ + printf( MEM_SUBPART_PRINT_STR,\ + gpu_sim_cycle + gpu_tot_sim_cycle,\ + Trace::trace_streams_str[Trace::MEMORY_SUBPARTITION_UNIT],\ + m_id );\ + printf(__VA_ARGS__);\ + }\ +} while (0) + #else #define MEMPART_DTRACE(x) (false) #define MEMPART_DPRINTF(x, ...) do {} while (0) +#define MEM_SUBPART_DTRACE(x) (false) +#define MEM_SUBPART_DPRINTF(x, ...) do {} while (0) + #endif diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc index 729636d..a260a35 100644 --- a/src/gpgpu-sim/mem_fetch.cc +++ b/src/gpgpu-sim/mem_fetch.cc @@ -39,7 +39,10 @@ mem_fetch::mem_fetch( const mem_access_t &access, unsigned wid, unsigned sid, unsigned tpc, - const struct memory_config *config ) + const struct memory_config *config, + mem_fetch *m_original_mf, + mem_fetch *m_original_wr_mf) + { m_request_uid = sm_next_mf_request_uid++; m_access = access; @@ -61,6 +64,8 @@ mem_fetch::mem_fetch( const mem_access_t &access, m_status_change = gpu_sim_cycle + gpu_tot_sim_cycle; m_mem_config = config; icnt_flit_size = config->icnt_flit_size; + original_mf = m_original_mf; + original_wr_mf = m_original_wr_mf; } mem_fetch::~mem_fetch() diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index de98748..e5efffd 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -55,7 +55,9 @@ public: unsigned wid, unsigned sid, unsigned tpc, - const struct memory_config *config ); + const struct memory_config *config, + mem_fetch *original_mf = NULL, + mem_fetch *original_wr_mf = NULL); ~mem_fetch(); void set_status( enum mem_fetch_status status, unsigned long long cycle ); @@ -104,6 +106,7 @@ public: enum mem_access_type get_access_type() const { return m_access.get_type(); } const active_mask_t& get_access_warp_mask() const { return m_access.get_warp_mask(); } mem_access_byte_mask_t get_access_byte_mask() const { return m_access.get_byte_mask(); } + mem_access_sector_mask_t get_access_sector_mask() const { return m_access.get_sector_mask(); } address_type get_pc() const { return m_inst.empty()?-1:m_inst.pc; } const warp_inst_t &get_inst() { return m_inst; } @@ -112,6 +115,10 @@ public: const memory_config *get_mem_config(){return m_mem_config;} unsigned get_num_flits(bool simt_to_mem); + + mem_fetch* get_original_mf() { return original_mf; } + mem_fetch* get_original_wr_mf() { return original_wr_mf; } + private: // request source information unsigned m_request_uid; @@ -143,6 +150,10 @@ private: const struct memory_config *m_mem_config; unsigned icnt_flit_size; + + mem_fetch* original_mf; //this pointer is set up when a request is divided into sector requests at L2 cache (if the req size > L2 sector size), so the pointer refers to the original request + mem_fetch* original_wr_mf; //this pointer refers to the original write req, when fetch-on-write policy is used + }; #endif diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index fde0eff..c5452b9 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -75,6 +75,10 @@ memory_stats_t::memory_stats_t( unsigned n_shader, const struct shader_core_conf max_mf_latency = 0; max_icnt2mem_latency = 0; max_icnt2sh_latency = 0; + tot_icnt2mem_latency = 0; + tot_icnt2sh_latency = 0; + tot_mrq_num = 0; + tot_mrq_latency = 0; memset(mrq_lat_table, 0, sizeof(unsigned)*32); memset(dq_lat_table, 0, sizeof(unsigned)*32); memset(mf_lat_table, 0, sizeof(unsigned)*32); @@ -158,6 +162,7 @@ void memory_stats_t::memlatstat_read_done(mem_fetch *mf) mf_max_lat_table[mf->get_tlx_addr().chip][mf->get_tlx_addr().bk] = mf_latency; unsigned icnt2sh_latency; icnt2sh_latency = (gpu_tot_sim_cycle+gpu_sim_cycle) - mf->get_return_timestamp(); + tot_icnt2sh_latency += icnt2sh_latency; icnt2sh_lat_table[LOGB2(icnt2sh_latency)]++; if (icnt2sh_latency > max_icnt2sh_latency) max_icnt2sh_latency = icnt2sh_latency; @@ -191,6 +196,7 @@ void memory_stats_t::memlatstat_icnt2mem_pop(mem_fetch *mf) if (m_memory_config->gpgpu_memlatency_stat) { unsigned icnt2mem_latency; icnt2mem_latency = (gpu_tot_sim_cycle+gpu_sim_cycle) - mf->get_timestamp(); + tot_icnt2mem_latency += icnt2mem_latency; icnt2mem_lat_table[LOGB2(icnt2mem_latency)]++; if (icnt2mem_latency > max_icnt2mem_latency) max_icnt2mem_latency = icnt2mem_latency; @@ -216,14 +222,19 @@ void memory_stats_t::memlatstat_print( unsigned n_mem, unsigned gpu_mem_n_bk ) unsigned max_bank_accesses, min_bank_accesses, max_chip_accesses, min_chip_accesses; if (m_memory_config->gpgpu_memlatency_stat) { + printf("maxmflatency = %d \n", max_mf_latency); + printf("max_icnt2mem_latency = %d \n", max_icnt2mem_latency); printf("maxmrqlatency = %d \n", max_mrq_latency); - printf("maxdqlatency = %d \n", max_dq_latency); - printf("maxmflatency = %d \n", max_mf_latency); + //printf("maxdqlatency = %d \n", max_dq_latency); + printf("max_icnt2sh_latency = %d \n", max_icnt2sh_latency); if (num_mfs) { printf("averagemflatency = %lld \n", mf_total_lat/num_mfs); + printf("avg_icnt2mem_latency = %lld \n", tot_icnt2mem_latency/num_mfs); + if(tot_mrq_num) + printf("avg_mrq_latency = %lld \n", tot_mrq_latency/tot_mrq_num); + + printf("avg_icnt2sh_latency = %lld \n", tot_icnt2sh_latency/num_mfs); } - printf("max_icnt2mem_latency = %d \n", max_icnt2mem_latency); - printf("max_icnt2sh_latency = %d \n", max_icnt2sh_latency); printf("mrq_lat_table:"); for (i=0; i< 32; i++) { printf("%d \t", mrq_lat_table[i]); diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h index 4968a3b..5b89202 100644 --- a/src/gpgpu-sim/mem_latency_stat.h +++ b/src/gpgpu-sim/mem_latency_stat.h @@ -56,6 +56,10 @@ public: unsigned max_dq_latency; unsigned max_mf_latency; unsigned max_icnt2mem_latency; + unsigned long long int tot_icnt2mem_latency; + unsigned long long int tot_icnt2sh_latency; + unsigned long long int tot_mrq_latency; + unsigned long long int tot_mrq_num; unsigned max_icnt2sh_latency; unsigned mrq_lat_table[32]; unsigned dq_lat_table[32]; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index f9cfa58..82f9181 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -74,13 +74,14 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, shader_core_stats *stats ) : core_t( gpu, NULL, config->warp_size, config->n_thread_per_shader ), m_barriers( this, config->max_warps_per_shader, config->max_cta_per_core, config->max_barriers_per_cta, config->warp_size ), - m_dynamic_warp_id(0) + m_dynamic_warp_id(0), m_active_warps(0) { m_cluster = cluster; m_config = config; m_memory_config = mem_config; m_stats = stats; unsigned warp_size=config->warp_size; + Issue_Prio = 0; m_sid = shader_id; m_tpc = tpc_id; @@ -131,6 +132,8 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE : sched_config.find("gto") != std::string::npos ? CONCRETE_SCHEDULER_GTO : + sched_config.find("old") != std::string::npos ? + CONCRETE_SCHEDULER_OLDEST_FIRST : sched_config.find("warp_limiting") != std::string::npos ? CONCRETE_SCHEDULER_WARP_LIMITING: NUM_CONCRETE_SCHEDULERS; @@ -147,6 +150,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], @@ -162,6 +166,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], @@ -178,6 +183,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], @@ -185,6 +191,22 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, ) ); break; + case CONCRETE_SCHEDULER_OLDEST_FIRST: + schedulers.push_back( + new oldest_scheduler( m_stats, + this, + m_scoreboard, + m_simt_stack, + &m_warp, + &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_DP], + &m_pipeline_reg[ID_OC_SFU], + &m_pipeline_reg[ID_OC_TENSOR_CORE], + &m_pipeline_reg[ID_OC_MEM], + i + ) + ); + break; case CONCRETE_SCHEDULER_WARP_LIMITING: schedulers.push_back( new swl_scheduler( m_stats, @@ -193,6 +215,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], @@ -215,8 +238,9 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, } //op collector configuration - enum { SP_CUS, SFU_CUS, TENSOR_CORE_CUS, MEM_CUS, GEN_CUS }; + enum { SP_CUS, DP_CUS, SFU_CUS, MEM_CUS, TENSOR_CORE_CUS, GEN_CUS }; m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp); + m_operand_collector.add_cu_set(DP_CUS, m_config->gpgpu_operand_collector_num_units_dp, m_config->gpgpu_operand_collector_num_out_ports_dp); m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu); m_operand_collector.add_cu_set(TENSOR_CORE_CUS, config->gpgpu_operand_collector_num_units_tensor_core, config->gpgpu_operand_collector_num_out_ports_tensor_core); m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem); @@ -234,6 +258,15 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, in_ports.clear(),out_ports.clear(),cu_sets.clear(); } + for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_dp; i++) { + in_ports.push_back(&m_pipeline_reg[ID_OC_DP]); + out_ports.push_back(&m_pipeline_reg[OC_EX_DP]); + cu_sets.push_back((unsigned)DP_CUS); + cu_sets.push_back((unsigned)GEN_CUS); + m_operand_collector.add_port(in_ports,out_ports,cu_sets); + in_ports.clear(),out_ports.clear(),cu_sets.clear(); + } + for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sfu; i++) { in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]); out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]); @@ -279,7 +312,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_operand_collector.init( m_config->gpgpu_num_reg_banks, this ); // execute - m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + config->gpgpu_num_tensor_core_units + 1; // sp_unit, sfu, ldst_unit + m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_dp_units + m_config->gpgpu_num_sfu_units + m_config->gpgpu_num_tensor_core_units + 1; // sp_unit, sfu, ldst_unit //m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ]; //m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ]; @@ -291,6 +324,12 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_issue_port.push_back(OC_EX_SP); } + for (int k = 0; k < m_config->gpgpu_num_dp_units; k++) { + m_fu.push_back(new dp_unit( &m_pipeline_reg[EX_WB], m_config, this )); + m_dispatch_port.push_back(ID_OC_DP); + m_issue_port.push_back(OC_EX_DP); + } + for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) { m_fu.push_back(new sfu( &m_pipeline_reg[EX_WB], m_config, this )); m_dispatch_port.push_back(ID_OC_SFU); @@ -307,7 +346,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_fu.push_back(m_ldst_unit); m_dispatch_port.push_back(ID_OC_MEM); m_issue_port.push_back(OC_EX_MEM); - + assert(m_num_function_units == m_fu.size() and m_fu.size() == m_dispatch_port.size() and m_fu.size() == m_issue_port.size()); //there are as many result buses as the width of the EX_WB stage @@ -341,6 +380,7 @@ void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread, bool re m_occupied_ctas = 0; m_occupied_hwtid.reset(); m_occupied_cta_to_hwtid.clear(); + m_active_warps = 0; } for (unsigned i = start_thread; iget_pdom_stack_top_info(pc,rpc); } +float shader_core_ctx::get_current_occupancy( unsigned long long & active, unsigned long long & total ) const +{ + // To match the achieved_occupancy in nvprof, only SMs that are active are counted toward the occupancy. + if ( m_active_warps > 0 ) { + total += m_warp.size(); + active += m_active_warps; + return float(active) / float(total); + } else { + return 0; + } +} + void shader_core_stats::print( FILE* fout ) const { unsigned long long thread_icount_uarch=0; @@ -436,15 +489,15 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout, "gpgpu_n_intrawarp_mshr_merge = %d\n", gpgpu_n_intrawarp_mshr_merge); fprintf(fout, "gpgpu_n_cmem_portconflict = %d\n", gpgpu_n_cmem_portconflict); - fprintf(fout, "gpgpu_stall_shd_mem[c_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]); - fprintf(fout, "gpgpu_stall_shd_mem[c_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][MSHR_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[c_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][ICNT_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[c_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][DATA_PORT_STALL]); - fprintf(fout, "gpgpu_stall_shd_mem[t_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][MSHR_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[t_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][ICNT_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[t_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][DATA_PORT_STALL]); + fprintf(fout, "gpgpu_stall_shd_mem[c_mem][resource_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]); + //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][MSHR_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][ICNT_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[c_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][DATA_PORT_STALL]); + //fprintf(fout, "gpgpu_stall_shd_mem[t_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][MSHR_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[t_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][ICNT_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[t_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][DATA_PORT_STALL]); fprintf(fout, "gpgpu_stall_shd_mem[s_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[S_MEM][BK_CONF]); - fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][bk_conf] = %d\n", + fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][resource_stall] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][BK_CONF] + gpu_stall_shd_mem_breakdown[G_MEM_ST][BK_CONF] + gpu_stall_shd_mem_breakdown[L_MEM_LD][BK_CONF] + @@ -462,22 +515,22 @@ void shader_core_stats::print( FILE* fout ) const gpu_stall_shd_mem_breakdown[L_MEM_LD][DATA_PORT_STALL] + gpu_stall_shd_mem_breakdown[L_MEM_ST][DATA_PORT_STALL] ); // data port stall at data cache - fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][MSHR_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][ICNT_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_ICNT_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_CACHE_RSRV_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][MSHR_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][ICNT_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_ICNT_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_CACHE_RSRV_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][MSHR_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][ICNT_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_ICNT_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_CACHE_RSRV_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][MSHR_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][ICNT_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_ICNT_RC_FAIL]); - fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_CACHE_RSRV_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][MSHR_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][ICNT_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_ICNT_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_CACHE_RSRV_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][MSHR_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][ICNT_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_ICNT_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_CACHE_RSRV_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][MSHR_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][ICNT_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_ICNT_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_CACHE_RSRV_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][MSHR_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][ICNT_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_ICNT_RC_FAIL]); + //fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_CACHE_RSRV_FAIL]); fprintf(fout, "gpu_reg_bank_conflict_stalls = %d\n", gpu_reg_bank_conflict_stalls); @@ -488,6 +541,14 @@ void shader_core_stats::print( FILE* fout ) const for (unsigned i = 3; i < m_config->warp_size + 3; i++) fprintf(fout, "\tW%d:%d", i-2, shader_cycle_distro[i]); fprintf(fout, "\n"); + fprintf(fout, "single_issue_nums: "); + for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++) + fprintf(fout, "WS%d:%d\t", i, single_issue_nums[i]); + fprintf(fout, "\n"); + fprintf(fout, "dual_issue_nums: "); + for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++) + fprintf(fout, "WS%d:%d\t", i, dual_issue_nums[i]); + fprintf(fout, "\n"); m_outgoing_traffic_stats->print(fout); m_incoming_traffic_stats->print(fout); @@ -669,13 +730,15 @@ void shader_core_ctx::fetch() } if( did_exit ) m_warp[warp_id].set_done_exit(); + --m_active_warps; + assert(m_active_warps >= 0); } // this code fetches instructions from the i-cache or generates memory requests if( !m_warp[warp_id].functional_done() && !m_warp[warp_id].imiss_pending() && m_warp[warp_id].ibuffer_empty() ) { address_type pc = m_warp[warp_id].get_pc(); address_type ppc = pc + PROGRAM_MEM_START; - unsigned nbytes=16; + unsigned nbytes=16; unsigned offset_in_block = pc & (m_config->m_L1I_config.get_line_sz()-1); if( (offset_in_block+nbytes) > m_config->m_L1I_config.get_line_sz() ) nbytes = (m_config->m_L1I_config.get_line_sz()-offset_in_block); @@ -750,10 +813,19 @@ void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* } void shader_core_ctx::issue(){ + + //Ensure fair round robin issu between schedulers + unsigned j; + for (unsigned i = 0; i < schedulers.size(); i++) { + j = (Issue_Prio + i) % schedulers.size(); + schedulers[j]->cycle(); + } + Issue_Prio = (Issue_Prio+1)% schedulers.size(); + //really is issue; - for (unsigned i = 0; i < schedulers.size(); i++) { - schedulers[i]->cycle(); - } + //for (unsigned i = 0; i < schedulers.size(); i++) { + // schedulers[i]->cycle(); + //} } shd_warp_t& scheduler_unit::warp(int i){ @@ -868,7 +940,10 @@ void scheduler_unit::cycle() unsigned warp_id = (*iter)->get_warp_id(); unsigned checked=0; unsigned issued=0; - unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; + exec_unit_type_t previous_issued_inst_exec_type = exec_unit_type_t::NONE; + unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; + bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units; + while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) { const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst(); //Jin: handle cdp latency; @@ -901,18 +976,21 @@ void scheduler_unit::cycle() ready_inst = true; const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask(); assert( warp(warp_id).inst_in_pipeline() ); - if ( (pI->op == LOAD_OP)||(pI->op ==TENSOR_CORE_LOAD_OP)|| (pI->op == STORE_OP)|| (pI->op==TENSOR_CORE_STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) { - if( m_mem_out->has_free() ) { - m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id); - issued++; - issued_inst=true; - warp_inst_issued = true; - } + if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP)||(pI->op==TENSOR_CORE_LOAD_OP)||(pI->op==TENSOR_CORE_STORE_OP) ) { + if( m_mem_out->has_free() && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::MEM)) { + m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id); + issued++; + issued_inst=true; + warp_inst_issued = true; + previous_issued_inst_exec_type = exec_unit_type_t::MEM; + } } else { + bool sp_pipe_avail = m_sp_out->has_free(); bool sfu_pipe_avail = m_sfu_out->has_free(); bool tensor_core_pipe_avail = m_tensor_core_out->has_free(); - if( sp_pipe_avail && (pI->op != SFU_OP) && (pI->op != TENSOR_CORE_OP) ) { + bool dp_pipe_avail = m_dp_out->has_free(); + if( sp_pipe_avail && (pI->op != TENSOR_CORE_OP) && (pI->op != SFU_OP && pI->op != DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SP)) { //Jin: special for CDP api if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) { @@ -937,12 +1015,23 @@ void scheduler_unit::cycle() issued++; issued_inst=true; warp_inst_issued = true; - } else if ( (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP) ) { + previous_issued_inst_exec_type = exec_unit_type_t::SP; + } else if ( (m_shader->m_config->gpgpu_num_dp_units != 0) && (pI->op == DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::DP)) { + if( dp_pipe_avail ) { + m_shader->issue_warp(*m_dp_out,pI,active_mask,warp_id); + issued++; + issued_inst=true; + warp_inst_issued = true; + previous_issued_inst_exec_type = exec_unit_type_t::DP; + } + } //If the DP units = 0 (like in Fermi archi), then change DP inst to SFU inst + else if ( ((m_shader->m_config->gpgpu_num_dp_units == 0 && pI->op == DP_OP) || (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP)) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SFU)) { if( sfu_pipe_avail ) { m_shader->issue_warp(*m_sfu_out,pI,active_mask,warp_id); issued++; issued_inst=true; warp_inst_issued = true; + previous_issued_inst_exec_type = exec_unit_type_t::SFU; } } else if ( (pI->op == TENSOR_CORE_OP) ) { @@ -952,12 +1041,12 @@ void scheduler_unit::cycle() issued_inst=true; warp_inst_issued = true; } - } - } - } else { + } + }//end of else + } else { SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails scoreboard\n", (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() ); - } + } } } else if( valid ) { // this case can happen after a return instruction in diverged warp @@ -988,6 +1077,14 @@ void scheduler_unit::cycle() m_last_supervised_issued = supervised_iter; } } + + if(issued == 1) + m_stats->single_issue_nums[m_id]++; + else if(issued > 1) + m_stats->dual_issue_nums[m_id]++; + else + abort(); //issued should be > 0 + break; } } @@ -1045,6 +1142,16 @@ void gto_scheduler::order_warps() scheduler_unit::sort_warps_by_oldest_dynamic_id ); } +void oldest_scheduler::order_warps() +{ + order_by_priority( m_next_cycle_prioritized_warps, + m_supervised_warps, + m_last_supervised_issued, + m_supervised_warps.size(), + ORDERED_PRIORITY_FUNC_ONLY, + scheduler_unit::sort_warps_by_oldest_dynamic_id ); +} + void two_level_active_scheduler::do_on_warp_issued( unsigned warp_id, unsigned num_issued, @@ -1117,12 +1224,13 @@ swl_scheduler::swl_scheduler ( shader_core_stats* stats, shader_core_ctx* shader Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* tensor_core_out, register_set* mem_out, int id, char* config_string ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ) + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ) { unsigned m_prioritization_readin; int ret = sscanf( config_string, @@ -1386,8 +1494,14 @@ ldst_unit::process_cache_access( cache_t* cache, mem_stage_stall_type result = NO_RC_FAIL; bool write_sent = was_write_sent(events); bool read_sent = was_read_sent(events); - if( write_sent ) - m_core->inc_store_req( inst.warp_id() ); + if( write_sent ) { + unsigned inc_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)? + (mf->get_data_size()/SECTOR_SIZE) : 1; + + for(unsigned i=0; i< inc_ack; ++i) + m_core->inc_store_req( inst.warp_id() ); + + } if ( status == HIT ) { assert( !read_sent ); inst.accessq_pop_back(); @@ -1399,7 +1513,7 @@ ldst_unit::process_cache_access( cache_t* cache, if( !write_sent ) delete mf; } else if ( status == RESERVATION_FAIL ) { - result = COAL_STALL; + result = BK_CONF; assert( !read_sent ); assert( !write_sent ); delete mf; @@ -1408,8 +1522,8 @@ ldst_unit::process_cache_access( cache_t* cache, //inst.clear_active( access.get_warp_mask() ); // threads in mf writeback when mf returns inst.accessq_pop_back(); } - if( !inst.accessq_empty() ) - result = BK_CONF; + if( !inst.accessq_empty() && result == NO_RC_FAIL) + result = COAL_STALL; return result; } @@ -1429,6 +1543,111 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue( cache_t *cache, war return process_cache_access( cache, mf->get_addr(), inst, events, mf, status ); } +mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache( l1_cache *cache, warp_inst_t &inst ) +{ + mem_stage_stall_type result = NO_RC_FAIL; + if( inst.accessq_empty() ) + return result; + + mem_fetch *mf = m_mf_allocator->alloc(inst,inst.accessq_back()); + + if(m_config->m_L1D_config.l1_latency > 0) + { + if((l1_latency_queue[m_config->m_L1D_config.l1_latency-1]) == NULL) + { + l1_latency_queue[m_config->m_L1D_config.l1_latency-1] = mf; + + if( mf->get_inst().is_store() ) { + unsigned inc_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)? + (mf->get_data_size()/SECTOR_SIZE) : 1; + + for(unsigned i=0; i< inc_ack; ++i) + m_core->inc_store_req( inst.warp_id() ); + } + + inst.accessq_pop_back(); + } + else + { + result = BK_CONF; + delete mf; + } + if( !inst.accessq_empty() && result !=BK_CONF) + result = COAL_STALL; + return result; + } + else + { + std::list events; + enum cache_request_status status = cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle,events); + return process_cache_access( cache, mf->get_addr(), inst, events, mf, status ); + } +} + +void ldst_unit::L1_latency_queue_cycle() +{ + //std::deque< std::pair >::iterator it = m_latency_queue.begin(); + if((l1_latency_queue[0]) != NULL) + { + mem_fetch* mf_next = l1_latency_queue[0]; + std::list events; + enum cache_request_status status = m_L1D->access(mf_next->get_addr(),mf_next,gpu_sim_cycle+gpu_tot_sim_cycle,events); + + bool write_sent = was_write_sent(events); + bool read_sent = was_read_sent(events); + + if ( status == HIT ) { + assert( !read_sent ); + l1_latency_queue[0] = NULL; + if ( mf_next->get_inst().is_load() ) { + for ( unsigned r=0; r < 4; r++) + if (mf_next->get_inst().out[r] > 0) + { + assert(m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]]>0); + unsigned still_pending = --m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]]; + if(!still_pending) + { + m_pending_writes[mf_next->get_inst().warp_id()].erase(mf_next->get_inst().out[r]); + m_scoreboard->releaseRegister(mf_next->get_inst().warp_id(),mf_next->get_inst().out[r]); + m_core->warp_inst_complete(mf_next->get_inst()); + } + } + } + + //For write hit in WB policy + if(mf_next->get_inst().is_store() && !write_sent) + { + unsigned dec_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)? + (mf_next->get_data_size()/SECTOR_SIZE) : 1; + + mf_next->set_reply(); + + for(unsigned i=0; i< dec_ack; ++i) + m_core->store_ack(mf_next); + } + + if( !write_sent ) + delete mf_next; + + } else if ( status == RESERVATION_FAIL ) { + assert( !read_sent ); + assert( !write_sent ); + } else { + assert( status == MISS || status == HIT_RESERVED ); + l1_latency_queue[0] = NULL; + } + } + + for( unsigned stage = 0; stagem_L1D_config.l1_latency-1; ++stage) + if( l1_latency_queue[stage] == NULL) { + l1_latency_queue[stage] = l1_latency_queue[stage+1] ; + l1_latency_queue[stage+1] = NULL; + } + +} + + + bool ldst_unit::constant_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type) { if( inst.empty() || ((inst.space.get_type() != const_space) && (inst.space.get_type() != param_space_kernel)) ) @@ -1478,7 +1697,7 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea bypassL1D = true; } else if (inst.space.is_global()) { // global memory access // skip L1 cache if the option is enabled - if (m_core->get_config()->gmem_skip_L1D) + if (m_core->get_config()->gmem_skip_L1D && (CACHE_L1 != inst.cache_op)) bypassL1D = true; } if( bypassL1D ) { @@ -1502,9 +1721,9 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea } } else { assert( CACHE_UNDEFINED != inst.cache_op ); - stall_cond = process_memory_access_queue(m_L1D,inst); + stall_cond = process_memory_access_queue_l1cache(m_L1D,inst); } - if( !inst.accessq_empty() ) + if( !inst.accessq_empty() && stall_cond == NO_RC_FAIL) stall_cond = COAL_STALL; if (stall_cond != NO_RC_FAIL) { stall_reason = stall_cond; @@ -1534,6 +1753,11 @@ void ldst_unit::flush(){ m_L1D->flush(); } +void ldst_unit::invalidate(){ + // Flush L1D cache + m_L1D->invalidate(); +} + simd_function_unit::simd_function_unit( const shader_core_config *config ) { m_config=config; @@ -1586,6 +1810,13 @@ void sp_unit::active_lanes_in_pipeline(){ m_core->incfuactivelanes_stat(active_count); m_core->incfumemactivelanes_stat(active_count); } +void dp_unit::active_lanes_in_pipeline(){ + unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline(); + assert(active_count<=m_core->get_config()->warp_size); + m_core->incspactivelanes_stat(active_count); + m_core->incfuactivelanes_stat(active_count); + m_core->incfumemactivelanes_stat(active_count); +} void sfu::active_lanes_in_pipeline(){ unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline(); @@ -1610,6 +1841,12 @@ sp_unit::sp_unit( register_set* result_port, const shader_core_config *config,sh m_name = "SP "; } +dp_unit::dp_unit( register_set* result_port, const shader_core_config *config,shader_core_ctx *core) + : pipelined_simd_unit(result_port,config,config->max_sfu_latency,core) +{ + m_name = "DP "; +} + void sp_unit :: issue(register_set& source_reg) { warp_inst_t** ready_reg = source_reg.get_ready(); @@ -1619,6 +1856,14 @@ void sp_unit :: issue(register_set& source_reg) pipelined_simd_unit::issue(source_reg); } +void dp_unit :: issue(register_set& source_reg) +{ + warp_inst_t** ready_reg = source_reg.get_ready(); + //m_core->incexecstat((*ready_reg)); + (*ready_reg)->op_pipe=DP__OP; + m_core->incsp_stat(m_core->get_config()->warp_size,(*ready_reg)->latency); + pipelined_simd_unit::issue(source_reg); +} pipelined_simd_unit::pipelined_simd_unit( register_set* result_port, const shader_core_config *config, unsigned max_latency,shader_core_ctx *core ) : simd_function_unit(config) @@ -1712,8 +1957,9 @@ ldst_unit::ldst_unit( mem_fetch_interface *icnt, const memory_config *mem_config, shader_core_stats *stats, unsigned sid, - unsigned tpc ) : pipelined_simd_unit(NULL,config,3,core), m_next_wb(config) + unsigned tpc ) : pipelined_simd_unit(NULL,config,config->smem_latency,core), m_next_wb(config) { + assert(config->smem_latency > 1); init( icnt, mf_allocator, core, @@ -1734,6 +1980,12 @@ ldst_unit::ldst_unit( mem_fetch_interface *icnt, m_icnt, m_mf_allocator, IN_L1D_MISS_QUEUE ); + + if(m_config->m_L1D_config.l1_latency > 0) + { + for(int i=0; im_L1D_config.l1_latency; i++ ) + l1_latency_queue.push_back((mem_fetch*)NULL); + } } } @@ -1916,12 +2168,12 @@ void ldst_unit::cycle() if( !m_response_fifo.empty() ) { mem_fetch *mf = m_response_fifo.front(); - if (mf->istexture()) { + if (mf->get_access_type() == TEXTURE_ACC_R) { if (m_L1T->fill_port_free()) { m_L1T->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle); m_response_fifo.pop_front(); } - } else if (mf->isconst()) { + } else if (mf->get_access_type() == CONST_ACC_R) { if (m_L1C->fill_port_free()) { mf->set_status(IN_SHADER_FETCHED,gpu_sim_cycle+gpu_tot_sim_cycle); m_L1C->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle); @@ -1960,7 +2212,11 @@ void ldst_unit::cycle() m_L1T->cycle(); m_L1C->cycle(); - if( m_L1D ) m_L1D->cycle(); + if( m_L1D ) { + m_L1D->cycle(); + if(m_config->m_L1D_config.l1_latency > 0) + L1_latency_queue_cycle(); + } warp_inst_t &pipe_reg = *m_dispatch_reg; enum mem_stage_stall_type rc_fail = NO_RC_FAIL; @@ -1983,9 +2239,9 @@ void ldst_unit::cycle() unsigned warp_id = pipe_reg.warp_id(); if( pipe_reg.is_load() ) { if( pipe_reg.space.get_type() == shared_space ) { - if( m_pipeline_reg[2]->empty() ) { + if( m_pipeline_reg[m_config->smem_latency-1]->empty() ) { // new shared memory request - move_warp(m_pipeline_reg[2],m_dispatch_reg); + move_warp(m_pipeline_reg[m_config->smem_latency-1],m_dispatch_reg); m_dispatch_reg->clear(); } } else { @@ -2562,9 +2818,42 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const assert( result <= MAX_CTA_PER_SHADER ); if (result < 1) { printf ("GPGPU-Sim uArch: ERROR ** Kernel requires more resources than shader has.\n"); + if(gpgpu_ignore_resources_limitation) { + printf ("GPGPU-Sim uArch: gpgpu_ignore_resources_limitation is set, ignore the ERROR!\n"); + return 1; + } abort(); } + if(adpative_volta_cache_config && !k.volta_cache_config_set) { + //For Volta, we assign the remaining shared memory to L1 cache + //For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x + unsigned total_shmed = kernel_info->smem * result; + assert(total_shmed >=0 && total_shmed <= gpgpu_shmem_size); + assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared + assert(m_L1D_config.get_nset() == 4); //Volta L1 has four sets + if(total_shmed < gpgpu_shmem_size){ + if(total_shmed == 0) + m_L1D_config.set_assoc(256); //L1 is 128KB ans shd=0 + else if(total_shmed > 0 && total_shmed <= 8192) + m_L1D_config.set_assoc(240); //L1 is 120KB ans shd=8KB + else if(total_shmed > 8192 && total_shmed <= 16384) + m_L1D_config.set_assoc(224); //L1 is 112KB ans shd=16KB + else if(total_shmed > 16384 && total_shmed <= 32768) + m_L1D_config.set_assoc(192); //L1 is 96KB ans shd=32KB + else if(total_shmed > 32768 && total_shmed <= 65536) + m_L1D_config.set_assoc(128); //L1 is 64KB ans shd=64KB + else if(total_shmed > 65536 && total_shmed <= gpgpu_shmem_size) + m_L1D_config.set_assoc(64); //L1 is 32KB and shd=96KB + else + assert(0); + + printf ("GPGPU-Sim: Reconfigure L1 cache in Volta Archi to %uKB\n", m_L1D_config.get_total_size_inKB()); + } + + k.volta_cache_config_set = true; + } + return result; } @@ -2586,6 +2875,11 @@ void shader_core_ctx::cache_flush() m_ldst_unit->flush(); } +void shader_core_ctx::cache_invalidate() +{ + m_ldst_unit->invalidate(); +} + // modifiers std::list opndcoll_rfu_t::arbiter_t::allocate_reads() { @@ -3340,6 +3634,15 @@ void simt_core_cluster::print_not_completed( FILE *fp ) const } } + +float simt_core_cluster::get_current_occupancy( unsigned long long& active, unsigned long long& total ) const { + float aggregate = 0.f; + for( unsigned i=0; i < m_config->n_simt_cores_per_cluster; i++ ) { + aggregate+=m_core[i]->get_current_occupancy( active, total ); + } + return aggregate / m_config->n_simt_cores_per_cluster; +} + unsigned simt_core_cluster::get_n_active_cta() const { unsigned n=0; @@ -3403,6 +3706,12 @@ void simt_core_cluster::cache_flush() m_core[i]->cache_flush(); } +void simt_core_cluster::cache_invalidate() +{ + for( unsigned i=0; i < m_config->n_simt_cores_per_cluster; i++ ) + m_core[i]->cache_invalidate(); +} + bool simt_core_cluster::icnt_injection_buffer_full(unsigned size, bool write) { unsigned request_size = size; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 97e438f..437506c 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -70,6 +70,14 @@ #define WRITE_MASK_SIZE 8 +enum exec_unit_type_t +{ + NONE = 0, + SP = 1, + SFU = 2, + MEM = 3, + DP = 4 +}; class thread_ctx_t { public: @@ -308,6 +316,7 @@ enum concrete_scheduler CONCRETE_SCHEDULER_GTO, CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE, CONCRETE_SCHEDULER_WARP_LIMITING, + CONCRETE_SCHEDULER_OLDEST_FIRST, NUM_CONCRETE_SCHEDULERS }; @@ -317,13 +326,14 @@ public: Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* tensor_core_out, register_set* mem_out, int id) : m_supervised_warps(), m_stats(stats), m_shader(shader), m_scoreboard(scoreboard), m_simt_stack(simt), /*m_pipeline_reg(pipe_regs),*/ m_warp(warp), - m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){} + m_sp_out(sp_out),m_dp_out(dp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){} virtual ~scheduler_unit(){} virtual void add_supervised_warp_id(int i) { m_supervised_warps.push_back(&warp(i)); @@ -395,6 +405,7 @@ protected: //warp_inst_t** m_pipeline_reg; std::vector* m_warp; register_set* m_sp_out; + register_set* m_dp_out; register_set* m_sfu_out; register_set* m_tensor_core_out; register_set* m_mem_out; @@ -408,11 +419,12 @@ public: Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* tensor_core_out, register_set* mem_out, int id ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){} + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){} virtual ~lrr_scheduler () {} virtual void order_warps (); virtual void done_adding_supervised_warps() { @@ -426,11 +438,12 @@ public: Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* tensor_core_out, register_set* mem_out, int id ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){} + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){} virtual ~gto_scheduler () {} virtual void order_warps (); virtual void done_adding_supervised_warps() { @@ -439,6 +452,25 @@ public: }; +class oldest_scheduler : public scheduler_unit { +public: + oldest_scheduler ( shader_core_stats* stats, shader_core_ctx* shader, + Scoreboard* scoreboard, simt_stack** simt, + std::vector* warp, + register_set* sp_out, + register_set* dp_out, + register_set* sfu_out, + register_set* tensor_core_out, + register_set* mem_out, + int id ) + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ){} + virtual ~oldest_scheduler () {} + virtual void order_warps (); + virtual void done_adding_supervised_warps() { + m_last_supervised_issued = m_supervised_warps.begin(); + } + +}; class two_level_active_scheduler : public scheduler_unit { public: @@ -446,12 +478,13 @@ public: Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* tensor_core_out, register_set* mem_out, int id, char* config_str ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ), + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out,tensor_core_out, mem_out, id ), m_pending_warps() { unsigned inner_level_readin; @@ -497,6 +530,7 @@ public: Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* tensor_core_out, register_set* mem_out, @@ -1060,6 +1094,23 @@ public: switch(inst.op) { case SFU_OP: break; case ALU_SFU_OP: break; + case DP_OP: break; //for compute <= 29 (i..e Fermi and GT200) + default: return false; + } + return pipelined_simd_unit::can_issue(inst); + } + virtual void active_lanes_in_pipeline(); + virtual void issue( register_set& source_reg ); +}; + +class dp_unit : public pipelined_simd_unit +{ +public: + dp_unit( register_set* result_port, const shader_core_config *config, shader_core_ctx *core ); + virtual bool can_issue( const warp_inst_t &inst ) const + { + switch(inst.op) { + case DP_OP: break; default: return false; } return pipelined_simd_unit::can_issue(inst); @@ -1098,6 +1149,7 @@ public: case STORE_OP: return false; case TENSOR_CORE_STORE_OP: return false; case MEMORY_BARRIER_OP: return false; + case DP_OP: return false; default: break; } return pipelined_simd_unit::can_issue(inst); @@ -1129,6 +1181,7 @@ public: void fill( mem_fetch *mf ); void flush(); + void invalidate(); void writeback(); // accessors @@ -1195,6 +1248,7 @@ protected: mem_fetch *mf, enum cache_request_status status ); mem_stage_stall_type process_memory_access_queue( cache_t *cache, warp_inst_t &inst ); + mem_stage_stall_type process_memory_access_queue_l1cache( l1_cache *cache, warp_inst_t &inst ); const memory_config *m_memory_config; class mem_fetch_interface *m_icnt; @@ -1223,13 +1277,18 @@ protected: // for debugging unsigned long long m_last_inst_gpu_sim_cycle; unsigned long long m_last_inst_gpu_tot_sim_cycle; + + std::deque l1_latency_queue; + void L1_latency_queue_cycle(); }; enum pipeline_stage_name_t { ID_OC_SP=0, + ID_OC_DP, ID_OC_SFU, ID_OC_MEM, OC_EX_SP, + OC_EX_DP, OC_EX_SFU, OC_EX_MEM, EX_WB, @@ -1240,9 +1299,11 @@ enum pipeline_stage_name_t { const char* const pipeline_stage_name_decode[] = { "ID_OC_SP", + "ID_OC_DP", "ID_OC_SFU", "ID_OC_MEM", "OC_EX_SP", + "OC_EX_DP", "OC_EX_SFU", "OC_EX_MEM", "EX_WB", @@ -1340,27 +1401,29 @@ struct shader_core_config : public core_config mutable cache_config m_L1C_config; mutable l1d_cache_config m_L1D_config; - bool gmem_skip_L1D; // on = global memory access always skip the L1 cache - bool gpgpu_dwf_reg_bankconflict; int gpgpu_num_sched_per_core; int gpgpu_max_insn_issue_per_warp; + bool gpgpu_dual_issue_diff_exec_units; //op collector int gpgpu_operand_collector_num_units_sp; + int gpgpu_operand_collector_num_units_dp; int gpgpu_operand_collector_num_units_sfu; int gpgpu_operand_collector_num_units_tensor_core; int gpgpu_operand_collector_num_units_mem; int gpgpu_operand_collector_num_units_gen; unsigned int gpgpu_operand_collector_num_in_ports_sp; + unsigned int gpgpu_operand_collector_num_in_ports_dp; unsigned int gpgpu_operand_collector_num_in_ports_sfu; unsigned int gpgpu_operand_collector_num_in_ports_tensor_core; unsigned int gpgpu_operand_collector_num_in_ports_mem; unsigned int gpgpu_operand_collector_num_in_ports_gen; unsigned int gpgpu_operand_collector_num_out_ports_sp; + unsigned int gpgpu_operand_collector_num_out_ports_dp; unsigned int gpgpu_operand_collector_num_out_ports_sfu; unsigned int gpgpu_operand_collector_num_out_ports_tensor_core; unsigned int gpgpu_operand_collector_num_out_ports_mem; @@ -1368,6 +1431,7 @@ struct shader_core_config : public core_config int gpgpu_num_sp_units; int gpgpu_tensor_core_avail; + int gpgpu_num_dp_units; int gpgpu_num_sfu_units; int gpgpu_num_tensor_core_units; int gpgpu_num_mem_units; @@ -1379,6 +1443,7 @@ struct shader_core_config : public core_config unsigned gpgpu_num_reg_banks; bool gpgpu_reg_bank_use_warp_id; bool gpgpu_local_mem_map; + bool gpgpu_ignore_resources_limitation; unsigned max_sp_latency; unsigned max_sfu_latency; @@ -1391,10 +1456,14 @@ struct shader_core_config : public core_config int simt_core_sim_order; + unsigned smem_latency; + unsigned mem2device(unsigned memid) const { return memid + n_simt_clusters; } //Jin: concurrent kernel on sm bool gpgpu_concurrent_kernel_sm; + + bool adpative_volta_cache_config; }; struct shader_core_stats_pod { @@ -1457,6 +1526,8 @@ struct shader_core_stats_pod { unsigned *last_shader_cycle_distro; unsigned *num_warps_issuable; unsigned gpgpu_n_stall_shd_mem; + unsigned* single_issue_nums; + unsigned* dual_issue_nums; //memory access classification int gpgpu_n_mem_read_local; @@ -1528,6 +1599,8 @@ public: m_n_diverge = (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); shader_cycle_distro = (unsigned*) calloc(config->warp_size+3, sizeof(unsigned)); last_shader_cycle_distro = (unsigned*) calloc(m_config->warp_size+3, sizeof(unsigned)); + single_issue_nums = (unsigned*) calloc(config->gpgpu_num_sched_per_core,sizeof(unsigned)); + dual_issue_nums = (unsigned*) calloc(config->gpgpu_num_sched_per_core, sizeof(unsigned)); n_simt_to_mem = (long *)calloc(config->num_shader(), sizeof(long)); n_mem_to_simt = (long *)calloc(config->num_shader(), sizeof(long)); @@ -1651,6 +1724,7 @@ public: void issue_block2core( class kernel_info_t &kernel ); void cache_flush(); + void cache_invalidate(); void accept_fetch_response( mem_fetch *mf ); void accept_ldst_unit_response( class mem_fetch * mf ); void broadcast_barrier_reduction(unsigned cta_id, unsigned bar_id,warp_set_t warps); @@ -1679,6 +1753,7 @@ public: // accessors virtual bool warp_waiting_at_barrier( unsigned warp_id ) const; void get_pdom_stack_top_info( unsigned tid, unsigned *pc, unsigned *rpc ) const; + float get_current_occupancy( unsigned long long & active, unsigned long long & total ) const; // used by pipeline timing model components: // modifiers @@ -1885,10 +1960,14 @@ public: std::vector m_pipeline_reg; Scoreboard *m_scoreboard; opndcoll_rfu_t m_operand_collector; + int m_active_warps; //schedule std::vector schedulers; + //issue + unsigned int Issue_Prio; + // execute unsigned m_num_function_units; std::vector m_dispatch_port; @@ -1940,6 +2019,7 @@ public: void reinit(); unsigned issue_block2core(); void cache_flush(); + void cache_invalidate(); bool icnt_injection_buffer_full(unsigned size, bool write); void icnt_inject_request_packet(class mem_fetch *mf); @@ -1970,6 +2050,7 @@ public: void get_L1T_sub_stats(struct cache_sub_stats &css) const; void get_icnt_stats(long &n_simt_to_mem, long &n_mem_to_simt) const; + float get_current_occupancy( unsigned long long& active, unsigned long long & total ) const; private: unsigned m_cluster_id; diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index ede9f20..52e2f5e 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -172,6 +172,7 @@ void *gpgpu_sim_thread_concurrent(void*) g_sim_active = false; pthread_mutex_unlock(&g_sim_lock); } while( !g_sim_done ); + printf("GPGPU-Sim: *** simulation thread exiting ***\n"); fflush(stdout); diff --git a/src/gpuwattch/makefile b/src/gpuwattch/makefile index ab718cc..354c9ec 100644 --- a/src/gpuwattch/makefile +++ b/src/gpuwattch/makefile @@ -11,10 +11,10 @@ opt: $(TAR).mk obj_opt @$(MAKE) TAG=opt -C . -f $(TAR).mk obj_dbg: - mkdir $@ + mkdir -p $@ obj_opt: - mkdir $@ + mkdir -p $@ depend: @$(MAKE) TAG=opt -C . -f $(TAR).mk depend diff --git a/src/intersim2/Makefile b/src/intersim2/Makefile index bd42000..7d10b3f 100644 --- a/src/intersim2/Makefile +++ b/src/intersim2/Makefile @@ -36,7 +36,7 @@ DEBUG ?= 0 LEX = flex YACC = bison -y DEFINE = #-DTRACK_STALLS -DTRACK_BUFFERS -DTRACK_FLOWS -DTRACK_CREDITS -INCPATH = -I. -Iarbiters -Iallocators -Irouters -Inetworks -Ipower +INCPATH = -I. -Iarbiters -Iallocators -Irouters -Inetworks -Ipower -I$(GPGPUSIM_ROOT)/src ifeq ($(CREATE_LIBRARY),1) INCPATH += -I$(GPGPUSIM_ROOT)/src/gpgpu-sim/ diff --git a/src/intersim2/interconnect_interface.cpp b/src/intersim2/interconnect_interface.cpp index 4386821..1e1a2d7 100644 --- a/src/intersim2/interconnect_interface.cpp +++ b/src/intersim2/interconnect_interface.cpp @@ -44,6 +44,7 @@ #include "booksim.hpp" #include "intersim_config.hpp" #include "network.hpp" +#include "trace.h" InterconnectInterface* InterconnectInterface::New(const char* const config_file) { @@ -147,6 +148,8 @@ void InterconnectInterface::Push(unsigned input_deviceID, unsigned output_device { // it should have free buffer assert(HasBuffer(input_deviceID, size)); + + DPRINTF(INTERCONNECT, "Sent %d bytes from %d to %d", size, input_deviceID, output_deviceID); int output_icntID = _node_map[output_deviceID]; int input_icntID = _node_map[input_deviceID]; @@ -178,7 +181,11 @@ void InterconnectInterface::Push(unsigned input_deviceID, unsigned output_device case WRITE_REQUEST: packet_type = Flit::WRITE_REQUEST ;break; case READ_REPLY: packet_type = Flit::READ_REPLY ;break; case WRITE_ACK: packet_type = Flit::WRITE_REPLY ;break; - default: assert (0); + default: + { + cout<<"Type "<get_type()<<" is undefined!"<