From dcf7e6a8445a5d8e4383add44ca6f5d0d198ab02 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 17 Jul 2017 22:32:30 -0400 Subject: Improving GPU core model. This commits contains: 1- round robin inst issue for warp multiple schedulers 2- add sector mask in the memory request (to bused later for L2 sector cache) 3- Adding Fermi coalescer 4- Ensure different exen units are used in dual_issue mode 5- Report how many dual_issue happened 6- Adding oldest_first scheduler --- src/abstract_hardware_model.cc | 54 +++++++++++++++++++++++++++++++----------- 1 file changed, 40 insertions(+), 14 deletions(-) (limited to 'src/abstract_hardware_model.cc') diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index fe6f8ab..f75c525 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -314,12 +314,12 @@ void warp_inst_t::generate_mem_accesses() break; case global_space: case local_space: case param_space_local: - if( m_config->gpgpu_coalesce_arch == 13 ) { - if(isatomic()) - memory_coalescing_arch_13_atomic(is_write, access_type); - else - memory_coalescing_arch_13(is_write, access_type); - } else abort(); + if( m_config->gpgpu_coalesce_arch == 13 || m_config->gpgpu_coalesce_arch == 20) { + if(isatomic()) + memory_coalescing_arch_atomic(is_write, access_type); + else + memory_coalescing_arch(is_write, access_type); + } else abort(); break; @@ -343,7 +343,7 @@ void warp_inst_t::generate_mem_accesses() byte_mask.set(idx+i); } for( a=accesses.begin(); a != accesses.end(); ++a ) - m_accessq.push_back( mem_access_t(access_type,a->first,cache_block_size,is_write,a->second,byte_mask) ); + m_accessq.push_back( mem_access_t(access_type,a->first,cache_block_size,is_write,a->second, byte_mask, mem_access_sector_mask_t())); } if ( space.get_type() == global_space ) { @@ -352,11 +352,37 @@ void warp_inst_t::generate_mem_accesses() m_mem_accesses_created=true; } -void warp_inst_t::memory_coalescing_arch_13( bool is_write, mem_access_type access_type ) +void warp_inst_t::memory_coalescing_arch( bool is_write, mem_access_type access_type ) { // see the CUDA manual where it discusses coalescing rules before reading this unsigned segment_size = 0; - unsigned warp_parts = m_config->mem_warp_parts; + unsigned warp_parts; + + //TO DO: need to double check how double number are coalesced! + if(data_size == 1) + { + //If it is byte data, then coalesce on the whole 32 threads, regardless the arch version + warp_parts = 1; + } + else if(m_config->gpgpu_coalesce_arch == 13) + { + //mem_warp_parts should equal 2 for arch=13 + //we still use the parameter mem_warp_parts for arch=13 to ensure it is backward compatibility with older gpgpu config files + warp_parts = m_config->mem_warp_parts; + } + else if(m_config->gpgpu_coalesce_arch == 20) + { + //It is expected that L1_warp_parts_non_cached = 4 and L1_warp_parts_cached = 1 for arch=20 + //non cached, coalesce on 8 threads to generate 32 bytes accesses + //cached, coalesce on 32 threads to generate 128 bytes accesses + if(m_config->gmem_skip_L1D || cache_op == CACHE_GLOBAL) + warp_parts = m_config->L1_warp_parts_non_cached; + else + warp_parts = m_config->L1_warp_parts_cached; + } + else + abort(); + switch( data_size ) { case 1: segment_size = 32; break; case 2: segment_size = 64; break; @@ -410,13 +436,13 @@ void warp_inst_t::memory_coalescing_arch_13( bool is_write, mem_access_type acce new_addr_type addr = t->first; const transaction_info &info = t->second; - memory_coalescing_arch_13_reduce_and_send(is_write, access_type, info, addr, segment_size); + memory_coalescing_arch_reduce_and_send(is_write, access_type, info, addr, segment_size); } } } -void warp_inst_t::memory_coalescing_arch_13_atomic( bool is_write, mem_access_type access_type ) +void warp_inst_t::memory_coalescing_arch_atomic( bool is_write, mem_access_type access_type ) { assert(space.get_type() == global_space); // Atomics allowed only for global memory @@ -485,13 +511,13 @@ void warp_inst_t::memory_coalescing_arch_13_atomic( bool is_write, mem_access_ty for(t=transaction_list.begin(); t!=transaction_list.end(); t++) { // For each transaction const transaction_info &info = *t; - memory_coalescing_arch_13_reduce_and_send(is_write, access_type, info, addr, segment_size); + memory_coalescing_arch_reduce_and_send(is_write, access_type, info, addr, segment_size); } } } } -void warp_inst_t::memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size ) +void warp_inst_t::memory_coalescing_arch_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size ) { assert( (addr & (segment_size-1)) == 0 ); @@ -540,7 +566,7 @@ void warp_inst_t::memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_ assert(lower_half_used && upper_half_used); } } - m_accessq.push_back( mem_access_t(access_type,addr,size,is_write,info.active,info.bytes) ); + m_accessq.push_back( mem_access_t(access_type,addr,size,is_write,info.active,info.bytes, info.chunks) ); } void warp_inst_t::completed( unsigned long long cycle ) const -- cgit v1.3 From b806d3a4021a12638e1e67fcd67012dca4b1689e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 17 Jul 2017 23:20:42 -0400 Subject: Fixing some typos and adding comments --- src/abstract_hardware_model.cc | 14 +++++++------- src/abstract_hardware_model.h | 2 +- src/gpgpu-sim/gpu-cache.cc | 2 +- src/gpgpu-sim/gpu-sim.cc | 12 ++++++------ src/gpgpu-sim/gpu-sim.h | 2 -- src/gpgpu-sim/shader.cc | 43 +++++++++++++++++++++--------------------- src/gpgpu-sim/shader.h | 4 ++-- 7 files changed, 39 insertions(+), 40 deletions(-) (limited to 'src/abstract_hardware_model.cc') diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index f75c525..64eb43c 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -315,11 +315,11 @@ void warp_inst_t::generate_mem_accesses() case global_space: case local_space: case param_space_local: if( m_config->gpgpu_coalesce_arch == 13 || m_config->gpgpu_coalesce_arch == 20) { - if(isatomic()) - memory_coalescing_arch_atomic(is_write, access_type); - else - memory_coalescing_arch(is_write, access_type); - } else abort(); + if(isatomic()) + memory_coalescing_arch_atomic(is_write, access_type); + else + memory_coalescing_arch(is_write, access_type); + } else abort(); break; @@ -358,7 +358,7 @@ void warp_inst_t::memory_coalescing_arch( bool is_write, mem_access_type access_ unsigned segment_size = 0; unsigned warp_parts; - //TO DO: need to double check how double number are coalesced! + //TO DO: need to double check how doubles are coalesced! if(data_size == 1) { //If it is byte data, then coalesce on the whole 32 threads, regardless the arch version @@ -367,7 +367,7 @@ void warp_inst_t::memory_coalescing_arch( bool is_write, mem_access_type access_ else if(m_config->gpgpu_coalesce_arch == 13) { //mem_warp_parts should equal 2 for arch=13 - //we still use the parameter mem_warp_parts for arch=13 to ensure it is backward compatibility with older gpgpu config files + //use the parameter mem_warp_parts for arch=13 to ensure it is backward compatibility with older gpgpu config files warp_parts = m_config->mem_warp_parts; } else if(m_config->gpgpu_coalesce_arch == 20) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cd185a1..910a9ed 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -685,7 +685,7 @@ public: bool wr, const active_mask_t &active_mask, const mem_access_byte_mask_t &byte_mask, - const mem_access_sector_mask_t §or_mask) + const mem_access_sector_mask_t §or_mask) : m_warp_mask(active_mask), m_byte_mask(byte_mask), m_sector_mask(sector_mask) { init(); diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index cfd0dc8..7af7db0 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -868,7 +868,7 @@ data_cache::wr_miss_wa( new_addr_type addr, false, // Now performing a read mf->get_access_warp_mask(), mf->get_access_byte_mask(), - mf->get_access_sector_mask()); + mf->get_access_sector_mask()); mem_fetch *n_mf = new mem_fetch( *ma, NULL, diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 26432c4..483a7b6 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -302,7 +302,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "0"); option_parser_register(opp, "-gpgpu_local_mem_map", OPT_BOOL, &gpgpu_local_mem_map, "Mapping from local memory space address to simulated GPU physical address space (default = enabled)", - "1"); + "1"); option_parser_register(opp, "-gpgpu_num_reg_banks", OPT_INT32, &gpgpu_num_reg_banks, "Number of register banks (default = 8)", "8"); @@ -346,17 +346,17 @@ void shader_core_config::reg_options(class OptionParser * opp) "number of collector unit in ports (default = 0)", "0"); option_parser_register(opp, "-gpgpu_coalesce_arch", OPT_INT32, &gpgpu_coalesce_arch, - "Coalescing arch (GT200 = 13, Fermi = 20)", + "Coalescing arch (GT200 = 13, Fermi = 20)", "13"); option_parser_register(opp, "-gpgpu_num_sched_per_core", OPT_INT32, &gpgpu_num_sched_per_core, "Number of warp schedulers per core", "1"); option_parser_register(opp, "-gpgpu_max_insn_issue_per_warp", OPT_INT32, &gpgpu_max_insn_issue_per_warp, - "Max number of instructions that can be issued per warp in one cycle by scheduler (either 1 or 2)", - "2"); + "Max number of instructions that can be issued per warp in one cycle by scheduler (either 1 or 2)", + "2"); option_parser_register(opp, "-gpgpu_dual_issue_diff_exec_units", OPT_BOOL, &gpgpu_dual_issue_diff_exec_units, - "should dual issue use two different execution unit resources", - "1"); + "should dual issue use two different execution unit resources", + "1"); option_parser_register(opp, "-gpgpu_simt_core_sim_order", OPT_INT32, &simt_core_sim_order, "Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)", "1"); diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 23e6144..7d92c66 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -314,8 +314,6 @@ public: unsigned num_shader() const { return m_shader_config.num_shader(); } unsigned num_cluster() const { return m_shader_config.n_simt_clusters; } unsigned get_max_concurrent_kernel() const { return max_concurrent_kernel; } - unsigned get_gpu_max_cycle_opt() const { return gpu_max_cycle_opt; } - unsigned get_gpu_max_insn_opt() const { return gpu_max_insn_opt; } private: void init_clock_domains(void ); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 015995e..d826b69 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -132,8 +132,8 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE : sched_config.find("gto") != std::string::npos ? CONCRETE_SCHEDULER_GTO : - sched_config.find("old") != std::string::npos ? - CONCRETE_SCHEDULER_OLDEST_FIRST : + sched_config.find("old") != std::string::npos ? + CONCRETE_SCHEDULER_OLDEST_FIRST : sched_config.find("warp_limiting") != std::string::npos ? CONCRETE_SCHEDULER_WARP_LIMITING: NUM_CONCRETE_SCHEDULERS; @@ -187,16 +187,16 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, break; case CONCRETE_SCHEDULER_OLDEST_FIRST: schedulers.push_back( - new oldest_scheduler( m_stats, - this, - m_scoreboard, - m_simt_stack, - &m_warp, - &m_pipeline_reg[ID_OC_SP], - &m_pipeline_reg[ID_OC_SFU], - &m_pipeline_reg[ID_OC_MEM], - i - ) + new oldest_scheduler( m_stats, + this, + m_scoreboard, + m_simt_stack, + &m_warp, + &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_SFU], + &m_pipeline_reg[ID_OC_MEM], + i + ) ); break; case CONCRETE_SCHEDULER_WARP_LIMITING: @@ -750,12 +750,13 @@ void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* void shader_core_ctx::issue(){ - unsigned j; - for (unsigned i = 0; i < schedulers.size(); i++) { - j = (Issue_Prio + i) % schedulers.size(); - schedulers[j]->cycle(); - } - Issue_Prio = (Issue_Prio+1)% schedulers.size(); + //Ensure fair round robin issu between schedulers + unsigned j; + for (unsigned i = 0; i < schedulers.size(); i++) { + j = (Issue_Prio + i) % schedulers.size(); + schedulers[j]->cycle(); + } + Issue_Prio = (Issue_Prio+1)% schedulers.size(); //really is issue; //for (unsigned i = 0; i < schedulers.size(); i++) { @@ -876,8 +877,8 @@ void scheduler_unit::cycle() unsigned checked=0; unsigned issued=0; exec_unit_type_t previous_issued_inst_exec_type = exec_unit_type_t::NONE; - unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; - bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units; + unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; + bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units; while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) { const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst(); //Jin: handle cdp latency; @@ -1062,7 +1063,7 @@ void oldest_scheduler::order_warps() m_supervised_warps, m_last_supervised_issued, m_supervised_warps.size(), - ORDERED_PRIORITY_FUNC_ONLY, + ORDERED_PRIORITY_FUNC_ONLY, scheduler_unit::sort_warps_by_oldest_dynamic_id ); } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 395c1ed..2fed420 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -316,7 +316,7 @@ enum concrete_scheduler CONCRETE_SCHEDULER_GTO, CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE, CONCRETE_SCHEDULER_WARP_LIMITING, - CONCRETE_SCHEDULER_OLDEST_FIRST, + CONCRETE_SCHEDULER_OLDEST_FIRST, NUM_CONCRETE_SCHEDULERS }; @@ -456,7 +456,7 @@ public: : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ){} virtual ~oldest_scheduler () {} virtual void order_warps (); - virtual void done_adding_supervised_warps() { + virtual void done_adding_supervised_warps() { m_last_supervised_issued = m_supervised_warps.begin(); } -- cgit v1.3