From 0efd3c00f5611bfa82b01d87d175122388d621cc Mon Sep 17 00:00:00 2001
From: Tor Aamodt <aamodt@ece.ubc.ca>
Date: Sun, 24 Oct 2010 23:41:43 -0800
Subject: 0.9756 correlation.  Set L1T line size to 128 bytes... problem was
 stalling to send four requests per warp into L1T tag lookup.

If L1T is really 32B blocks (as per Henry's paper), this suggests
banking of L1T needs to be modeled.

Other changes:
1. bug fix in memory access generation for texture/const cache access
2. adding back memory latency measurement for visualizer

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
---
 src/abstract_hardware_model.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/abstract_hardware_model.h')

diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index bc73fbc..cdecc14 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -717,7 +717,7 @@ protected:
     bool m_per_scalar_thread_valid;
     std::vector<per_thread_info> m_per_scalar_thread;
     bool m_mem_accesses_created;
-    std::vector<mem_access_t> m_accessq;
+    std::list<mem_access_t> m_accessq;
 
     static unsigned sm_next_uid;
 };
-- 
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