From 553346445486367799d4d67bf3537e54b7c83859 Mon Sep 17 00:00:00 2001 From: Aaron Barnes Date: Sun, 9 May 2021 13:11:39 -0400 Subject: parition CU allocation, add prints --- src/abstract_hardware_model.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src/abstract_hardware_model.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index c012de0..636052a 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1315,7 +1315,17 @@ class register_set { } return false; } - + unsigned get_ready_reg_id() { + // for sub core model we need to figure which reg_id has the ready warp + // this function should only be called if has_ready() was true + assert(has_ready()); + for (unsigned i = 0; i < regs.size(); i++) { + if (not regs[i]->empty()) { + return i; + } + } + abort(); + } void move_in(warp_inst_t *&src) { warp_inst_t **free = get_free(); move_warp(*free, src); -- cgit v1.3 From 645a0eaa6b431c5d4279330c72905ac6b6e7abb2 Mon Sep 17 00:00:00 2001 From: Aaron M Barnes Date: Sun, 9 May 2021 13:23:12 -0400 Subject: minor fixes --- src/abstract_hardware_model.h | 1 + src/gpgpu-sim/shader.cc | 2 +- src/gpgpu-sim/shader.h | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src/abstract_hardware_model.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 636052a..4d2bb4c 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1291,6 +1291,7 @@ class register_set { } m_name = name; } + const char * get_name() {return m_name;} bool has_free() { for (unsigned i = 0; i < regs.size(); i++) { if (regs[i]->empty()) { diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 40120ec..372bc12 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3867,7 +3867,7 @@ void opndcoll_rfu_t::init(unsigned num_banks, shader_core_ctx *shader) { assert((m_bank_warp_shift == 5) || (m_warp_size != 32)); sub_core_model = shader->get_config()->sub_core_model; - m_num_warp_sceds = shader->get_config()->gpgpu_num_sched_per_core; + m_num_warp_scheds = shader->get_config()->gpgpu_num_sched_per_core; if (sub_core_model) assert(num_banks % shader->get_config()->gpgpu_num_sched_per_core == 0); m_num_banks_per_sched = diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 6481790..05c0e4c 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -947,7 +947,7 @@ class opndcoll_rfu_t { // operand collector based register file unit arbiter_t m_arbiter; unsigned m_num_banks_per_sched; - unsigned m_num_warp_sceds; + unsigned m_num_warp_scheds; bool sub_core_model; // unsigned m_num_ports; -- cgit v1.3 From b67288046af824a88f8bb94541ded14cc711ef35 Mon Sep 17 00:00:00 2001 From: Aaron M Barnes Date: Sun, 9 May 2021 14:42:29 -0400 Subject: validated collector unit partitioning based on scheduler --- src/abstract_hardware_model.h | 16 ++++++++++++++-- src/gpgpu-sim/shader.cc | 8 +++++--- 2 files changed, 19 insertions(+), 5 deletions(-) (limited to 'src/abstract_hardware_model.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 4d2bb4c..ba32358 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1320,12 +1320,24 @@ class register_set { // for sub core model we need to figure which reg_id has the ready warp // this function should only be called if has_ready() was true assert(has_ready()); + warp_inst_t **ready; + ready = NULL; + unsigned reg_id; for (unsigned i = 0; i < regs.size(); i++) { if (not regs[i]->empty()) { - return i; + if (ready and (*ready)->get_uid() < regs[i]->get_uid()) { + // ready is oldest + } else { + ready = ®s[i]; + reg_id = i; + } } } - abort(); + return reg_id; + } + unsigned get_schd_id(unsigned reg_id) { + assert(not regs[reg_id]->empty()); + return regs[reg_id]->get_schd_id(); } void move_in(warp_inst_t *&src) { warp_inst_t **free = get_free(); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 895a2ef..5c27b9b 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3976,19 +3976,21 @@ void opndcoll_rfu_t::allocate_cu(unsigned port_num) { bool allocated = false; unsigned cuLowerBound = 0; unsigned cuUpperBound = cu_set.size(); + unsigned schd_id; if(sub_core_model) { // Sub core model only allocates on the subset of CUs assigned to the scheduler that issued unsigned reg_id = (*inp.m_in[i]).get_ready_reg_id(); + schd_id = (*inp.m_in[i]).get_schd_id(reg_id); assert(cu_set.size() % m_num_warp_scheds == 0); unsigned cusPerSched = cu_set.size() / m_num_warp_scheds; - cuLowerBound = reg_id * cusPerSched; + cuLowerBound = schd_id * cusPerSched; cuUpperBound = cuLowerBound + cusPerSched; - std::cout << "reg_id: " << reg_id << " cusPerSched: " << cusPerSched << " lowerBound: " << cuLowerBound << std::endl; + std::cout << "reg_id: " << reg_id << " schd_id: " << schd_id << " cusPerSched: " << cusPerSched << " lowerBound: " << cuLowerBound << std::endl; assert(0 <= cuLowerBound && cuUpperBound <= cu_set.size()); } for (unsigned k = cuLowerBound; k < cuUpperBound; k++) { if (cu_set[k].is_free()) { - std::cout << "Allocated on cu: " << k << std::endl; + std::cout << "Allocated schd_id: " << schd_id << " on cu: " << k << std::endl; collector_unit_t *cu = &cu_set[k]; allocated = cu->allocate(inp.m_in[i], inp.m_out[i]); m_arbiter.add_read_requests(cu); -- cgit v1.3 From fa76ab438b0b8c2d2e8abf5f395c7a98a3d5fd9b Mon Sep 17 00:00:00 2001 From: Aaron Barnes Date: Mon, 10 May 2021 15:05:06 -0400 Subject: sub core model dispatches only to assigned exec pipelines --- src/abstract_hardware_model.h | 11 +++++++++++ src/gpgpu-sim/shader.cc | 17 ++++++++++------- src/gpgpu-sim/shader.h | 10 ++++++---- 3 files changed, 27 insertions(+), 11 deletions(-) (limited to 'src/abstract_hardware_model.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ba32358..d70c3eb 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1346,6 +1346,17 @@ class register_set { // void copy_in( warp_inst_t* src ){ // src->copy_contents_to(*get_free()); //} + void move_in(bool sub_core_model, unsigned reg_id, warp_inst_t *&src) { + warp_inst_t **free; + if (!sub_core_model) { + free = get_free(); + } else { + assert(reg_id < regs.size()); + free = get_free(sub_core_model, reg_id); + } + move_warp(*free, src); + } + void move_out_to(warp_inst_t *&dest) { warp_inst_t **ready = get_ready(); move_warp(dest, *ready); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 5c27b9b..ec10733 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3939,7 +3939,7 @@ bool opndcoll_rfu_t::writeback(warp_inst_t &inst) { void opndcoll_rfu_t::dispatch_ready_cu() { for (unsigned p = 0; p < m_dispatch_units.size(); ++p) { dispatch_unit_t &du = m_dispatch_units[p]; - collector_unit_t *cu = du.find_ready(); + collector_unit_t *cu = du.find_ready(sub_core_model, p); if (cu) { for (unsigned i = 0; i < (cu->get_num_operands() - cu->get_num_regs()); i++) { @@ -3961,7 +3961,9 @@ void opndcoll_rfu_t::dispatch_ready_cu() { m_shader->get_config()->warp_size); // cu->get_active_count()); } } - cu->dispatch(); + unsigned cusPerSched = du->get_num_collectors() / m_num_warp_scheds; + unsigned reg_id = p / cusPerSched; + cu->dispatch(sub_core_model, reg_id); } } } @@ -3985,7 +3987,6 @@ void opndcoll_rfu_t::allocate_cu(unsigned port_num) { unsigned cusPerSched = cu_set.size() / m_num_warp_scheds; cuLowerBound = schd_id * cusPerSched; cuUpperBound = cuLowerBound + cusPerSched; - std::cout << "reg_id: " << reg_id << " schd_id: " << schd_id << " cusPerSched: " << cusPerSched << " lowerBound: " << cuLowerBound << std::endl; assert(0 <= cuLowerBound && cuUpperBound <= cu_set.size()); } for (unsigned k = cuLowerBound; k < cuUpperBound; k++) { @@ -4046,8 +4047,8 @@ void opndcoll_rfu_t::allocate_reads() { } } -bool opndcoll_rfu_t::collector_unit_t::ready() const { - return (!m_free) && m_not_ready.none() && (*m_output_register).has_free(); +bool opndcoll_rfu_t::collector_unit_t::ready(bool sub_core_model, unsigned reg_id) const { + return (!m_free) && m_not_ready.none() && (*m_output_register).has_free(sub_core_model, reg_id); } void opndcoll_rfu_t::collector_unit_t::dump( @@ -4110,7 +4111,7 @@ bool opndcoll_rfu_t::collector_unit_t::allocate(register_set *pipeline_reg_set, return false; } -void opndcoll_rfu_t::collector_unit_t::dispatch() { +void opndcoll_rfu_t::collector_unit_t::dispatch(bool sub_core_model, unsigned reg_id) { assert(m_not_ready.none()); // move_warp(*m_output_register,m_warp); // Print out which OC dispatched which warp sched id to which exec pipeline @@ -4122,8 +4123,10 @@ void opndcoll_rfu_t::collector_unit_t::dispatch() { << m_warp->get_schd_id() << "\tto execution register: " << m_output_register->get_name() + << "\treg id: " + << reg_id << std::endl; - m_output_register->move_in(m_warp); + m_output_register->move_in(sub_core_model, reg_id, m_warp); m_free = true; m_output_register = NULL; for (unsigned i = 0; i < MAX_REG_OPERANDS * 2; i++) m_src_op[i].reset(); diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 05c0e4c..74bf320 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -867,7 +867,7 @@ class opndcoll_rfu_t { // operand collector based register file unit m_bank_warp_shift = 0; } // accessors - bool ready() const; + bool ready(bool sub_core_modle, unsigned reg_id) const; const op_t *get_operands() const { return m_src_op; } void dump(FILE *fp, const shader_core_ctx *shader) const; @@ -888,7 +888,7 @@ class opndcoll_rfu_t { // operand collector based register file unit void collect_operand(unsigned op) { m_not_ready.reset(op); } unsigned get_num_operands() const { return m_warp->get_num_operands(); } unsigned get_num_regs() const { return m_warp->get_num_regs(); } - void dispatch(); + void dispatch(bool sub_core_model, unsigned reg_id); bool is_free() { return m_free; } private: @@ -917,10 +917,10 @@ class opndcoll_rfu_t { // operand collector based register file unit m_next_cu = 0; } - collector_unit_t *find_ready() { + collector_unit_t *find_ready(bool sub_core_model, unsigned reg_id) { for (unsigned n = 0; n < m_num_collectors; n++) { unsigned c = (m_last_cu + n + 1) % m_num_collectors; - if ((*m_collector_units)[c].ready()) { + if ((*m_collector_units)[c].ready(sub_core_model, reg_id)) { m_last_cu = c; return &((*m_collector_units)[c]); } @@ -928,6 +928,8 @@ class opndcoll_rfu_t { // operand collector based register file unit return NULL; } + unsigned get_num_collectors(){return m_num_collectors;} + private: unsigned m_num_collectors; std::vector *m_collector_units; -- cgit v1.3 From 28d056519c7f1771557f90d5b0b295b7f75c1a2d Mon Sep 17 00:00:00 2001 From: Aaron Barnes Date: Tue, 11 May 2021 18:13:37 -0400 Subject: partition issue() in the shader execute stage --- src/abstract_hardware_model.h | 16 ++++++++++ src/gpgpu-sim/shader.cc | 72 ++++++++++++++++++++++++------------------- src/gpgpu-sim/shader.h | 26 +++++++++++----- 3 files changed, 74 insertions(+), 40 deletions(-) (limited to 'src/abstract_hardware_model.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index d70c3eb..90ae448 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1316,6 +1316,12 @@ class register_set { } return false; } + bool has_ready(bool sub_core_model, unsigned reg_id) { + if (!sub_core_model) return has_ready(); + assert(reg_id < regs.size()); + return (not regs[reg_id]->empty()) + } + unsigned get_ready_reg_id() { // for sub core model we need to figure which reg_id has the ready warp // this function should only be called if has_ready() was true @@ -1376,6 +1382,16 @@ class register_set { } return ready; } + warp_inst_t **get_ready(bool sub_core_model, unsigned reg_id) { + if (!sub_core_model) + return get_ready(); + warp_inst_t **ready; + ready = NULL; + assert(reg_id < regs.size()); + if (not regs[reg_id]->empty) + ready = ®s[reg_id]; + return ready; + } void print(FILE *fp) const { fprintf(fp, "%s : @%p\n", m_name, this); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index e3a3e9c..ca421de 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -377,41 +377,41 @@ void shader_core_ctx::create_exec_pipeline() { // m_fu = new simd_function_unit*[m_num_function_units]; - for (int k = 0; k < m_config->gpgpu_num_sp_units; k++) { - m_fu.push_back(new sp_unit(&m_pipeline_reg[EX_WB], m_config, this)); + for (unsigned k = 0; k < m_config->gpgpu_num_sp_units; k++) { + m_fu.push_back(new sp_unit(&m_pipeline_reg[EX_WB], m_config, this, k)); m_dispatch_port.push_back(ID_OC_SP); m_issue_port.push_back(OC_EX_SP); } - for (int k = 0; k < m_config->gpgpu_num_dp_units; k++) { - m_fu.push_back(new dp_unit(&m_pipeline_reg[EX_WB], m_config, this)); + for (unsigned k = 0; k < m_config->gpgpu_num_dp_units; k++) { + m_fu.push_back(new dp_unit(&m_pipeline_reg[EX_WB], m_config, this, k)); m_dispatch_port.push_back(ID_OC_DP); m_issue_port.push_back(OC_EX_DP); } - for (int k = 0; k < m_config->gpgpu_num_int_units; k++) { - m_fu.push_back(new int_unit(&m_pipeline_reg[EX_WB], m_config, this)); + for (unsigned k = 0; k < m_config->gpgpu_num_int_units; k++) { + m_fu.push_back(new int_unit(&m_pipeline_reg[EX_WB], m_config, this, k)); m_dispatch_port.push_back(ID_OC_INT); m_issue_port.push_back(OC_EX_INT); } - for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) { - m_fu.push_back(new sfu(&m_pipeline_reg[EX_WB], m_config, this)); + for (unsigned k = 0; k < m_config->gpgpu_num_sfu_units; k++) { + m_fu.push_back(new sfu(&m_pipeline_reg[EX_WB], m_config, this, k)); m_dispatch_port.push_back(ID_OC_SFU); m_issue_port.push_back(OC_EX_SFU); } - for (int k = 0; k < m_config->gpgpu_num_tensor_core_units; k++) { - m_fu.push_back(new tensor_core(&m_pipeline_reg[EX_WB], m_config, this)); + for (unsigned k = 0; k < m_config->gpgpu_num_tensor_core_units; k++) { + m_fu.push_back(new tensor_core(&m_pipeline_reg[EX_WB], m_config, this, k)); m_dispatch_port.push_back(ID_OC_TENSOR_CORE); m_issue_port.push_back(OC_EX_TENSOR_CORE); } - for (int j = 0; j < m_config->m_specialized_unit.size(); j++) { + for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) { for (unsigned k = 0; k < m_config->m_specialized_unit[j].num_units; k++) { m_fu.push_back(new specialized_unit( &m_pipeline_reg[EX_WB], m_config, this, SPEC_UNIT_START_ID + j, m_config->m_specialized_unit[j].name, - m_config->m_specialized_unit[j].latency)); + m_config->m_specialized_unit[j].latency, k)); m_dispatch_port.push_back(m_config->m_specialized_unit[j].ID_OC_SPEC_ID); m_issue_port.push_back(m_config->m_specialized_unit[j].OC_EX_SPEC_ID); } @@ -419,7 +419,7 @@ void shader_core_ctx::create_exec_pipeline() { m_ldst_unit = new ldst_unit(m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, m_config, - m_memory_config, m_stats, m_sid, m_tpc); + m_memory_config, m_stats, m_sid, m_tpc, static_cast(0)); m_fu.push_back(m_ldst_unit); m_dispatch_port.push_back(ID_OC_MEM); m_issue_port.push_back(OC_EX_MEM); @@ -1669,8 +1669,13 @@ void shader_core_ctx::execute() { m_fu[n]->active_lanes_in_pipeline(); unsigned issue_port = m_issue_port[n]; register_set &issue_inst = m_pipeline_reg[issue_port]; - warp_inst_t **ready_reg = issue_inst.get_ready(); - if (issue_inst.has_ready() && m_fu[n]->can_issue(**ready_reg)) { + unsigned reg_id; + bool partition_issue = m_config->sub_core_model && m_fu[n]->is_issue_partitioned(); + if (m_config->sub_core_model) { + reg_id = m_fu[n]->get_issue_reg_id(); + } + warp_inst_t **ready_reg = issue_inst.get_ready(partition_issue, reg_id); + if (issue_inst.has_ready(partition_issue, reg_id) && m_fu[n]->can_issue(**ready_reg)) { bool schedule_wb_now = !m_fu[n]->stallable(); int resbus = -1; if (schedule_wb_now && @@ -2113,16 +2118,17 @@ simd_function_unit::simd_function_unit(const shader_core_config *config) { } sfu::sfu(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core) - : pipelined_simd_unit(result_port, config, config->max_sfu_latency, core) { + shader_core_ctx *core, unsigned issue_reg_id) + : pipelined_simd_unit(result_port, config, config->max_sfu_latency, core, + issue_reg_id) { m_name = "SFU"; } tensor_core::tensor_core(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core) + shader_core_ctx *core, unsigned issue_reg_id) : pipelined_simd_unit(result_port, config, config->max_tensor_core_latency, - core) { + core, issue_reg_id) { m_name = "TENSOR_CORE"; } @@ -2208,29 +2214,29 @@ void tensor_core::active_lanes_in_pipeline() { } sp_unit::sp_unit(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core) - : pipelined_simd_unit(result_port, config, config->max_sp_latency, core) { + shader_core_ctx *core, unsigned issue_reg_id) + : pipelined_simd_unit(result_port, config, config->max_sp_latency, core, issue_reg_id) { m_name = "SP "; } specialized_unit::specialized_unit(register_set *result_port, const shader_core_config *config, shader_core_ctx *core, unsigned supported_op, - char *unit_name, unsigned latency) - : pipelined_simd_unit(result_port, config, latency, core) { + char *unit_name, unsigned latency, unsigned issue_reg_id) + : pipelined_simd_unit(result_port, config, latency, core, issue_reg_id) { m_name = unit_name; m_supported_op = supported_op; } dp_unit::dp_unit(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core) - : pipelined_simd_unit(result_port, config, config->max_dp_latency, core) { + shader_core_ctx *core, unsigned issue_reg_id) + : pipelined_simd_unit(result_port, config, config->max_dp_latency, core, issue_reg_id) { m_name = "DP "; } int_unit::int_unit(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core) - : pipelined_simd_unit(result_port, config, config->max_int_latency, core) { + shader_core_ctx *core, unsigned issue_reg_id) + : pipelined_simd_unit(result_port, config, config->max_int_latency, core, issue_reg_id) { m_name = "INT "; } @@ -2269,7 +2275,8 @@ void int_unit ::issue(register_set &source_reg) { pipelined_simd_unit::pipelined_simd_unit(register_set *result_port, const shader_core_config *config, unsigned max_latency, - shader_core_ctx *core) + shader_core_ctx *core, + unsigned issue_reg_id) : simd_function_unit(config) { m_result_port = result_port; m_pipeline_depth = max_latency; @@ -2277,6 +2284,7 @@ pipelined_simd_unit::pipelined_simd_unit(register_set *result_port, for (unsigned i = 0; i < m_pipeline_depth; i++) m_pipeline_reg[i] = new warp_inst_t(config); m_core = core; + m_issue_reg_id = issue_reg_id; active_insts_in_pipeline = 0; } @@ -2359,8 +2367,8 @@ ldst_unit::ldst_unit(mem_fetch_interface *icnt, shader_core_ctx *core, opndcoll_rfu_t *operand_collector, Scoreboard *scoreboard, const shader_core_config *config, const memory_config *mem_config, shader_core_stats *stats, - unsigned sid, unsigned tpc) - : pipelined_simd_unit(NULL, config, config->smem_latency, core), + unsigned sid, unsigned tpc, unsigned issue_reg_id) + : pipelined_simd_unit(NULL, config, config->smem_latency, core, issue_reg_id), m_next_wb(config) { assert(config->smem_latency > 1); init(icnt, mf_allocator, core, operand_collector, scoreboard, config, @@ -2387,8 +2395,8 @@ ldst_unit::ldst_unit(mem_fetch_interface *icnt, shader_core_ctx *core, opndcoll_rfu_t *operand_collector, Scoreboard *scoreboard, const shader_core_config *config, const memory_config *mem_config, shader_core_stats *stats, - unsigned sid, unsigned tpc, l1_cache *new_l1d_cache) - : pipelined_simd_unit(NULL, config, 3, core), + unsigned sid, unsigned tpc, l1_cache *new_l1d_cache, unsigned issue_reg_id) + : pipelined_simd_unit(NULL, config, 3, core, issue_reg_id), m_L1D(new_l1d_cache), m_next_wb(config) { init(icnt, mf_allocator, core, operand_collector, scoreboard, config, diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 00e7deb..ba37b0c 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1075,7 +1075,7 @@ class pipelined_simd_unit : public simd_function_unit { public: pipelined_simd_unit(register_set *result_port, const shader_core_config *config, unsigned max_latency, - shader_core_ctx *core); + shader_core_ctx *core, unsigned issue_reg_id); // modifiers virtual void cycle(); @@ -1096,6 +1096,7 @@ class pipelined_simd_unit : public simd_function_unit { virtual bool can_issue(const warp_inst_t &inst) const { return simd_function_unit::can_issue(inst); } + unsigned get_issue_reg_id() { return m_issue_reg_id; } virtual void print(FILE *fp) const { simd_function_unit::print(fp); for (int s = m_pipeline_depth - 1; s >= 0; s--) { @@ -1111,6 +1112,8 @@ class pipelined_simd_unit : public simd_function_unit { warp_inst_t **m_pipeline_reg; register_set *m_result_port; class shader_core_ctx *m_core; + unsigned m_issue_reg_id; // if sub_core_model is enabled we can only issue from a + // subset of operand collectors unsigned active_insts_in_pipeline; }; @@ -1118,7 +1121,7 @@ class pipelined_simd_unit : public simd_function_unit { class sfu : public pipelined_simd_unit { public: sfu(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core); + shader_core_ctx *core, unsigned issue_reg_id); virtual bool can_issue(const warp_inst_t &inst) const { switch (inst.op) { case SFU_OP: @@ -1134,12 +1137,13 @@ class sfu : public pipelined_simd_unit { } virtual void active_lanes_in_pipeline(); virtual void issue(register_set &source_reg); + bool is_issue_partitioned() { return true; } }; class dp_unit : public pipelined_simd_unit { public: dp_unit(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core); + shader_core_ctx *core, unsigned issue_reg_id); virtual bool can_issue(const warp_inst_t &inst) const { switch (inst.op) { case DP_OP: @@ -1151,12 +1155,13 @@ class dp_unit : public pipelined_simd_unit { } virtual void active_lanes_in_pipeline(); virtual void issue(register_set &source_reg); + bool is_issue_partitioned() { return true; } }; class tensor_core : public pipelined_simd_unit { public: tensor_core(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core); + shader_core_ctx *core, unsigned issue_reg_id); virtual bool can_issue(const warp_inst_t &inst) const { switch (inst.op) { case TENSOR_CORE_OP: @@ -1168,12 +1173,13 @@ class tensor_core : public pipelined_simd_unit { } virtual void active_lanes_in_pipeline(); virtual void issue(register_set &source_reg); + bool is_issue_partitioned() { return true; } }; class int_unit : public pipelined_simd_unit { public: int_unit(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core); + shader_core_ctx *core, unsigned issue_reg_id); virtual bool can_issue(const warp_inst_t &inst) const { switch (inst.op) { case SFU_OP: @@ -1199,12 +1205,13 @@ class int_unit : public pipelined_simd_unit { } virtual void active_lanes_in_pipeline(); virtual void issue(register_set &source_reg); + bool is_issue_partitioned() { return true; } }; class sp_unit : public pipelined_simd_unit { public: sp_unit(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core); + shader_core_ctx *core, unsigned issue_reg_id); virtual bool can_issue(const warp_inst_t &inst) const { switch (inst.op) { case SFU_OP: @@ -1228,13 +1235,14 @@ class sp_unit : public pipelined_simd_unit { } virtual void active_lanes_in_pipeline(); virtual void issue(register_set &source_reg); + bool is_issue_partitioned() { return true; } }; class specialized_unit : public pipelined_simd_unit { public: specialized_unit(register_set *result_port, const shader_core_config *config, shader_core_ctx *core, unsigned supported_op, - char *unit_name, unsigned latency); + char *unit_name, unsigned latency, unsigned issue_reg_id); virtual bool can_issue(const warp_inst_t &inst) const { if (inst.op != m_supported_op) { return false; @@ -1243,6 +1251,7 @@ class specialized_unit : public pipelined_simd_unit { } virtual void active_lanes_in_pipeline(); virtual void issue(register_set &source_reg); + bool is_issue_partitioned() { return false; } private: unsigned m_supported_op; @@ -1260,10 +1269,11 @@ class ldst_unit : public pipelined_simd_unit { shader_core_ctx *core, opndcoll_rfu_t *operand_collector, Scoreboard *scoreboard, const shader_core_config *config, const memory_config *mem_config, class shader_core_stats *stats, - unsigned sid, unsigned tpc); + unsigned sid, unsigned tpc, unsigned issue_reg_id); // modifiers virtual void issue(register_set &inst); + bool is_issue_partitioned() { return false; } virtual void cycle(); void fill(mem_fetch *mf); -- cgit v1.3 From ec55c68bcdf4406743efa591fcb30e4f467012a0 Mon Sep 17 00:00:00 2001 From: Aaron M Barnes Date: Tue, 11 May 2021 19:30:09 -0400 Subject: minor fixes, pure virtual calls --- src/abstract_hardware_model.h | 4 ++-- src/gpgpu-sim/shader.cc | 16 ++++++++-------- src/gpgpu-sim/shader.h | 7 +++++-- 3 files changed, 15 insertions(+), 12 deletions(-) (limited to 'src/abstract_hardware_model.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 90ae448..6d431fc 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1319,7 +1319,7 @@ class register_set { bool has_ready(bool sub_core_model, unsigned reg_id) { if (!sub_core_model) return has_ready(); assert(reg_id < regs.size()); - return (not regs[reg_id]->empty()) + return (not regs[reg_id]->empty()); } unsigned get_ready_reg_id() { @@ -1388,7 +1388,7 @@ class register_set { warp_inst_t **ready; ready = NULL; assert(reg_id < regs.size()); - if (not regs[reg_id]->empty) + if (not regs[reg_id]->empty()) ready = ®s[reg_id]; return ready; } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 17cf5ba..d98f10a 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -411,7 +411,7 @@ void shader_core_ctx::create_exec_pipeline() { m_fu.push_back(new specialized_unit( &m_pipeline_reg[EX_WB], m_config, this, SPEC_UNIT_START_ID + j, m_config->m_specialized_unit[j].name, - m_config->m_specialized_unit[j].latency, k)); + m_config->m_specialized_unit[j].latency)); m_dispatch_port.push_back(m_config->m_specialized_unit[j].ID_OC_SPEC_ID); m_issue_port.push_back(m_config->m_specialized_unit[j].OC_EX_SPEC_ID); } @@ -419,7 +419,7 @@ void shader_core_ctx::create_exec_pipeline() { m_ldst_unit = new ldst_unit(m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, m_config, - m_memory_config, m_stats, m_sid, m_tpc, static_cast(0)); + m_memory_config, m_stats, m_sid, m_tpc); m_fu.push_back(m_ldst_unit); m_dispatch_port.push_back(ID_OC_MEM); m_issue_port.push_back(OC_EX_MEM); @@ -2222,8 +2222,8 @@ sp_unit::sp_unit(register_set *result_port, const shader_core_config *config, specialized_unit::specialized_unit(register_set *result_port, const shader_core_config *config, shader_core_ctx *core, unsigned supported_op, - char *unit_name, unsigned latency, unsigned issue_reg_id) - : pipelined_simd_unit(result_port, config, latency, core, issue_reg_id) { + char *unit_name, unsigned latency) + : pipelined_simd_unit(result_port, config, latency, core, 0) { m_name = unit_name; m_supported_op = supported_op; } @@ -2367,8 +2367,8 @@ ldst_unit::ldst_unit(mem_fetch_interface *icnt, shader_core_ctx *core, opndcoll_rfu_t *operand_collector, Scoreboard *scoreboard, const shader_core_config *config, const memory_config *mem_config, shader_core_stats *stats, - unsigned sid, unsigned tpc, unsigned issue_reg_id) - : pipelined_simd_unit(NULL, config, config->smem_latency, core, issue_reg_id), + unsigned sid, unsigned tpc) + : pipelined_simd_unit(NULL, config, config->smem_latency, core, 0), m_next_wb(config) { assert(config->smem_latency > 1); init(icnt, mf_allocator, core, operand_collector, scoreboard, config, @@ -2395,8 +2395,8 @@ ldst_unit::ldst_unit(mem_fetch_interface *icnt, shader_core_ctx *core, opndcoll_rfu_t *operand_collector, Scoreboard *scoreboard, const shader_core_config *config, const memory_config *mem_config, shader_core_stats *stats, - unsigned sid, unsigned tpc, l1_cache *new_l1d_cache, unsigned issue_reg_id) - : pipelined_simd_unit(NULL, config, 3, core, issue_reg_id), + unsigned sid, unsigned tpc, l1_cache *new_l1d_cache) + : pipelined_simd_unit(NULL, config, 3, core, 0), m_L1D(new_l1d_cache), m_next_wb(config) { init(icnt, mf_allocator, core, operand_collector, scoreboard, config, diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 5c5e9a4..62abd35 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1053,6 +1053,8 @@ class simd_function_unit { virtual bool can_issue(const warp_inst_t &inst) const { return m_dispatch_reg->empty() && !occupied.test(inst.latency); } + virtual bool is_issue_partitioned() = 0; + virtual unsigned get_issue_reg_id() = 0; virtual bool stallable() const = 0; virtual void print(FILE *fp) const { fprintf(fp, "%s dispatch= ", m_name.c_str()); @@ -1093,6 +1095,7 @@ class pipelined_simd_unit : public simd_function_unit { virtual bool can_issue(const warp_inst_t &inst) const { return simd_function_unit::can_issue(inst); } + virtual bool is_issue_partitioned() = 0; unsigned get_issue_reg_id() { return m_issue_reg_id; } virtual void print(FILE *fp) const { simd_function_unit::print(fp); @@ -1239,7 +1242,7 @@ class specialized_unit : public pipelined_simd_unit { public: specialized_unit(register_set *result_port, const shader_core_config *config, shader_core_ctx *core, unsigned supported_op, - char *unit_name, unsigned latency, unsigned issue_reg_id); + char *unit_name, unsigned latency); virtual bool can_issue(const warp_inst_t &inst) const { if (inst.op != m_supported_op) { return false; @@ -1266,7 +1269,7 @@ class ldst_unit : public pipelined_simd_unit { shader_core_ctx *core, opndcoll_rfu_t *operand_collector, Scoreboard *scoreboard, const shader_core_config *config, const memory_config *mem_config, class shader_core_stats *stats, - unsigned sid, unsigned tpc, unsigned issue_reg_id); + unsigned sid, unsigned tpc); // modifiers virtual void issue(register_set &inst); -- cgit v1.3 From 640674b74b12ef4b0188b267884eda9391f4bf34 Mon Sep 17 00:00:00 2001 From: Aaron Barnes Date: Tue, 11 May 2021 20:25:49 -0400 Subject: issue function needed to be constrained --- src/abstract_hardware_model.h | 5 +++++ src/gpgpu-sim/shader.cc | 12 ++++++------ src/gpgpu-sim/shader.h | 2 +- 3 files changed, 12 insertions(+), 7 deletions(-) (limited to 'src/abstract_hardware_model.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 6d431fc..e9da429 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1367,6 +1367,11 @@ class register_set { warp_inst_t **ready = get_ready(); move_warp(dest, *ready); } + void move_out_to(bool sub_core_model, unsigned reg_id, warp_inst_t *&dest) { + if (!sub_core_model) { return move_out_to(dest);} + warp_inst_t **ready = get_ready(sub_core_model, reg_id); + move_warp(dest, *ready); + } warp_inst_t **get_ready() { warp_inst_t **ready; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index f838ba1..659d159 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2152,7 +2152,7 @@ tensor_core::tensor_core(register_set *result_port, } void sfu::issue(register_set &source_reg) { - warp_inst_t **ready_reg = source_reg.get_ready(); + warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); // m_core->incexecstat((*ready_reg)); (*ready_reg)->op_pipe = SFU__OP; @@ -2161,7 +2161,7 @@ void sfu::issue(register_set &source_reg) { } void tensor_core::issue(register_set &source_reg) { - warp_inst_t **ready_reg = source_reg.get_ready(); + warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); // m_core->incexecstat((*ready_reg)); (*ready_reg)->op_pipe = TENSOR_CORE__OP; @@ -2260,7 +2260,7 @@ int_unit::int_unit(register_set *result_port, const shader_core_config *config, } void sp_unit ::issue(register_set &source_reg) { - warp_inst_t **ready_reg = source_reg.get_ready(); + warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); // m_core->incexecstat((*ready_reg)); (*ready_reg)->op_pipe = SP__OP; m_core->incsp_stat(m_core->get_config()->warp_size, (*ready_reg)->latency); @@ -2268,7 +2268,7 @@ void sp_unit ::issue(register_set &source_reg) { } void dp_unit ::issue(register_set &source_reg) { - warp_inst_t **ready_reg = source_reg.get_ready(); + warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); // m_core->incexecstat((*ready_reg)); (*ready_reg)->op_pipe = DP__OP; m_core->incsp_stat(m_core->get_config()->warp_size, (*ready_reg)->latency); @@ -2284,7 +2284,7 @@ void specialized_unit ::issue(register_set &source_reg) { } void int_unit ::issue(register_set &source_reg) { - warp_inst_t **ready_reg = source_reg.get_ready(); + warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); // m_core->incexecstat((*ready_reg)); (*ready_reg)->op_pipe = INTP__OP; m_core->incsp_stat(m_core->get_config()->warp_size, (*ready_reg)->latency); @@ -2330,7 +2330,7 @@ void pipelined_simd_unit::cycle() { void pipelined_simd_unit::issue(register_set &source_reg) { // move_warp(m_dispatch_reg,source_reg); - warp_inst_t **ready_reg = source_reg.get_ready(); + warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); m_core->incexecstat((*ready_reg)); // source_reg.move_out_to(m_dispatch_reg); simd_function_unit::issue(source_reg); diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 62abd35..2b0c710 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1042,7 +1042,7 @@ class simd_function_unit { // modifiers virtual void issue(register_set &source_reg) { - source_reg.move_out_to(m_dispatch_reg); + source_reg.move_out_to(m_config->sub_core_model, this->get_issue_reg_id(), m_dispatch_reg); occupied.set(m_dispatch_reg->latency); } virtual void cycle() = 0; -- cgit v1.3 From 6ae23912133b158670343da08469747cefef97d1 Mon Sep 17 00:00:00 2001 From: Aaron M Barnes Date: Wed, 12 May 2021 12:53:36 -0400 Subject: fix prints / segfault --- src/abstract_hardware_model.h | 1 + src/gpgpu-sim/shader.cc | 32 +++++++++----------------------- 2 files changed, 10 insertions(+), 23 deletions(-) (limited to 'src/abstract_hardware_model.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index e9da429..129ed69 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1370,6 +1370,7 @@ class register_set { void move_out_to(bool sub_core_model, unsigned reg_id, warp_inst_t *&dest) { if (!sub_core_model) { return move_out_to(dest);} warp_inst_t **ready = get_ready(sub_core_model, reg_id); + assert(ready != NULL); move_warp(dest, *ready); } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 349f954..8816959 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1671,7 +1671,7 @@ void shader_core_ctx::execute() { register_set &issue_inst = m_pipeline_reg[issue_port]; unsigned reg_id; bool partition_issue = m_config->sub_core_model && m_fu[n]->is_issue_partitioned(); - if (m_config->sub_core_model) { + if (partition_issue) { reg_id = m_fu[n]->get_issue_reg_id(); } warp_inst_t **ready_reg = issue_inst.get_ready(partition_issue, reg_id); @@ -1683,28 +1683,10 @@ void shader_core_ctx::execute() { assert((*ready_reg)->latency < MAX_ALU_LATENCY); m_result_bus[resbus]->set((*ready_reg)->latency); m_fu[n]->issue(issue_inst); - warp_inst_t** instr = issue_inst.get_ready(true, reg_id); - std::cout << "EX stage issued warp_id: " - << (*instr)->warp_id() - << " schd_id: " - << (*instr)->get_schd_id() - << " to pipeline: " - << m_fu[n]->get_name() - << " issue reg_id: " - << m_fu[n]->get_issue_reg_id() - << std::endl; + warp_inst_t** instr = issue_inst.get_ready(partition_issue, reg_id); } else if (!schedule_wb_now) { m_fu[n]->issue(issue_inst); - warp_inst_t** instr = issue_inst.get_ready(true, reg_id); - std::cout << "EX stage issued warp_id: " - << (*instr)->warp_id() - << " schd_id: " - << (*instr)->get_schd_id() - << " to pipeline: " - << m_fu[n]->get_name() - << " issue reg_id: " - << m_fu[n]->get_issue_reg_id() - << std::endl; + warp_inst_t** instr = issue_inst.get_ready(partition_issue, reg_id); } else { // stall issue (cannot reserve result bus) } @@ -2138,7 +2120,10 @@ simd_function_unit::simd_function_unit(const shader_core_config *config) { } void simd_function_unit::issue(register_set &source_reg) { - source_reg.move_out_to(m_config->sub_core_model, this->get_issue_reg_id(), m_dispatch_reg); + bool partition_issue = m_config->sub_core_model && this->is_issue_partitioned(); + source_reg.move_out_to(partition_issue, this->get_issue_reg_id(), m_dispatch_reg); + std::cout << "EX stage issue stats:" << std::endl; + this->print(stdout); occupied.set(m_dispatch_reg->latency); } @@ -2336,7 +2321,8 @@ void pipelined_simd_unit::cycle() { void pipelined_simd_unit::issue(register_set &source_reg) { // move_warp(m_dispatch_reg,source_reg); - warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); + bool partition_issue = m_config->sub_core_model && this->is_issue_partitioned(); + warp_inst_t **ready_reg = source_reg.get_ready(partition_issue, m_issue_reg_id); m_core->incexecstat((*ready_reg)); // source_reg.move_out_to(m_dispatch_reg); simd_function_unit::issue(source_reg); -- cgit v1.3 From 92c814a49dc98e282a46031543d289426dc04b00 Mon Sep 17 00:00:00 2001 From: Aaron Barnes Date: Thu, 13 May 2021 10:54:41 -0400 Subject: run changes through clang-format --- src/abstract_hardware_model.h | 32 ++++++------- src/gpgpu-sim/shader.cc | 104 ++++++++++++++++++++++++------------------ src/gpgpu-sim/shader.h | 20 ++++---- 3 files changed, 87 insertions(+), 69 deletions(-) (limited to 'src/abstract_hardware_model.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 129ed69..982e416 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1291,7 +1291,7 @@ class register_set { } m_name = name; } - const char * get_name() {return m_name;} + const char *get_name() { return m_name; } bool has_free() { for (unsigned i = 0; i < regs.size(); i++) { if (regs[i]->empty()) { @@ -1342,8 +1342,8 @@ class register_set { return reg_id; } unsigned get_schd_id(unsigned reg_id) { - assert(not regs[reg_id]->empty()); - return regs[reg_id]->get_schd_id(); + assert(not regs[reg_id]->empty()); + return regs[reg_id]->get_schd_id(); } void move_in(warp_inst_t *&src) { warp_inst_t **free = get_free(); @@ -1353,14 +1353,14 @@ class register_set { // src->copy_contents_to(*get_free()); //} void move_in(bool sub_core_model, unsigned reg_id, warp_inst_t *&src) { - warp_inst_t **free; - if (!sub_core_model) { - free = get_free(); - } else { - assert(reg_id < regs.size()); - free = get_free(sub_core_model, reg_id); - } - move_warp(*free, src); + warp_inst_t **free; + if (!sub_core_model) { + free = get_free(); + } else { + assert(reg_id < regs.size()); + free = get_free(sub_core_model, reg_id); + } + move_warp(*free, src); } void move_out_to(warp_inst_t *&dest) { @@ -1368,7 +1368,9 @@ class register_set { move_warp(dest, *ready); } void move_out_to(bool sub_core_model, unsigned reg_id, warp_inst_t *&dest) { - if (!sub_core_model) { return move_out_to(dest);} + if (!sub_core_model) { + return move_out_to(dest); + } warp_inst_t **ready = get_ready(sub_core_model, reg_id); assert(ready != NULL); move_warp(dest, *ready); @@ -1389,13 +1391,11 @@ class register_set { return ready; } warp_inst_t **get_ready(bool sub_core_model, unsigned reg_id) { - if (!sub_core_model) - return get_ready(); + if (!sub_core_model) return get_ready(); warp_inst_t **ready; ready = NULL; assert(reg_id < regs.size()); - if (not regs[reg_id]->empty()) - ready = ®s[reg_id]; + if (not regs[reg_id]->empty()) ready = ®s[reg_id]; return ready; } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 3059b51..e84e38d 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -166,18 +166,15 @@ void shader_core_ctx::create_schedulers() { // must currently occur after all inputs have been initialized. std::string sched_config = m_config->gpgpu_scheduler_string; const concrete_scheduler scheduler = - sched_config.find("lrr") != std::string::npos - ? CONCRETE_SCHEDULER_LRR - : sched_config.find("two_level_active") != std::string::npos - ? CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE - : sched_config.find("gto") != std::string::npos - ? CONCRETE_SCHEDULER_GTO - : sched_config.find("old") != std::string::npos - ? CONCRETE_SCHEDULER_OLDEST_FIRST - : sched_config.find("warp_limiting") != - std::string::npos - ? CONCRETE_SCHEDULER_WARP_LIMITING - : NUM_CONCRETE_SCHEDULERS; + sched_config.find("lrr") != std::string::npos ? CONCRETE_SCHEDULER_LRR + : sched_config.find("two_level_active") != std::string::npos + ? CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE + : sched_config.find("gto") != std::string::npos ? CONCRETE_SCHEDULER_GTO + : sched_config.find("old") != std::string::npos + ? CONCRETE_SCHEDULER_OLDEST_FIRST + : sched_config.find("warp_limiting") != std::string::npos + ? CONCRETE_SCHEDULER_WARP_LIMITING + : NUM_CONCRETE_SCHEDULERS; assert(scheduler != NUM_CONCRETE_SCHEDULERS); for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++) { @@ -1670,12 +1667,14 @@ void shader_core_ctx::execute() { unsigned issue_port = m_issue_port[n]; register_set &issue_inst = m_pipeline_reg[issue_port]; unsigned reg_id; - bool partition_issue = m_config->sub_core_model && m_fu[n]->is_issue_partitioned(); + bool partition_issue = + m_config->sub_core_model && m_fu[n]->is_issue_partitioned(); if (partition_issue) { reg_id = m_fu[n]->get_issue_reg_id(); } warp_inst_t **ready_reg = issue_inst.get_ready(partition_issue, reg_id); - if (issue_inst.has_ready(partition_issue, reg_id) && m_fu[n]->can_issue(**ready_reg)) { + if (issue_inst.has_ready(partition_issue, reg_id) && + m_fu[n]->can_issue(**ready_reg)) { bool schedule_wb_now = !m_fu[n]->stallable(); int resbus = -1; if (schedule_wb_now && @@ -1685,7 +1684,7 @@ void shader_core_ctx::execute() { m_fu[n]->issue(issue_inst); } else if (!schedule_wb_now) { m_fu[n]->issue(issue_inst); - } else { + } else { // stall issue (cannot reserve result bus) } } @@ -2118,15 +2117,17 @@ simd_function_unit::simd_function_unit(const shader_core_config *config) { } void simd_function_unit::issue(register_set &source_reg) { - bool partition_issue = m_config->sub_core_model && this->is_issue_partitioned(); - source_reg.move_out_to(partition_issue, this->get_issue_reg_id(), m_dispatch_reg); - occupied.set(m_dispatch_reg->latency); - } + bool partition_issue = + m_config->sub_core_model && this->is_issue_partitioned(); + source_reg.move_out_to(partition_issue, this->get_issue_reg_id(), + m_dispatch_reg); + occupied.set(m_dispatch_reg->latency); +} sfu::sfu(register_set *result_port, const shader_core_config *config, shader_core_ctx *core, unsigned issue_reg_id) : pipelined_simd_unit(result_port, config, config->max_sfu_latency, core, - issue_reg_id) { + issue_reg_id) { m_name = "SFU"; } @@ -2139,7 +2140,8 @@ tensor_core::tensor_core(register_set *result_port, } void sfu::issue(register_set &source_reg) { - warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); + warp_inst_t **ready_reg = + source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); // m_core->incexecstat((*ready_reg)); (*ready_reg)->op_pipe = SFU__OP; @@ -2148,7 +2150,8 @@ void sfu::issue(register_set &source_reg) { } void tensor_core::issue(register_set &source_reg) { - warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); + warp_inst_t **ready_reg = + source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); // m_core->incexecstat((*ready_reg)); (*ready_reg)->op_pipe = TENSOR_CORE__OP; @@ -2221,14 +2224,16 @@ void tensor_core::active_lanes_in_pipeline() { sp_unit::sp_unit(register_set *result_port, const shader_core_config *config, shader_core_ctx *core, unsigned issue_reg_id) - : pipelined_simd_unit(result_port, config, config->max_sp_latency, core, issue_reg_id) { + : pipelined_simd_unit(result_port, config, config->max_sp_latency, core, + issue_reg_id) { m_name = "SP "; } specialized_unit::specialized_unit(register_set *result_port, const shader_core_config *config, shader_core_ctx *core, unsigned supported_op, - char *unit_name, unsigned latency, unsigned issue_reg_id) + char *unit_name, unsigned latency, + unsigned issue_reg_id) : pipelined_simd_unit(result_port, config, latency, core, issue_reg_id) { m_name = unit_name; m_supported_op = supported_op; @@ -2236,18 +2241,21 @@ specialized_unit::specialized_unit(register_set *result_port, dp_unit::dp_unit(register_set *result_port, const shader_core_config *config, shader_core_ctx *core, unsigned issue_reg_id) - : pipelined_simd_unit(result_port, config, config->max_dp_latency, core, issue_reg_id) { + : pipelined_simd_unit(result_port, config, config->max_dp_latency, core, + issue_reg_id) { m_name = "DP "; } int_unit::int_unit(register_set *result_port, const shader_core_config *config, shader_core_ctx *core, unsigned issue_reg_id) - : pipelined_simd_unit(result_port, config, config->max_int_latency, core, issue_reg_id) { + : pipelined_simd_unit(result_port, config, config->max_int_latency, core, + issue_reg_id) { m_name = "INT "; } void sp_unit ::issue(register_set &source_reg) { - warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); + warp_inst_t **ready_reg = + source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); // m_core->incexecstat((*ready_reg)); (*ready_reg)->op_pipe = SP__OP; m_core->incsp_stat(m_core->get_config()->warp_size, (*ready_reg)->latency); @@ -2255,7 +2263,8 @@ void sp_unit ::issue(register_set &source_reg) { } void dp_unit ::issue(register_set &source_reg) { - warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); + warp_inst_t **ready_reg = + source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); // m_core->incexecstat((*ready_reg)); (*ready_reg)->op_pipe = DP__OP; m_core->incsp_stat(m_core->get_config()->warp_size, (*ready_reg)->latency); @@ -2271,7 +2280,8 @@ void specialized_unit ::issue(register_set &source_reg) { } void int_unit ::issue(register_set &source_reg) { - warp_inst_t **ready_reg = source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); + warp_inst_t **ready_reg = + source_reg.get_ready(m_config->sub_core_model, m_issue_reg_id); // m_core->incexecstat((*ready_reg)); (*ready_reg)->op_pipe = INTP__OP; m_core->incsp_stat(m_core->get_config()->warp_size, (*ready_reg)->latency); @@ -2317,8 +2327,10 @@ void pipelined_simd_unit::cycle() { void pipelined_simd_unit::issue(register_set &source_reg) { // move_warp(m_dispatch_reg,source_reg); - bool partition_issue = m_config->sub_core_model && this->is_issue_partitioned(); - warp_inst_t **ready_reg = source_reg.get_ready(partition_issue, m_issue_reg_id); + bool partition_issue = + m_config->sub_core_model && this->is_issue_partitioned(); + warp_inst_t **ready_reg = + source_reg.get_ready(partition_issue, m_issue_reg_id); m_core->incexecstat((*ready_reg)); // source_reg.move_out_to(m_dispatch_reg); simd_function_unit::issue(source_reg); @@ -3886,7 +3898,8 @@ void opndcoll_rfu_t::init(unsigned num_banks, shader_core_ctx *shader) { unsigned reg_id; if (sub_core_model) { assert(num_banks % shader->get_config()->gpgpu_num_sched_per_core == 0); - assert(m_num_warp_scheds <= m_cu.size() && m_cu.size() % m_num_warp_scheds == 0); + assert(m_num_warp_scheds <= m_cu.size() && + m_cu.size() % m_num_warp_scheds == 0); } m_num_banks_per_sched = num_banks / shader->get_config()->gpgpu_num_sched_per_core; @@ -3999,11 +4012,13 @@ void opndcoll_rfu_t::allocate_cu(unsigned port_num) { unsigned cuLowerBound = 0; unsigned cuUpperBound = cu_set.size(); unsigned schd_id; - if(sub_core_model) { - // Sub core model only allocates on the subset of CUs assigned to the scheduler that issued + if (sub_core_model) { + // Sub core model only allocates on the subset of CUs assigned to the + // scheduler that issued unsigned reg_id = (*inp.m_in[i]).get_ready_reg_id(); schd_id = (*inp.m_in[i]).get_schd_id(reg_id); - assert(cu_set.size() % m_num_warp_scheds == 0 && cu_set.size() >= m_num_warp_scheds); + assert(cu_set.size() % m_num_warp_scheds == 0 && + cu_set.size() >= m_num_warp_scheds); unsigned cusPerSched = cu_set.size() / m_num_warp_scheds; cuLowerBound = schd_id * cusPerSched; cuUpperBound = cuLowerBound + cusPerSched; @@ -4019,8 +4034,9 @@ void opndcoll_rfu_t::allocate_cu(unsigned port_num) { } if (allocated) break; // cu has been allocated, no need to search more. } - //break; // can only service a single input, if it failed it will fail for - // others. + // break; // can only service a single input, if it failed it will fail + // for + // others. } } } @@ -4067,7 +4083,8 @@ void opndcoll_rfu_t::allocate_reads() { } bool opndcoll_rfu_t::collector_unit_t::ready() const { - return (!m_free) && m_not_ready.none() && (*m_output_register).has_free(m_sub_core_model, m_reg_id); + return (!m_free) && m_not_ready.none() && + (*m_output_register).has_free(m_sub_core_model, m_reg_id); } void opndcoll_rfu_t::collector_unit_t::dump( @@ -4085,13 +4102,10 @@ void opndcoll_rfu_t::collector_unit_t::dump( } } -void opndcoll_rfu_t::collector_unit_t::init(unsigned n, unsigned num_banks, - unsigned log2_warp_size, - const core_config *config, - opndcoll_rfu_t *rfu, - bool sub_core_model, - unsigned reg_id, - unsigned banks_per_sched) { +void opndcoll_rfu_t::collector_unit_t::init( + unsigned n, unsigned num_banks, unsigned log2_warp_size, + const core_config *config, opndcoll_rfu_t *rfu, bool sub_core_model, + unsigned reg_id, unsigned banks_per_sched) { m_rfu = rfu; m_cuid = n; m_num_banks = num_banks; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index fa71af3..8c02fd7 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -238,7 +238,10 @@ class shd_warp_t { unsigned get_dynamic_warp_id() const { return m_dynamic_warp_id; } unsigned get_warp_id() const { return m_warp_id; } - class shader_core_ctx * get_shader() { return m_shader; } + class shader_core_ctx *get_shader() { + return m_shader; + } + private: static const unsigned IBUFFER_SIZE = 2; class shader_core_ctx *m_shader; @@ -883,7 +886,8 @@ class opndcoll_rfu_t { // operand collector based register file unit // modifiers void init(unsigned n, unsigned num_banks, unsigned log2_warp_size, const core_config *config, opndcoll_rfu_t *rfu, - bool m_sub_core_model, unsigned reg_id, unsigned num_banks_per_sched); + bool m_sub_core_model, unsigned reg_id, + unsigned num_banks_per_sched); bool allocate(register_set *pipeline_reg, register_set *output_reg); void collect_operand(unsigned op) { m_not_ready.reset(op); } @@ -907,7 +911,7 @@ class opndcoll_rfu_t { // operand collector based register file unit unsigned m_num_banks_per_sched; bool m_sub_core_model; - unsigned m_reg_id; // if sub_core_model enabled, limit regs this cu can r/w + unsigned m_reg_id; // if sub_core_model enabled, limit regs this cu can r/w }; class dispatch_unit_t { @@ -1051,7 +1055,7 @@ class simd_function_unit { return m_dispatch_reg->empty() && !occupied.test(inst.latency); } virtual bool is_issue_partitioned() = 0; - virtual unsigned get_issue_reg_id() = 0; + virtual unsigned get_issue_reg_id() = 0; virtual bool stallable() const = 0; virtual void print(FILE *fp) const { fprintf(fp, "%s dispatch= ", m_name.c_str()); @@ -1109,8 +1113,8 @@ class pipelined_simd_unit : public simd_function_unit { warp_inst_t **m_pipeline_reg; register_set *m_result_port; class shader_core_ctx *m_core; - unsigned m_issue_reg_id; // if sub_core_model is enabled we can only issue from a - // subset of operand collectors + unsigned m_issue_reg_id; // if sub_core_model is enabled we can only issue + // from a subset of operand collectors unsigned active_insts_in_pipeline; }; @@ -2145,8 +2149,8 @@ class shader_core_ctx : public core_t { friend class TwoLevelScheduler; friend class LooseRoundRobbinScheduler; virtual void issue_warp(register_set &warp, const warp_inst_t *pI, - const active_mask_t &active_mask, unsigned warp_id, - unsigned sch_id); + const active_mask_t &active_mask, unsigned warp_id, + unsigned sch_id); void create_front_pipeline(); void create_schedulers(); -- cgit v1.3