From b0cf792926caf74b393a14e36de676c7afd68164 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Tue, 12 Oct 2010 00:46:24 -0800 Subject: 1. adding simt_core_cluster, which models a TPC or (for fermi) GPC... this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845] --- src/abstract_hardware_model.h | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) (limited to 'src/abstract_hardware_model.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 41fe025..b94aa48 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -480,6 +480,13 @@ struct shader_core_config unsigned null_bank_func(address_type, unsigned) const { return 1; } unsigned shmem_bank_func(address_type addr, unsigned) const; unsigned dcache_bank_func(address_type add, unsigned line_size) const; + + unsigned n_simt_cores_per_cluster; + unsigned n_simt_clusters; + unsigned n_simt_ejection_buffer_size; + unsigned ldst_unit_response_queue_size; + + unsigned mem2device(unsigned memid) const { return memid + n_simt_clusters; } }; typedef unsigned (shader_core_config::*bank_func_t)(address_type add, unsigned line_size) const; @@ -488,14 +495,22 @@ typedef address_type (*tag_func_t)(address_type add, unsigned line_size); class warp_inst_t: public inst_t { public: // constructors + warp_inst_t() + { + m_uid=0; + m_empty=true; + m_config=NULL; + } warp_inst_t( const struct shader_core_config *config ) { + m_uid=0; assert(config->warp_size<=MAX_WARP_SIZE); m_config=config; m_empty=true; m_isatomic=false; m_per_scalar_thread_valid=false; m_mem_accesses_created=false; + m_cache_hit=false; } // modifiers @@ -519,9 +534,11 @@ public: if( mask & (1< &inactive ) + { + std::vector::iterator i; + for(i=inactive.begin(); i!=inactive.end();i++) { + unsigned t=*i; + warp_active_mask.reset(t); + } + } void set_not_active( unsigned lane_id ) { warp_active_mask.reset(lane_id); @@ -618,7 +643,9 @@ public: void print( FILE *fout ) const; protected: + unsigned m_uid; bool m_empty; + bool m_cache_hit; unsigned long long issue_cycle; unsigned cycles; // used for implementing initiation interval delay bool m_isatomic; @@ -628,17 +655,17 @@ protected: struct per_thread_info { per_thread_info() { - cache_miss=false; memreqaddr=0; } dram_callback_t callback; new_addr_type memreqaddr; // effective address - bool cache_miss; }; bool m_per_scalar_thread_valid; std::vector m_per_scalar_thread; bool m_mem_accesses_created; std::vector m_accessq; + + static unsigned sm_next_uid; }; void move_warp( warp_inst_t *&dst, warp_inst_t *&src ); -- cgit v1.3