From 35cf76f383ec8de6de901bbbcd8fb478f69e46e4 Mon Sep 17 00:00:00 2001 From: sspenst Date: Wed, 6 Jul 2016 13:56:52 -0700 Subject: Added sstarr memory, which works the same as shared memory --- src/cuda-sim/cuda-sim.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/cuda-sim/cuda-sim.cc') diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 09e9a81..57da23f 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1407,6 +1407,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, std::list &active_threads = kernel.active_threads(); static std::map shared_memory_lookup; + static std::map sstarr_memory_lookup; static std::map ptx_cta_lookup; static std::map > local_memory_lookup; @@ -1450,6 +1451,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, //initializing new CTA ptx_cta_info *cta_info = NULL; memory_space *shared_mem = NULL; + memory_space *sstarr_mem = NULL; unsigned cta_size = kernel.threads_per_cta(); unsigned max_cta_per_sm = num_threads/cta_size; // e.g., 256 / 48 = 5 @@ -1466,6 +1468,9 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, snprintf(buf,512,"shared_%u", sid); shared_mem = new memory_space_impl<16*1024>(buf,4); shared_memory_lookup[sm_idx] = shared_mem; + snprintf(buf,512,"sstarr_%u", sid); + sstarr_mem = new memory_space_impl<16*1024>(buf,4); + sstarr_memory_lookup[sm_idx] = sstarr_mem; cta_info = new ptx_cta_info(sm_idx); ptx_cta_lookup[sm_idx] = cta_info; } else { @@ -1474,6 +1479,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, sm_idx, sid, max_cta_per_sm ); } shared_mem = shared_memory_lookup[sm_idx]; + sstarr_mem = sstarr_memory_lookup[sm_idx]; cta_info = ptx_cta_lookup[sm_idx]; cta_info->check_cta_thread_status_and_reset(); } @@ -1506,9 +1512,11 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, thd->cpy_tid_to_reg(tid3d); thd->set_valid(); thd->m_shared_mem = shared_mem; + thd->m_sstarr_mem = sstarr_mem; function_info *finfo = thd->func_info(); symbol_table *st = finfo->get_symtab(); thd->func_info()->param_to_shared(thd->m_shared_mem,st); + thd->func_info()->param_to_shared(thd->m_sstarr_mem,st); thd->m_cta_info = cta_info; cta_info->add_thread(thd); thd->m_local_mem = local_mem; -- cgit v1.3 From 877cbd077ffaf112b68973fdb7db8f10505303ee Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 8 Jul 2016 12:57:56 -0700 Subject: SST should now properly simulate the barrier operation --- src/cuda-sim/cuda-sim.cc | 4 ++++ src/cuda-sim/instructions.cc | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'src/cuda-sim/cuda-sim.cc') diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 57da23f..e194a2a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -572,6 +572,9 @@ void ptx_instruction::set_bar_type() abort(); } } + else if(m_opcode==SST_OP) { + bar_type = SYNC; + } } @@ -635,6 +638,7 @@ void ptx_instruction::set_opcode_and_latency() case TEX_OP: op = LOAD_OP; mem_op=TEX; break; case ATOM_OP: op = LOAD_OP; break; case BAR_OP: op = BARRIER_OP; break; + case SST_OP: op = BARRIER_OP; break; case MEMBAR_OP: op = MEMORY_BARRIER_OP; break; case CALL_OP: { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index aeaf9e6..8bdb94f 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3741,7 +3741,8 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { - const operand_info &dst = pI->dst(); + ptx_instruction * cpI = const_cast(pI); // constant + const operand_info &dst = cpI->dst(); const operand_info &src1 = pI->src1(); const operand_info &src2 = pI->src2(); const operand_info &src3 = pI->src3(); @@ -3763,8 +3764,13 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) // store data in sstarr memory mem->write(addr,size/8,&src3_data.s64,thread,pI); + // sync threads + cpI->set_bar_id(dst_data.u32); + thread->m_last_effective_address = addr; thread->m_last_memory_space = space; + thread->m_last_dram_callback.function = bar_callback; + thread->m_last_dram_callback.instruction = cpI; int NUM_THREADS = 8; // (how do you get this dynamically?) if (src2_data.s64 == NUM_THREADS-1) { -- cgit v1.3 From feda07a5e0053ef2f2bfa382f5ba9a7a0b6c6bf5 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 4 Aug 2016 13:09:41 -0700 Subject: A thread executing BSMAD is now able to access information from all threads in its warp --- src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 14 ++++ src/cuda-sim/instructions.cc | 158 ++++++++++++++++++++++++++++++++++++++++++ src/cuda-sim/opcodes.def | 3 + src/cuda-sim/opcodes.h | 4 +- src/cuda-sim/ptx.l | 3 + 6 files changed, 182 insertions(+), 1 deletion(-) (limited to 'src/cuda-sim/cuda-sim.cc') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 6ed9b8e..13dfce3 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1053,6 +1053,7 @@ class core_t { warp_inst_t getExecuteWarp(unsigned warpId); void get_pdom_stack_top_info( unsigned warpId, unsigned *pc, unsigned *rpc ) const; kernel_info_t * get_kernel_info(){ return m_kernel;} + class ptx_thread_info ** get_thread_info() { return m_thread; } unsigned get_warp_size() const { return m_warp_size; } void and_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] &= value; } void or_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] |= value; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index e194a2a..059fbe2 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -849,8 +849,10 @@ void ptx_instruction::pre_decode() switch ( get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF default: printf( "Execution error: Invalid opcode (0x%x)\n", get_opcode() ); break; @@ -1242,10 +1244,22 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) *((warp_inst_t*)pJ) = inst; // copy active mask information pI = pJ; } + /*const ptx_instruction **pA; + if( pI->get_opcode() == BSMAD_OP ) { + //pA = (const ptx_instruction**)malloc(get_core()->get_warp_size()*(sizeof(ptx_instruction*))); + pA = (const ptx_instruction**)malloc(8*(sizeof(ptx_instruction*))); + for (int i = 0; i < get_core()->get_warp_size() && inst.active(i); i++) { + //pA[i] = get_core()->get_thread_info()[inst.warp_id() * get_core()->get_warp_size() + i]->func_info()->get_instruction(pc+(i-lane_id)*(pI->inst_size())); + int tid = inst.warp_id() * get_core()->get_warp_size() + i; + pA[i] = get_core()->get_thread_info()[tid]->func_info()->get_instruction(pc); + } + }*/ switch ( pI->get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break; } delete pJ; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index b401bef..618add1 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -47,8 +47,10 @@ unsigned ptx_instruction::g_num_ptx_inst_uid=0; const char *g_opcode_string[NUM_OPCODES] = { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF }; void inst_not_implemented( const ptx_instruction * pI ) ; @@ -1456,6 +1458,162 @@ void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +{ + for (int i = 0; i < core->get_warp_size() && inst.active(i); i++) { + const operand_info &dst = pI->dst(); + unsigned type = pI->get_type(); + + int tid = inst.warp_id() * core->get_warp_size() + i; + ptx_thread_info *thread = core->get_thread_info()[tid]; + ptx_reg_t data = thread->get_operand_value(dst, dst, type, thread, 1); + printf("BSMAD - DATA FROM THREAD %d: %d\n", i, data.u32); + } + printf("\n"); + /*const unsigned OPERANDS = 9; + // 0 = output + // 1 = input precision + // 2 = output precision + // 3 = buffer0 + // 4 = buffer1 + // 5 = buffer2 + // 6 = buffer3 + // 7 = synapse value + // 8 = output value + // as a temporary solution, let 0 be the base address of output, which is an array of shared memory + // that will be filled when the last thread completes the bsmad instruction + // maybe you can store the addresses of other ptx_instruction in sstarr memory and then update dst later? + // not sure if that works + + //ptx_instruction * cpI = const_cast(pI); + const operand_info &src[OPERANDS]; + ptx_reg_t src_data[OPERANDS]; + unsigned type = pI->get_type(); + + for (int i = 0; i < OPERANDS; i++) { + src[i] = pI->operand_lookup(i); + src_data[i] = thread->get_operand_value(src[i], src[0], type, thread, 1); + } + + memory_space_t space = pI->get_space(); + memory_space *mem = NULL; + addr_t addr = thread->get_tid().x * 24; // 4 bytes per register * 6 registers per thread = 24 bytes + + decode_space(space,thread,src[0],mem,addr); + + size_t size; + int t; + type_info_key::type_decode(type,size,t); + + // store src_data[1:4] in sstarr memory + for (int i = 0; i < 6; i++) { + mem->write(addr + i*4,size/8,&src_data[i+3].s64,thread,pI); + } + + // sync threads + //cpI->set_bar_id(16); // use 16 for sst because bar uses an int from 0-15 + + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; + thread->m_last_dram_callback.function = bar_callback; + thread->m_last_dram_callback.instruction = cpI; + + // the last thread that executes loads all of the data back from sstarr memory + ptx_cta_info *cta_info = thread->m_cta_info;((32/ip)*4)/(32/op) + const int NUM_THREADS = cta_info->num_threads(); + cta_info->inc_bar_threads(); + if (NUM_THREADS == cta_info->get_bar_threads()) { + // load all things from sstarr memory + addr = 0; + ptx_reg_t data; + unsigned sstarr_data[NUM_THREADS*6]; + for (int i = 0; i < NUM_THREADS*6; i++) { + data.u64 = 0; + mem->read(addr+(i*4),size/8,&data.s64); + sstarr_data[i] = data.u32; + } + + // unpack registers, add data from across threads + unsigned ip = src_data[1].u32; + unsigned op = src_data[2].u32; + unsigned unpacked_output[(32/ip)*4]; + + for (unsigned i = 0; i < (32/ip)*4; i++) { + unsigned buf = i/(32/ip); + unsigned pos = i%(32/ip); + + unsigned mask = 0; + for (int b = 0; b < ip; b++) { + mask |= (1 << b); + } + mask <<= (pos*ip); + + int sum = 0; + for (int j = 0; j < NUM_THREADS; j++) { + sum += mask & sstarr_data[j*6 + buf]; + } + unpacked_output[i] = sum; + } + + // truncate result, repack, store in shared mem + unsigned output_regs[((32/ip)*4)/(32/op) + (((32/ip)*4)%(32/op) != 0)]; + + + + unsigned offset = 0; + addr = 0; + ptx_reg_t data; + float sstarr_fdata[NUM_THREADS]; + signed long long sstarr_ldata[NUM_THREADS]; + // loop through all of the threads + for (int tid = 0; tid < NUM_THREADS; tid++) { + data.u64=0; + mem->read(addr+(tid*4),size/8,&data.s64); + sstarr_fdata[tid] = data.f32; + sstarr_ldata[tid] = data.s64; + } + + // squeeze the zeros out of the array and store data back into original array + mem = NULL; + addr = src1_data.u32; + space.set_type(global_space); + decode_space(space,thread,src1,mem,addr); + // store nonzero entries and indices + for (int tid = 0; tid < NUM_THREADS; tid++) { + if (sstarr_fdata[tid] != 0) { + float ftid = (float)tid; + mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI); + mem->write(addr+((NUM_THREADS+offset)*4),size/8,&ftid,thread,pI); + offset++; + } + } + // store the number of nonzero elements in the array + data = thread->get_op((32/ip)*4)/(32/op)erand_value(src1, dst, type, thread, 1); + data.s64 += 4*(offset-1); + thread->set_operand_value(dst, data, type, thread, pI); + + // fill the rest of the array with zeros (dst should always have a 0 in it) + while (offset < NUM_THREADS) { + mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); + offset++; + } + + cta_info->reset_bar_threads(); + thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; + thread->m_last_memory_space = space; + }*/ +} + +void bsmul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("BSMUL instruction found.\n"); +} + +void buf_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("BUF instruction found.\n"); +} + void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { static unsigned call_uid_next = 1; diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 1af04ea..d0e6f25 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -52,6 +52,9 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3) OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) +OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1) +OP_DEF(BSMUL_OP,bsmul_impl,"bsmul",1,1) +OP_DEF(BUF_OP,buf_impl,"buf",0,5) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) diff --git a/src/cuda-sim/opcodes.h b/src/cuda-sim/opcodes.h index 871091c..aa133da 100644 --- a/src/cuda-sim/opcodes.h +++ b/src/cuda-sim/opcodes.h @@ -30,9 +30,11 @@ enum opcode_t { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP, +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP, #include "opcodes.def" - NUM_OPCODES + NUM_OPCODES #undef OP_DEF +#undef OP_W_DEF }; enum special_regs { diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 69349a0..e0d7b9d 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -68,6 +68,9 @@ bra TC; ptx_lval.int_value = BRA_OP; return OPCODE; brx TC; ptx_lval.int_value = BRX_OP; return OPCODE; brev TC; ptx_lval.int_value = BREV_OP; return OPCODE; brkpt TC; ptx_lval.int_value = BRKPT_OP; return OPCODE; +bsmad TC; ptx_lval.int_value = BSMAD_OP; return OPCODE; +bsmul TC; ptx_lval.int_value = BSMUL_OP; return OPCODE; +buf TC; ptx_lval.int_value = BUF_OP; return OPCODE; call TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode callp TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE; clz TC; ptx_lval.int_value = CLZ_OP; return OPCODE; -- cgit v1.3 From 9a6b68c5b11fbdb239d25afe60e5135bc2afa88d Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 5 Aug 2016 10:16:29 -0700 Subject: bsmad gives the correct output in the small cases I have tried, still need to complete the TODOs noted in bsmad_impl --- src/cuda-sim/cuda-sim.cc | 10 -- src/cuda-sim/instructions.cc | 211 +++++++++++++++++++------------------------ src/cuda-sim/opcodes.def | 2 - src/cuda-sim/ptx.l | 2 - 4 files changed, 95 insertions(+), 130 deletions(-) (limited to 'src/cuda-sim/cuda-sim.cc') diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 059fbe2..337463b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1244,16 +1244,6 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) *((warp_inst_t*)pJ) = inst; // copy active mask information pI = pJ; } - /*const ptx_instruction **pA; - if( pI->get_opcode() == BSMAD_OP ) { - //pA = (const ptx_instruction**)malloc(get_core()->get_warp_size()*(sizeof(ptx_instruction*))); - pA = (const ptx_instruction**)malloc(8*(sizeof(ptx_instruction*))); - for (int i = 0; i < get_core()->get_warp_size() && inst.active(i); i++) { - //pA[i] = get_core()->get_thread_info()[inst.warp_id() * get_core()->get_warp_size() + i]->func_info()->get_instruction(pc+(i-lane_id)*(pI->inst_size())); - int tid = inst.warp_id() * get_core()->get_warp_size() + i; - pA[i] = get_core()->get_thread_info()[tid]->func_info()->get_instruction(pc); - } - }*/ switch ( pI->get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 618add1..f58c4f5 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1460,17 +1460,7 @@ void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { - for (int i = 0; i < core->get_warp_size() && inst.active(i); i++) { - const operand_info &dst = pI->dst(); - unsigned type = pI->get_type(); - - int tid = inst.warp_id() * core->get_warp_size() + i; - ptx_thread_info *thread = core->get_thread_info()[tid]; - ptx_reg_t data = thread->get_operand_value(dst, dst, type, thread, 1); - printf("BSMAD - DATA FROM THREAD %d: %d\n", i, data.u32); - } - printf("\n"); - /*const unsigned OPERANDS = 9; + // operands: // 0 = output // 1 = input precision // 2 = output precision @@ -1480,65 +1470,61 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) // 6 = buffer3 // 7 = synapse value // 8 = output value - // as a temporary solution, let 0 be the base address of output, which is an array of shared memory - // that will be filled when the last thread completes the bsmad instruction - // maybe you can store the addresses of other ptx_instruction in sstarr memory and then update dst later? - // not sure if that works - - //ptx_instruction * cpI = const_cast(pI); - const operand_info &src[OPERANDS]; - ptx_reg_t src_data[OPERANDS]; - unsigned type = pI->get_type(); - - for (int i = 0; i < OPERANDS; i++) { - src[i] = pI->operand_lookup(i); - src_data[i] = thread->get_operand_value(src[i], src[0], type, thread, 1); - } - - memory_space_t space = pI->get_space(); - memory_space *mem = NULL; - addr_t addr = thread->get_tid().x * 24; // 4 bytes per register * 6 registers per thread = 24 bytes - - decode_space(space,thread,src[0],mem,addr); - - size_t size; - int t; - type_info_key::type_decode(type,size,t); - - // store src_data[1:4] in sstarr memory - for (int i = 0; i < 6; i++) { - mem->write(addr + i*4,size/8,&src_data[i+3].s64,thread,pI); - } - - // sync threads - //cpI->set_bar_id(16); // use 16 for sst because bar uses an int from 0-15 - - thread->m_last_effective_address = addr; - thread->m_last_memory_space = space; - thread->m_last_dram_callback.function = bar_callback; - thread->m_last_dram_callback.instruction = cpI; - // the last thread that executes loads all of the data back from sstarr memory - ptx_cta_info *cta_info = thread->m_cta_info;((32/ip)*4)/(32/op) + // TODO: what should happen when the output precision is larger than the input precision? + // TODO: create a ptx_warp_info that can do the same thing that ptx_cta_info does here + ptx_cta_info *cta_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_cta_info; const int NUM_THREADS = cta_info->num_threads(); + const int NUM_BUFFERS = 4; cta_info->inc_bar_threads(); - if (NUM_THREADS == cta_info->get_bar_threads()) { - // load all things from sstarr memory - addr = 0; - ptx_reg_t data; - unsigned sstarr_data[NUM_THREADS*6]; - for (int i = 0; i < NUM_THREADS*6; i++) { - data.u64 = 0; - mem->read(addr+(i*4),size/8,&data.s64); - sstarr_data[i] = data.u32; - } - // unpack registers, add data from across threads - unsigned ip = src_data[1].u32; - unsigned op = src_data[2].u32; - unsigned unpacked_output[(32/ip)*4]; + // threads within the warp are executed sequentially by the simulator, store output in first four registers + if (cta_info->get_bar_threads() <= NUM_BUFFERS) { + unsigned ip, op; // only get these when i = 0 + unsigned buffer[inst.active_count()][NUM_BUFFERS]; + unsigned synapse[inst.active_count()]; + unsigned output[NUM_BUFFERS]; + + // loop through all threads in the warp and get all data + for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { + if (inst.active(i)) { + const operand_info dst = pI->dst(); + const operand_info src1 = pI->operand_lookup(1); + const operand_info src2 = pI->operand_lookup(2); + const operand_info src3 = pI->operand_lookup(3); + const operand_info src4 = pI->operand_lookup(4); + const operand_info src5 = pI->operand_lookup(5); + const operand_info src6 = pI->operand_lookup(6); + const operand_info src7 = pI->operand_lookup(7); + const operand_info src8 = pI->operand_lookup(8); + unsigned type = pI->get_type(); + + int tid = inst.warp_id() * core->get_warp_size() + i; + ptx_thread_info *thread = core->get_thread_info()[tid]; + + // only get precision data once + if (j == 0) { + ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; + op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; + } + // get buffer data and synapse data from each thread + buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32; + buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32; + buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32; + buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32; + synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32; + // get output data from the first 4 threads + if (j < NUM_BUFFERS) { + output[j] = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; + } + j++; + } + } - for (unsigned i = 0; i < (32/ip)*4; i++) { + // unpack registers, compute enough outputs to fill an output register + unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned)); + unsigned buffer_data_start = (32/op)*(cta_info->get_bar_threads()-1); + for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*NUM_BUFFERS; i++) { unsigned buf = i/(32/ip); unsigned pos = i%(32/ip); @@ -1550,68 +1536,61 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) int sum = 0; for (int j = 0; j < NUM_THREADS; j++) { - sum += mask & sstarr_data[j*6 + buf]; + sum += (mask & buffer[j][buf]) >> (pos*ip); } - unpacked_output[i] = sum; + unpacked_output[i - buffer_data_start] = sum; } - // truncate result, repack, store in shared mem - unsigned output_regs[((32/ip)*4)/(32/op) + (((32/ip)*4)%(32/op) != 0)]; - - + // truncate output + for (unsigned i = 0; i < 32/op; i++) { + int mask = 1, latest_one = -1; + unsigned data = unpacked_output[i]; + for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { + int bit = data & mask; + if (bit == 1) latest_one = j; + data >>= 1; + } + if (latest_one >= op) { + // round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0 + int round_up = (unpacked_output[i] & (1 << (latest_one-op))) >> (latest_one-op); + unsigned shifted_output = unpacked_output[i] >> (latest_one-op+1); + // if shifted_output is a number like 1111, don't round up + if (shifted_output == (pow(2,op)-1)) round_up = 0; + unpacked_output[i] = shifted_output + round_up; + } + } - unsigned offset = 0; - addr = 0; - ptx_reg_t data; - float sstarr_fdata[NUM_THREADS]; - signed long long sstarr_ldata[NUM_THREADS]; - // loop through all of the threads - for (int tid = 0; tid < NUM_THREADS; tid++) { - data.u64=0; - mem->read(addr+(tid*4),size/8,&data.s64); - sstarr_fdata[tid] = data.f32; - sstarr_ldata[tid] = data.s64; + // create mask of 1s + unsigned mask = 0; + for (int b = 0; b < op; b++) { + mask |= (1 << b); } - // squeeze the zeros out of the array and store data back into original array - mem = NULL; - addr = src1_data.u32; - space.set_type(global_space); - decode_space(space,thread,src1,mem,addr); - // store nonzero entries and indices - for (int tid = 0; tid < NUM_THREADS; tid++) { - if (sstarr_fdata[tid] != 0) { - float ftid = (float)tid; - mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI); - mem->write(addr+((NUM_THREADS+offset)*4),size/8,&ftid,thread,pI); - offset++; - } + // pack the outputs into one register + unsigned output_data = 0; + for (int i = 0; i < 32/op; i++) { + output_data |= (unpacked_output[i] & mask) << (op*i); } - // store the number of nonzero elements in the array - data = thread->get_op((32/ip)*4)/(32/op)erand_value(src1, dst, type, thread, 1); - data.s64 += 4*(offset-1); - thread->set_operand_value(dst, data, type, thread, pI); - // fill the rest of the array with zeros (dst should always have a 0 in it) - while (offset < NUM_THREADS) { - mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); - offset++; + // store the result in the correct thread's output register + for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { + if (inst.active(i)) j++; + if (j == cta_info->get_bar_threads()) { + const operand_info &dst = pI->dst(); + unsigned type = pI->get_type(); + int tid = inst.warp_id() * core->get_warp_size() + i; + ptx_thread_info *thread = core->get_thread_info()[tid]; + ptx_reg_t data; + data.u32 = output_data; + thread->set_operand_value(dst, data, type, thread, pI); + break; + } } + } + if (cta_info->get_bar_threads() == NUM_THREADS) { cta_info->reset_bar_threads(); - thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; - thread->m_last_memory_space = space; - }*/ -} - -void bsmul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - printf("BSMUL instruction found.\n"); -} - -void buf_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - printf("BUF instruction found.\n"); + } } void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index d0e6f25..021eed8 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -53,8 +53,6 @@ OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1) -OP_DEF(BSMUL_OP,bsmul_impl,"bsmul",1,1) -OP_DEF(BUF_OP,buf_impl,"buf",0,5) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index e0d7b9d..001ec04 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -69,8 +69,6 @@ brx TC; ptx_lval.int_value = BRX_OP; return OPCODE; brev TC; ptx_lval.int_value = BREV_OP; return OPCODE; brkpt TC; ptx_lval.int_value = BRKPT_OP; return OPCODE; bsmad TC; ptx_lval.int_value = BSMAD_OP; return OPCODE; -bsmul TC; ptx_lval.int_value = BSMUL_OP; return OPCODE; -buf TC; ptx_lval.int_value = BUF_OP; return OPCODE; call TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode callp TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE; clz TC; ptx_lval.int_value = CLZ_OP; return OPCODE; -- cgit v1.3 From d1b45cf53a39261663a3eff0d409d6c1220d923d Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 5 Aug 2016 14:45:56 -0700 Subject: Added ptx_warp_info to know how many threads within a warp have executed --- src/abstract_hardware_model.h | 2 + src/cuda-sim/cuda-sim.cc | 10 +++++ src/cuda-sim/instructions.cc | 95 +++++++++++++++++++++++-------------------- src/cuda-sim/ptx_sim.cc | 21 ++++++++++ src/cuda-sim/ptx_sim.h | 12 ++++++ 5 files changed, 95 insertions(+), 45 deletions(-) (limited to 'src/cuda-sim/cuda-sim.cc') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 13dfce3..cfa8c9f 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1028,6 +1028,7 @@ class core_t { m_warp_count += 1; } assert( m_warp_count * m_warp_size > 0 ); + //m_warp = ( ptx_warp_info** )calloc( m_warp_count, sizeof( ptx_warp_info* ) ); m_thread = ( ptx_thread_info** ) calloc( m_warp_count * m_warp_size, sizeof( ptx_thread_info* ) ); @@ -1063,6 +1064,7 @@ class core_t { class gpgpu_sim *m_gpu; kernel_info_t *m_kernel; simt_stack **m_simt_stack; // pdom based reconvergence context for each warp + //class ptx_warp_info ** m_warp; class ptx_thread_info ** m_thread; unsigned m_warp_size; unsigned m_warp_count; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 337463b..ba0d00b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1417,6 +1417,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, static std::map shared_memory_lookup; static std::map sstarr_memory_lookup; static std::map ptx_cta_lookup; + static std::map ptx_warp_lookup; static std::map > local_memory_lookup; if ( *thread_info != NULL ) { @@ -1501,6 +1502,15 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, new_tid += tid; ptx_thread_info *thd = new ptx_thread_info(kernel); + ptx_warp_info *warp_info = NULL; + if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { + warp_info = new ptx_warp_info(); // num_threads should be threads in the warp + ptx_warp_lookup[hw_warp_id] = warp_info; + } else { + warp_info = ptx_warp_lookup[hw_warp_id]; + } + thd->m_warp_info = warp_info; + memory_space *local_mem = NULL; std::map::iterator l = local_mem_lookup.find(new_tid); if ( l != local_mem_lookup.end() ) { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index f58c4f5..9dcc25c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1471,74 +1471,81 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) // 7 = synapse value // 8 = output value - // TODO: what should happen when the output precision is larger than the input precision? - // TODO: create a ptx_warp_info that can do the same thing that ptx_cta_info does here - ptx_cta_info *cta_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_cta_info; - const int NUM_THREADS = cta_info->num_threads(); - const int NUM_BUFFERS = 4; - cta_info->inc_bar_threads(); + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + unsigned type = pI->get_type(); + int tid = inst.warp_id() * core->get_warp_size(); + ptx_thread_info *thread = core->get_thread_info()[tid]; + const int ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; + const int op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; + const int THREADS = inst.active_count(); + const int INBUFFERS = 4; + const int OUTBUFFERS = (((32/ip)*INBUFFERS) / (32/op)) + ((((32/ip)*INBUFFERS) % (32/op)) != 0); + if (OUTBUFFERS > THREADS) { + printf("GPGPU-Sim PTX: BSMAD ERROR - Number of output registers required (%d) is greater than the number available (%d)\n", OUTBUFFERS, THREADS); + abort(); + } + ptx_warp_info *warp_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_warp_info; + warp_info->inc_done_threads(); // threads within the warp are executed sequentially by the simulator, store output in first four registers - if (cta_info->get_bar_threads() <= NUM_BUFFERS) { - unsigned ip, op; // only get these when i = 0 - unsigned buffer[inst.active_count()][NUM_BUFFERS]; + if (warp_info->get_done_threads() <= OUTBUFFERS) { + unsigned buffer[inst.active_count()][INBUFFERS]; unsigned synapse[inst.active_count()]; - unsigned output[NUM_BUFFERS]; + unsigned output; // loop through all threads in the warp and get all data for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { if (inst.active(i)) { - const operand_info dst = pI->dst(); - const operand_info src1 = pI->operand_lookup(1); - const operand_info src2 = pI->operand_lookup(2); - const operand_info src3 = pI->operand_lookup(3); - const operand_info src4 = pI->operand_lookup(4); - const operand_info src5 = pI->operand_lookup(5); - const operand_info src6 = pI->operand_lookup(6); - const operand_info src7 = pI->operand_lookup(7); - const operand_info src8 = pI->operand_lookup(8); - unsigned type = pI->get_type(); - - int tid = inst.warp_id() * core->get_warp_size() + i; - ptx_thread_info *thread = core->get_thread_info()[tid]; - - // only get precision data once - if (j == 0) { - ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; - op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; - } + const operand_info &src3 = pI->operand_lookup(3); + const operand_info &src4 = pI->operand_lookup(4); + const operand_info &src5 = pI->operand_lookup(5); + const operand_info &src6 = pI->operand_lookup(6); + const operand_info &src7 = pI->operand_lookup(7); + const operand_info &src8 = pI->operand_lookup(8); + + thread = core->get_thread_info()[tid+i]; // get buffer data and synapse data from each thread buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32; buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32; buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32; buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32; synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32; + j++; // get output data from the first 4 threads - if (j < NUM_BUFFERS) { - output[j] = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; + if (j == warp_info->get_done_threads()) { + output = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; } - j++; } } // unpack registers, compute enough outputs to fill an output register unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned)); - unsigned buffer_data_start = (32/op)*(cta_info->get_bar_threads()-1); - for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*NUM_BUFFERS; i++) { + unsigned buffer_data_start = (32/op)*(warp_info->get_done_threads()-1); + for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*INBUFFERS; i++) { unsigned buf = i/(32/ip); unsigned pos = i%(32/ip); - unsigned mask = 0; + int sum = 0; + // sum values from the buffers for (int b = 0; b < ip; b++) { mask |= (1 << b); } mask <<= (pos*ip); - int sum = 0; - for (int j = 0; j < NUM_THREADS; j++) { + for (int j = 0; j < THREADS; j++) { sum += (mask & buffer[j][buf]) >> (pos*ip); } - unpacked_output[i - buffer_data_start] = sum; + // get the previous output + mask = 0; + for (int b = 0; b < op; b++) { + mask |= (1 << b); + } + mask <<= (op*(i-buffer_data_start)); + int past_output = (mask & output) >> (op*(i-buffer_data_start)); + + unpacked_output[i-buffer_data_start] = sum + past_output; } // truncate output @@ -1575,11 +1582,8 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) // store the result in the correct thread's output register for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { if (inst.active(i)) j++; - if (j == cta_info->get_bar_threads()) { - const operand_info &dst = pI->dst(); - unsigned type = pI->get_type(); - int tid = inst.warp_id() * core->get_warp_size() + i; - ptx_thread_info *thread = core->get_thread_info()[tid]; + if (j == warp_info->get_done_threads()) { + thread = core->get_thread_info()[tid+i]; ptx_reg_t data; data.u32 = output_data; thread->set_operand_value(dst, data, type, thread, pI); @@ -1588,8 +1592,9 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) } } - if (cta_info->get_bar_threads() == NUM_THREADS) { - cta_info->reset_bar_threads(); + // once the warp has finished, set the number of completed threads back to 0 for the next warp + if (warp_info->get_done_threads() == THREADS) { + warp_info->reset_done_threads(); } } diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index f48115b..820287d 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -144,6 +144,26 @@ void ptx_cta_info::reset_bar_threads() m_bar_threads = 0; } +ptx_warp_info::ptx_warp_info() +{ + reset_done_threads(); +} + +unsigned ptx_warp_info::get_done_threads() const +{ + return m_done_threads; +} + +void ptx_warp_info::inc_done_threads() +{ + m_done_threads++; +} + +void ptx_warp_info::reset_done_threads() +{ + m_done_threads = 0; +} + unsigned g_ptx_thread_info_uid_next=1; unsigned g_ptx_thread_info_delete_count=0; @@ -170,6 +190,7 @@ ptx_thread_info::ptx_thread_info( kernel_info_t &kernel ) m_branch_taken = 0; m_shared_mem = NULL; m_sstarr_mem = NULL; + m_warp_info = NULL; m_cta_info = NULL; m_local_mem = NULL; m_symbol_table = NULL; diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index 4e748e9..c62fa57 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -171,6 +171,17 @@ private: std::set m_dangling_pointers; }; +class ptx_warp_info { +public: + ptx_warp_info(); // add get_core or something, or threads? + unsigned get_done_threads() const; + void inc_done_threads(); + void reset_done_threads(); + +private: + unsigned m_done_threads; +}; + class symbol; struct stack_entry { @@ -430,6 +441,7 @@ public: memory_space *m_shared_mem; memory_space *m_sstarr_mem; memory_space *m_local_mem; + ptx_warp_info *m_warp_info; ptx_cta_info *m_cta_info; ptx_reg_t m_last_set_operand_value; -- cgit v1.3 From de21c009ca25fbbfd460047c3ae8a3cf59c31454 Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 5 Aug 2016 14:50:37 -0700 Subject: Deleted useless comments --- src/abstract_hardware_model.h | 2 -- src/cuda-sim/cuda-sim.cc | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'src/cuda-sim/cuda-sim.cc') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cfa8c9f..13dfce3 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1028,7 +1028,6 @@ class core_t { m_warp_count += 1; } assert( m_warp_count * m_warp_size > 0 ); - //m_warp = ( ptx_warp_info** )calloc( m_warp_count, sizeof( ptx_warp_info* ) ); m_thread = ( ptx_thread_info** ) calloc( m_warp_count * m_warp_size, sizeof( ptx_thread_info* ) ); @@ -1064,7 +1063,6 @@ class core_t { class gpgpu_sim *m_gpu; kernel_info_t *m_kernel; simt_stack **m_simt_stack; // pdom based reconvergence context for each warp - //class ptx_warp_info ** m_warp; class ptx_thread_info ** m_thread; unsigned m_warp_size; unsigned m_warp_count; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index ba0d00b..53ee25b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1504,7 +1504,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, ptx_warp_info *warp_info = NULL; if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { - warp_info = new ptx_warp_info(); // num_threads should be threads in the warp + warp_info = new ptx_warp_info(); ptx_warp_lookup[hw_warp_id] = warp_info; } else { warp_info = ptx_warp_lookup[hw_warp_id]; -- cgit v1.3 From 45f95f05a11e916933480422b9075767a4cfdf90 Mon Sep 17 00:00:00 2001 From: sspenst Date: Tue, 9 Aug 2016 19:20:02 -0700 Subject: Changed bsmad_impl to match Ahmed's output. Added latency and initiation_interval numbers for bsmad --- src/cuda-sim/cuda-sim.cc | 29 +++++++++++++++++------------ src/cuda-sim/instructions.cc | 30 ++++++++++++++++++++++++++---- src/cuda-sim/opcodes.def | 2 +- 3 files changed, 44 insertions(+), 17 deletions(-) (limited to 'src/cuda-sim/cuda-sim.cc') diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 53ee25b..4bae236 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -66,9 +66,9 @@ char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, - "Opcode latencies for integers " - "Default 1,1,19,25,145", - "1,1,19,25,145"); + "Opcode latencies for integers " + "Default 1,1,19,25,145,1", + "1,1,19,25,145,1"); option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, "Opcode latencies for single precision floating points " "Default 1,1,1,1,30", @@ -78,9 +78,9 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Default 8,8,8,8,335", "8,8,8,8,335"); option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers " - "Default 1,1,4,4,32", - "1,1,4,4,32"); + "Opcode initiation intervals for integers " + "Default 1,1,4,4,32,1", + "1,1,4,4,32,1"); option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, "Opcode initiation intervals for single precision floating points " "Default 1,1,1,1,5", @@ -580,10 +580,10 @@ void ptx_instruction::set_bar_type() void ptx_instruction::set_opcode_and_latency() { - unsigned int_latency[5]; + unsigned int_latency[6]; unsigned fp_latency[5]; unsigned dp_latency[5]; - unsigned int_init[5]; + unsigned int_init[6]; unsigned fp_init[5]; unsigned dp_init[5]; /* @@ -592,19 +592,20 @@ void ptx_instruction::set_opcode_and_latency() * [2] MUL * [3] MAD * [4] DIV + * [5] BSMAD */ - sscanf(opcode_latency_int, "%u,%u,%u,%u,%u", + sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u", &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4]); + &int_latency[3],&int_latency[4],&int_latency[5]); sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", &fp_latency[0],&fp_latency[1],&fp_latency[2], &fp_latency[3],&fp_latency[4]); sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", &dp_latency[0],&dp_latency[1],&dp_latency[2], &dp_latency[3],&dp_latency[4]); - sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u", + sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u", &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4]); + &int_init[3],&int_init[4],&int_init[5]); sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", &fp_init[0],&fp_init[1],&fp_init[2], &fp_init[3],&fp_init[4]); @@ -773,6 +774,10 @@ void ptx_instruction::set_opcode_and_latency() initiation_interval = dp_init[2]; op = SFU_OP; break; + case BSMAD_OP: + latency = int_latency[5]; + initiation_interval = int_init[5]; + break; default: break; } diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 3b938bb..bb15621 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1458,6 +1458,26 @@ void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +unsigned trunc(unsigned num, unsigned precision) { + int mask = 1, latest_one = -1; + unsigned data = num; + for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { + int bit = data & mask; + if (bit == 1) latest_one = j; + data >>= 1; + } + if (latest_one >= precision) { + // round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0 + //int round_up = (num & (1 << (latest_one-precision))) >> (latest_one-precision); + //unsigned shifted_output = num >> (latest_one-precision+1); + // if shifted_output is a number like 1111, don't round up + //if (shifted_output == (pow(2,precision)-1)) round_up = 0; + //num = shifted_output + round_up; + num >>= (latest_one-precision+1); + } + return num; +} + void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { // operands: @@ -1530,16 +1550,18 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) int sum = 0; unsigned mask = (unsigned)(pow(2,ip)-1) << (pos*ip); for (int j = 0; j < THREADS; j++) { - sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j]; + //sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j]; + sum += trunc(((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j], op); } // get the previous output mask = (unsigned)(pow(2,op)-1) << (op*(i-buffer_data_start)); int past_output = (mask & output) >> (op*(i-buffer_data_start)); - unpacked_output[i-buffer_data_start] = sum + past_output; + unpacked_output[i-buffer_data_start] = trunc(trunc(sum,op) + past_output,op); + // truncate sum, truncate (truncated sum + past_output) } // truncate output - for (unsigned i = 0; i < 32/op; i++) { + /*for (unsigned i = 0; i < 32/op; i++) { int mask = 1, latest_one = -1; unsigned data = unpacked_output[i]; for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { @@ -1555,7 +1577,7 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) if (shifted_output == (pow(2,op)-1)) round_up = 0; unpacked_output[i] = shifted_output + round_up; } - } + }*/ // pack the outputs into one register unsigned mask = pow(2,op)-1; diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 021eed8..b363dca 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -52,7 +52,7 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3) OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) -OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1) +OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",1,1) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) -- cgit v1.3 From 7c9b838bca837a3ccea5ea30f53c1cbd8e35252c Mon Sep 17 00:00:00 2001 From: Negar Date: Sun, 12 Nov 2017 19:03:27 -0800 Subject: Fix latency bug --- bsmad_test/.gdbinit | 97 ++ bsmad_test/Makefile | 6 + bsmad_test/bsmad | Bin 0 -> 2660316 bytes bsmad_test/bsmad_result.txt | 333 ++++ bsmad_test/bsmad_test.cu | 76 + bsmad_test/bsmadoutput.txt | 3004 +++++++++++++++++++++++++++++++++++ bsmad_test/config_fermi_islip.icnt | 70 + bsmad_test/d.log | 3049 ++++++++++++++++++++++++++++++++++++ bsmad_test/gpgpu_inst_stats.txt | 26 + bsmad_test/gpgpusim.config | 149 ++ bsmad_test/gpuwattch_gtx1080Ti.xml | 538 +++++++ bsmad_test/out.txt | 1837 ++++++++++++++++++++++ bsmad_test/output | 2338 +++++++++++++++++++++++++++ bsmad_test/output.txt | 2338 +++++++++++++++++++++++++++ bsmad_test/result | 2338 +++++++++++++++++++++++++++ src/cuda-sim/cuda-sim.cc | 30 +- 16 files changed, 16216 insertions(+), 13 deletions(-) create mode 100644 bsmad_test/.gdbinit create mode 100644 bsmad_test/Makefile create mode 100755 bsmad_test/bsmad create mode 100644 bsmad_test/bsmad_result.txt create mode 100644 bsmad_test/bsmad_test.cu create mode 100644 bsmad_test/bsmadoutput.txt create mode 100644 bsmad_test/config_fermi_islip.icnt create mode 100644 bsmad_test/d.log create mode 100644 bsmad_test/gpgpu_inst_stats.txt create mode 100644 bsmad_test/gpgpusim.config create mode 100755 bsmad_test/gpuwattch_gtx1080Ti.xml create mode 100644 bsmad_test/out.txt create mode 100644 bsmad_test/output create mode 100644 bsmad_test/output.txt create mode 100644 bsmad_test/result (limited to 'src/cuda-sim/cuda-sim.cc') diff --git a/bsmad_test/.gdbinit b/bsmad_test/.gdbinit new file mode 100644 index 0000000..b456895 --- /dev/null +++ b/bsmad_test/.gdbinit @@ -0,0 +1,97 @@ +# Provides some useful debugging macros. To use this file, copy to your home +# directory or to your simulation directory then run GPGPU-Sim in gdb. + +printf "\n ** loading GPGPU-Sim debugging macros... ** \n\n" + +set print pretty +set print array-indexes +set unwindonsignal on + +define dp + call g_the_gpu->dump_pipeline((0x40|0x4|0x1),$arg0,0) +end + +document dp +Usage: dp +Display pipeline state. +: index of shader core you would like to see the pipeline state of + +This function displays the state of the pipeline on a single shader core +(setting different values for the first argument of the call to +dump_pipeline will cause different information to be displayed-- +see the source code for more details) +end + +define dpc + call g_the_gpu->dump_pipeline((0x40|0x4|0x1),$arg0,0) + continue +end + +document dpc +Usage: dpc +Display pipeline state, then continue to next breakpoint. +: index of shader core you would like to see the pipeline state of + +This version is useful if you set a breakpoint where gpu_sim_cycle is +incremented in gpu_sim_loop() in src/gpgpu-sim/gpu-sim.c +repeatly hitting enter will advance to show the pipeline contents on +the next cycle. +end + +define dm + call g_the_gpu->dump_pipeline(0x10000|0x10000000,0,$arg0) +end + +define ptxdis + set $addr=$arg0 + printf "disassemble instructions from 0x%x to 0x%x\n", $arg0, $arg1 + call fflush(stdout) + while ( $addr <= $arg1 ) + printf "0x%04x (%4u) : ", $addr, $addr + call ptx_print_insn( $addr, stdout ) + call fflush(stdout) + set $addr = $addr + ptx_print_insn::size + end +end + +document ptxdis +Usage: ptxdis +Disassemble PTX instructions between and (PCs). +end + +define ptxdis_func + set $sid = $arg0 + set $cluster = g_the_gpu_config.m_shader_config.sid_to_cluster($sid) + set $cid = g_the_gpu_config.m_shader_config.sid_to_cid($sid) + set $ptx_tinfo = g_the_gpu->m_cluster[$cluster]->m_core[$cid]->m_thread[$arg1] + set $finfo = $ptx_tinfo->m_func_info + set $minpc = $finfo->m_start_PC + set $maxpc = $minpc + $finfo->m_instr_mem_size + printf "disassembly of function %s (min pc = %u, max pc = %u):\n", $finfo->m_name.c_str(), $minpc, $maxpc + ptxdis $minpc $maxpc +end + +document ptxdis_func +Usage: ptxdis_func (requires debug build) +: shader core number +: thread ID +end + +define ptx_tids2pcs + set $i = 0 + while ( $i < $arg1 ) + set $tid = $arg0[$i] + set $cluster = g_the_gpu_config.m_shader_config.sid_to_cluster($sid); + set $cid = g_the_gpu_config.m_shader_config.sid_to_cid($sid); + set $addr = g_the_gpu->m_cluster[$cluster]->m_core[$cid]->m_thread[$tid]->m_PC + printf "%2u : tid = %3u => pc = %d\n", $i, $tid, $addr + set $i = $i + 1 + end +end + +document ptx_tids2pcs +Usage: ptx_tids2pcs +: array of tids +: length of array +: shader core number +end diff --git a/bsmad_test/Makefile b/bsmad_test/Makefile new file mode 100644 index 0000000..b841c6b --- /dev/null +++ b/bsmad_test/Makefile @@ -0,0 +1,6 @@ +all: bsmad_test.cu + nvcc --gpu-architecture=compute_50 --gpu-code=compute_50 -lcudart -g -o bsmad bsmad_test.cu + +.PHONY: +clean: + rm bsmad diff --git a/bsmad_test/bsmad b/bsmad_test/bsmad new file mode 100755 index 0000000..56020ff Binary files /dev/null and b/bsmad_test/bsmad differ diff --git a/bsmad_test/bsmad_result.txt b/bsmad_test/bsmad_result.txt new file mode 100644 index 0000000..968a990 --- /dev/null +++ b/bsmad_test/bsmad_result.txt @@ -0,0 +1,333 @@ +GNU gdb (GDB) SUSE (7.5.1-2.5.1) +Copyright (C) 2012 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "x86_64-suse-linux". +For bug reporting instructions, please see: +... +Reading symbols from /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad...done. +To enable execution of this file add + add-auto-load-safe-path /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/.gdbinit +line to your configuration file "/home/negargoli93/.gdbinit". +To completely disable this security protection add + set auto-load safe-path / +line to your configuration file "/home/negargoli93/.gdbinit". +For more information about this security protection see the +"Auto-loading safe path" section in the GDB manual. E.g., run from the shell: + info "(gdb)Auto-loading safe path" +(gdb) r^C(gdb) r +Starting program: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +[Thread debugging using libthread_db enabled] +Using host libthread_db library "/lib64/libthread_db.so.1". + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-0751c1489add70d7494521c7f9d65f462e4391c6_modified_0] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace[New Thread 0x7ffff4512700 (LWP 5117)] +[Thread 0x7ffff4512700 (LWP 5117) exited] +[New Thread 0x7ffff4512700 (LWP 5120)] + +Program received signal SIGINT, Interrupt. +0x00007ffff6f78fef in pthread_join () from /lib64/libpthread.so.0 +Missing separate debuginfos, use: zypper install Mesa-libGL1-debuginfo-8.0.4-20.27.1.x86_64 Mesa-libglapi0-debuginfo-8.0.4-20.27.1.x86_64 glibc-debuginfo-2.15-22.17.1.x86_64 libX11-6-debuginfo-1.5.0-2.7.1.x86_64 libX11-xcb1-debuginfo-1.5.0-2.7.1.x86_64 libXau6-debuginfo-1.0.7-2.1.2.x86_64 libXdamage1-debuginfo-1.1.3-2.1.2.x86_64 libXext6-debuginfo-1.3.1-2.4.1.x86_64 libXfixes3-debuginfo-5.0-2.4.1.x86_64 libXxf86vm1-debuginfo-1.1.2-2.7.1.x86_64 libdrm2-debuginfo-2.4.33-2.3.2.x86_64 libgcc47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libstdc++47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libxcb-glx0-debuginfo-1.8.1-2.8.1.x86_64 libxcb1-debuginfo-1.8.1-2.8.1.x86_64 zlib-debuginfo-1.2.7-2.1.2.x86_64 +(gdb) +(gdb) quit +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? 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(y or n) EOF [assumed Y] diff --git a/bsmad_test/bsmad_test.cu b/bsmad_test/bsmad_test.cu new file mode 100644 index 0000000..9be6e74 --- /dev/null +++ b/bsmad_test/bsmad_test.cu @@ -0,0 +1,76 @@ +#include +#define SIZE 1024 +#define THREADS_PER_BLOCK 32 +#define PART_THREADS 1 +#define NUM_BLOCKS 1 +#define I_PREC 4 +#define O_PREC 4 + +__global__ void vector_add(int* A, int* B, int* res) +{ + int tid = threadIdx.x + blockIdx.x * blockDim.x; + res[tid] = A[tid] + B[tid]; +} + +__global__ void digit_serial_mad(unsigned* i_buffer, unsigned* i_synapse, unsigned* result, unsigned* accum) +{ + unsigned tid = threadIdx.x + blockIdx.x * blockDim.x; + unsigned buffer; + unsigned synapse; + if (tid < PART_THREADS) + { + buffer = i_buffer[tid]; + synapse = i_synapse[tid]; + } + + asm("/*"); + asm("CPTX_BEGIN"); + asm("bsmad.s32 %0, %1, %2, %3, %4, %5, %6, %7, %8;" : "=r"(result[tid]) : + "r"(I_PREC), "r"(O_PREC), "r"(buffer), "r"(0), "r"(0), "r"(0), "r"(synapse), "r"(accum[tid])); + asm("CPTX_END"); + asm("*/"); +} + +int main() +{ + // host values + unsigned *buffer = (unsigned*)malloc(sizeof(unsigned)); + unsigned *synapse = (unsigned*)malloc(sizeof(unsigned)); + unsigned *result = (unsigned*)calloc(THREADS_PER_BLOCK, sizeof(unsigned)); + unsigned *accum = (unsigned*)calloc(THREADS_PER_BLOCK, sizeof(unsigned)); + // assign host values + *buffer = 0x5000003F; + *synapse = 0x00000002; + *accum = 0; + // device pointers + unsigned *d_buffer; + unsigned *d_synapse; + unsigned *d_result; + unsigned *d_accum; + // allocate device memory + cudaMalloc(&d_buffer, sizeof(unsigned)); + cudaMalloc(&d_synapse, sizeof(unsigned)); + cudaMalloc(&d_result, sizeof(unsigned)); + cudaMalloc(&d_accum, sizeof(unsigned)); + // copy data to device + cudaMemcpy(d_buffer, buffer, sizeof(unsigned), cudaMemcpyHostToDevice); + cudaMemcpy(d_synapse, synapse, sizeof(unsigned), cudaMemcpyHostToDevice); + cudaMemcpy(d_result, result, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyHostToDevice); + cudaMemcpy(d_accum, accum, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyHostToDevice); + // call kernel + digit_serial_mad<<>>(d_buffer, d_synapse, d_result, d_accum); + // copy data back to host + cudaMemcpy(result, d_result, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyDeviceToHost); + // read out result + printf("Result: %#X\n", result[0]); + // clean up device memory + cudaFree(d_buffer); + cudaFree(d_synapse); + cudaFree(d_result); + cudaFree(d_accum); + // clean up host memory + free(buffer); + free(synapse); + free(result); + free(accum); +} diff --git a/bsmad_test/bsmadoutput.txt b/bsmad_test/bsmadoutput.txt new file mode 100644 index 0000000..7c5f9d5 --- /dev/null +++ b/bsmad_test/bsmadoutput.txt @@ -0,0 +1,3004 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +057a78a8e028f9794c162a7c4e45415d /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_A4Dkbu +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_3lcy4c" +Running: cat _ptx_3lcy4c | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_6DnMXV +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_6DnMXV --output-file /dev/null 2> _ptx_3lcy4cinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_3lcy4c _ptx2_6DnMXV _ptx_3lcy4cinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 + 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 17:28:53 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA +GPGPU-Sim uArch: Shader 1 finished CTA #0 (1081,0), 0 CTAs running +GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z16digit_serial_madPjS_S_S_'). +GPGPU-Sim uArch: GPU detected kernel 1 '_Z16digit_serial_madPjS_S_S_' finished on shader 1. +Destroy streams for kernel 1: size 0 +kernel_name = _Z16digit_serial_madPjS_S_S_ +kernel_launch_uid = 1 +gpu_sim_cycle = 1082 +gpu_sim_insn = 675 +gpu_ipc = 0.6238 +gpu_tot_sim_cycle = 1082 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6238 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1902 W0_Scoreboard:294 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} +maxmrqlatency = 7 +maxdqlatency = 0 +maxmflatency = 252 +averagemflatency = 250 +max_icnt2mem_latency = 6 +max_icnt2sh_latency = 1081 +mrq_lat_table:7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 750 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 759 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1066 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1038 0 0 0 0 228 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 2.000000 -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan 1.000000 +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 8/6 = 1.333333 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 7 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 1 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 252 none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none 250 none none none none none +dram[2]: none none none none none none none none none none 250 none none none none none +dram[3]: none none none none none none none none none none 122 none none none none none +dram[4]: none none none none none none none none none none 252 none none none none 0 +dram[5]: none none none none none none none none none none none none none none 0 none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 244 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 252 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 4a 1989i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents +MSHR: tag=0x3e20200, atomic=0 1 entries : 0x7f51d804c750 : mf: uid= 22, sid01:w00, part=3, addr=0x3e20200, load , size=128, unknown status = IN_PARTITION_DRAM (1081), + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2000 n_act=1 n_pre=0 n_req=2 n_rd=3 n_write=4 bw_util=0.006972 +n_activity=29 dram_eff=0.4828 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 3a 1979i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=1 avg=0.0059761 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=1998 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007968 +n_activity=80 dram_eff=0.2 +bk0: 0a 2006i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 4a 1988i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2009i bk14: 4a 1989i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 7 +L2_total_cache_misses = 7 +L2_total_cache_miss_rate = 1.0000 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 3 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 1 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.001 + +icnt_total_pkts_mem_to_simt=23 +icnt_total_pkts_simt_to_mem=11 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = 7.42857 + minimum = 6 + maximum = 10 +Network latency average = 7.42857 + minimum = 6 + maximum = 10 +Slowest packet = 1 +Flit latency average = 6 + minimum = 6 + maximum = 6 +Slowest flit = 0 +Fragmentation average = 0 + minimum = 0 + maximum = 0 +Injected packet rate average = 0.00012951 + minimum = 0 (at node 0) + maximum = 0.00323774 (at node 1) +Accepted packet rate average = 0.00012951 + minimum = 0 (at node 0) + maximum = 0.00323774 (at node 1) +Injected flit rate average = 0.000314524 + minimum = 0 (at node 0) + maximum = 0.00508788 (at node 1) +Accepted flit rate average= 0.000314524 + minimum = 0 (at node 0) + maximum = 0.0106383 (at node 1) +Injected packet length average = 2.42857 +Accepted packet length average = 2.42857 +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Network latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Flit latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Fragmentation average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Injected packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected packet size average = -nan (5 samples) +Accepted packet size average = -nan (5 samples) +Hops average = -nan (5 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- + + +gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) +gpgpu_simulation_rate = 675 (inst/sec) +gpgpu_simulation_rate = 1082 (cycle/sec) +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 1082 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6238 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1902 W0_Scoreboard:294 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} +Result: 0XA000006F diff --git a/bsmad_test/config_fermi_islip.icnt b/bsmad_test/config_fermi_islip.icnt new file mode 100644 index 0000000..2a69ddd --- /dev/null +++ b/bsmad_test/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 50; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/bsmad_test/d.log b/bsmad_test/d.log new file mode 100644 index 0000000..50ba43f --- /dev/null +++ b/bsmad_test/d.log @@ -0,0 +1,3049 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +e1ffbb239b1e632822e743b7e0c60b46 /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_8Ypfya +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_CMkVsP" +Running: cat _ptx_CMkVsP | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_bVrCnu +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_bVrCnu --output-file /dev/null 2> _ptx_CMkVsPinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_CMkVsP _ptx2_bVrCnu _ptx_CMkVsPinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) + -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 18:22:19 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA +GPGPU-Sim uArch: Shader 1 finished CTA #0 (1079,0), 0 CTAs running +GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z16digit_serial_madPjS_S_S_'). +GPGPU-Sim uArch: GPU detected kernel 1 '_Z16digit_serial_madPjS_S_S_' finished on shader 1. +Destroy streams for kernel 1: size 0 +kernel_name = _Z16digit_serial_madPjS_S_S_ +kernel_launch_uid = 1 +gpu_sim_cycle = 1080 +gpu_sim_insn = 675 +gpu_ipc = 0.6250 +gpu_tot_sim_cycle = 1080 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6250 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} +maxmrqlatency = 7 +maxdqlatency = 0 +maxmflatency = 252 +averagemflatency = 250 +max_icnt2mem_latency = 6 +max_icnt2sh_latency = 1079 +mrq_lat_table:7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 750 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 759 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1064 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1038 0 0 0 0 228 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 2.000000 -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan 1.000000 +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 8/6 = 1.333333 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 7 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 1 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 252 none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none 250 none none none none none +dram[2]: none none none none none none none none none none 250 none none none none none +dram[3]: none none none none none none none none none none 122 none none none none none +dram[4]: none none none none none none none none none none 252 none none none none 0 +dram[5]: none none none none none none none none none none none none none none 0 none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 244 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 252 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 4a 1985i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents +MSHR: tag=0x3e20200, atomic=0 1 entries : 0x7f6d3018f8f0 : mf: uid= 22, sid01:w00, part=3, addr=0x3e20200, load , size=128, unknown status = IN_PARTITION_DRAM (1079), + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1996 n_act=1 n_pre=0 n_req=2 n_rd=3 n_write=4 bw_util=0.006986 +n_activity=29 dram_eff=0.4828 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 3a 1975i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=1 avg=0.00598802 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1994 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007984 +n_activity=80 dram_eff=0.2 +bk0: 0a 2002i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 4a 1984i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2005i bk14: 4a 1985i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 7 +L2_total_cache_misses = 7 +L2_total_cache_miss_rate = 1.0000 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 3 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 1 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.001 + +icnt_total_pkts_mem_to_simt=23 +icnt_total_pkts_simt_to_mem=11 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = 7.42857 + minimum = 6 + maximum = 10 +Network latency average = 7.42857 + minimum = 6 + maximum = 10 +Slowest packet = 1 +Flit latency average = 6 + minimum = 6 + maximum = 6 +Slowest flit = 0 +Fragmentation average = 0 + minimum = 0 + maximum = 0 +Injected packet rate average = 0.00012975 + minimum = 0 (at node 0) + maximum = 0.00324374 (at node 1) +Accepted packet rate average = 0.00012975 + minimum = 0 (at node 0) + maximum = 0.00324374 (at node 1) +Injected flit rate average = 0.000315107 + minimum = 0 (at node 0) + maximum = 0.00509731 (at node 1) +Accepted flit rate average= 0.000315107 + minimum = 0 (at node 0) + maximum = 0.010658 (at node 1) +Injected packet length average = 2.42857 +Accepted packet length average = 2.42857 +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Network latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Flit latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Fragmentation average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Injected packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected packet size average = -nan (5 samples) +Accepted packet size average = -nan (5 samples) +Hops average = -nan (5 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- + + +gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) +gpgpu_simulation_rate = 675 (inst/sec) +gpgpu_simulation_rate = 1080 (cycle/sec) +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 1080 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6250 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +Result: 0XA000006F + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} diff --git a/bsmad_test/gpgpu_inst_stats.txt b/bsmad_test/gpgpu_inst_stats.txt new file mode 100644 index 0000000..96fa69d --- /dev/null +++ b/bsmad_test/gpgpu_inst_stats.txt @@ -0,0 +1,26 @@ +kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence +_1.ptx 92 : 32 160 128 0 0 1 1 0 0 +_1.ptx 90 : 32 448 0 0 0 0 0 0 0 +_1.ptx 67 : 32 186 0 0 0 0 0 0 1 +_1.ptx 66 : 32 224 0 0 0 0 0 0 0 +_1.ptx 65 : 32 416 0 0 0 0 0 0 0 +_1.ptx 88 : 32 192 0 0 0 0 0 0 0 +_1.ptx 64 : 32 192 0 0 0 0 0 0 0 +_1.ptx 87 : 32 192 0 0 0 0 0 0 0 +_1.ptx 63 : 32 192 0 0 0 0 0 0 0 +_1.ptx 86 : 32 8256 128 0 0 1 1 0 0 +_1.ptx 99 : 32 192 0 0 0 0 0 0 0 +_1.ptx 62 : 32 192 0 0 0 0 0 0 0 +_1.ptx 85 : 32 352 0 0 0 0 0 0 0 +_1.ptx 61 : 32 8192 0 0 0 0 0 0 0 +_1.ptx 84 : 32 352 0 0 0 0 0 0 0 +_1.ptx 60 : 32 8192 0 0 0 0 0 0 0 +_1.ptx 83 : 32 320 0 0 0 0 0 0 0 +_1.ptx 59 : 32 8224 0 0 0 0 0 0 0 +_1.ptx 58 : 32 8224 128 0 0 0 0 0 0 +_1.ptx 69 : 1 7 0 0 0 0 0 0 0 +_1.ptx 70 : 1 256 128 0 0 1 1 0 0 +_1.ptx 71 : 1 7 0 0 0 0 0 0 0 +_1.ptx 72 : 1 256 128 0 0 1 1 0 0 +_1.ptx 75 : 32 224 0 0 0 0 0 0 0 +_1.ptx 76 : 32 224 0 0 0 0 0 0 0 diff --git a/bsmad_test/gpgpusim.config b/bsmad_test/gpgpusim.config new file mode 100644 index 0000000..6b512ba --- /dev/null +++ b/bsmad_test/gpgpusim.config @@ -0,0 +1,149 @@ +# This config models the Pascal GP102 (GeForceGTX 1080Ti) + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 60 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 11 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145,4,4 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 1,2,1,1,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The default is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) +# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/bsmad_test/gpuwattch_gtx1080Ti.xml b/bsmad_test/gpuwattch_gtx1080Ti.xml new file mode 100755 index 0000000..02619ff --- /dev/null +++ b/bsmad_test/gpuwattch_gtx1080Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsmad_test/out.txt b/bsmad_test/out.txt new file mode 100644 index 0000000..4e95cb1 --- /dev/null +++ b/bsmad_test/out.txt @@ -0,0 +1,1837 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_leydyg +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_8pgp00" +Running: cat _ptx_8pgp00 | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_ZhKBsL +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_ZhKBsL --output-file /dev/null 2> _ptx_8pgp00info" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_8pgp00 _ptx2_ZhKBsL _ptx_8pgp00info" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 +bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:03:17 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/output b/bsmad_test/output new file mode 100644 index 0000000..db0d524 --- /dev/null +++ b/bsmad_test/output @@ -0,0 +1,2338 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +733602e7cd2fc7896e7fece60068330a /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_Fvj0UD +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_qiCCrA" +Running: cat _ptx_qiCCrA | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_zIGfYw +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_zIGfYw --output-file /dev/null 2> _ptx_qiCCrAinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_qiCCrA _ptx2_zIGfYw _ptx_qiCCrAinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 13:33:51 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/output.txt b/bsmad_test/output.txt new file mode 100644 index 0000000..7414f61 --- /dev/null +++ b/bsmad_test/output.txt @@ -0,0 +1,2338 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_r35nHZ +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_hSOoDH" +Running: cat _ptx_hSOoDH | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_FSgqzp +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_FSgqzp --output-file /dev/null 2> _ptx_hSOoDHinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_hSOoDH _ptx2_FSgqzp _ptx_hSOoDHinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) + 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:02:01 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/result b/bsmad_test/result new file mode 100644 index 0000000..210fed9 --- /dev/null +++ b/bsmad_test/result @@ -0,0 +1,2338 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_ppZXax +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_D0f3bm" +Running: cat _ptx_D0f3bm | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_ctl9cb +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_ctl9cb --output-file /dev/null 2> _ptx_D0f3bminfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_D0f3bm _ptx2_ctl9cb _ptx_D0f3bminfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:27:07 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index b5b79e7..54d8796 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -69,9 +69,9 @@ unsigned cdp_latency[5]; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, - "Opcode latencies for integers " - "Default 1,1,19,25,145,1", - "1,1,19,25,145,1"); + "Opcode latencies for integers " + "Default 1,1,19,25,145,1,4", + "1,1,19,25,145,1,4"); option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, "Opcode latencies for single precision floating points " "Default 1,1,1,1,30", @@ -81,8 +81,8 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Default 8,8,8,8,335", "8,8,8,8,335"); option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers " - "Default 1,1,4,4,32,1", + "Opcode initiation intervals for integers " + "Default 1,1,4,4,32,1,1", "1,1,4,4,32,1"); option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, "Opcode initiation intervals for single precision floating points " @@ -589,10 +589,14 @@ void ptx_instruction::set_bar_type() void ptx_instruction::set_opcode_and_latency() { - unsigned int_latency[6]; + unsigned int_latency[5]; + unsigned int_precision; + unsigned int_lane_width; unsigned fp_latency[5]; unsigned dp_latency[5]; - unsigned int_init[6]; + unsigned int_init[5]; + unsigned int_init_precision; + unsigned int_init_lane_width; unsigned fp_init[5]; unsigned dp_init[5]; /* @@ -603,18 +607,18 @@ void ptx_instruction::set_opcode_and_latency() * [4] DIV * [5] BSMAD */ - sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u", + sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u,%u", &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4],&int_latency[5]); + &int_latency[3],&int_latency[4],&int_precision,&int_lane_width); sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", &fp_latency[0],&fp_latency[1],&fp_latency[2], &fp_latency[3],&fp_latency[4]); sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", &dp_latency[0],&dp_latency[1],&dp_latency[2], &dp_latency[3],&dp_latency[4]); - sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u", + sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u, %u", &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4],&int_init[5]); + &int_init[3],&int_init[4],&int_init_precision,&int_init_lane_width); sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", &fp_init[0],&fp_init[1],&fp_init[2], &fp_init[3],&fp_init[4]); @@ -789,8 +793,8 @@ void ptx_instruction::set_opcode_and_latency() op = SFU_OP; break; case BSMAD_OP: - latency = int_latency[5]; - initiation_interval = int_init[5]; + latency = int_precision/int_lane_width; + initiation_interval = int_init_precision/int_init_lane_width; break; case SHFL_OP: latency = 32; -- cgit v1.3 From 68674d4ba230df0d3bf9f4e5b035f4cf9cfc185b Mon Sep 17 00:00:00 2001 From: negargoli93 Date: Sat, 12 May 2018 16:09:04 -0700 Subject: commit for eece527project --- src/abstract_hardware_model.h | 6 +- src/cuda-sim/cuda-sim.cc | 11 ++- src/cuda-sim/instructions.cc | 213 +++++++++++++++++++----------------------- src/cuda-sim/opcodes.def | 2 +- src/cuda-sim/ptx.l | 2 +- src/cuda-sim/ptx_ir.h | 25 +++++ src/gpgpu-sim/scoreboard.cc | 4 + src/gpgpusim_entrypoint.cc | 1 - 8 files changed, 136 insertions(+), 128 deletions(-) (limited to 'src/cuda-sim/cuda-sim.cc') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cdd9cf3..9dc58d4 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -750,7 +750,7 @@ public: }; // the maximum number of destination, source, or address uarch operands in a instruction -#define MAX_REG_OPERANDS 8 +#define MAX_REG_OPERANDS 32 struct dram_callback_t { dram_callback_t() { function=NULL; instruction=NULL; thread=NULL; } @@ -825,8 +825,8 @@ public: address_type reconvergence_pc; // -1 => not a branch, -2 => use function return address - unsigned out[4]; - unsigned in[4]; + unsigned out[8]; + unsigned in[8]; unsigned char is_vectorin; unsigned char is_vectorout; int pred; // predicate register number diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 54d8796..006738a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -792,9 +792,9 @@ void ptx_instruction::set_opcode_and_latency() initiation_interval = dp_init[2]; op = SFU_OP; break; - case BSMAD_OP: - latency = int_precision/int_lane_width; - initiation_interval = int_init_precision/int_init_lane_width; + case MMA_OP: + latency = 64; + initiation_interval = 64; break; case SHFL_OP: latency = 32; @@ -1301,6 +1301,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) *((warp_inst_t*)pJ) = inst; // copy active mask information pI = pJ; } + if((pI->get_opcode()!=MMA_OP)||((pI->get_opcode()==MMA_OP)&&(lane_id==0))){ switch ( pI->get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; @@ -1308,7 +1309,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) #undef OP_DEF #undef OP_W_DEF default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break; - } + }} delete pJ; pI = pI_saved; @@ -1930,7 +1931,7 @@ void functionalCoreSim::executeWarp(unsigned i, bool &allAtBarrier, bool & someO { if(!m_warpAtBarrier[i] && m_liveThreadCount[i]!=0){ warp_inst_t inst =getExecuteWarp(i); - execute_warp_inst_t(inst,i); + execute_warp_inst_t(inst,i); if(inst.isatomic()) inst.do_atomic(true); if(inst.op==BARRIER_OP || inst.op==MEMORY_BARRIER_OP ) m_warpAtBarrier[i]=true; updateSIMTStack( i, &inst ); diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 493e307..7903343 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -771,6 +771,17 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) unsigned i_type = pI->get_type(); src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + //unsigned warpId_aa,warp_size_aa; + //warpId_aa = pI->warp_id(); + //warp_size_aa=32; + //dim3 t=thread->get_tid(); + //unsigned tid_aa=warp_size_aa*warpId_aa; + + ptx_thread_info *thread2; + thread2=thread; + src1_data = thread2->get_operand_value(src1, dst, i_type, thread2, 1); + src2_data = thread2->get_operand_value(src2, dst, i_type, thread2, 1); + unsigned rounding_mode = pI->rounding_mode(); int orig_rm = fegetround(); @@ -1483,135 +1494,102 @@ unsigned trunc(unsigned num, unsigned precision) { return num; } -void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { - // operands: - // 0 = output - // 1 = input precision - // 2 = output precision - // 3 = buffer0 - // 4 = buffer1 - // 5 = buffer2 - // 6 = buffer3 - // 7 = synapse value - // 8 = output value + int i,j,k,thrd; + int row,offset; + printf("mmaWorld\n"); + ptx_reg_t matrix_a[16][16]; + ptx_reg_t matrix_b[16][16]; + ptx_reg_t matrix_c[16][16]; + ptx_reg_t matrix_d[16][16]; + ptx_reg_t src_data; + ptx_thread_info *thread; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); unsigned type = pI->get_type(); int tid = inst.warp_id_func() * core->get_warp_size(); - ptx_thread_info *thread = core->get_thread_info()[tid]; - const int ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; - const int op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; - const int THREADS = inst.active_count(); - const int INBUFFERS = 4; - const int OUTBUFFERS = (((32/ip)*INBUFFERS) / (32/op)) + ((((32/ip)*INBUFFERS) % (32/op)) != 0); - if (OUTBUFFERS > THREADS) { - printf("GPGPU-Sim PTX: BSMAD ERROR - Number of output registers required (%d) is greater than the number available (%d)\n", OUTBUFFERS, THREADS); - abort(); - } - ptx_warp_info *warp_info = thread->m_warp_info; - warp_info->inc_done_threads(); + const operand_info &dst = pI->operand_lookup(0); + +//NOT WOR thread = core->get_thread_info()[tid]; +//NOT WOR const operand_info &src_a= pI->operand_lookup(1); +//NOT WOR src_data= (thread->get_operand_value(src_a, dst, type, thread, 1)); +//NOT WOR thread->set_operand_value(dst, src_data, type, thread, pI); + for (thrd=0; thrd < core->get_warp_size(); thrd++){ + row=thrd/2; + offset=8*(thrd%2); + thread = core->get_thread_info()[tid+thrd]; + printf("thread=%d:",thrd); + for(i=8;i<=31;i++){ + const operand_info &src_a= pI->operand_lookup(i); + src_data= (thread->get_operand_value(src_a, dst, type, thread, 1)); + printf("%f ",src_data.f32); + if(i<=15) + matrix_a[row][offset+(i)%8]=src_data; + else if((i>15)&&(i<=23)) + matrix_b[row][offset+(i)%8]=src_data; + else if(i>23) + matrix_c[row][offset+(i)%8]=src_data; + - // threads within the warp are executed sequentially by the simulator, store output in first four registers - if (warp_info->get_done_threads() <= OUTBUFFERS) { - unsigned buffer[THREADS][INBUFFERS]; - unsigned synapse[THREADS]; - unsigned output; - - // loop through all threads in the warp and get all data - for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { - if (inst.active(i)) { - const operand_info &src3 = pI->operand_lookup(3); - const operand_info &src4 = pI->operand_lookup(4); - const operand_info &src5 = pI->operand_lookup(5); - const operand_info &src6 = pI->operand_lookup(6); - const operand_info &src7 = pI->operand_lookup(7); - const operand_info &src8 = pI->operand_lookup(8); - - thread = core->get_thread_info()[tid+i]; - // get buffer data and synapse data from each thread - buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32; - buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32; - buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32; - buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32; - synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32; - j++; - // get output data from the first 4 threads - if (j == warp_info->get_done_threads()) { - output = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; - } - } } + printf("\n"); + } - // unpack registers, compute enough outputs to fill an output register - unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned)); - unsigned buffer_data_start = (32/op)*(warp_info->get_done_threads()-1); - for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*INBUFFERS; i++) { - unsigned buf = i/(32/ip); - unsigned pos = i%(32/ip); - // sum values from the buffers - int sum = 0; - unsigned mask = (unsigned)(pow(2,ip)-1) << (pos*ip); - for (int j = 0; j < THREADS; j++) { - //sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j]; - sum += trunc(((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j], op); - } - // get the previous output - mask = (unsigned)(pow(2,op)-1) << (op*(i-buffer_data_start)); - int past_output = (mask & output) >> (op*(i-buffer_data_start)); - unpacked_output[i-buffer_data_start] = trunc(trunc(sum,op) + past_output,op); - // truncate sum, truncate (truncated sum + past_output) + printf("MATRIX_A\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_a[i][j].f32); } - - // truncate output - /*for (unsigned i = 0; i < 32/op; i++) { - int mask = 1, latest_one = -1; - unsigned data = unpacked_output[i]; - for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { - int bit = data & mask; - if (bit == 1) latest_one = j; - data >>= 1; - } - if (latest_one >= op) { - // round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0 - int round_up = (unpacked_output[i] & (1 << (latest_one-op))) >> (latest_one-op); - unsigned shifted_output = unpacked_output[i] >> (latest_one-op+1); - // if shifted_output is a number like 1111, don't round up - if (shifted_output == (pow(2,op)-1)) round_up = 0; - unpacked_output[i] = shifted_output + round_up; - } - }*/ - - // pack the outputs into one register - unsigned mask = pow(2,op)-1; - unsigned output_data = 0; - for (int i = 0; i < 32/op; i++) { - output_data |= (unpacked_output[i] & mask) << (op*i); + printf("\n"); + } + printf("MATRIX_B\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_b[i][j].f32); } - - // store the result in the correct thread's output register - for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { - if (inst.active(i)) j++; - if (j == warp_info->get_done_threads()) { - thread = core->get_thread_info()[tid+i]; - ptx_reg_t data; - data.u32 = output_data; - thread->set_operand_value(dst, data, type, thread, pI); - break; + printf("\n"); + } + printf("MATRIX_C\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_c[i][j].f32); + } + printf("\n"); + } + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + matrix_d[i][j].f32=0; + } + } + + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + for(k=0;k<16;k++){ + matrix_d[i][j].f32=matrix_d[i][j].f32+matrix_a[i][k].f32*matrix_b[j][k].f32; } + matrix_d[i][j].f32+=matrix_c[i][j].f32; } } - - // once the warp has finished, set the number of completed threads back to 0 for the next warp - if (warp_info->get_done_threads() == THREADS) { - warp_info->reset_done_threads(); + printf("MATRIX_D\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_d[i][j].f32); + } + printf("\n"); + } + for (thrd=0; thrd < core->get_warp_size(); thrd++){ + thread = core->get_thread_info()[tid+thrd]; + row=thrd/2; + offset=8*(thrd%2); + for(i=0;i<8;i++){ + const operand_info &dst = pI->operand_lookup(i); + const symbol *r2; + r2=dst.get_symbol(); + printf("thrd=%d,i=%d,register%s, data=%f\n",thrd,i,(r2->name()).c_str(),matrix_d[row][offset+i].f32); + thread->set_operand_value(dst, matrix_d[row][offset+i], type, thread, pI); + } } - - // set the latency assuming 4 bits of each input get processed every cycle - // mutable latency variable??? - //pI->latency = (ip+3)/4; + } void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) @@ -4098,7 +4076,8 @@ void st_impl( const ptx_instruction *pI, ptx_thread_info *thread ) if (!vector_spec) { data = thread->get_operand_value(src1, dst, type, thread, 1); mem->write(addr,size/8,&data.s64,thread,pI); - } else { + printf("addr=%d data=%d\n",addr,data.s64); + } else { if (vector_spec == V2_TYPE) { ptx_reg_t* ptx_regs = new ptx_reg_t[2]; thread->get_vector_operand_values(src1, ptx_regs, 2); diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 41f2f22..a3cc83f 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -52,7 +52,7 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3) OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) -OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",1,1) +OP_W_DEF(MMA_OP,mma_impl,"mma",1,1) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 7620134..e07e339 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -68,7 +68,7 @@ bra TC; ptx_lval.int_value = BRA_OP; return OPCODE; brx TC; ptx_lval.int_value = BRX_OP; return OPCODE; brev TC; ptx_lval.int_value = BREV_OP; return OPCODE; brkpt TC; ptx_lval.int_value = BRKPT_OP; return OPCODE; -bsmad TC; ptx_lval.int_value = BSMAD_OP; return OPCODE; +mma TC; ptx_lval.int_value = MMA_OP; return OPCODE; call TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode callp TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE; clz TC; ptx_lval.int_value = CLZ_OP; return OPCODE; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 4c10373..0601b97 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -948,6 +948,31 @@ public: assert( m_operands.size() > 3 ); return m_operands[3]; } + const operand_info &src4() const + { + assert( m_operands.size() > 4 ); + return m_operands[4]; + } + const operand_info &src5() const + { + assert( m_operands.size() > 5 ); + return m_operands[5]; + } + const operand_info &src6() const + { + assert( m_operands.size() > 6 ); + return m_operands[6]; + } + const operand_info &src7() const + { + assert( m_operands.size() > 7 ); + return m_operands[7]; + } + const operand_info &src8() const + { + assert( m_operands.size() > 8 ); + return m_operands[8]; + } const operand_info &operand_lookup( unsigned n ) const { diff --git a/src/gpgpu-sim/scoreboard.cc b/src/gpgpu-sim/scoreboard.cc index f412054..b538fdf 100644 --- a/src/gpgpu-sim/scoreboard.cc +++ b/src/gpgpu-sim/scoreboard.cc @@ -146,6 +146,10 @@ bool Scoreboard::checkCollision( unsigned wid, const class inst_t *inst ) const if(inst->in[1] > 0) inst_regs.insert(inst->in[1]); if(inst->in[2] > 0) inst_regs.insert(inst->in[2]); if(inst->in[3] > 0) inst_regs.insert(inst->in[3]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[4]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[5]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[6]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[7]); if(inst->pred > 0) inst_regs.insert(inst->pred); if(inst->ar1 > 0) inst_regs.insert(inst->ar1); if(inst->ar2 > 0) inst_regs.insert(inst->ar2); diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 04845e7..a6d7eb4 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -134,7 +134,6 @@ void *gpgpu_sim_thread_concurrent(void*) gpgpu_cuda_ptx_sim_main_func(*kernel); g_the_gpu->finish_functional_sim(kernel); } - //performance simulation if( g_the_gpu->active() ) { g_the_gpu->cycle(); -- cgit v1.3 From 5b1ba75a3d5d02fbc12b5218abaaae4fcf2b5c2d Mon Sep 17 00:00:00 2001 From: aamir Date: Wed, 30 May 2018 17:34:14 -0700 Subject: changes for vector operands --- src/abstract_hardware_model.h | 2 +- src/cuda-sim/cuda-sim.cc | 24 +++++++++---- src/cuda-sim/instructions.cc | 80 +++++++++++++++++++++++++++++++++---------- src/cuda-sim/ptx_ir.h | 10 +++++- 4 files changed, 88 insertions(+), 28 deletions(-) (limited to 'src/cuda-sim/cuda-sim.cc') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 9dc58d4..e00c941 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -826,7 +826,7 @@ public: address_type reconvergence_pc; // -1 => not a branch, -2 => use function return address unsigned out[8]; - unsigned in[8]; + unsigned in[24]; unsigned char is_vectorin; unsigned char is_vectorout; int pred; // predicate register number diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 006738a..62077e6 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -852,8 +852,10 @@ void ptx_instruction::pre_decode() { pc = m_PC; isize = m_inst_size; - for( unsigned i=0; i<4; i++) { + for(unsigned i=0; i<8; i++) { out[i] = 0; + } + for(unsigned i=0; i<24; i++) { in[i] = 0; } is_vectorin = 0; @@ -922,6 +924,10 @@ void ptx_instruction::pre_decode() if( num_elem >= 2 ) out[1] = o.reg2_num(); if( num_elem >= 3 ) out[2] = o.reg3_num(); if( num_elem >= 4 ) out[3] = o.reg4_num(); + if( num_elem >= 5 ) out[4] = o.reg5_num(); + if( num_elem >= 6 ) out[5] = o.reg6_num(); + if( num_elem >= 7 ) out[6] = o.reg7_num(); + if( num_elem >= 8 ) out[7] = o.reg8_num(); for (int i = 0; i < num_elem; i++) arch_reg.dst[i] = o.arch_reg_num(i); } @@ -940,13 +946,17 @@ void ptx_instruction::pre_decode() //assert(m == 0); //only support 1 vector operand (for textures) right now is_vectorout = 1; unsigned num_elem = o.get_vect_nelem(); - if( num_elem >= 1 ) in[0] = o.reg1_num(); - if( num_elem >= 2 ) in[1] = o.reg2_num(); - if( num_elem >= 3 ) in[2] = o.reg3_num(); - if( num_elem >= 4 ) in[3] = o.reg4_num(); + if( num_elem >= 1 ) in[m+0] = o.reg1_num(); + if( num_elem >= 2 ) in[m+1] = o.reg2_num(); + if( num_elem >= 3 ) in[m+2] = o.reg3_num(); + if( num_elem >= 4 ) in[m+3] = o.reg4_num(); + if( num_elem >= 5 ) in[m+4] = o.reg5_num(); + if( num_elem >= 6 ) in[m+5] = o.reg6_num(); + if( num_elem >= 7 ) in[m+6] = o.reg7_num(); + if( num_elem >= 8 ) in[m+7] = o.reg8_num(); for (int i = 0; i < num_elem; i++) - arch_reg.src[i] = o.arch_reg_num(i); - m+=4; + arch_reg.src[m+i] = o.arch_reg_num(i); + m+=num_elem; } } } diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 7407269..446cdbf 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -748,7 +748,7 @@ void addp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case U64_TYPE: data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=src1_data.f16+src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; default: assert(0); break; @@ -826,7 +826,7 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case U64_TYPE: data.u64 = src1_data.u64 + src2_data.u64; break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=src1_data.f16+src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; default: assert(0); break; @@ -1878,7 +1878,9 @@ ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, } } else { switch ( to_width ) { - case 16: assert(0); break; + case 16: //assert(0); break; + y.f16 = x.f32; + break; case 32: assert(0); break; // handled by f2f case 64: y.f64 = x.f32; @@ -2140,7 +2142,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=truncf(data.f16);break;//assert(0); break; case F32_TYPE: data.f32 = truncf(data.f32); break; @@ -2163,7 +2165,13 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE:// assert(0); break; +#if CUDART_VERSION >= 3000 + data.f16 = nearbyintf(data.f16); +#else + data.f16 = cuda_math::__cuda_nearbyintf(data.f16); +#endif + break; case F32_TYPE: #if CUDART_VERSION >= 3000 data.f32 = nearbyintf(data.f32); @@ -2186,7 +2194,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=floorf(data.f16);break;//assert(0); break; case F32_TYPE: data.f32 = floorf(data.f32); break; @@ -2205,7 +2213,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 = ceilf(data.f16); break; //assert(0); break; case F32_TYPE: data.f32 = ceilf(data.f32); break; case F64_TYPE: case FF64_TYPE: data.f64 = ceil(data.f64); break; default: assert(0); break; @@ -2246,7 +2254,10 @@ void ptx_saturate(ptx_reg_t& data, int saturation_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to clamp an integer to 1??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: //assert(0); break; + if (data.f16 > 1.0f) data.f16 = 1.0f; //negative + if (data.f16 < 0.0f) data.f16 = 0.0f; //positive + break; case F32_TYPE: if (data.f32 > 1.0f) data.f32 = 1.0f; //negative if (data.f32 < 0.0f) data.f32 = 0.0f; //positive @@ -2270,8 +2281,8 @@ void cvt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) unsigned rounding_mode = pI->rounding_mode(); unsigned saturation_mode = pI->saturation_mode(); - if ( to_type == F16_TYPE || from_type == F16_TYPE ) - abort(); +// if ( to_type == F16_TYPE || from_type == F16_TYPE ) +// abort(); int to_sign, from_sign; size_t from_width, to_width; @@ -2406,7 +2417,7 @@ void div_impl( const ptx_instruction *pI, ptx_thread_info *thread ) data.u32 = src1_data.u32 / src2_data.u32; break; case B64_TYPE: data.u64 = src1_data.u64 / src2_data.u64; break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 = src1_data.f16 / src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 / src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 / src2_data.f64; break; default: assert(0); break; @@ -2744,9 +2755,24 @@ void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry if ( pI->is_lo() ) d.u64 = t.u64 + c.u64 + carry_bit.pred; else assert(0); break; - case F16_TYPE: - assert(0); - break; + case F16_TYPE:{ + // assert(0); + // break; + assert( use_carry == false); + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + d.f16 = a.f16 * b.f16 + c.f16; + if ( pI->saturation_mode() ) { + if ( d.f16 < 0 ) d.f16 = 0; + else if ( d.f16 > 1.0f ) d.f16 = 1.0f; + } + fesetround( orig_rm ); + break; + } case F32_TYPE: { assert( use_carry == false); int orig_rm = fegetround(); @@ -3046,9 +3072,25 @@ void mul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) if ( pI->is_lo() ) d.u64 = t.u64; else assert(0); break; - case F16_TYPE: - assert(0); - break; + case F16_TYPE:{ + //assert(0); + //break; + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + + d.f16 = a.f16 * b.f16; + + if ( pI->saturation_mode() ) { + if ( d.f16 < 0 ) d.f16 = 0; + else if ( d.f16 > 1.0f ) d.f16 = 1.0f; + } + fesetround( orig_rm ); + break; + } case F32_TYPE: { int orig_rm = fegetround(); switch ( rounding_mode ) { @@ -3111,7 +3153,7 @@ void neg_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case U32_TYPE: case U64_TYPE: assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 =0.0f - src1_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = 0.0f - src1_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = 0.0f - src1_data.f64; break; default: assert(0); break; @@ -4165,7 +4207,7 @@ void sub_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case B64_TYPE: case U64_TYPE: data.u64 = src1_data.u64 - src2_data.u64; break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 = src1_data.f16 - src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 - src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 - src2_data.f64; break; default: assert(0); break; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index ff24a66..833f175 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -656,7 +656,11 @@ public: if( !m_value.m_vector_symbolic[1] ) return 1; if( !m_value.m_vector_symbolic[2] ) return 2; if( !m_value.m_vector_symbolic[3] ) return 3; - return 4; + if( !m_value.m_vector_symbolic[4] ) return 4; + if( !m_value.m_vector_symbolic[5] ) return 5; + if( !m_value.m_vector_symbolic[6] ) return 6; + if( !m_value.m_vector_symbolic[7] ) return 7; + return 8; } const symbol* vec_symbol(int idx) const @@ -718,6 +722,10 @@ public: int reg2_num() const { return m_value.m_vector_symbolic[1]->reg_num();} int reg3_num() const { return m_value.m_vector_symbolic[2]?m_value.m_vector_symbolic[2]->reg_num():0; } int reg4_num() const { return m_value.m_vector_symbolic[3]?m_value.m_vector_symbolic[3]->reg_num():0; } + int reg5_num() const { return m_value.m_vector_symbolic[4]?m_value.m_vector_symbolic[4]->reg_num():0; } + int reg6_num() const { return m_value.m_vector_symbolic[5]?m_value.m_vector_symbolic[5]->reg_num():0; } + int reg7_num() const { return m_value.m_vector_symbolic[6]?m_value.m_vector_symbolic[6]->reg_num():0; } + int reg8_num() const { return m_value.m_vector_symbolic[7]?m_value.m_vector_symbolic[7]->reg_num():0; } int arch_reg_num() const { return m_value.m_symbolic->arch_reg_num(); } int arch_reg_num(unsigned n) const { return (m_value.m_vector_symbolic[n])? m_value.m_vector_symbolic[n]->arch_reg_num() : -1; } bool is_label() const { return m_type == label_t;} -- cgit v1.3 From e5f532a3b65e17f49991ed08a275f87ac2d68d0a Mon Sep 17 00:00:00 2001 From: aamir Date: Fri, 1 Jun 2018 09:52:12 -0700 Subject: wmma load working --- cuda-kernels/gpgpu_inst_stats.txt | 19 + cuda-kernels/log | 6328 +++++++++++++++++++++++++++++++++++++ cuda-kernels/log1 | 512 +++ cuda-kernels/tensor_core | Bin 2750968 -> 2750968 bytes src/cuda-sim/Makefile | 2 +- src/cuda-sim/cuda-math.h | 1 + src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/half.hpp | 3067 ++++++++++++++++++ src/cuda-sim/instructions.cc | 96 +- src/cuda-sim/ptx_sim.h | 6 +- 10 files changed, 9988 insertions(+), 45 deletions(-) create mode 100644 cuda-kernels/log create mode 100644 cuda-kernels/log1 create mode 100644 src/cuda-sim/half.hpp (limited to 'src/cuda-sim/cuda-sim.cc') diff --git a/cuda-kernels/gpgpu_inst_stats.txt b/cuda-kernels/gpgpu_inst_stats.txt index acb1839..41f06a4 100755 --- a/cuda-kernels/gpgpu_inst_stats.txt +++ b/cuda-kernels/gpgpu_inst_stats.txt @@ -1 +1,20 @@ kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence +_1.ptx 164 : 512 2560 1024 0 0 16 16 0 0 +_1.ptx 163 : 512 5696 0 0 0 0 0 0 0 +_1.ptx 162 : 512 5664 0 0 0 0 0 0 0 +_1.ptx 161 : 512 3616 0 0 0 0 0 0 0 +_1.ptx 158 : 512 3616 0 0 0 0 0 0 0 +_1.ptx 156 : 512 134048 2048 0 0 16 16 0 0 +_1.ptx 155 : 512 5632 0 0 0 0 0 0 0 +_1.ptx 154 : 512 5376 0 0 0 0 0 0 0 +_1.ptx 143 : 512 100864 128 0 0 0 0 0 0 +_1.ptx 167 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 144 : 512 100864 0 0 0 0 0 0 0 +_1.ptx 145 : 512 1536 0 0 0 0 0 0 0 +_1.ptx 146 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 147 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 148 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 149 : 512 8384 0 0 0 0 0 0 0 +_1.ptx 150 : 512 4096 0 0 0 0 0 0 0 +_1.ptx 151 : 512 0 0 0 0 0 0 0 0 +_1.ptx 153 : 512 3968 0 0 0 0 0 0 0 diff --git a/cuda-kernels/log b/cuda-kernels/log new file mode 100644 index 0000000..98df26a --- /dev/null +++ b/cuda-kernels/log @@ -0,0 +1,6328 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-03de5ae03420ba5666d669c6f76faccf2704fa58_modified_17] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 70 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 40 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,16,4 # Opcode latencies for integers Default 1,1,19,25,145,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,16,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +a9478053306cbb4803bedf0d6ea12100 /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +Running md5sum using "md5sum /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core " +Parsing file _cuobjdump_complete_output_c7ZC8M +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_70 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z17convertFp32ToFp16P6__halfPfi : hostFun 0x0x401dd7, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 70 + _1.ptx:13 => (ptx_parser.cc:175) start_function + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:13 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:13 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B32_TYPE + _1.ptx:14 => (ptx_parser.cc:189) add_function_name vprintf (extern) + _1.ptx:14 => (ptx_parser.cc:381) add_identifier "func_retval0" (0) +GPGPU-Sim PTX: allocating stack frame region for .param "func_retval0" from 0x0 to 0x4 + _1.ptx:14 => (ptx_parser.cc:144) init_directive_state + _1.ptx:15 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:15 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:15 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:15 => (ptx_parser.cc:381) add_identifier "vprintf_param_0" (1) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_0" from 0x4 to 0xc + _1.ptx:15 => (ptx_parser.cc:577) add_function_arg "vprintf_param_0" + _1.ptx:15 => (ptx_parser.cc:219) add_directive + _1.ptx:15 => (ptx_parser.cc:144) init_directive_state + _1.ptx:16 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:16 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:16 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:17 => (ptx_parser.cc:381) add_identifier "vprintf_param_1" (2) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_1" from 0xc to 0x14 + _1.ptx:17 => (ptx_parser.cc:577) add_function_arg "vprintf_param_1" + _1.ptx:17 => (ptx_parser.cc:219) add_directive + _1.ptx:17 => (ptx_parser.cc:144) init_directive_state + _1.ptx:19 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:19 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:19 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:19 => (ptx_parser.cc:331) set_variable_type space_spec=global_space scalar_type_spec=B8_TYPE + _1.ptx:19 => (ptx_parser.cc:381) add_identifier "$str" (3) +GPGPU-Sim PTX: allocating global region for "$str" from 0x100 to 0x109 (global memory space) + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:319) add_variables + _1.ptx:19 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:175) start_function + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:189) add_function_name _Z12wmma_exampleP6__halfS0_Pfiiiff (entrypoint) + _1.ptx:22 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:22 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:22 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:22 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" (4) + _1.ptx:22 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" + _1.ptx:22 => (ptx_parser.cc:219) add_directive + _1.ptx:22 => (ptx_parser.cc:144) init_directive_state + _1.ptx:23 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:23 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:23 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:23 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" (5) + _1.ptx:23 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" + _1.ptx:23 => (ptx_parser.cc:219) add_directive + _1.ptx:23 => (ptx_parser.cc:144) init_directive_state + _1.ptx:24 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:24 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:24 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:24 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" (6) + _1.ptx:24 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" + _1.ptx:24 => (ptx_parser.cc:219) add_directive + _1.ptx:24 => (ptx_parser.cc:144) init_directive_state + _1.ptx:25 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:25 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:25 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:25 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" (7) + _1.ptx:25 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" + _1.ptx:25 => (ptx_parser.cc:219) add_directive + _1.ptx:25 => (ptx_parser.cc:144) init_directive_state + _1.ptx:26 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:26 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:26 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:26 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" (8) + _1.ptx:26 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" + _1.ptx:26 => (ptx_parser.cc:219) add_directive + _1.ptx:26 => (ptx_parser.cc:144) init_directive_state + _1.ptx:27 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:27 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:27 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:27 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" (9) + _1.ptx:27 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" + _1.ptx:27 => (ptx_parser.cc:219) add_directive + _1.ptx:27 => (ptx_parser.cc:144) init_directive_state + _1.ptx:28 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:28 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:28 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:28 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" (10) + _1.ptx:28 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" + _1.ptx:28 => (ptx_parser.cc:219) add_directive + _1.ptx:28 => (ptx_parser.cc:144) init_directive_state + _1.ptx:29 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:29 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:29 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:30 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" (11) + _1.ptx:30 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" + _1.ptx:30 => (ptx_parser.cc:219) add_directive + _1.ptx:30 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:32 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:32 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:32 => (ptx_parser.cc:331) set_variable_type space_spec=local_space scalar_type_spec=B8_TYPE + _1.ptx:32 => (ptx_parser.cc:381) add_identifier "__local_depot0" (12) +GPGPU-Sim PTX: allocating stack frame region for .local "__local_depot0" from 0x0 to 0x8 + _1.ptx:32 => (ptx_parser.cc:319) add_variables + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:219) add_directive + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:33 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:33 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:33 => (ptx_parser.cc:381) add_identifier "%SP" (13) + _1.ptx:33 => (ptx_parser.cc:319) add_variables + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:219) add_directive + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:34 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:34 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:34 => (ptx_parser.cc:381) add_identifier "%SPL" (14) + _1.ptx:34 => (ptx_parser.cc:319) add_variables + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:219) add_directive + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:35 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:35 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=PRED_TYPE + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p0" (15) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p1" (16) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p2" (17) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p3" (18) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p4" (19) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p5" (20) + _1.ptx:35 => (ptx_parser.cc:319) add_variables + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:219) add_directive + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:36 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:36 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=F32_TYPE + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f0" (21) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f1" (22) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f2" (23) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f3" (24) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f4" (25) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f5" (26) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f6" (27) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f7" (28) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f8" (29) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f9" (30) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f10" (31) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f11" (32) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f12" (33) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f13" (34) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f14" (35) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f15" (36) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f16" (37) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f17" (38) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f18" (39) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f19" (40) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f20" (41) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f21" (42) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f22" (43) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f23" (44) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f24" (45) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f25" (46) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f26" (47) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f27" (48) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f28" (49) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f29" (50) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f30" (51) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f31" (52) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f32" (53) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f33" (54) + _1.ptx:36 => (ptx_parser.cc:319) add_variables + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:219) add_directive + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:37 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:37 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B32_TYPE + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r0" (55) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r1" (56) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r2" (57) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r3" (58) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r4" (59) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r5" (60) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r6" (61) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r7" (62) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r8" (63) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r9" (64) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r10" (65) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r11" (66) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r12" (67) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r13" (68) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r14" (69) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r15" (70) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r16" (71) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r17" (72) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r18" (73) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r19" (74) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r20" (75) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r21" (76) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r22" (77) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r23" (78) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r24" (79) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r25" (80) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r26" (81) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r27" (82) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r28" (83) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r29" (84) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r30" (85) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r31" (86) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r32" (87) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r33" (88) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r34" (89) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r35" (90) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r36" (91) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r37" (92) + _1.ptx:37 => (ptx_parser.cc:319) add_variables + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:219) add_directive + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:38 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:38 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd0" (93) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd1" (94) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd2" (95) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd3" (96) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd4" (97) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd5" (98) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd6" (99) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd7" (100) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd8" (101) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd9" (102) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd10" (103) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd11" (104) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd12" (105) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd13" (106) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd14" (107) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd15" (108) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd16" (109) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd17" (110) + _1.ptx:38 => (ptx_parser.cc:319) add_variables + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:219) add_directive + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:41 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:41 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:41 => (ptx_parser.cc:144) init_directive_state + _1.ptx:42 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:42 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:42 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:42 => (ptx_parser.cc:144) init_directive_state + _1.ptx:43 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:43 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:43 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:43 => (ptx_parser.cc:929) add_address_operand + _1.ptx:43 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:43 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:43 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:43 => (ptx_parser.cc:144) init_directive_state + _1.ptx:44 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:44 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:44 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:44 => (ptx_parser.cc:929) add_address_operand + _1.ptx:44 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:44 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:44 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:44 => (ptx_parser.cc:144) init_directive_state + _1.ptx:45 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:45 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:45 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:45 => (ptx_parser.cc:929) add_address_operand + _1.ptx:45 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:45 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:45 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:45 => (ptx_parser.cc:144) init_directive_state + _1.ptx:46 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:46 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:46 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:46 => (ptx_parser.cc:929) add_address_operand + _1.ptx:46 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:46 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:46 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:46 => (ptx_parser.cc:144) init_directive_state + _1.ptx:47 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:47 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:47 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:47 => (ptx_parser.cc:929) add_address_operand + _1.ptx:47 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:47 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:47 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:47 => (ptx_parser.cc:144) init_directive_state + _1.ptx:48 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:48 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:48 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:48 => (ptx_parser.cc:929) add_address_operand + _1.ptx:48 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:48 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:48 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:48 => (ptx_parser.cc:144) init_directive_state + _1.ptx:50 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:50 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:50 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:50 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:50 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:50 => (ptx_parser.cc:144) init_directive_state + _1.ptx:52 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:52 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:52 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:52 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:52 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:52 => (ptx_parser.cc:144) init_directive_state + _1.ptx:53 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:53 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:53 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:53 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:53 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:53 => (ptx_parser.cc:144) init_directive_state + _1.ptx:54 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:54 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:54 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:54 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:54 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:54 => (ptx_parser.cc:144) init_directive_state + _1.ptx:55 => (ptx_parser.cc:672) add_option + _1.ptx:55 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:55 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:55 => (ptx_parser.cc:144) init_directive_state + _1.ptx:56 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:56 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:56 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:56 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:56 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:56 => (ptx_parser.cc:144) init_directive_state + _1.ptx:57 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:295) add_instruction: div + _1.ptx:57 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:57 => (ptx_parser.cc:144) init_directive_state + _1.ptx:58 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:58 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:58 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:58 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:58 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:58 => (ptx_parser.cc:144) init_directive_state + _1.ptx:59 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:59 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:59 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:59 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:59 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:59 => (ptx_parser.cc:144) init_directive_state + _1.ptx:60 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:60 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:60 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:60 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:60 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:60 => (ptx_parser.cc:144) init_directive_state + _1.ptx:61 => (ptx_parser.cc:672) add_option + _1.ptx:61 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:61 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:61 => (ptx_parser.cc:144) init_directive_state + _1.ptx:62 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:883) add_literal_int + _1.ptx:62 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:62 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:62 => (ptx_parser.cc:144) init_directive_state + _1.ptx:63 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:883) add_literal_int + _1.ptx:63 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:63 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:63 => (ptx_parser.cc:144) init_directive_state + _1.ptx:64 => (ptx_parser.cc:672) add_option + _1.ptx:64 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:64 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:64 => (ptx_parser.cc:144) init_directive_state + _1.ptx:65 => (ptx_parser.cc:672) add_option + _1.ptx:65 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:883) add_literal_int + _1.ptx:65 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:65 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:65 => (ptx_parser.cc:144) init_directive_state + _1.ptx:66 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:66 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:66 => (ptx_parser.cc:144) init_directive_state + _1.ptx:67 => (ptx_parser.cc:672) add_option + _1.ptx:67 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:67 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:67 => (ptx_parser.cc:144) init_directive_state + _1.ptx:68 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:68 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:68 => (ptx_parser.cc:144) init_directive_state + _1.ptx:69 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:69 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:69 => (ptx_parser.cc:889) add_literal_float + _1.ptx:69 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:69 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:69 => (ptx_parser.cc:144) init_directive_state + _1.ptx:70 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:70 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:70 => (ptx_parser.cc:144) init_directive_state + _1.ptx:71 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:71 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:71 => (ptx_parser.cc:144) init_directive_state + _1.ptx:72 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:72 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:72 => (ptx_parser.cc:144) init_directive_state + _1.ptx:73 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:73 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:73 => (ptx_parser.cc:144) init_directive_state + _1.ptx:74 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:74 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:74 => (ptx_parser.cc:144) init_directive_state + _1.ptx:75 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:75 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:75 => (ptx_parser.cc:144) init_directive_state + _1.ptx:76 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:76 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:76 => (ptx_parser.cc:144) init_directive_state + _1.ptx:77 => (ptx_parser.cc:659) add_pred + _1.ptx:77 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:77 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:77 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:77 => (ptx_parser.cc:144) init_directive_state + _1.ptx:78 => (ptx_parser.cc:672) add_option + _1.ptx:78 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:78 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:78 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:78 => (ptx_parser.cc:144) init_directive_state + _1.ptx:80 => (ptx_parser.cc:643) add_label + _1.ptx:80 => (ptx_parser.cc:295) add_instruction: