From 826a0dc10ca939af1f2c24d0d2e63eb2b33cb731 Mon Sep 17 00:00:00 2001
From: Tor Aamodt <aamodt@ece.ubc.ca>
Date: Sun, 24 Oct 2010 13:05:48 -0800
Subject: 1. updates to .gdbinit file 2. update texture to bypass ROP-delay
 queue... correlation now 0.9592

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7912]
---
 src/cuda-sim/cuda-sim.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/cuda-sim/cuda-sim.cc')

diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 1967b2f..1982218 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -427,6 +427,7 @@ void gpgpu_t::gpu_memset( size_t dst_start_addr, int c, size_t count )
 
 void ptx_print_insn( address_type pc, FILE *fp )
 {
+   static unsigned size=1;
    std::map<unsigned,function_info*>::iterator f = g_pc_to_finfo.find(pc);
    if( f == g_pc_to_finfo.end() ) {
        fprintf(fp,"<no instruction at address 0x%x>", pc );
@@ -434,7 +435,7 @@ void ptx_print_insn( address_type pc, FILE *fp )
    }
    function_info *finfo = f->second;
    assert( finfo );
-   finfo->print_insn(pc,fp);
+   size = finfo->print_insn(pc,fp);
 }
 
 void ptx_instruction::set_opcode_and_latency()
-- 
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