From 8019833f6c9d9552c70739dc2bf45e53655666ec Mon Sep 17 00:00:00 2001 From: Mengchi Zhang Date: Thu, 11 Jul 2019 11:01:27 -0400 Subject: Move g_total_param_size Signed-off-by: Mengchi Zhang --- src/cuda-sim/instructions.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/cuda-sim/instructions.cc') diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 46a262d..a72bc0c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -56,6 +56,8 @@ class ptx_recognizer; #include "cuda_device_runtime.h" #include +#include "../../libcuda/gpgpu_context.h" + using half_float::half; unsigned ptx_instruction::g_num_ptx_inst_uid=0; @@ -2095,7 +2097,7 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) #if (CUDART_VERSION >= 5000) //Jin: handle device runtime apis for CDP else if(fname == "cudaGetParameterBufferV2") { - gpgpusim_cuda_getParameterBufferV2(pI, thread, target_func); + target_func->gpgpu_ctx->device_runtime->gpgpusim_cuda_getParameterBufferV2(pI, thread, target_func); return; } else if(fname == "cudaLaunchDeviceV2") { -- cgit v1.3 From db406fd188f389f3050879e8cd76c3817b1630f8 Mon Sep 17 00:00:00 2001 From: Mengchi Zhang Date: Thu, 11 Jul 2019 13:23:12 -0400 Subject: Move ptx_tex_regs Signed-off-by: Mengchi Zhang --- src/cuda-sim/cuda-sim.h | 2 ++ src/cuda-sim/instructions.cc | 20 ++++++++++---------- 2 files changed, 12 insertions(+), 10 deletions(-) (limited to 'src/cuda-sim/instructions.cc') diff --git a/src/cuda-sim/cuda-sim.h b/src/cuda-sim/cuda-sim.h index 194309a..b3b6b73 100644 --- a/src/cuda-sim/cuda-sim.h +++ b/src/cuda-sim/cuda-sim.h @@ -133,6 +133,7 @@ class cuda_sim { g_assemble_code_next_pc=0; g_debug_thread_uid = 0; g_override_embedded_ptx = false; + ptx_tex_regs = NULL; gpgpu_ctx = ctx; } //global variables @@ -169,6 +170,7 @@ class cuda_sim { int g_debug_thread_uid; bool g_override_embedded_ptx; std::set g_ptx_cta_info_sm_idx_used; + ptx_reg_t* ptx_tex_regs; // backward pointer class gpgpu_context* gpgpu_ctx; //global functions diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index a72bc0c..dfe5af6 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -5146,7 +5146,6 @@ void sured_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not void sust_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } void suq_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -ptx_reg_t* ptx_tex_regs = NULL; union intfloat { int a; @@ -5260,9 +5259,10 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) unsigned c_type = pI->get_type2(); fflush(stdout); ptx_reg_t data1, data2, data3, data4; - if (!ptx_tex_regs) ptx_tex_regs = new ptx_reg_t[4]; + if (!thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs) + thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs = new ptx_reg_t[4]; unsigned nelem = src2.get_vect_nelem(); - thread->get_vector_operand_values(src2, ptx_tex_regs, nelem); //ptx_reg should be 4 entry vector type...coordinates into texture + thread->get_vector_operand_values(src2, thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs, nelem); //ptx_reg should be 4 entry vector type...coordinates into texture /* For programs with many streams, textures can be bound and unbound asynchronously. This means we need to use the kernel's "snapshot" of @@ -5299,7 +5299,7 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) height = cuArray->height; if (texref->normalized) { assert(c_type == F32_TYPE); - x_f32 = ptx_tex_regs[0].f32; + x_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32; if (texref->addressMode[0] == cudaAddressModeClamp) { x_f32 = (x_f32 > 1.0)? 1.0 : x_f32; x_f32 = (x_f32 < 0.0)? 0.0 : x_f32; @@ -5322,11 +5322,11 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) } else { switch ( c_type ) { case S32_TYPE: - x = ptx_tex_regs[0].s32; + x = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].s32; assert(texref->filterMode == cudaFilterModePoint); break; case F32_TYPE: - x_f32 = ptx_tex_regs[0].f32; + x_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32; alpha = x_f32 - floor(x_f32); // offset into subtexel (for linear sampling) x = (int) x_f32; break; @@ -5349,8 +5349,8 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) width = cuArray->width; height = cuArray->height; if (texref->normalized) { - x_f32 = reduce_precision(ptx_tex_regs[0].f32,16); - y_f32 = reduce_precision(ptx_tex_regs[1].f32,15); + x_f32 = reduce_precision(thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32,16); + y_f32 = reduce_precision(thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[1].f32,15); if (texref->addressMode[0]) {//clamp if (x_f32<0) x_f32 = 0; @@ -5380,8 +5380,8 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) y = (int) floor(y_f32 * height); } } else { - x_f32 = ptx_tex_regs[0].f32; - y_f32 = ptx_tex_regs[1].f32; + x_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32; + y_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[1].f32; alpha = x_f32 - floor(x_f32); beta = y_f32 - floor(y_f32); -- cgit v1.3 From b1385157251803aa45eaff154637218c9f6b15b1 Mon Sep 17 00:00:00 2001 From: Mengchi Zhang Date: Thu, 11 Jul 2019 14:23:13 -0400 Subject: Move g_cuda_device_launch_param_map and g_cuda_device_launch_op Signed-off-by: Mengchi Zhang --- src/cuda-sim/cuda_device_runtime.cc | 41 ++---------------------------------- src/cuda-sim/cuda_device_runtime.h | 42 +++++++++++++++++++++++++++++++++---- src/cuda-sim/instructions.cc | 4 ++-- 3 files changed, 42 insertions(+), 45 deletions(-) (limited to 'src/cuda-sim/instructions.cc') diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index 22304db..326a1c5 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -27,44 +27,7 @@ unsigned long long g_max_total_param_size = 0; std::cout.flush(); \ } -class device_launch_config_t { - -public: - device_launch_config_t() {} - - device_launch_config_t(dim3 _grid_dim, - dim3 _block_dim, - unsigned int _shared_mem, - function_info * _entry): - grid_dim(_grid_dim), - block_dim(_block_dim), - shared_mem(_shared_mem), - entry(_entry) {} - - dim3 grid_dim; - dim3 block_dim; - unsigned int shared_mem; - function_info * entry; - -}; - -class device_launch_operation_t { - -public: - device_launch_operation_t() {} - device_launch_operation_t(kernel_info_t *_grid, - CUstream_st * _stream) : - grid(_grid), stream(_stream) {} - - kernel_info_t * grid; //a new child grid - - CUstream_st * stream; - -}; - -std::map g_cuda_device_launch_param_map; -std::list g_cuda_device_launch_op; //extern stream_manager *g_stream_manager(); //Handling device runtime api: @@ -142,7 +105,7 @@ void cuda_device_runtime::gpgpusim_cuda_getParameterBufferV2(const ptx_instructi //Handling device runtime api: //cudaError_t cudaLaunchDeviceV2(void *parameterBuffer, cudaStream_t stream) -void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func) { +void cuda_device_runtime::gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func) { DEV_RUNTIME_REPORT("Calling cudaLaunchDeviceV2"); unsigned n_return = target_func->has_return(); @@ -263,7 +226,7 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * //Handling device runtime api: //cudaError_t cudaStreamCreateWithFlags ( cudaStream_t* pStream, unsigned int flags) //flags can only be cudaStreamNonBlocking -void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func) { +void cuda_device_runtime::gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func) { DEV_RUNTIME_REPORT("Calling cudaStreamCreateWithFlags"); unsigned n_return = target_func->has_return(); diff --git a/src/cuda-sim/cuda_device_runtime.h b/src/cuda-sim/cuda_device_runtime.h index dd908ae..b49d0eb 100644 --- a/src/cuda-sim/cuda_device_runtime.h +++ b/src/cuda-sim/cuda_device_runtime.h @@ -3,10 +3,40 @@ #if (CUDART_VERSION >= 5000) #pragma once -void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); -void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); -#endif -#if (CUDART_VERSION >= 5000) +class device_launch_config_t { + +public: + device_launch_config_t() {} + + device_launch_config_t(dim3 _grid_dim, + dim3 _block_dim, + unsigned int _shared_mem, + function_info * _entry): + grid_dim(_grid_dim), + block_dim(_block_dim), + shared_mem(_shared_mem), + entry(_entry) {} + + dim3 grid_dim; + dim3 block_dim; + unsigned int shared_mem; + function_info * entry; + +}; + +class device_launch_operation_t { + +public: + device_launch_operation_t() {} + device_launch_operation_t(kernel_info_t *_grid, + CUstream_st * _stream) : + grid(_grid), stream(_stream) {} + + kernel_info_t * grid; //a new child grid + + CUstream_st * stream; + +}; class gpgpu_context; @@ -17,8 +47,12 @@ class cuda_device_runtime { gpgpu_ctx = ctx; } unsigned long long g_total_param_size; + std::map g_cuda_device_launch_param_map; + std::list g_cuda_device_launch_op; // backward pointer class gpgpu_context* gpgpu_ctx; + void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); + void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); void gpgpusim_cuda_getParameterBufferV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); void launch_all_device_kernels(); void launch_one_device_kernel(); diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index dfe5af6..565340c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2101,11 +2101,11 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) return; } else if(fname == "cudaLaunchDeviceV2") { - gpgpusim_cuda_launchDeviceV2(pI, thread, target_func); + target_func->gpgpu_ctx->device_runtime->gpgpusim_cuda_launchDeviceV2(pI, thread, target_func); return; } else if(fname == "cudaStreamCreateWithFlags") { - gpgpusim_cuda_streamCreateWithFlags(pI, thread, target_func); + target_func->gpgpu_ctx->device_runtime->gpgpusim_cuda_streamCreateWithFlags(pI, thread, target_func); return; } #endif -- cgit v1.3 From 3b88f9db669d8ec9ffc477352dcfd2a3d423781f Mon Sep 17 00:00:00 2001 From: Mengchi Zhang Date: Mon, 15 Jul 2019 13:38:38 -0400 Subject: Move g_num_ptx_inst_uid Signed-off-by: Mengchi Zhang --- libcuda/gpgpu_context.h | 2 ++ src/cuda-sim/instructions.cc | 1 - src/cuda-sim/ptx_ir.cc | 2 +- src/cuda-sim/ptx_ir.h | 2 -- 4 files changed, 3 insertions(+), 4 deletions(-) (limited to 'src/cuda-sim/instructions.cc') diff --git a/libcuda/gpgpu_context.h b/libcuda/gpgpu_context.h index 337ebb2..909f267 100644 --- a/libcuda/gpgpu_context.h +++ b/libcuda/gpgpu_context.h @@ -16,6 +16,7 @@ class gpgpu_context { warp_inst_sm_next_uid=0; operand_info_sm_next_uid = 1; kernel_info_m_next_uid = 1; + g_num_ptx_inst_uid = 0; api = new cuda_runtime_api(this); ptxinfo = new ptxinfo_data(this); ptx_parser = new ptx_recognizer(this); @@ -31,6 +32,7 @@ class gpgpu_context { unsigned warp_inst_sm_next_uid; unsigned operand_info_sm_next_uid;//uid for operand_info unsigned kernel_info_m_next_uid;//uid for kernel_info_t + unsigned g_num_ptx_inst_uid; //uid for ptx inst inside ptx_instruction // objects pointers for each file cuda_runtime_api* api; ptxinfo_data* ptxinfo; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 565340c..4d4a80d 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -60,7 +60,6 @@ class ptx_recognizer; using half_float::half; -unsigned ptx_instruction::g_num_ptx_inst_uid=0; bool debug_tensorcore = 0; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 0fa29eb..849cc5d 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1100,7 +1100,7 @@ ptx_instruction::ptx_instruction( int opcode, gpgpu_context* ctx ) : warp_inst_t(config), m_return_var(ctx) { gpgpu_ctx = ctx; - m_uid = ++g_num_ptx_inst_uid; + m_uid = ++(ctx->g_num_ptx_inst_uid); m_PC = 0; m_opcode = opcode; m_pred = pred; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 8ed94d9..1ffbebc 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -878,7 +878,6 @@ private: }; extern const char *g_opcode_string[]; -extern unsigned g_num_ptx_inst_uid; struct basic_block_t { basic_block_t( unsigned ID, ptx_instruction *begin, ptx_instruction *end, bool entry, bool ex) { @@ -1194,7 +1193,6 @@ private: virtual void pre_decode(); friend class function_info; - static unsigned g_num_ptx_inst_uid; // backward pointer class gpgpu_context* gpgpu_ctx; }; -- cgit v1.3 From e1fa1a3cc7c509417064a8e4cdab71e3f7feb881 Mon Sep 17 00:00:00 2001 From: Mengchi Zhang Date: Mon, 15 Jul 2019 22:16:55 -0400 Subject: Move debug_tensorcore Signed-off-by: Mengchi Zhang --- libcuda/gpgpu_context.h | 2 ++ src/cuda-sim/instructions.cc | 43 +++++++++++++++++++++---------------------- 2 files changed, 23 insertions(+), 22 deletions(-) (limited to 'src/cuda-sim/instructions.cc') diff --git a/libcuda/gpgpu_context.h b/libcuda/gpgpu_context.h index 346a8a4..45c5cdd 100644 --- a/libcuda/gpgpu_context.h +++ b/libcuda/gpgpu_context.h @@ -20,6 +20,7 @@ class gpgpu_context { g_ptx_cta_info_uid = 1; symbol_sm_next_uid = 1; function_info_sm_next_uid = 1; + debug_tensorcore = 0; api = new cuda_runtime_api(this); ptxinfo = new ptxinfo_data(this); ptx_parser = new ptx_recognizer(this); @@ -40,6 +41,7 @@ class gpgpu_context { unsigned symbol_sm_next_uid; //uid for symbol unsigned function_info_sm_next_uid; std::vector s_g_pc_to_insn; // a direct mapping from PC to instruction + bool debug_tensorcore; // objects pointers for each file cuda_runtime_api* api; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 4d4a80d..58a077e 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -60,7 +60,6 @@ class ptx_recognizer; using half_float::half; -bool debug_tensorcore = 0; const char *g_opcode_string[NUM_OPCODES] = { @@ -1840,14 +1839,14 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) for (thrd=0; thrd < core->get_warp_size(); thrd++){ thread = core->get_thread_info()[tid+thrd]; - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) printf("THREAD=%d\n:",thrd); for(int operand_num=1;operand_num<=3;operand_num++){ const operand_info &src_a= pI->operand_lookup(operand_num); unsigned nelem = src_a.get_vect_nelem(); ptx_reg_t v[8]; thread->get_vector_operand_values( src_a, v, nelem ); - if(debug_tensorcore){ + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){ printf("Thread%d_Iteration=%d\n:",thrd,operand_num); for(k=0;kget_gpu()->gpgpu_ctx->debug_tensorcore) printf("%.2f ",temp); } - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) printf("\n"); } else{ - if(debug_tensorcore){ + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){ for(k=0;k<8;k++){ printf("%.2f ",v[k].f32); } @@ -1887,7 +1886,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) case 1 ://operand 1 for(k=0;k<8;k++){ mapping(thrd,LOAD_A,a_layout,F16_TYPE,k,16,row,col,offset); - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) printf("A:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset); matrix_a[row][col]=nw_v[offset]; } @@ -1895,7 +1894,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) case 2 ://operand 2 for(k=0;k<8;k++){ mapping(thrd,LOAD_B,b_layout,F16_TYPE,k,16,row,col,offset); - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) printf("B:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset); matrix_b[row][col]=nw_v[offset]; } @@ -1903,7 +1902,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) case 3 ://operand 3 for(k=0;k<8;k++){ mapping(thrd,LOAD_C,ROW,type2,k,16,row,col,offset); - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) printf("C:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset); if(type2!=F16_TYPE){ matrix_c[row][col]=v[offset]; @@ -1917,10 +1916,10 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) printf("Invalid Operand Index\n" ); } } - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) printf("\n"); } - if(debug_tensorcore){ + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){ printf("MATRIX_A\n"); for (i=0;i<16;i++){ for(j=0;j<16;j++){ @@ -1980,7 +1979,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) } } } - if(debug_tensorcore){ + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){ printf("MATRIX_D\n"); for (i=0;i<16;i++){ for(j=0;j<16;j++){ @@ -1999,7 +1998,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) int col_t[8]; for(k=0;k<8;k++){ mapping(thrd,LOAD_C,ROW,type,k,16,row_t[k],col_t[k],offset); - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) printf("mma:store:row:%d,col%d\n",row_t[k],col_t[k]); } thread = core->get_thread_info()[tid+thrd]; @@ -2008,7 +2007,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) if(type==F32_TYPE){ thread->set_wmma_vector_operand_values(dst,matrix_d[row_t[0]][col_t[0]],matrix_d[row_t[1]][col_t[1]],matrix_d[row_t[2]][col_t[2]],matrix_d[row_t[3]][col_t[3]],matrix_d[row_t[4]][col_t[4]],matrix_d[row_t[5]][col_t[5]],matrix_d[row_t[6]][col_t[6]],matrix_d[row_t[7]][col_t[7]]); - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) { printf("thread%d:",thrd); for(k=0;k<8;k++){ @@ -2018,7 +2017,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) } } else if(type==F16_TYPE){ - if(debug_tensorcore){ + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){ printf("thread%d:",thrd); for(k=0;k<8;k++){ temp=matrix_d[row_t[k]][col_t[k]].f16; @@ -2038,7 +2037,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) nw_data3.s64=((matrix_d[row_t[4]][col_t[4]].s64 & 0xffff))|((matrix_d[row_t[5]][col_t[5]].s64&0xffff)<<16); nw_data4.s64=((matrix_d[row_t[6]][col_t[6]].s64 & 0xffff))|((matrix_d[row_t[7]][col_t[7]].s64&0xffff)<<16); thread->set_vector_operand_values(dst,nw_data1,nw_data2,nw_data3,nw_data4); - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) printf("thread%d=%x,%x,%x,%x",thrd,nw_data1.s64,nw_data2.s64,nw_data3.s64,nw_data4.s64); } @@ -3132,7 +3131,7 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) decode_space(space,thread,src1,mem,addr); type_info_key::type_decode(type,size,t); - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) printf("mma_st: thrd=%d,addr=%x, fp(size=%d), stride=%d\n",thrd,addr_reg.u32,size,src2_data.u32); addr_t new_addr = addr+thread_group_offset(thrd,wmma_type,wmma_layout,type,stride)*size/8; addr_t push_addr; @@ -3152,7 +3151,7 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) mem->write(push_addr,size/8,&v[k].s64,thread,pI); mem_txn_addr[num_mem_txn++]=push_addr; - if(debug_tensorcore){ + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){ printf("wmma:store:thread%d=%x,%x,%x,%x,%x,%x,%x,%x\n",thrd,v[0].s64,v[1].s64,v[2].s64,v[3].s64,v[4].s64,v[5].s64,v[6].s64,v[7].s64); float temp; int l; @@ -3179,7 +3178,7 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) mem_txn_addr[num_mem_txn++]=push_addr; } - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) printf("wmma:store:thread%d=%x,%x,%x,%x,%x,%x,%x,%x\n",thrd,nw_v[0].s64,nw_v[1].s64,nw_v[2].s64,nw_v[3].s64,nw_v[4].s64,nw_v[5].s64,nw_v[6].s64,nw_v[7].s64); } } @@ -3242,7 +3241,7 @@ void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) type_info_key::type_decode(type,size,t); ptx_reg_t data[16]; - if(debug_tensorcore) + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore) printf("mma_ld: thrd=%d,addr=%x, fpsize=%d, stride=%d\n",thrd,src1_data.u32,size,src2_data.u32); addr_t new_addr = addr+thread_group_offset(thrd,wmma_type,wmma_layout,type,stride)*size/8; @@ -3338,7 +3337,7 @@ void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) inst.data_size = 4; // 4 byte transaction assert( inst.memory_op == insn_memory_op ); - if(debug_tensorcore){ + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){ if(type==F16_TYPE){ printf("\nmma_ld:thread%d= ",thrd); for(i=0;i<16;i++){ @@ -3388,7 +3387,7 @@ void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) thread->set_vector_operand_values(dst,nw_data[0],nw_data[1],nw_data[2],nw_data[3]); else thread->set_wmma_vector_operand_values(dst,nw_data[0],nw_data[1],nw_data[2],nw_data[3],nw_data[4],nw_data[5],nw_data[6],nw_data[7]); - if(debug_tensorcore){ + if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){ printf("mma_ld:data[0].s64=%x,data[1].s64=%x,new_data[0].s64=%x\n",data[0].u64,data[1].u64,nw_data[0].u64); printf("mma_ld:data[2].s64=%x,data[3].s64=%x,new_data[1].s64=%x\n",data[2].u64,data[3].u64,nw_data[1].u64); printf("mma_ld:data[4].s64=%x,data[5].s64=%x,new_data[2].s64=%x\n",data[4].u64,data[5].u64,nw_data[2].u64); -- cgit v1.3