From 46aad91327a265c2fea2cfe629cc38eadb629200 Mon Sep 17 00:00:00 2001 From: speverel Date: Thu, 2 Jun 2016 11:28:15 -0700 Subject: Added handling of .cc option for arithmetic instructions. NOTE: Only made changes to parse instructions. Carry functionality NOT fully implemented; .cc instructions function like their unmodified ueqivelents. Also modified GTX750Ti config to model L1 data cache as simply not being used for global loads (instead of not existing at all). Changed ptxinfo parsing to avoid crashing when info includes texture information. --- src/cuda-sim/instructions.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cuda-sim/instructions.cc') diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index cf7f04a..4dd5ed8 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2421,7 +2421,7 @@ void mad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) mad_def(pI, thread, false); } -void madp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +void madc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { mad_def(pI, thread, true); } -- cgit v1.3 From 8ed1522aede92bcafc60f69d7e03e6d48c44a86c Mon Sep 17 00:00:00 2001 From: speverel Date: Mon, 6 Jun 2016 14:48:13 -0700 Subject: Added support for BFE (Bit field extract) instruction. --- src/cuda-sim/instructions.cc | 77 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) (limited to 'src/cuda-sim/instructions.cc') diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 4dd5ed8..02ce01c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1336,7 +1336,82 @@ void bar_impl( const ptx_instruction *pIin, ptx_thread_info *thread ) thread->m_last_dram_callback.instruction = pIin; } -void bfe_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void bfe_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + unsigned i_type = pI->get_type(); + unsigned msb = (i_type == U32_TYPE || i_type == S32_TYPE) ? 31 : 63; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); + ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); + unsigned pos = b.u32 & 0xFF; + unsigned len = c.u32 & 0xFF; + unsigned d = 0; + switch (i_type) + { + case U32_TYPE: + { + unsigned mask; + d = a.u32 >> pos; + mask = 0xFFFFFFFF >> (32 - len); + d &= mask; + break; + } + case U64_TYPE: + { + unsigned long mask; + d = a.u64 >> pos; + mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); + d &= mask; + break; + } + case S32_TYPE: + { + unsigned mask; + unsigned min = MY_MIN_I(pos + len - 1, msb); + unsigned sbit = len == 0 ? 0 : (a.s32 >> min) & 0x1; + d = a.s32 >> pos; + if (sbit > 0) + { + mask = 0xFFFFFFFF << len; + d |= mask; + } + else + { + mask = 0xFFFFFFFF >> (32 - len); + d &= mask; + } + break; + } + case S64_TYPE: + { + unsigned long mask; + unsigned min = MY_MIN_I(pos + len - 1, msb); + unsigned sbit = len == 0 ? 0 : (a.s64 >> min) & 0x1; + d = a.s64 >> pos; + if (sbit > 0) + { + mask = 0xFFFFFFFFFFFFFFFF << len; + d |= mask; + } + else + { + mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); + d &= mask; + } + break; + } + default: + printf("Operand type not supported for BFE instruction.\n"); + abort(); + return; + } + thread->set_operand_value(dst,d, i_type, thread, pI); +} + void bfi_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } void bfind_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -- cgit v1.3 From 281798191f9bc37a75592d34a5e38cc5d6c41b6d Mon Sep 17 00:00:00 2001 From: speverel Date: Thu, 16 Jun 2016 15:51:17 -0700 Subject: Added the ability to inject arbitrary PTX instructions. This will be used to add custom instructions in the future; the imaginary instructions 'spr' and 'ama' have been added as samples. --- src/cuda-sim/instructions.cc | 10 ++++++++++ src/cuda-sim/opcodes.def | 2 ++ src/cuda-sim/ptx.l | 6 +++++- 3 files changed, 17 insertions(+), 1 deletion(-) (limited to 'src/cuda-sim/instructions.cc') diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 02ce01c..922e14a 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -816,6 +816,11 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void addc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void ama_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("AMA instruction found.\n"); +} + void and_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ptx_reg_t src1_data, src2_data, data; @@ -3698,6 +3703,11 @@ void slct_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->set_operand_value(dst,d, i_type, thread, pI); } +void spr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("SPR instruction found.\n"); +} + void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ptx_reg_t a, d; diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 874acc7..33ee0ca 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -41,6 +41,7 @@ OP_DEF(ABS_OP,abs_impl,"abs",1,1) OP_DEF(ADD_OP,add_impl,"add",1,1) OP_DEF(ADDP_OP,addp_impl,"addp",1,1) OP_DEF(ADDC_OP,addc_impl,"addc",1,1) +OP_DEF(AMA_OP,ama_impl,"ama",1,2) OP_DEF(AND_OP,and_impl,"and",1,1) OP_DEF(ANDN_OP,andn_impl,"andn",1,1) OP_DEF(ATOM_OP,atom_impl,"atom",1,3) @@ -101,6 +102,7 @@ OP_DEF(SHL_OP,shl_impl,"shl",1,1) OP_DEF(SHR_OP,shr_impl,"shr",1,1) OP_DEF(SIN_OP,sin_impl,"sin",1,4) OP_DEF(SLCT_OP,slct_impl,"slct",1,1) +OP_DEF(SPR_OP,spr_impl,"spr",1,1) OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4) OP_DEF(SSY_OP,ssy_impl,"ssy",0,3) OP_DEF(ST_OP,st_impl,"st",0,5) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index a44177b..026270a 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -145,6 +145,8 @@ xor TC; ptx_lval.int_value = XOR_OP; return OPCODE; nop TC; ptx_lval.int_value = NOP_OP; return OPCODE; break TC; ptx_lval.int_value = BREAK_OP; return OPCODE; breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; +spr TC; ptx_lval.int_value = SPR_OP; return OPCODE; +ama TC; ptx_lval.int_value = AMA_OP; return OPCODE; { @@ -390,7 +392,9 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; } { "*/" BEGIN(INITIAL); -[^*\n]+ // eat comment in chunks +"CPTX_BEGIN" printf("BEGINNING CUSTOM PTX.\n"); BEGIN(INITIAL); +[^C*\n]+ // eat comment in chunks +"C" "*" // eat the lone star \n TC; } -- cgit v1.3 From f7c57e76c086ce417626f37ffc91097c839c687d Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 4 Jul 2016 09:43:36 -0700 Subject: Reverted part of the previous commit so that our new changes related to DNNs can be done in a different branch --- src/cuda-sim/instructions.cc | 10 ---------- src/cuda-sim/opcodes.def | 2 -- src/cuda-sim/ptx.l | 2 -- 3 files changed, 14 deletions(-) (limited to 'src/cuda-sim/instructions.cc') diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 922e14a..02ce01c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -816,11 +816,6 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void addc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void ama_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - printf("AMA instruction found.\n"); -} - void and_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ptx_reg_t src1_data, src2_data, data; @@ -3703,11 +3698,6 @@ void slct_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->set_operand_value(dst,d, i_type, thread, pI); } -void spr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - printf("SPR instruction found.\n"); -} - void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ptx_reg_t a, d; diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 33ee0ca..874acc7 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -41,7 +41,6 @@ OP_DEF(ABS_OP,abs_impl,"abs",1,1) OP_DEF(ADD_OP,add_impl,"add",1,1) OP_DEF(ADDP_OP,addp_impl,"addp",1,1) OP_DEF(ADDC_OP,addc_impl,"addc",1,1) -OP_DEF(AMA_OP,ama_impl,"ama",1,2) OP_DEF(AND_OP,and_impl,"and",1,1) OP_DEF(ANDN_OP,andn_impl,"andn",1,1) OP_DEF(ATOM_OP,atom_impl,"atom",1,3) @@ -102,7 +101,6 @@ OP_DEF(SHL_OP,shl_impl,"shl",1,1) OP_DEF(SHR_OP,shr_impl,"shr",1,1) OP_DEF(SIN_OP,sin_impl,"sin",1,4) OP_DEF(SLCT_OP,slct_impl,"slct",1,1) -OP_DEF(SPR_OP,spr_impl,"spr",1,1) OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4) OP_DEF(SSY_OP,ssy_impl,"ssy",0,3) OP_DEF(ST_OP,st_impl,"st",0,5) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 026270a..b8ce497 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -145,8 +145,6 @@ xor TC; ptx_lval.int_value = XOR_OP; return OPCODE; nop TC; ptx_lval.int_value = NOP_OP; return OPCODE; break TC; ptx_lval.int_value = BREAK_OP; return OPCODE; breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; -spr TC; ptx_lval.int_value = SPR_OP; return OPCODE; -ama TC; ptx_lval.int_value = AMA_OP; return OPCODE; { -- cgit v1.3