From 46aad91327a265c2fea2cfe629cc38eadb629200 Mon Sep 17 00:00:00 2001
From: speverel <speverelle8@gmail.com>
Date: Thu, 2 Jun 2016 11:28:15 -0700
Subject: Added handling of .cc option for arithmetic instructions. NOTE: Only
 made changes to parse instructions. Carry functionality NOT fully
 implemented; .cc instructions function like their unmodified ueqivelents.
 Also modified GTX750Ti config to model L1 data cache as simply not being used
 for global loads (instead of not existing at all). Changed ptxinfo parsing to
 avoid crashing when info includes texture information.

---
 src/cuda-sim/opcodes.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index 7aaa14f..874acc7 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -69,7 +69,7 @@ OP_DEF(LDU_OP,ldu_impl,"ldu",1,5)
 OP_DEF(LG2_OP,lg2_impl,"lg2",1,4)
 OP_DEF(MAD24_OP,mad24_impl,"mad24",1,2)
 OP_DEF(MAD_OP,mad_impl,"mad",1,2)
-OP_DEF(MADP_OP,madp_impl,"madp",1,2)
+OP_DEF(MADC_OP,madc_impl,"madc",1,2)
 OP_DEF(MAX_OP,max_impl,"max",1,1)
 OP_DEF(MEMBAR_OP,membar_impl,"membar",1,3)
 OP_DEF(MIN_OP,min_impl,"min",1,1)
-- 
cgit v1.3


From 281798191f9bc37a75592d34a5e38cc5d6c41b6d Mon Sep 17 00:00:00 2001
From: speverel <speverelle8@gmail.com>
Date: Thu, 16 Jun 2016 15:51:17 -0700
Subject: Added the ability to inject arbitrary PTX instructions.              
           This will be used to add custom instructions in the future; the
 imaginary instructions 'spr' and 'ama' have been added as samples.

---
 src/cuda-sim/instructions.cc | 10 ++++++++++
 src/cuda-sim/opcodes.def     |  2 ++
 src/cuda-sim/ptx.l           |  6 +++++-
 3 files changed, 17 insertions(+), 1 deletion(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 02ce01c..922e14a 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -816,6 +816,11 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread )
 
 void addc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
 
+void ama_impl(  const ptx_instruction *pI, ptx_thread_info *thread )
+{
+	printf("AMA instruction found.\n");	
+}
+
 void and_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
 { 
    ptx_reg_t src1_data, src2_data, data;
@@ -3698,6 +3703,11 @@ void slct_impl( const ptx_instruction *pI, ptx_thread_info *thread )
    thread->set_operand_value(dst,d, i_type, thread, pI);
 }
 
+void spr_impl( const ptx_instruction *pI, ptx_thread_info *thread )
+{
+	printf("SPR instruction found.\n");
+}
+
 void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
 { 
    ptx_reg_t a, d;
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index 874acc7..33ee0ca 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -41,6 +41,7 @@ OP_DEF(ABS_OP,abs_impl,"abs",1,1)
 OP_DEF(ADD_OP,add_impl,"add",1,1)
 OP_DEF(ADDP_OP,addp_impl,"addp",1,1)
 OP_DEF(ADDC_OP,addc_impl,"addc",1,1)
+OP_DEF(AMA_OP,ama_impl,"ama",1,2)
 OP_DEF(AND_OP,and_impl,"and",1,1)
 OP_DEF(ANDN_OP,andn_impl,"andn",1,1)
 OP_DEF(ATOM_OP,atom_impl,"atom",1,3)
@@ -101,6 +102,7 @@ OP_DEF(SHL_OP,shl_impl,"shl",1,1)
 OP_DEF(SHR_OP,shr_impl,"shr",1,1)
 OP_DEF(SIN_OP,sin_impl,"sin",1,4)
 OP_DEF(SLCT_OP,slct_impl,"slct",1,1)
+OP_DEF(SPR_OP,spr_impl,"spr",1,1)
 OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4)
 OP_DEF(SSY_OP,ssy_impl,"ssy",0,3)
 OP_DEF(ST_OP,st_impl,"st",0,5)
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index a44177b..026270a 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -145,6 +145,8 @@ xor     TC; ptx_lval.int_value = XOR_OP; return OPCODE;
 nop     TC; ptx_lval.int_value = NOP_OP; return OPCODE;
 break  TC; ptx_lval.int_value = BREAK_OP; return OPCODE;
 breakaddr  TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE;
+spr TC; ptx_lval.int_value = SPR_OP; return OPCODE;
+ama TC; ptx_lval.int_value = AMA_OP; return OPCODE;
 
 <INITIAL,NOT_OPCODE,IN_INST,IN_FUNC_DECL>{
 
@@ -390,7 +392,9 @@ breakaddr  TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE;
 }
 <IN_COMMENT>{
 "*/"      BEGIN(INITIAL);
-[^*\n]+   // eat comment in chunks
+"CPTX_BEGIN" printf("BEGINNING CUSTOM PTX.\n"); BEGIN(INITIAL);
+[^C*\n]+   // eat comment in chunks
+"C"
 "*"       // eat the lone star
 \n        TC; 
 }
-- 
cgit v1.3


From f7c57e76c086ce417626f37ffc91097c839c687d Mon Sep 17 00:00:00 2001
From: sspenst <spencerspenst@gmail.com>
Date: Mon, 4 Jul 2016 09:43:36 -0700
Subject: Reverted part of the previous commit so that our new changes related
 to DNNs can be done in a different branch

---
 src/cuda-sim/instructions.cc | 10 ----------
 src/cuda-sim/opcodes.def     |  2 --
 src/cuda-sim/ptx.l           |  2 --
 3 files changed, 14 deletions(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 922e14a..02ce01c 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -816,11 +816,6 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread )
 
 void addc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
 
-void ama_impl(  const ptx_instruction *pI, ptx_thread_info *thread )
-{
-	printf("AMA instruction found.\n");	
-}
-
 void and_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
 { 
    ptx_reg_t src1_data, src2_data, data;
@@ -3703,11 +3698,6 @@ void slct_impl( const ptx_instruction *pI, ptx_thread_info *thread )
    thread->set_operand_value(dst,d, i_type, thread, pI);
 }
 
-void spr_impl( const ptx_instruction *pI, ptx_thread_info *thread )
-{
-	printf("SPR instruction found.\n");
-}
-
 void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
 { 
    ptx_reg_t a, d;
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index 33ee0ca..874acc7 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -41,7 +41,6 @@ OP_DEF(ABS_OP,abs_impl,"abs",1,1)
 OP_DEF(ADD_OP,add_impl,"add",1,1)
 OP_DEF(ADDP_OP,addp_impl,"addp",1,1)
 OP_DEF(ADDC_OP,addc_impl,"addc",1,1)
-OP_DEF(AMA_OP,ama_impl,"ama",1,2)
 OP_DEF(AND_OP,and_impl,"and",1,1)
 OP_DEF(ANDN_OP,andn_impl,"andn",1,1)
 OP_DEF(ATOM_OP,atom_impl,"atom",1,3)
@@ -102,7 +101,6 @@ OP_DEF(SHL_OP,shl_impl,"shl",1,1)
 OP_DEF(SHR_OP,shr_impl,"shr",1,1)
 OP_DEF(SIN_OP,sin_impl,"sin",1,4)
 OP_DEF(SLCT_OP,slct_impl,"slct",1,1)
-OP_DEF(SPR_OP,spr_impl,"spr",1,1)
 OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4)
 OP_DEF(SSY_OP,ssy_impl,"ssy",0,3)
 OP_DEF(ST_OP,st_impl,"st",0,5)
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index 026270a..b8ce497 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -145,8 +145,6 @@ xor     TC; ptx_lval.int_value = XOR_OP; return OPCODE;
 nop     TC; ptx_lval.int_value = NOP_OP; return OPCODE;
 break  TC; ptx_lval.int_value = BREAK_OP; return OPCODE;
 breakaddr  TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE;
-spr TC; ptx_lval.int_value = SPR_OP; return OPCODE;
-ama TC; ptx_lval.int_value = AMA_OP; return OPCODE;
 
 <INITIAL,NOT_OPCODE,IN_INST,IN_FUNC_DECL>{
 
-- 
cgit v1.3


From 2683b8bd7ba9950e0aa174915ef9ff64e0a20421 Mon Sep 17 00:00:00 2001
From: speverel <speverelle8@gmail.com>
Date: Mon, 4 Jul 2016 15:07:50 -0700
Subject: Restored madp instruction.

---
 src/cuda-sim/cuda-sim.cc     | 2 +-
 src/cuda-sim/instructions.cc | 5 +++++
 src/cuda-sim/opcodes.def     | 1 +
 src/cuda-sim/ptx.l           | 1 +
 4 files changed, 8 insertions(+), 1 deletion(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index fba3a59..09e9a81 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -719,7 +719,7 @@ void ptx_instruction::set_opcode_and_latency()
 		   break;
 	   }
 	   break;
-   case MAD_OP: case MADC_OP:
+   case MAD_OP: case MADC_OP: case MADP_OP:
 	   //MAD latency
 	   switch(get_type()){
 	   case F32_TYPE:
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 02ce01c..7b0f4fa 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -2496,6 +2496,11 @@ void mad_impl( const ptx_instruction *pI, ptx_thread_info *thread )
    mad_def(pI, thread, false);
 }
 
+void madp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
+{
+   mad_def(pI, thread, true);
+}
+
 void madc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
 {
    mad_def(pI, thread, true);
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index 874acc7..2ee6976 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -70,6 +70,7 @@ OP_DEF(LG2_OP,lg2_impl,"lg2",1,4)
 OP_DEF(MAD24_OP,mad24_impl,"mad24",1,2)
 OP_DEF(MAD_OP,mad_impl,"mad",1,2)
 OP_DEF(MADC_OP,madc_impl,"madc",1,2)
+OP_DEF(MADP_OP,madp_impl,"madp",1,2)
 OP_DEF(MAX_OP,max_impl,"max",1,1)
 OP_DEF(MEMBAR_OP,membar_impl,"membar",1,3)
 OP_DEF(MIN_OP,min_impl,"min",1,1)
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index b8ce497..88ccf6a 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -87,6 +87,7 @@ lg2	TC; ptx_lval.int_value = LG2_OP; return OPCODE;
 mad24   TC; ptx_lval.int_value = MAD24_OP; return OPCODE;
 mad     TC; ptx_lval.int_value = MAD_OP; return OPCODE;
 madc	TC; ptx_lval.int_value = MADC_OP; return OPCODE;
+madp	TC; ptx_lval.int_value = MADP_OP; return OPCODE;
 max     TC; ptx_lval.int_value = MAX_OP; return OPCODE;
 membar  TC; ptx_lval.int_value = MEMBAR_OP; return OPCODE;
 min     TC; ptx_lval.int_value = MIN_OP; return OPCODE;
-- 
cgit v1.3


From 91b2afe09dbeb0fa1c5eb57cd4b416a5eb24bf60 Mon Sep 17 00:00:00 2001
From: sspenst <spencerspenst@gmail.com>
Date: Mon, 4 Jul 2016 16:25:11 -0700
Subject: Initial SST recognition from PTX parser

---
 src/cuda-sim/instructions.cc | 5 +++++
 src/cuda-sim/opcodes.def     | 1 +
 src/cuda-sim/ptx.l           | 1 +
 3 files changed, 7 insertions(+)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 7b0f4fa..36aa29f 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -3734,6 +3734,11 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread )
    thread->set_operand_value(dst,d, i_type, thread, pI);
 }
 
+void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
+{
+	printf("SST instruction found.\n");
+}
+
 void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
 {
    //printf("Execution Warning: unimplemented ssy instruction is treated as a nop\n");
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index 2ee6976..0c0eda9 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -103,6 +103,7 @@ OP_DEF(SHR_OP,shr_impl,"shr",1,1)
 OP_DEF(SIN_OP,sin_impl,"sin",1,4)
 OP_DEF(SLCT_OP,slct_impl,"slct",1,1)
 OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4)
+OP_DEF(SST_OP,sst_impl,"sst",1,1)
 OP_DEF(SSY_OP,ssy_impl,"ssy",0,3)
 OP_DEF(ST_OP,st_impl,"st",0,5)
 OP_DEF(SUB_OP,sub_impl,"sub",1,1)
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index 88ccf6a..1ac047c 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -120,6 +120,7 @@ shr     TC; ptx_lval.int_value = SHR_OP; return OPCODE;
 sin	TC; ptx_lval.int_value = SIN_OP; return OPCODE;
 slct	TC; ptx_lval.int_value = SLCT_OP; return OPCODE;
 sqrt	TC; ptx_lval.int_value = SQRT_OP; return OPCODE;
+sst	TC; ptx_lval.int_value = SST_OP; return OPCODE;
 ssy     TC; ptx_lval.int_value = SSY_OP; return OPCODE;
 st      TC; ptx_lval.int_value = ST_OP; return OPCODE;
 st.volatile TC; ptx_lval.int_value = ST_OP; return OPCODE;
-- 
cgit v1.3


From 6c1fb702e17b00fd7de72ac7dd4a31584d5978b9 Mon Sep 17 00:00:00 2001
From: sspenst <spencerspenst@gmail.com>
Date: Fri, 8 Jul 2016 14:51:44 -0700
Subject: Made gridDim and blockDim global variables so that they can be
 accessed from sst_impl

---
 libcuda/cuda_runtime_api.cc   | 7 +++++--
 src/abstract_hardware_model.h | 3 +++
 src/cuda-sim/instructions.cc  | 3 +--
 src/cuda-sim/opcodes.def      | 2 +-
 4 files changed, 10 insertions(+), 5 deletions(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc
index e8a0e91..3eff4af 100644
--- a/libcuda/cuda_runtime_api.cc
+++ b/libcuda/cuda_runtime_api.cc
@@ -180,6 +180,9 @@ cudaError_t g_last_cudaError = cudaSuccess;
 
 extern stream_manager *g_stream_manager;
 
+dim3 gridDim = (dim3){1,1,1};
+dim3 blockDim = (dim3){1,1,1};
+
 void register_ptx_function( const char *name, function_info *impl )
 {
 	// no longer need this
@@ -959,8 +962,8 @@ __host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun )
 			g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 );
 	kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context);
 	std::string kname = grid->name();
-	dim3 gridDim = config.grid_dim();
-	dim3 blockDim = config.block_dim();
+	gridDim = config.grid_dim();
+	blockDim = config.block_dim();
 	printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n",
 			kname.c_str(), stream?stream->get_uid():0, gridDim.x,gridDim.y,gridDim.z,blockDim.x,blockDim.y,blockDim.z );
 	stream_operation op(grid,g_ptx_sim_mode,stream);
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 6ed9b8e..46c3279 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -162,6 +162,9 @@ struct dim3 {
 };
 #endif
 
+extern dim3 gridDim;
+extern dim3 blockDim;
+
 void increment_x_then_y_then_z( dim3 &i, const dim3 &bound);
 
 class kernel_info_t {
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 8bdb94f..fd3b1fa 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -3772,7 +3772,7 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread )
 	thread->m_last_dram_callback.function = bar_callback;
 	thread->m_last_dram_callback.instruction = cpI;
 
-	int NUM_THREADS = 8; // (how do you get this dynamically?)
+	int NUM_THREADS = blockDim.x * blockDim.y * blockDim.z;
 	if (src2_data.s64 == NUM_THREADS-1) {
 		// pick only one thread to load all of the data back from sstarr memory
 		unsigned offset = 0;
@@ -3809,7 +3809,6 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread )
 		// fill the rest of the array with zeros (dst should always have a 0 in it)
 		while (offset < NUM_THREADS) {
 			mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI);
-			mem->write(addr+((NUM_THREADS+offset)*4),size/8,&dst_data.s64,thread,pI);
 			offset++;
 		}
 
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index 0c0eda9..1af04ea 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -103,7 +103,7 @@ OP_DEF(SHR_OP,shr_impl,"shr",1,1)
 OP_DEF(SIN_OP,sin_impl,"sin",1,4)
 OP_DEF(SLCT_OP,slct_impl,"slct",1,1)
 OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4)
-OP_DEF(SST_OP,sst_impl,"sst",1,1)
+OP_DEF(SST_OP,sst_impl,"sst",1,5)
 OP_DEF(SSY_OP,ssy_impl,"ssy",0,3)
 OP_DEF(ST_OP,st_impl,"st",0,5)
 OP_DEF(SUB_OP,sub_impl,"sub",1,1)
-- 
cgit v1.3


From feda07a5e0053ef2f2bfa382f5ba9a7a0b6c6bf5 Mon Sep 17 00:00:00 2001
From: sspenst <spencerspenst@gmail.com>
Date: Thu, 4 Aug 2016 13:09:41 -0700
Subject: A thread executing BSMAD is now able to access information from all
 threads in its warp

---
 src/abstract_hardware_model.h |   1 +
 src/cuda-sim/cuda-sim.cc      |  14 ++++
 src/cuda-sim/instructions.cc  | 158 ++++++++++++++++++++++++++++++++++++++++++
 src/cuda-sim/opcodes.def      |   3 +
 src/cuda-sim/opcodes.h        |   4 +-
 src/cuda-sim/ptx.l            |   3 +
 6 files changed, 182 insertions(+), 1 deletion(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 6ed9b8e..13dfce3 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -1053,6 +1053,7 @@ class core_t {
         warp_inst_t getExecuteWarp(unsigned warpId);
         void get_pdom_stack_top_info( unsigned warpId, unsigned *pc, unsigned *rpc ) const;
         kernel_info_t * get_kernel_info(){ return m_kernel;}
+        class ptx_thread_info ** get_thread_info() { return m_thread; }
         unsigned get_warp_size() const { return m_warp_size; }
         void and_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] &= value; }
         void or_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] |= value; }
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index e194a2a..059fbe2 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -849,8 +849,10 @@ void ptx_instruction::pre_decode()
 
    switch ( get_opcode() ) {
 #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break;
+#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break;
 #include "opcodes.def"
 #undef OP_DEF
+#undef OP_W_DEF
    default:
       printf( "Execution error: Invalid opcode (0x%x)\n", get_opcode() );
       break;
@@ -1242,10 +1244,22 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
          *((warp_inst_t*)pJ) = inst; // copy active mask information
          pI = pJ;
       }
+      /*const ptx_instruction **pA;
+      if( pI->get_opcode() == BSMAD_OP ) {
+    	  //pA = (const ptx_instruction**)malloc(get_core()->get_warp_size()*(sizeof(ptx_instruction*)));
+    	  pA = (const ptx_instruction**)malloc(8*(sizeof(ptx_instruction*)));
+    	  for (int i = 0; i < get_core()->get_warp_size() && inst.active(i); i++) {
+    		  //pA[i] = get_core()->get_thread_info()[inst.warp_id() * get_core()->get_warp_size() + i]->func_info()->get_instruction(pc+(i-lane_id)*(pI->inst_size()));
+    		  int tid = inst.warp_id() * get_core()->get_warp_size() + i;
+    		  pA[i] = get_core()->get_thread_info()[tid]->func_info()->get_instruction(pc);
+    	  }
+      }*/
       switch ( pI->get_opcode() ) {
 #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break;
+#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break;
 #include "opcodes.def"
 #undef OP_DEF
+#undef OP_W_DEF
       default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break;
       }
       delete pJ;
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index b401bef..618add1 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -47,8 +47,10 @@ unsigned ptx_instruction::g_num_ptx_inst_uid=0;
 
 const char *g_opcode_string[NUM_OPCODES] = {
 #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR,
+#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR,
 #include "opcodes.def"
 #undef OP_DEF
+#undef OP_W_DEF
 };
 
 void inst_not_implemented( const ptx_instruction * pI ) ;
@@ -1456,6 +1458,162 @@ void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread )
 void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
 void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
 
+void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
+{
+	for (int i = 0; i < core->get_warp_size() && inst.active(i); i++) {
+		const operand_info &dst = pI->dst();
+		unsigned type = pI->get_type();
+
+		int tid = inst.warp_id() * core->get_warp_size() + i;
+		ptx_thread_info *thread = core->get_thread_info()[tid];
+		ptx_reg_t data = thread->get_operand_value(dst, dst, type, thread, 1);
+		printf("BSMAD - DATA FROM THREAD %d: %d\n", i, data.u32);
+	}
+	printf("\n");
+	/*const unsigned OPERANDS = 9;
+	// 0 = output
+	// 1 = input precision
+	// 2 = output precision
+	// 3 = buffer0
+	// 4 = buffer1
+	// 5 = buffer2
+	// 6 = buffer3
+	// 7 = synapse value
+	// 8 = output value
+	// as a temporary solution, let 0 be the base address of output, which is an array of shared memory
+	// that will be filled when the last thread completes the bsmad instruction
+	// maybe you can store the addresses of other ptx_instruction in sstarr memory and then update dst later?
+	// not sure if that works
+
+	//ptx_instruction * cpI = const_cast<ptx_instruction *>(pI);
+	const operand_info &src[OPERANDS];
+	ptx_reg_t src_data[OPERANDS];
+	unsigned type = pI->get_type();
+
+	for (int i = 0; i < OPERANDS; i++) {
+		src[i] = pI->operand_lookup(i);
+		src_data[i] = thread->get_operand_value(src[i], src[0], type, thread, 1);
+	}
+
+	memory_space_t space = pI->get_space();
+	memory_space *mem = NULL;
+	addr_t addr = thread->get_tid().x * 24; // 4 bytes per register * 6 registers per thread = 24 bytes
+
+	decode_space(space,thread,src[0],mem,addr);
+
+	size_t size;
+	int t;
+	type_info_key::type_decode(type,size,t);
+
+	// store src_data[1:4] in sstarr memory
+	for (int i = 0; i < 6; i++) {
+		mem->write(addr + i*4,size/8,&src_data[i+3].s64,thread,pI);
+	}
+
+	// sync threads
+	//cpI->set_bar_id(16); // use 16 for sst because bar uses an int from 0-15
+
+	thread->m_last_effective_address = addr;
+	thread->m_last_memory_space = space;
+	thread->m_last_dram_callback.function = bar_callback;
+	thread->m_last_dram_callback.instruction = cpI;
+
+	// the last thread that executes loads all of the data back from sstarr memory
+	ptx_cta_info *cta_info = thread->m_cta_info;((32/ip)*4)/(32/op)
+	const int NUM_THREADS = cta_info->num_threads();
+	cta_info->inc_bar_threads();
+	if (NUM_THREADS == cta_info->get_bar_threads()) {
+		// load all things from sstarr memory
+		addr = 0;
+		ptx_reg_t data;
+		unsigned sstarr_data[NUM_THREADS*6];
+		for (int i = 0; i < NUM_THREADS*6; i++) {
+			data.u64 = 0;
+			mem->read(addr+(i*4),size/8,&data.s64);
+			sstarr_data[i] = data.u32;
+		}
+
+		// unpack registers, add data from across threads
+		unsigned ip = src_data[1].u32;
+		unsigned op = src_data[2].u32;
+		unsigned unpacked_output[(32/ip)*4];
+
+		for (unsigned i = 0; i < (32/ip)*4; i++) {
+			unsigned buf = i/(32/ip);
+			unsigned pos = i%(32/ip);
+
+			unsigned mask = 0;
+			for (int b = 0; b < ip; b++) {
+				mask |= (1 << b);
+			}
+			mask <<= (pos*ip);
+
+			int sum = 0;
+			for (int j = 0; j < NUM_THREADS; j++) {
+				sum += mask & sstarr_data[j*6 + buf];
+			}
+			unpacked_output[i] = sum;
+		}
+
+		// truncate result, repack, store in shared mem
+		unsigned output_regs[((32/ip)*4)/(32/op) + (((32/ip)*4)%(32/op) != 0)];
+
+
+
+		unsigned offset = 0;
+		addr = 0;
+		ptx_reg_t data;
+		float sstarr_fdata[NUM_THREADS];
+		signed long long sstarr_ldata[NUM_THREADS];
+		// loop through all of the threads
+		for (int tid = 0; tid < NUM_THREADS; tid++) {
+			data.u64=0;
+			mem->read(addr+(tid*4),size/8,&data.s64);
+			sstarr_fdata[tid] = data.f32;
+			sstarr_ldata[tid] = data.s64;
+		}
+
+		// squeeze the zeros out of the array and store data back into original array
+		mem = NULL;
+		addr = src1_data.u32;
+		space.set_type(global_space);
+		decode_space(space,thread,src1,mem,addr);
+		// store nonzero entries and indices
+		for (int tid = 0; tid < NUM_THREADS; tid++) {
+			if (sstarr_fdata[tid] != 0) {
+				float ftid = (float)tid;
+				mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI);
+				mem->write(addr+((NUM_THREADS+offset)*4),size/8,&ftid,thread,pI);
+				offset++;
+			}
+		}
+		// store the number of nonzero elements in the array
+		data = thread->get_op((32/ip)*4)/(32/op)erand_value(src1, dst, type, thread, 1);
+		data.s64 += 4*(offset-1);
+		thread->set_operand_value(dst, data, type, thread, pI);
+
+		// fill the rest of the array with zeros (dst should always have a 0 in it)
+		while (offset < NUM_THREADS) {
+			mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI);
+			offset++;
+		}
+
+		cta_info->reset_bar_threads();
+		thread->m_last_effective_address = addr+(NUM_THREADS-1)*4;
+		thread->m_last_memory_space = space;
+	}*/
+}
+
+void bsmul_impl( const ptx_instruction *pI, ptx_thread_info *thread )
+{
+	printf("BSMUL instruction found.\n");
+}
+
+void buf_impl( const ptx_instruction *pI, ptx_thread_info *thread )
+{
+	printf("BUF instruction found.\n");
+}
+
 void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
 {
    static unsigned call_uid_next = 1;
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index 1af04ea..d0e6f25 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -52,6 +52,9 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3)
 OP_DEF(BRX_OP,brx_impl,"brx",0,3)
 OP_DEF(BREV_OP,brev_impl,"brev",1,1)
 OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9)
+OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1)
+OP_DEF(BSMUL_OP,bsmul_impl,"bsmul",1,1)
+OP_DEF(BUF_OP,buf_impl,"buf",0,5)
 OP_DEF(CALL_OP,call_impl,"call",1,3)
 OP_DEF(CALLP_OP,callp_impl,"callp",1,3)
 OP_DEF(CLZ_OP,clz_impl,"clz",1,1)
diff --git a/src/cuda-sim/opcodes.h b/src/cuda-sim/opcodes.h
index 871091c..aa133da 100644
--- a/src/cuda-sim/opcodes.h
+++ b/src/cuda-sim/opcodes.h
@@ -30,9 +30,11 @@
 
 enum opcode_t {
 #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP,
+#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP,
 #include "opcodes.def"
-   NUM_OPCODES
+	NUM_OPCODES
 #undef OP_DEF
+#undef OP_W_DEF
 };
 
 enum special_regs {
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index 69349a0..e0d7b9d 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -68,6 +68,9 @@ bra     TC; ptx_lval.int_value = BRA_OP; return OPCODE;
 brx     TC; ptx_lval.int_value = BRX_OP; return OPCODE;
 brev    TC; ptx_lval.int_value = BREV_OP; return OPCODE;
 brkpt   TC; ptx_lval.int_value = BRKPT_OP; return OPCODE;
+bsmad	TC; ptx_lval.int_value = BSMAD_OP; return OPCODE;
+bsmul	TC; ptx_lval.int_value = BSMUL_OP; return OPCODE;
+buf	TC; ptx_lval.int_value = BUF_OP; return OPCODE;
 call	TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode
 callp    TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE;
 clz	TC; ptx_lval.int_value = CLZ_OP; return OPCODE;
-- 
cgit v1.3


From 9a6b68c5b11fbdb239d25afe60e5135bc2afa88d Mon Sep 17 00:00:00 2001
From: sspenst <spencerspenst@gmail.com>
Date: Fri, 5 Aug 2016 10:16:29 -0700
Subject: bsmad gives the correct output in the small cases I have tried, still
 need to complete the TODOs noted in bsmad_impl

---
 src/cuda-sim/cuda-sim.cc     |  10 --
 src/cuda-sim/instructions.cc | 211 +++++++++++++++++++------------------------
 src/cuda-sim/opcodes.def     |   2 -
 src/cuda-sim/ptx.l           |   2 -
 4 files changed, 95 insertions(+), 130 deletions(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 059fbe2..337463b 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -1244,16 +1244,6 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
          *((warp_inst_t*)pJ) = inst; // copy active mask information
          pI = pJ;
       }
-      /*const ptx_instruction **pA;
-      if( pI->get_opcode() == BSMAD_OP ) {
-    	  //pA = (const ptx_instruction**)malloc(get_core()->get_warp_size()*(sizeof(ptx_instruction*)));
-    	  pA = (const ptx_instruction**)malloc(8*(sizeof(ptx_instruction*)));
-    	  for (int i = 0; i < get_core()->get_warp_size() && inst.active(i); i++) {
-    		  //pA[i] = get_core()->get_thread_info()[inst.warp_id() * get_core()->get_warp_size() + i]->func_info()->get_instruction(pc+(i-lane_id)*(pI->inst_size()));
-    		  int tid = inst.warp_id() * get_core()->get_warp_size() + i;
-    		  pA[i] = get_core()->get_thread_info()[tid]->func_info()->get_instruction(pc);
-    	  }
-      }*/
       switch ( pI->get_opcode() ) {
 #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break;
 #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break;
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 618add1..f58c4f5 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -1460,17 +1460,7 @@ void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not
 
 void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 {
-	for (int i = 0; i < core->get_warp_size() && inst.active(i); i++) {
-		const operand_info &dst = pI->dst();
-		unsigned type = pI->get_type();
-
-		int tid = inst.warp_id() * core->get_warp_size() + i;
-		ptx_thread_info *thread = core->get_thread_info()[tid];
-		ptx_reg_t data = thread->get_operand_value(dst, dst, type, thread, 1);
-		printf("BSMAD - DATA FROM THREAD %d: %d\n", i, data.u32);
-	}
-	printf("\n");
-	/*const unsigned OPERANDS = 9;
+	// operands:
 	// 0 = output
 	// 1 = input precision
 	// 2 = output precision
@@ -1480,65 +1470,61 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 	// 6 = buffer3
 	// 7 = synapse value
 	// 8 = output value
-	// as a temporary solution, let 0 be the base address of output, which is an array of shared memory
-	// that will be filled when the last thread completes the bsmad instruction
-	// maybe you can store the addresses of other ptx_instruction in sstarr memory and then update dst later?
-	// not sure if that works
-
-	//ptx_instruction * cpI = const_cast<ptx_instruction *>(pI);
-	const operand_info &src[OPERANDS];
-	ptx_reg_t src_data[OPERANDS];
-	unsigned type = pI->get_type();
-
-	for (int i = 0; i < OPERANDS; i++) {
-		src[i] = pI->operand_lookup(i);
-		src_data[i] = thread->get_operand_value(src[i], src[0], type, thread, 1);
-	}
-
-	memory_space_t space = pI->get_space();
-	memory_space *mem = NULL;
-	addr_t addr = thread->get_tid().x * 24; // 4 bytes per register * 6 registers per thread = 24 bytes
-
-	decode_space(space,thread,src[0],mem,addr);
-
-	size_t size;
-	int t;
-	type_info_key::type_decode(type,size,t);
-
-	// store src_data[1:4] in sstarr memory
-	for (int i = 0; i < 6; i++) {
-		mem->write(addr + i*4,size/8,&src_data[i+3].s64,thread,pI);
-	}
-
-	// sync threads
-	//cpI->set_bar_id(16); // use 16 for sst because bar uses an int from 0-15
-
-	thread->m_last_effective_address = addr;
-	thread->m_last_memory_space = space;
-	thread->m_last_dram_callback.function = bar_callback;
-	thread->m_last_dram_callback.instruction = cpI;
 
-	// the last thread that executes loads all of the data back from sstarr memory
-	ptx_cta_info *cta_info = thread->m_cta_info;((32/ip)*4)/(32/op)
+	// TODO: what should happen when the output precision is larger than the input precision?
+	// TODO: create a ptx_warp_info that can do the same thing that ptx_cta_info does here
+	ptx_cta_info *cta_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_cta_info;
 	const int NUM_THREADS = cta_info->num_threads();
+	const int NUM_BUFFERS = 4;
 	cta_info->inc_bar_threads();
-	if (NUM_THREADS == cta_info->get_bar_threads()) {
-		// load all things from sstarr memory
-		addr = 0;
-		ptx_reg_t data;
-		unsigned sstarr_data[NUM_THREADS*6];
-		for (int i = 0; i < NUM_THREADS*6; i++) {
-			data.u64 = 0;
-			mem->read(addr+(i*4),size/8,&data.s64);
-			sstarr_data[i] = data.u32;
-		}
 
-		// unpack registers, add data from across threads
-		unsigned ip = src_data[1].u32;
-		unsigned op = src_data[2].u32;
-		unsigned unpacked_output[(32/ip)*4];
+	// threads within the warp are executed sequentially by the simulator, store output in first four registers
+	if (cta_info->get_bar_threads() <= NUM_BUFFERS) {
+		unsigned ip, op; // only get these when i = 0
+		unsigned buffer[inst.active_count()][NUM_BUFFERS];
+		unsigned synapse[inst.active_count()];
+		unsigned output[NUM_BUFFERS];
+
+		// loop through all threads in the warp and get all data
+		for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) {
+			if (inst.active(i)) {
+				const operand_info dst = pI->dst();
+				const operand_info src1 = pI->operand_lookup(1);
+				const operand_info src2 = pI->operand_lookup(2);
+				const operand_info src3 = pI->operand_lookup(3);
+				const operand_info src4 = pI->operand_lookup(4);
+				const operand_info src5 = pI->operand_lookup(5);
+				const operand_info src6 = pI->operand_lookup(6);
+				const operand_info src7 = pI->operand_lookup(7);
+				const operand_info src8 = pI->operand_lookup(8);
+				unsigned type = pI->get_type();
+
+				int tid = inst.warp_id() * core->get_warp_size() + i;
+				ptx_thread_info *thread = core->get_thread_info()[tid];
+
+				// only get precision data once
+				if (j == 0) {
+					ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32;
+					op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32;
+				}
+				// get buffer data and synapse data from each thread
+				buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32;
+				buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32;
+				buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32;
+				buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32;
+				synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32;
+				// get output data from the first 4 threads
+				if (j < NUM_BUFFERS) {
+					output[j] = (thread->get_operand_value(src8, dst, type, thread, 1)).u32;
+				}
+				j++;
+			}
+		}
 
-		for (unsigned i = 0; i < (32/ip)*4; i++) {
+		// unpack registers, compute enough outputs to fill an output register
+		unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned));
+		unsigned buffer_data_start = (32/op)*(cta_info->get_bar_threads()-1);
+		for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*NUM_BUFFERS; i++) {
 			unsigned buf = i/(32/ip);
 			unsigned pos = i%(32/ip);
 
@@ -1550,68 +1536,61 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 
 			int sum = 0;
 			for (int j = 0; j < NUM_THREADS; j++) {
-				sum += mask & sstarr_data[j*6 + buf];
+				sum += (mask & buffer[j][buf]) >> (pos*ip);
 			}
-			unpacked_output[i] = sum;
+			unpacked_output[i - buffer_data_start] = sum;
 		}
 
-		// truncate result, repack, store in shared mem
-		unsigned output_regs[((32/ip)*4)/(32/op) + (((32/ip)*4)%(32/op) != 0)];
-
-
+		// truncate output
+		for (unsigned i = 0; i < 32/op; i++) {
+			int mask = 1, latest_one = -1;
+			unsigned data = unpacked_output[i];
+			for (unsigned j = 0; j < sizeof(unsigned)*8; j++) {
+				int bit = data & mask;
+				if (bit == 1) latest_one = j;
+				data >>= 1;
+			}
+			if (latest_one >= op) {
+				// round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0
+				int round_up = (unpacked_output[i] & (1 << (latest_one-op))) >> (latest_one-op);
+				unsigned shifted_output = unpacked_output[i] >> (latest_one-op+1);
+				// if shifted_output is a number like 1111, don't round up
+				if (shifted_output == (pow(2,op)-1)) round_up = 0;
+				unpacked_output[i] = shifted_output + round_up;
+			}
+		}
 
-		unsigned offset = 0;
-		addr = 0;
-		ptx_reg_t data;
-		float sstarr_fdata[NUM_THREADS];
-		signed long long sstarr_ldata[NUM_THREADS];
-		// loop through all of the threads
-		for (int tid = 0; tid < NUM_THREADS; tid++) {
-			data.u64=0;
-			mem->read(addr+(tid*4),size/8,&data.s64);
-			sstarr_fdata[tid] = data.f32;
-			sstarr_ldata[tid] = data.s64;
+		// create mask of 1s
+		unsigned mask = 0;
+		for (int b = 0; b < op; b++) {
+			mask |= (1 << b);
 		}
 
-		// squeeze the zeros out of the array and store data back into original array
-		mem = NULL;
-		addr = src1_data.u32;
-		space.set_type(global_space);
-		decode_space(space,thread,src1,mem,addr);
-		// store nonzero entries and indices
-		for (int tid = 0; tid < NUM_THREADS; tid++) {
-			if (sstarr_fdata[tid] != 0) {
-				float ftid = (float)tid;
-				mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI);
-				mem->write(addr+((NUM_THREADS+offset)*4),size/8,&ftid,thread,pI);
-				offset++;
-			}
+		// pack the outputs into one register
+		unsigned output_data = 0;
+		for (int i = 0; i < 32/op; i++) {
+			output_data |= (unpacked_output[i] & mask) << (op*i);
 		}
-		// store the number of nonzero elements in the array
-		data = thread->get_op((32/ip)*4)/(32/op)erand_value(src1, dst, type, thread, 1);
-		data.s64 += 4*(offset-1);
-		thread->set_operand_value(dst, data, type, thread, pI);
 
-		// fill the rest of the array with zeros (dst should always have a 0 in it)
-		while (offset < NUM_THREADS) {
-			mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI);
-			offset++;
+		// store the result in the correct thread's output register
+		for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) {
+			if (inst.active(i)) j++;
+			if (j == cta_info->get_bar_threads()) {
+				const operand_info &dst = pI->dst();
+				unsigned type = pI->get_type();
+				int tid = inst.warp_id() * core->get_warp_size() + i;
+				ptx_thread_info *thread = core->get_thread_info()[tid];
+				ptx_reg_t data;
+				data.u32 = output_data;
+				thread->set_operand_value(dst, data, type, thread, pI);
+				break;
+			}
 		}
+	}
 
+	if (cta_info->get_bar_threads() == NUM_THREADS)	{
 		cta_info->reset_bar_threads();
-		thread->m_last_effective_address = addr+(NUM_THREADS-1)*4;
-		thread->m_last_memory_space = space;
-	}*/
-}
-
-void bsmul_impl( const ptx_instruction *pI, ptx_thread_info *thread )
-{
-	printf("BSMUL instruction found.\n");
-}
-
-void buf_impl( const ptx_instruction *pI, ptx_thread_info *thread )
-{
-	printf("BUF instruction found.\n");
+	}
 }
 
 void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index d0e6f25..021eed8 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -53,8 +53,6 @@ OP_DEF(BRX_OP,brx_impl,"brx",0,3)
 OP_DEF(BREV_OP,brev_impl,"brev",1,1)
 OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9)
 OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1)
-OP_DEF(BSMUL_OP,bsmul_impl,"bsmul",1,1)
-OP_DEF(BUF_OP,buf_impl,"buf",0,5)
 OP_DEF(CALL_OP,call_impl,"call",1,3)
 OP_DEF(CALLP_OP,callp_impl,"callp",1,3)
 OP_DEF(CLZ_OP,clz_impl,"clz",1,1)
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index e0d7b9d..001ec04 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -69,8 +69,6 @@ brx     TC; ptx_lval.int_value = BRX_OP; return OPCODE;
 brev    TC; ptx_lval.int_value = BREV_OP; return OPCODE;
 brkpt   TC; ptx_lval.int_value = BRKPT_OP; return OPCODE;
 bsmad	TC; ptx_lval.int_value = BSMAD_OP; return OPCODE;
-bsmul	TC; ptx_lval.int_value = BSMUL_OP; return OPCODE;
-buf	TC; ptx_lval.int_value = BUF_OP; return OPCODE;
 call	TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode
 callp    TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE;
 clz	TC; ptx_lval.int_value = CLZ_OP; return OPCODE;
-- 
cgit v1.3


From 45f95f05a11e916933480422b9075767a4cfdf90 Mon Sep 17 00:00:00 2001
From: sspenst <spencerspenst@gmail.com>
Date: Tue, 9 Aug 2016 19:20:02 -0700
Subject: Changed bsmad_impl to match Ahmed's output. Added latency and
 initiation_interval numbers for bsmad

---
 src/cuda-sim/cuda-sim.cc     | 29 +++++++++++++++++------------
 src/cuda-sim/instructions.cc | 30 ++++++++++++++++++++++++++----
 src/cuda-sim/opcodes.def     |  2 +-
 3 files changed, 44 insertions(+), 17 deletions(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 53ee25b..4bae236 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -66,9 +66,9 @@ char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp;
 
 void ptx_opcocde_latency_options (option_parser_t opp) {
 	option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int,
-			"Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV>"
-			"Default 1,1,19,25,145",
-			"1,1,19,25,145");
+			"Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>"
+			"Default 1,1,19,25,145,1",
+			"1,1,19,25,145,1");
 	option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp,
 			"Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>"
 			"Default 1,1,1,1,30",
@@ -78,9 +78,9 @@ void ptx_opcocde_latency_options (option_parser_t opp) {
 			"Default 8,8,8,8,335",
 			"8,8,8,8,335");
 	option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int,
-			"Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV>"
-			"Default 1,1,4,4,32",
-			"1,1,4,4,32");
+			"Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>"
+			"Default 1,1,4,4,32,1",
+			"1,1,4,4,32,1");
 	option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp,
 			"Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>"
 			"Default 1,1,1,1,5",
@@ -580,10 +580,10 @@ void ptx_instruction::set_bar_type()
 
 void ptx_instruction::set_opcode_and_latency()
 {
-	unsigned int_latency[5];
+	unsigned int_latency[6];
 	unsigned fp_latency[5];
 	unsigned dp_latency[5];
-	unsigned int_init[5];
+	unsigned int_init[6];
 	unsigned fp_init[5];
 	unsigned dp_init[5];
 	/*
@@ -592,19 +592,20 @@ void ptx_instruction::set_opcode_and_latency()
 	 * [2] MUL
 	 * [3] MAD
 	 * [4] DIV
+	 * [5] BSMAD
 	 */
-	sscanf(opcode_latency_int, "%u,%u,%u,%u,%u",
+	sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u",
 			&int_latency[0],&int_latency[1],&int_latency[2],
-			&int_latency[3],&int_latency[4]);
+			&int_latency[3],&int_latency[4],&int_latency[5]);
 	sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u",
 			&fp_latency[0],&fp_latency[1],&fp_latency[2],
 			&fp_latency[3],&fp_latency[4]);
 	sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u",
 			&dp_latency[0],&dp_latency[1],&dp_latency[2],
 			&dp_latency[3],&dp_latency[4]);
-	sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u",
+	sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u",
 			&int_init[0],&int_init[1],&int_init[2],
-			&int_init[3],&int_init[4]);
+			&int_init[3],&int_init[4],&int_init[5]);
 	sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u",
 			&fp_init[0],&fp_init[1],&fp_init[2],
 			&fp_init[3],&fp_init[4]);
@@ -773,6 +774,10 @@ void ptx_instruction::set_opcode_and_latency()
 	  initiation_interval = dp_init[2];
       op = SFU_OP;
       break;
+   case BSMAD_OP:
+	   latency = int_latency[5];
+	   initiation_interval = int_init[5];
+	   break;
    default: 
        break;
    }
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 3b938bb..bb15621 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -1458,6 +1458,26 @@ void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread )
 void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
 void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
 
+unsigned trunc(unsigned num, unsigned precision) {
+	int mask = 1, latest_one = -1;
+	unsigned data = num;
+	for (unsigned j = 0; j < sizeof(unsigned)*8; j++) {
+		int bit = data & mask;
+		if (bit == 1) latest_one = j;
+		data >>= 1;
+	}
+	if (latest_one >= precision) {
+		// round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0
+		//int round_up = (num & (1 << (latest_one-precision))) >> (latest_one-precision);
+		//unsigned shifted_output = num >> (latest_one-precision+1);
+		// if shifted_output is a number like 1111, don't round up
+		//if (shifted_output == (pow(2,precision)-1)) round_up = 0;
+		//num = shifted_output + round_up;
+		num >>= (latest_one-precision+1);
+	}
+	return num;
+}
+
 void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 {
 	// operands:
@@ -1530,16 +1550,18 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 			int sum = 0;
 			unsigned mask = (unsigned)(pow(2,ip)-1) << (pos*ip);
 			for (int j = 0; j < THREADS; j++) {
-				sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j];
+				//sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j];
+				sum += trunc(((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j], op);
 			}
 			// get the previous output
 			mask = (unsigned)(pow(2,op)-1) << (op*(i-buffer_data_start));
 			int past_output = (mask & output) >> (op*(i-buffer_data_start));
-			unpacked_output[i-buffer_data_start] = sum + past_output;
+			unpacked_output[i-buffer_data_start] = trunc(trunc(sum,op) + past_output,op);
+			// truncate sum, truncate (truncated sum + past_output)
 		}
 
 		// truncate output
-		for (unsigned i = 0; i < 32/op; i++) {
+		/*for (unsigned i = 0; i < 32/op; i++) {
 			int mask = 1, latest_one = -1;
 			unsigned data = unpacked_output[i];
 			for (unsigned j = 0; j < sizeof(unsigned)*8; j++) {
@@ -1555,7 +1577,7 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 				if (shifted_output == (pow(2,op)-1)) round_up = 0;
 				unpacked_output[i] = shifted_output + round_up;
 			}
-		}
+		}*/
 
 		// pack the outputs into one register
 		unsigned mask = pow(2,op)-1;
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index 021eed8..b363dca 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -52,7 +52,7 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3)
 OP_DEF(BRX_OP,brx_impl,"brx",0,3)
 OP_DEF(BREV_OP,brev_impl,"brev",1,1)
 OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9)
-OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1)
+OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",1,1)
 OP_DEF(CALL_OP,call_impl,"call",1,3)
 OP_DEF(CALLP_OP,callp_impl,"callp",1,3)
 OP_DEF(CLZ_OP,clz_impl,"clz",1,1)
-- 
cgit v1.3


From 68336f112117bcef5b943650819a6764e9ebf4ce Mon Sep 17 00:00:00 2001
From: sspenst <spencerspenst@gmail.com>
Date: Wed, 24 Aug 2016 15:24:19 -0700
Subject: Added shfl instruction

---
 src/abstract_hardware_model.h |  1 +
 src/cuda-sim/cuda-sim.cc      | 20 +++++++++++-
 src/cuda-sim/instructions.cc  | 75 +++++++++++++++++++++++++++++++++++++++++++
 src/cuda-sim/opcodes.def      |  1 +
 src/cuda-sim/opcodes.h        |  4 ++-
 src/cuda-sim/ptx.l            |  6 ++++
 src/cuda-sim/ptx.y            |  8 +++++
 src/cuda-sim/ptx_ir.cc        |  6 ++++
 src/cuda-sim/ptx_ir.h         |  2 ++
 src/cuda-sim/ptx_sim.cc       | 21 ++++++++++++
 src/cuda-sim/ptx_sim.h        | 12 +++++++
 11 files changed, 154 insertions(+), 2 deletions(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index b29f918..d0c807d 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -1051,6 +1051,7 @@ class core_t {
         warp_inst_t getExecuteWarp(unsigned warpId);
         void get_pdom_stack_top_info( unsigned warpId, unsigned *pc, unsigned *rpc ) const;
         kernel_info_t * get_kernel_info(){ return m_kernel;}
+        class ptx_thread_info ** get_thread_info() { return m_thread; }
         unsigned get_warp_size() const { return m_warp_size; }
         void and_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] &= value; }
         void or_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] |= value; }
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 09e9a81..8bf4ec8 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -769,6 +769,10 @@ void ptx_instruction::set_opcode_and_latency()
 	  initiation_interval = dp_init[2];
       op = SFU_OP;
       break;
+   case SHFL_OP:
+	   latency = 32;
+	   initiation_interval = 15;
+	   break;
    default: 
        break;
    }
@@ -845,8 +849,10 @@ void ptx_instruction::pre_decode()
 
    switch ( get_opcode() ) {
 #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break;
+#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break;
 #include "opcodes.def"
 #undef OP_DEF
+#undef OP_W_DEF
    default:
       printf( "Execution error: Invalid opcode (0x%x)\n", get_opcode() );
       break;
@@ -1240,8 +1246,10 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
       }
       switch ( pI->get_opcode() ) {
 #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break;
+#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break;
 #include "opcodes.def"
 #undef OP_DEF
+#undef OP_W_DEF
       default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break;
       }
       delete pJ;
@@ -1408,6 +1416,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel,
 
    static std::map<unsigned,memory_space*> shared_memory_lookup;
    static std::map<unsigned,ptx_cta_info*> ptx_cta_lookup;
+   static std::map<unsigned,ptx_warp_info*> ptx_warp_lookup;
    static std::map<unsigned,std::map<unsigned,memory_space*> > local_memory_lookup;
 
    if ( *thread_info != NULL ) {
@@ -1486,7 +1495,16 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel,
       kernel.increment_thread_id();
       new_tid += tid;
       ptx_thread_info *thd = new ptx_thread_info(kernel);
-   
+
+      ptx_warp_info *warp_info = NULL;
+      if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) {
+    	  warp_info = new ptx_warp_info(); // num_threads should be threads in the warp
+    	  ptx_warp_lookup[hw_warp_id] = warp_info;
+      } else {
+    	  warp_info = ptx_warp_lookup[hw_warp_id];
+      }
+      thd->m_warp_info = warp_info;
+
       memory_space *local_mem = NULL;
       std::map<unsigned,memory_space*>::iterator l = local_mem_lookup.find(new_tid);
       if ( l != local_mem_lookup.end() ) {
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 7b0f4fa..05ba78f 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -47,8 +47,10 @@ unsigned ptx_instruction::g_num_ptx_inst_uid=0;
 
 const char *g_opcode_string[NUM_OPCODES] = {
 #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR,
+#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR,
 #include "opcodes.def"
 #undef OP_DEF
+#undef OP_W_DEF
 };
 
 void inst_not_implemented( const ptx_instruction * pI ) ;
@@ -3516,6 +3518,79 @@ void set_impl( const ptx_instruction *pI, ptx_thread_info *thread )
 
 }
 
+void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
+{
+	unsigned i_type = pI->get_type();
+	int tid = inst.warp_id() * core->get_warp_size();
+	ptx_thread_info *thread = core->get_thread_info()[tid];
+	ptx_warp_info *warp_info = thread->m_warp_info;
+	int lane = warp_info->get_done_threads();
+	thread = core->get_thread_info()[tid + lane];
+
+	const operand_info &dst = pI->dst();
+	const operand_info &src1 = pI->src1();
+	const operand_info &src2 = pI->src2();
+	const operand_info &src3 = pI->src3();
+	int bval = (thread->get_operand_value(src2, dst, i_type, thread, 1)).u32;
+	int cval = (thread->get_operand_value(src3, dst, i_type, thread, 1)).u32;
+	int mask = cval >> 8;
+	cval &= 0x1F;
+
+	int maxLane = (lane & mask) | (cval & ~mask);
+	int minLane = lane & mask;
+
+	int src_idx;
+	int p;
+	switch(pI->shfl_op()) {
+	case UP_OPTION:
+		src_idx = lane - bval;
+		p = (src_idx >= maxLane);
+		break;
+	case DOWN_OPTION:
+		src_idx = lane + bval;
+		p = (src_idx <= maxLane);
+		break;
+	case BFLY_OPTION:
+		src_idx = lane ^ bval;
+		p = (src_idx <= maxLane);
+		break;
+	case IDX_OPTION:
+		src_idx = minLane | (bval & ~mask);
+		p = (src_idx <= maxLane);
+		break;
+	default:
+		printf("GPGPU-Sim PTX: ERROR: Unrecognized shfl option\n");
+		assert(0);
+		break;
+	}
+	// copy from own lane
+	if (!p) src_idx = lane;
+	// copy input from lane src_idx
+	ptx_reg_t data;
+	/*if (inst.active(src_idx) && i_type == PRED_TYPE) {
+		ptx_thread_info *source = core->get_thread_info()[tid + src_idx];
+		data = source->get_operand_value(src1, dst, i_type, source, 1);
+		data.pred = p;
+	} else {
+		printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for inactive/predicated-off threads in a warp\n");
+		data.u32 = 0;
+	}*/
+	if (inst.active(src_idx)) {
+		ptx_thread_info *source = core->get_thread_info()[tid + src_idx];
+		data = source->get_operand_value(src1, dst, i_type, source, 1);
+	}
+	if (i_type == PRED_TYPE) {
+		data.pred = p;
+	}
+	thread->set_operand_value(dst, data, i_type, thread, pI);
+
+	// keep track of the number of threads that have executed in the warp
+	warp_info->inc_done_threads();
+	if (warp_info->get_done_threads() == inst.active_count()) {
+		warp_info->reset_done_threads();
+	}
+}
+
 void shl_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
 {
    ptx_reg_t a, b, d;
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index 2ee6976..e1b1422 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -98,6 +98,7 @@ OP_DEF(SAD_OP,sad_impl,"sad",1,1)
 OP_DEF(SELP_OP,selp_impl,"selp",1,1)
 OP_DEF(SETP_OP,setp_impl,"setp",1,1)
 OP_DEF(SET_OP,set_impl,"set",1,1)
+OP_W_DEF(SHFL_OP,shfl_impl,"shfl",1,10)
 OP_DEF(SHL_OP,shl_impl,"shl",1,1)
 OP_DEF(SHR_OP,shr_impl,"shr",1,1)
 OP_DEF(SIN_OP,sin_impl,"sin",1,4)
diff --git a/src/cuda-sim/opcodes.h b/src/cuda-sim/opcodes.h
index 871091c..aa133da 100644
--- a/src/cuda-sim/opcodes.h
+++ b/src/cuda-sim/opcodes.h
@@ -30,9 +30,11 @@
 
 enum opcode_t {
 #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP,
+#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP,
 #include "opcodes.def"
-   NUM_OPCODES
+	NUM_OPCODES
 #undef OP_DEF
+#undef OP_W_DEF
 };
 
 enum special_regs {
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index 88ccf6a..8fac4ac 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -115,6 +115,7 @@ sad     TC; ptx_lval.int_value = SAD_OP; return OPCODE;
 selp	TC; ptx_lval.int_value = SELP_OP; return OPCODE;
 setp    TC; ptx_lval.int_value = SETP_OP; return OPCODE;
 set	TC; ptx_lval.int_value = SET_OP; return OPCODE;
+shfl	TC; ptx_lval.int_value = SHFL_OP; return OPCODE;
 shl     TC; ptx_lval.int_value = SHL_OP; return OPCODE;
 shr     TC; ptx_lval.int_value = SHR_OP; return OPCODE;
 sin	TC; ptx_lval.int_value = SIN_OP; return OPCODE;
@@ -329,6 +330,11 @@ breakaddr  TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE;
 
 \.nc	TC; return NC_OPTION;
 
+\.up	TC; return UP_OPTION;
+\.down	TC; return DOWN_OPTION;
+\.bfly	TC; return BFLY_OPTION;
+\.idx	TC; return IDX_OPTION;
+
 \.popc	TC; return ATOMIC_POPC;
 \.and	TC; return ATOMIC_AND;
 \.or	TC; return ATOMIC_OR;
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index 4de39d1..166b15d 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -194,6 +194,10 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 %token  WB_OPTION;
 %token  WT_OPTION;
 %token	NC_OPTION;
+%token	UP_OPTION;
+%token	DOWN_OPTION;
+%token	BFLY_OPTION;
+%token	IDX_OPTION;
 
 %type <int_value> function_decl_header
 %type <ptr_value> function_decl
@@ -451,6 +455,10 @@ option: type_spec
 	| WB_OPTION { add_option(WB_OPTION); }
 	| WT_OPTION { add_option(WT_OPTION); }
 	| NC_OPTION { add_option(NC_OPTION); }
+	| UP_OPTION { add_option(UP_OPTION); }
+	| DOWN_OPTION { add_option(DOWN_OPTION); }
+	| BFLY_OPTION { add_option(BFLY_OPTION); }
+	| IDX_OPTION { add_option(IDX_OPTION); }
 	;
 
 atomic_operation_spec: ATOMIC_AND { add_option(ATOMIC_AND); } 
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index 2eccabc..4cfe1b9 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -1171,6 +1171,12 @@ ptx_instruction::ptx_instruction( int opcode,
 		 break;
 	  case NC_OPTION:
 		 break;
+	  case UP_OPTION:
+	  case DOWN_OPTION:
+	  case BFLY_OPTION:
+	  case IDX_OPTION:
+		  m_shfl_op = last_ptx_inst_option;
+		  break;
       default:
          assert(0);
          break;
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 601a13d..0abbc83 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -993,6 +993,7 @@ public:
    unsigned saturation_mode() const { return m_saturation_mode;}
    unsigned dimension() const { return m_geom_spec;}
    unsigned barrier_op() const {return m_barrier_op;}
+   unsigned shfl_op() const {return m_shfl_op;}
    enum vote_mode_t { vote_any, vote_all, vote_uni, vote_ballot };
    enum vote_mode_t vote_mode() const { return m_vote_mode; }
 
@@ -1058,6 +1059,7 @@ private:
    unsigned            m_compare_op;
    unsigned            m_saturation_mode;
    unsigned 		   m_barrier_op;
+   unsigned			   m_shfl_op;
 
    std::list<int>          m_scalar_type;
    memory_space_t m_space_spec;
diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc
index 09844ae..a3e43aa 100644
--- a/src/cuda-sim/ptx_sim.cc
+++ b/src/cuda-sim/ptx_sim.cc
@@ -128,6 +128,26 @@ unsigned ptx_cta_info::get_sm_idx() const
    return m_sm_idx;
 }
 
+ptx_warp_info::ptx_warp_info()
+{
+	reset_done_threads();
+}
+
+unsigned ptx_warp_info::get_done_threads() const
+{
+	return m_done_threads;
+}
+
+void ptx_warp_info::inc_done_threads()
+{
+	m_done_threads++;
+}
+
+void ptx_warp_info::reset_done_threads()
+{
+	m_done_threads = 0;
+}
+
 unsigned g_ptx_thread_info_uid_next=1;
 unsigned g_ptx_thread_info_delete_count=0;
 
@@ -153,6 +173,7 @@ ptx_thread_info::ptx_thread_info( kernel_info_t &kernel )
    m_last_memory_space = undefined_space; 
    m_branch_taken = 0;
    m_shared_mem = NULL;
+   m_warp_info = NULL;
    m_cta_info = NULL;
    m_local_mem = NULL;
    m_symbol_table = NULL;
diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h
index f926e6d..449511f 100644
--- a/src/cuda-sim/ptx_sim.h
+++ b/src/cuda-sim/ptx_sim.h
@@ -167,6 +167,17 @@ private:
    std::set<ptx_thread_info*>  m_dangling_pointers;
 };
 
+class ptx_warp_info {
+public:
+	ptx_warp_info();
+	unsigned get_done_threads() const;
+	void inc_done_threads();
+	void reset_done_threads();
+
+private:
+	unsigned m_done_threads;
+};
+
 class symbol;
 
 struct stack_entry {
@@ -425,6 +436,7 @@ public:
    dram_callback_t   m_last_dram_callback; 
    memory_space   *m_shared_mem;
    memory_space   *m_local_mem;
+   ptx_warp_info  *m_warp_info;
    ptx_cta_info   *m_cta_info;
    ptx_reg_t m_last_set_operand_value;
 
-- 
cgit v1.3


From 68674d4ba230df0d3bf9f4e5b035f4cf9cfc185b Mon Sep 17 00:00:00 2001
From: negargoli93 <negargoli93@ece.ubc.ca>
Date: Sat, 12 May 2018 16:09:04 -0700
Subject: commit for eece527project

---
 src/abstract_hardware_model.h |   6 +-
 src/cuda-sim/cuda-sim.cc      |  11 ++-
 src/cuda-sim/instructions.cc  | 213 +++++++++++++++++++-----------------------
 src/cuda-sim/opcodes.def      |   2 +-
 src/cuda-sim/ptx.l            |   2 +-
 src/cuda-sim/ptx_ir.h         |  25 +++++
 src/gpgpu-sim/scoreboard.cc   |   4 +
 src/gpgpusim_entrypoint.cc    |   1 -
 8 files changed, 136 insertions(+), 128 deletions(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index cdd9cf3..9dc58d4 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -750,7 +750,7 @@ public:
 };
 
 // the maximum number of destination, source, or address uarch operands in a instruction
-#define MAX_REG_OPERANDS 8
+#define MAX_REG_OPERANDS 32 
 
 struct dram_callback_t {
    dram_callback_t() { function=NULL; instruction=NULL; thread=NULL; }
@@ -825,8 +825,8 @@ public:
 
     address_type reconvergence_pc; // -1 => not a branch, -2 => use function return address
     
-    unsigned out[4];
-    unsigned in[4];
+    unsigned out[8];
+    unsigned in[8];
     unsigned char is_vectorin;
     unsigned char is_vectorout;
     int pred; // predicate register number
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 54d8796..006738a 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -792,9 +792,9 @@ void ptx_instruction::set_opcode_and_latency()
 	  initiation_interval = dp_init[2];
       op = SFU_OP;
       break;
-   case BSMAD_OP:
-	   latency = int_precision/int_lane_width;
-	   initiation_interval = int_init_precision/int_init_lane_width;
+   case MMA_OP:
+	   latency = 64;
+	   initiation_interval = 64;
 	   break;
    case SHFL_OP:
 	   latency = 32;
@@ -1301,6 +1301,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
          *((warp_inst_t*)pJ) = inst; // copy active mask information
          pI = pJ;
       }
+      if((pI->get_opcode()!=MMA_OP)||((pI->get_opcode()==MMA_OP)&&(lane_id==0))){
       switch ( pI->get_opcode() ) {
 #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break;
 #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break;
@@ -1308,7 +1309,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
 #undef OP_DEF
 #undef OP_W_DEF
       default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break;
-      }
+      }}
       delete pJ;
       pI = pI_saved;
       
@@ -1930,7 +1931,7 @@ void functionalCoreSim::executeWarp(unsigned i, bool &allAtBarrier, bool & someO
 {
     if(!m_warpAtBarrier[i] && m_liveThreadCount[i]!=0){
         warp_inst_t inst =getExecuteWarp(i);
-        execute_warp_inst_t(inst,i);
+	execute_warp_inst_t(inst,i);
         if(inst.isatomic()) inst.do_atomic(true);
         if(inst.op==BARRIER_OP || inst.op==MEMORY_BARRIER_OP ) m_warpAtBarrier[i]=true;
         updateSIMTStack( i, &inst );
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 493e307..7903343 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -771,6 +771,17 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread )
    unsigned i_type = pI->get_type();
    src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1);
    src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1);
+   //unsigned warpId_aa,warp_size_aa;
+   //warpId_aa = pI->warp_id();
+   //warp_size_aa=32;
+   //dim3 t=thread->get_tid();
+   //unsigned tid_aa=warp_size_aa*warpId_aa;
+
+   ptx_thread_info *thread2;
+   thread2=thread; 
+   src1_data = thread2->get_operand_value(src1, dst, i_type, thread2, 1);
+   src2_data = thread2->get_operand_value(src2, dst, i_type, thread2, 1);
+
 
    unsigned rounding_mode = pI->rounding_mode();
    int orig_rm = fegetround();
@@ -1483,135 +1494,102 @@ unsigned trunc(unsigned num, unsigned precision) {
 	return num;
 }
 
-void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
+void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 {
-	// operands:
-	// 0 = output
-	// 1 = input precision
-	// 2 = output precision
-	// 3 = buffer0
-	// 4 = buffer1
-	// 5 = buffer2
-	// 6 = buffer3
-	// 7 = synapse value
-	// 8 = output value
+	int i,j,k,thrd;
+	int row,offset;
+	printf("mmaWorld\n");
+   	ptx_reg_t matrix_a[16][16];
+   	ptx_reg_t matrix_b[16][16];
+   	ptx_reg_t matrix_c[16][16];
+   	ptx_reg_t matrix_d[16][16];
+   	ptx_reg_t src_data;
+	ptx_thread_info *thread;
 
-	const operand_info &dst = pI->dst();
-	const operand_info &src1 = pI->src1();
-	const operand_info &src2 = pI->src2();
 	unsigned type = pI->get_type();
 	int tid = inst.warp_id_func() * core->get_warp_size();
-	ptx_thread_info *thread = core->get_thread_info()[tid];
-	const int ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32;
-	const int op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32;
-	const int THREADS = inst.active_count();
-	const int INBUFFERS = 4;
-	const int OUTBUFFERS = (((32/ip)*INBUFFERS) / (32/op)) + ((((32/ip)*INBUFFERS) % (32/op)) != 0);
-	if (OUTBUFFERS > THREADS) {
-		printf("GPGPU-Sim PTX: BSMAD ERROR - Number of output registers required (%d) is greater than the number available (%d)\n", OUTBUFFERS, THREADS);
-		abort();
-	}
-	ptx_warp_info *warp_info = thread->m_warp_info;
-	warp_info->inc_done_threads();
+	const operand_info &dst = pI->operand_lookup(0);
+	
+//NOT WOR	thread = core->get_thread_info()[tid];
+//NOT WOR	const operand_info &src_a=  pI->operand_lookup(1);
+//NOT WOR	src_data= (thread->get_operand_value(src_a, dst, type, thread, 1));
+//NOT WOR 	thread->set_operand_value(dst, src_data, type, thread, pI);
+	for (thrd=0; thrd < core->get_warp_size(); thrd++){
+		row=thrd/2;
+		offset=8*(thrd%2);
+		thread = core->get_thread_info()[tid+thrd];
+		printf("thread=%d:",thrd);
+		for(i=8;i<=31;i++){
+			const operand_info &src_a=  pI->operand_lookup(i);
+			src_data= (thread->get_operand_value(src_a, dst, type, thread, 1));
+			printf("%f ",src_data.f32);
+			if(i<=15)
+				matrix_a[row][offset+(i)%8]=src_data;
+			else if((i>15)&&(i<=23))
+				matrix_b[row][offset+(i)%8]=src_data;
+			else if(i>23)	 
+				matrix_c[row][offset+(i)%8]=src_data;
+			
 
-	// threads within the warp are executed sequentially by the simulator, store output in first four registers
-	if (warp_info->get_done_threads() <= OUTBUFFERS) {
-		unsigned buffer[THREADS][INBUFFERS];
-		unsigned synapse[THREADS];
-		unsigned output;
-
-		// loop through all threads in the warp and get all data
-		for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) {
-			if (inst.active(i)) {
-				const operand_info &src3 = pI->operand_lookup(3);
-				const operand_info &src4 = pI->operand_lookup(4);
-				const operand_info &src5 = pI->operand_lookup(5);
-				const operand_info &src6 = pI->operand_lookup(6);
-				const operand_info &src7 = pI->operand_lookup(7);
-				const operand_info &src8 = pI->operand_lookup(8);
-
-				thread = core->get_thread_info()[tid+i];
-				// get buffer data and synapse data from each thread
-				buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32;
-				buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32;
-				buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32;
-				buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32;
-				synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32;
-				j++;
-				// get output data from the first 4 threads
-				if (j == warp_info->get_done_threads()) {
-					output = (thread->get_operand_value(src8, dst, type, thread, 1)).u32;
-				}
-			}
 		}
+		printf("\n");
+	}
 
-		// unpack registers, compute enough outputs to fill an output register
-		unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned));
-		unsigned buffer_data_start = (32/op)*(warp_info->get_done_threads()-1);
-		for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*INBUFFERS; i++) {
-			unsigned buf = i/(32/ip);
-			unsigned pos = i%(32/ip);
-			// sum values from the buffers
-			int sum = 0;
-			unsigned mask = (unsigned)(pow(2,ip)-1) << (pos*ip);
-			for (int j = 0; j < THREADS; j++) {
-				//sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j];
-				sum += trunc(((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j], op);
-			}
-			// get the previous output
-			mask = (unsigned)(pow(2,op)-1) << (op*(i-buffer_data_start));
-			int past_output = (mask & output) >> (op*(i-buffer_data_start));
-			unpacked_output[i-buffer_data_start] = trunc(trunc(sum,op) + past_output,op);
-			// truncate sum, truncate (truncated sum + past_output)
+	printf("MATRIX_A\n");
+	for (i=0;i<16;i++){
+		for(j=0;j<16;j++){
+			printf("%f ",matrix_a[i][j].f32);
 		}
-
-		// truncate output
-		/*for (unsigned i = 0; i < 32/op; i++) {
-			int mask = 1, latest_one = -1;
-			unsigned data = unpacked_output[i];
-			for (unsigned j = 0; j < sizeof(unsigned)*8; j++) {
-				int bit = data & mask;
-				if (bit == 1) latest_one = j;
-				data >>= 1;
-			}
-			if (latest_one >= op) {
-				// round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0
-				int round_up = (unpacked_output[i] & (1 << (latest_one-op))) >> (latest_one-op);
-				unsigned shifted_output = unpacked_output[i] >> (latest_one-op+1);
-				// if shifted_output is a number like 1111, don't round up
-				if (shifted_output == (pow(2,op)-1)) round_up = 0;
-				unpacked_output[i] = shifted_output + round_up;
-			}
-		}*/
-
-		// pack the outputs into one register
-		unsigned mask = pow(2,op)-1;
-		unsigned output_data = 0;
-		for (int i = 0; i < 32/op; i++) {
-			output_data |= (unpacked_output[i] & mask) << (op*i);
+		printf("\n");
+	}	
+	printf("MATRIX_B\n");
+	for (i=0;i<16;i++){
+		for(j=0;j<16;j++){
+			printf("%f ",matrix_b[i][j].f32);
 		}
-
-		// store the result in the correct thread's output register
-		for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) {
-			if (inst.active(i)) j++;
-			if (j == warp_info->get_done_threads()) {
-				thread = core->get_thread_info()[tid+i];
-				ptx_reg_t data;
-				data.u32 = output_data;
-				thread->set_operand_value(dst, data, type, thread, pI);
-				break;
+		printf("\n");
+	}	
+	printf("MATRIX_C\n");
+	for (i=0;i<16;i++){
+		for(j=0;j<16;j++){
+			printf("%f ",matrix_c[i][j].f32);
+		}
+		printf("\n");
+	}	
+	for (i=0;i<16;i++){
+		for(j=0;j<16;j++){
+				matrix_d[i][j].f32=0;
+		}
+	}
+	
+	for (i=0;i<16;i++){
+		for(j=0;j<16;j++){
+			for(k=0;k<16;k++){
+				matrix_d[i][j].f32=matrix_d[i][j].f32+matrix_a[i][k].f32*matrix_b[j][k].f32;
 			}
+			matrix_d[i][j].f32+=matrix_c[i][j].f32;
 		}
 	}
-
-	// once the warp has finished, set the number of completed threads back to 0 for the next warp
-	if (warp_info->get_done_threads() == THREADS)	{
-		warp_info->reset_done_threads();
+	printf("MATRIX_D\n");
+	for (i=0;i<16;i++){
+		for(j=0;j<16;j++){
+			printf("%f ",matrix_d[i][j].f32);
+		}
+		printf("\n");
+	}	
+	for (thrd=0; thrd < core->get_warp_size(); thrd++){
+		thread = core->get_thread_info()[tid+thrd];
+		row=thrd/2;
+		offset=8*(thrd%2);
+		for(i=0;i<8;i++){
+			const operand_info &dst = pI->operand_lookup(i);
+			const symbol *r2;
+			r2=dst.get_symbol();
+			printf("thrd=%d,i=%d,register%s, data=%f\n",thrd,i,(r2->name()).c_str(),matrix_d[row][offset+i].f32);
+			thread->set_operand_value(dst, matrix_d[row][offset+i], type, thread, pI);
+		}
 	}
-
-	// set the latency assuming 4 bits of each input get processed every cycle
-	// mutable latency variable???
-	//pI->latency = (ip+3)/4;
+   
 }
 
 void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
@@ -4098,7 +4076,8 @@ void st_impl( const ptx_instruction *pI, ptx_thread_info *thread )
    if (!vector_spec) {
       data = thread->get_operand_value(src1, dst, type, thread, 1);
       mem->write(addr,size/8,&data.s64,thread,pI);
-   } else {
+      printf("addr=%d data=%d\n",addr,data.s64);
+    } else {
       if (vector_spec == V2_TYPE) {
          ptx_reg_t* ptx_regs = new ptx_reg_t[2]; 
          thread->get_vector_operand_values(src1, ptx_regs, 2); 
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index 41f2f22..a3cc83f 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -52,7 +52,7 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3)
 OP_DEF(BRX_OP,brx_impl,"brx",0,3)
 OP_DEF(BREV_OP,brev_impl,"brev",1,1)
 OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9)
-OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",1,1)
+OP_W_DEF(MMA_OP,mma_impl,"mma",1,1)
 OP_DEF(CALL_OP,call_impl,"call",1,3)
 OP_DEF(CALLP_OP,callp_impl,"callp",1,3)
 OP_DEF(CLZ_OP,clz_impl,"clz",1,1)
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index 7620134..e07e339 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -68,7 +68,7 @@ bra     TC; ptx_lval.int_value = BRA_OP; return OPCODE;
 brx     TC; ptx_lval.int_value = BRX_OP; return OPCODE;
 brev    TC; ptx_lval.int_value = BREV_OP; return OPCODE;
 brkpt   TC; ptx_lval.int_value = BRKPT_OP; return OPCODE;
-bsmad	TC; ptx_lval.int_value = BSMAD_OP; return OPCODE;
+mma	TC; ptx_lval.int_value = MMA_OP; return OPCODE;
 call	TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode
 callp    TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE;
 clz	TC; ptx_lval.int_value = CLZ_OP; return OPCODE;
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 4c10373..0601b97 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -948,6 +948,31 @@ public:
       assert( m_operands.size() > 3 );
       return m_operands[3];
    }
+   const operand_info &src4() const 
+   { 
+      assert( m_operands.size() > 4 );
+      return m_operands[4];
+   }
+   const operand_info &src5() const 
+   { 
+      assert( m_operands.size() > 5 );
+      return m_operands[5];
+   }
+   const operand_info &src6() const 
+   { 
+      assert( m_operands.size() > 6 );
+      return m_operands[6];
+   }
+   const operand_info &src7() const 
+   { 
+      assert( m_operands.size() > 7 );
+      return m_operands[7];
+   }
+   const operand_info &src8() const 
+   { 
+      assert( m_operands.size() > 8 );
+      return m_operands[8];
+   }
 
    const operand_info &operand_lookup( unsigned n ) const
    {
diff --git a/src/gpgpu-sim/scoreboard.cc b/src/gpgpu-sim/scoreboard.cc
index f412054..b538fdf 100644
--- a/src/gpgpu-sim/scoreboard.cc
+++ b/src/gpgpu-sim/scoreboard.cc
@@ -146,6 +146,10 @@ bool Scoreboard::checkCollision( unsigned wid, const class inst_t *inst ) const
 	if(inst->in[1] > 0) inst_regs.insert(inst->in[1]);
 	if(inst->in[2] > 0) inst_regs.insert(inst->in[2]);
 	if(inst->in[3] > 0) inst_regs.insert(inst->in[3]);
+        if(inst->in[3] > 0) inst_regs.insert(inst->in[4]);
+        if(inst->in[3] > 0) inst_regs.insert(inst->in[5]);
+        if(inst->in[3] > 0) inst_regs.insert(inst->in[6]);
+        if(inst->in[3] > 0) inst_regs.insert(inst->in[7]);
 	if(inst->pred > 0) inst_regs.insert(inst->pred);
 	if(inst->ar1 > 0) inst_regs.insert(inst->ar1);
 	if(inst->ar2 > 0) inst_regs.insert(inst->ar2);
diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc
index 04845e7..a6d7eb4 100644
--- a/src/gpgpusim_entrypoint.cc
+++ b/src/gpgpusim_entrypoint.cc
@@ -134,7 +134,6 @@ void *gpgpu_sim_thread_concurrent(void*)
                 gpgpu_cuda_ptx_sim_main_func(*kernel);
                 g_the_gpu->finish_functional_sim(kernel);
             }
-
             //performance simulation
             if( g_the_gpu->active() ) {
                 g_the_gpu->cycle();
-- 
cgit v1.3


From 7dfa2ae2e6f8ccaaf133318265a7ab00de546e82 Mon Sep 17 00:00:00 2001
From: aamir <araihan@ece.ubc.ca>
Date: Sun, 27 May 2018 14:18:53 -0700
Subject: added wmma parsing but execution getting aborted

---
 cuda-kernels/Makefile                              |    7 +
 cuda-kernels/_cuobjdump_1.elf                      |   15 +
 cuda-kernels/_cuobjdump_1.ptx                      |  170 ++++
 cuda-kernels/_cuobjdump_1.sass                     |    2 +
 cuda-kernels/_cuobjdump_2.elf                      |  494 +++++++++
 cuda-kernels/_cuobjdump_2.sass                     |  348 +++++++
 cuda-kernels/_cuobjdump_complete_output_EIGzTK     | 1055 ++++++++++++++++++++
 cuda-kernels/_cuobjdump_complete_output_rndQyq     | 1055 ++++++++++++++++++++
 cuda-kernels/config_fermi_islip.icnt               |   70 ++
 cuda-kernels/gpgpu_inst_stats.txt                  |    1 +
 cuda-kernels/gpgpusim.config                       |  149 +++
 ...usim_power_report__Sun-May-27-14-17-34-2018.log |  324 ++++++
 ...usim_power_report__Sun-May-27-14-17-47-2018.log |  324 ++++++
 cuda-kernels/gpuwattch_gtx1080Ti.xml               |  538 ++++++++++
 cuda-kernels/tensor_core                           |  Bin 0 -> 48541 bytes
 cuda-kernels/tensor_core.cu                        |  250 +++++
 cuobjdump_to_ptxplus/ptx_parser.h                  |    2 +
 src/cuda-sim/instructions.cc                       |    8 +-
 src/cuda-sim/opcodes.def                           |    2 +
 src/cuda-sim/opcodes.h                             |   11 +-
 src/cuda-sim/ptx.l                                 |   18 +-
 src/cuda-sim/ptx.y                                 |   10 +
 src/cuda-sim/ptx_ir.cc                             |    6 +-
 src/cuda-sim/ptx_ir.h                              |   33 +
 src/cuda-sim/ptx_parser.cc                         |   33 +-
 src/cuda-sim/ptx_parser.h                          |    2 +
 26 files changed, 4918 insertions(+), 9 deletions(-)
 create mode 100755 cuda-kernels/Makefile
 create mode 100644 cuda-kernels/_cuobjdump_1.elf
 create mode 100644 cuda-kernels/_cuobjdump_1.ptx
 create mode 100644 cuda-kernels/_cuobjdump_1.sass
 create mode 100644 cuda-kernels/_cuobjdump_2.elf
 create mode 100644 cuda-kernels/_cuobjdump_2.sass
 create mode 100644 cuda-kernels/_cuobjdump_complete_output_EIGzTK
 create mode 100644 cuda-kernels/_cuobjdump_complete_output_rndQyq
 create mode 100755 cuda-kernels/config_fermi_islip.icnt
 create mode 100755 cuda-kernels/gpgpu_inst_stats.txt
 create mode 100755 cuda-kernels/gpgpusim.config
 create mode 100644 cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log
 create mode 100644 cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log
 create mode 100755 cuda-kernels/gpuwattch_gtx1080Ti.xml
 create mode 100755 cuda-kernels/tensor_core
 create mode 100644 cuda-kernels/tensor_core.cu

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/cuda-kernels/Makefile b/cuda-kernels/Makefile
new file mode 100755
index 0000000..51a7760
--- /dev/null
+++ b/cuda-kernels/Makefile
@@ -0,0 +1,7 @@
+all: tensor_core.cu
+	nvcc -arch=sm_70 -lcudart -g -o tensor_core tensor_core.cu
+
+.PHONY:
+clean:
+	rm tensorcore 
+#	nvcc -arch=sm_70 --gpu-architecture=compute_50 --gpu-code=compute_50 -lcudart -g -o tensor_core tensor_core.cu
diff --git a/cuda-kernels/_cuobjdump_1.elf b/cuda-kernels/_cuobjdump_1.elf
new file mode 100644
index 0000000..672b0f0
--- /dev/null
+++ b/cuda-kernels/_cuobjdump_1.elf
@@ -0,0 +1,15 @@
+64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546
+Sections:
+Index Offset   Size ES Align   Type   Flags Link     Info Name
+    1     40     32  0  1    STRTAB       0    0        0 .shstrtab
+    2     72     32  0  1    STRTAB       0    0        0 .strtab
+    3     a8     18 18  8    SYMTAB       0    2        0 .symtab
+
+.section .strtab
+
+.section .shstrtab
+
+.section .symtab
+ index           value           size      info    other  shndx    name  
+   0               0               0        0        0      0     (null)
+
diff --git a/cuda-kernels/_cuobjdump_1.ptx b/cuda-kernels/_cuobjdump_1.ptx
new file mode 100644
index 0000000..3453f4a
--- /dev/null
+++ b/cuda-kernels/_cuobjdump_1.ptx
@@ -0,0 +1,170 @@
+
+
+
+
+
+
+
+.version 6.0
+.target sm_70
+.address_size 64
+
+
+.extern .func (.param .b32 func_retval0) vprintf
+(
+.param .b64 vprintf_param_0,
+.param .b64 vprintf_param_1
+)
+;
+.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0};
+
+.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff(
+.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0,
+.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1,
+.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2,
+.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3,
+.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4,
+.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5,
+.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6,
+.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7
+)
+{
+.local .align 8 .b8 __local_depot0[8];
+.reg .b64 %SP;
+.reg .b64 %SPL;
+.reg .pred %p<6>;
+.reg .f32 %f<34>;
+.reg .b32 %r<38>;
+.reg .b64 %rd<18>;
+
+
+mov.u64 %rd17, __local_depot0;
+cvta.local.u64 %SP, %rd17;
+ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0];
+ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1];
+ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2];
+ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3];
+ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4];
+ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5];
+
+	mov.u32 %r6, %clock;
+
+	mov.u32 %r8, %ntid.x;
+mov.u32 %r9, %ctaid.x;
+mov.u32 %r10, %tid.x;
+mad.lo.s32 %r11, %r8, %r9, %r10;
+mov.u32 %r12, WARP_SZ;
+div.u32 %r13, %r11, %r12;
+mov.u32 %r14, %ntid.y;
+mov.u32 %r15, %ctaid.y;
+mov.u32 %r16, %tid.y;
+mad.lo.s32 %r17, %r14, %r15, %r16;
+shl.b32 %r2, %r13, 4;
+shl.b32 %r3, %r17, 4;
+setp.lt.s32	%p1, %r2, %r4;
+setp.gt.s32	%p2, %r5, 0;
+and.pred %p3, %p1, %p2;
+setp.lt.s32	%p4, %r3, %r7;
+and.pred %p5, %p3, %p4;
+mov.f32 %f26, 0f00000000;
+mov.f32 %f27, %f26;
+mov.f32 %f28, %f26;
+mov.f32 %f29, %f26;
+mov.f32 %f30, %f26;
+mov.f32 %f31, %f26;
+mov.f32 %f32, %f26;
+mov.f32 %f33, %f26;
+@!%p5 bra BB0_2;
+bra.uni BB0_1;
+
+BB0_1:
+mul.wide.s32 %rd4, %r2, 2;
+add.s64 %rd5, %rd1, %rd4;
+wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4;
+mul.wide.s32 %rd6, %r3, 2;
+add.s64 %rd7, %rd2, %rd6;
+wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5;
+mov.f32 %f25, 0f00000000;
+wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25};
+
+BB0_2:
+add.u64 %rd8, %SP, 0;
+cvta.to.local.u64 %rd9, %rd8;
+mul.lo.s32 %r35, %r3, %r4;
+cvt.s64.s32	%rd10, %r35;
+cvt.s64.s32	%rd11, %r2;
+add.s64 %rd12, %rd10, %rd11;
+shl.b64 %rd13, %rd12, 2;
+add.s64 %rd14, %rd3, %rd13;
+wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4;
+
+	mov.u32 %r34, %clock;
+
+	sub.s32 %r36, %r34, %r6;
+st.local.u32 [%rd9], %r36;
+mov.u64 %rd15, $str;
+cvta.global.u64 %rd16, %rd15;
+
+	{
+.reg .b32 temp_param_reg;
+
+	.param .b64 param0;
+st.param.b64	[param0+0], %rd16;
+.param .b64 param1;
+st.param.b64	[param1+0], %rd8;
+.param .b32 retval0;
+call.uni (retval0), 
+vprintf, 
+(
+param0, 
+param1
+);
+ld.param.b32	%r37, [retval0+0];
+
+
+	}
+	ret;
+}
+
+
+.visible .entry _Z17convertFp32ToFp16P6__halfPfi(
+.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0,
+.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1,
+.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2
+)
+{
+.reg .pred %p<2>;
+.reg .b16 %rs<2>;
+.reg .f32 %f<2>;
+.reg .b32 %r<6>;
+.reg .b64 %rd<9>;
+
+
+ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0];
+ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1];
+ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2];
+mov.u32 %r3, %ntid.x;
+mov.u32 %r4, %ctaid.x;
+mov.u32 %r5, %tid.x;
+mad.lo.s32 %r1, %r4, %r3, %r5;
+setp.ge.s32	%p1, %r1, %r2;
+@%p1 bra BB1_2;
+
+cvta.to.global.u64 %rd3, %rd2;
+mul.wide.s32 %rd4, %r1, 4;
+add.s64 %rd5, %rd3, %rd4;
+ld.global.f32 %f1, [%rd5];
+
+	{ cvt.rn.f16.f32 %rs1, %f1;}
+
+
+	cvta.to.global.u64 %rd6, %rd1;
+mul.wide.s32 %rd7, %r1, 2;
+add.s64 %rd8, %rd6, %rd7;
+st.global.u16 [%rd8], %rs1;
+
+BB1_2:
+ret;
+}
+
+
diff --git a/cuda-kernels/_cuobjdump_1.sass b/cuda-kernels/_cuobjdump_1.sass
new file mode 100644
index 0000000..2aac29a
--- /dev/null
+++ b/cuda-kernels/_cuobjdump_1.sass
@@ -0,0 +1,2 @@
+	code for sm_70
+
diff --git a/cuda-kernels/_cuobjdump_2.elf b/cuda-kernels/_cuobjdump_2.elf
new file mode 100644
index 0000000..c03b06d
--- /dev/null
+++ b/cuda-kernels/_cuobjdump_2.elf
@@ -0,0 +1,494 @@
+64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546
+Sections:
+Index Offset   Size ES Align   Type   Flags Link     Info Name
+    1     40    21b  0  1    STRTAB       0    0        0 .shstrtab
+    2    25b    273  0  1    STRTAB       0    0        0 .strtab
+    3    4d0    108 18  8    SYMTAB       0    2        7 .symtab
+    4    5d8     e0  0  1  PROGBITS       0    0        0 .debug_frame
+    5    6b8     48  0  4 CUDA_INFO       0    3        0 .nv.info
+    6    700     50  0  4 CUDA_INFO       0    3        d .nv.info._Z17convertFp32ToFp16P6__halfPfi
+    7    750     ac  0  4 CUDA_INFO       0    3        e .nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff
+    8    800     30 10  8       REL       0    3        e .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff
+    9    830     30 18  8      RELA       0    3        e .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff
+    a    860     20 10  8       REL       0    3        4 .rel.debug_frame
+    b    880    174  0  4  PROGBITS       2    0        d .nv.constant0._Z17convertFp32ToFp16P6__halfPfi
+    c    9f4    18c  0  4  PROGBITS       2    0        e .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff
+    d    b80    100  0 80  PROGBITS       6    3  9000008 .text._Z17convertFp32ToFp16P6__halfPfi
+    e    c80    980  0 80  PROGBITS       6    3 20000009 .text._Z12wmma_exampleP6__halfS0_Pfiiiff
+    f   1600      9  0 10  PROGBITS       3    0        0 .nv.global.init
+
+.section .strtab
+
+.section .shstrtab
+
+.section .symtab
+ index           value           size      info    other  shndx    name  
+   0               0               0        0        0      0     (null)
+   1               0               0        3        0      d     .text._Z17convertFp32ToFp16P6__halfPfi
+   2               0               0        3        0      f     .nv.global.init
+   3               0               9        1        0      f     $str
+   4               0               0        3        0      b     .nv.constant0._Z17convertFp32ToFp16P6__halfPfi
+   5               0               0        3        0      e     .text._Z12wmma_exampleP6__halfS0_Pfiiiff
+   6               0               0        3        0      c     .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff
+   7               0               0        3        0      4     .debug_frame
+   8               0             256       12       10      d     _Z17convertFp32ToFp16P6__halfPfi
+   9               0            2432       12       10      e     _Z12wmma_exampleP6__halfS0_Pfiiiff
+  10               0               0       12        0      0     vprintf
+
+
+.nv.constant0._Z17convertFp32ToFp16P6__halfPfi
+0x00000000  0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+
+
+
+.nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff
+0x00000000  0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  0x00000000  0x00000000  
+0x00000000  0x00000000  
+
+
+.nv.global.init
+0x636f6c63  0x64253d6b   0 
+
+
+.nv.info
+	<0x1>
+	Attribute:	EIATTR_MAX_STACK_SIZE
+	Format:	EIFMT_SVAL
+	Value:	0x9 0x0 
+	<0x2>
+	Attribute:	EIATTR_MIN_STACK_SIZE
+	Format:	EIFMT_SVAL
+	Value:	function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9)	min stack size: 0x8
+	<0x3>
+	Attribute:	EIATTR_FRAME_SIZE
+	Format:	EIFMT_SVAL
+	Value:	function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9)	frame size: 0x8
+	<0x4>
+	Attribute:	EIATTR_MAX_STACK_SIZE
+	Format:	EIFMT_SVAL
+	Value:	0x8 0x0 
+	<0x5>
+	Attribute:	EIATTR_MIN_STACK_SIZE
+	Format:	EIFMT_SVAL
+	Value:	function: _Z17convertFp32ToFp16P6__halfPfi(0x8)	min stack size: 0x0
+	<0x6>
+	Attribute:	EIATTR_FRAME_SIZE
+	Format:	EIFMT_SVAL
+	Value:	function: _Z17convertFp32ToFp16P6__halfPfi(0x8)	frame size: 0x0
+
+
+.nv.info._Z17convertFp32ToFp16P6__halfPfi
+	<0x1>
+	Attribute:	EIATTR_PARAM_CBANK
+	Format:	EIFMT_SVAL
+	Value:	0x4 0x140160 
+	<0x2>
+	Attribute:	EIATTR_CBANK_PARAM_SIZE
+	Format:	EIFMT_HVAL
+	Value:	0x14
+	<0x3>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
+	Value:	Index : 0x0	Ordinal : 0x2	Offset  : 0x10	Size    : 0x4
+		Pointee's logAlignment : 0x0	Space : 0x0	cbank : 0x1f	Parameter Space : CBANK	
+	<0x4>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
+	Value:	Index : 0x0	Ordinal : 0x1	Offset  : 0x8	Size    : 0x8
+		Pointee's logAlignment : 0x0	Space : 0x0	cbank : 0x1f	Parameter Space : CBANK	
+	<0x5>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
+	Value:	Index : 0x0	Ordinal : 0x0	Offset  : 0x0	Size    : 0x8
+		Pointee's logAlignment : 0x0	Space : 0x0	cbank : 0x1f	Parameter Space : CBANK	
+	<0x6>
+	Attribute:	EIATTR_MAXREG_COUNT
+	Format:	EIFMT_HVAL
+	Value:	0xff
+	<0x7>
+	Attribute:	EIATTR_EXIT_INSTR_OFFSETS
+	Format:	EIFMT_SVAL
+	Value:	0x60 0xe0 
+
+
+.nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff
+	<0x1>
+	Attribute:	EIATTR_PARAM_CBANK
+	Format:	EIFMT_SVAL
+	Value:	0x6 0x2c0160 
+	<0x2>
+	Attribute:	EIATTR_CBANK_PARAM_SIZE
+	Format:	EIFMT_HVAL
+	Value:	0x2c
+	<0x3>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
+	Value:	Index : 0x0	Ordinal : 0x7	Offset  : 0x28	Size    : 0x4
+		Pointee's logAlignment : 0x0	Space : 0x0	cbank : 0x1f	Parameter Space : CBANK	
+	<0x4>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
+	Value:	Index : 0x0	Ordinal : 0x6	Offset  : 0x24	Size    : 0x4
+		Pointee's logAlignment : 0x0	Space : 0x0	cbank : 0x1f	Parameter Space : CBANK	
+	<0x5>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
+	Value:	Index : 0x0	Ordinal : 0x5	Offset  : 0x20	Size    : 0x4
+		Pointee's logAlignment : 0x0	Space : 0x0	cbank : 0x1f	Parameter Space : CBANK	
+	<0x6>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
+	Value:	Index : 0x0	Ordinal : 0x4	Offset  : 0x1c	Size    : 0x4
+		Pointee's logAlignment : 0x0	Space : 0x0	cbank : 0x1f	Parameter Space : CBANK	
+	<0x7>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
+	Value:	Index : 0x0	Ordinal : 0x3	Offset  : 0x18	Size    : 0x4
+		Pointee's logAlignment : 0x0	Space : 0x0	cbank : 0x1f	Parameter Space : CBANK	
+	<0x8>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
+	Value:	Index : 0x0	Ordinal : 0x2	Offset  : 0x10	Size    : 0x8
+		Pointee's logAlignment : 0x0	Space : 0x0	cbank : 0x1f	Parameter Space : CBANK	
+	<0x9>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
+	Value:	Index : 0x0	Ordinal : 0x1	Offset  : 0x8	Size    : 0x8
+		Pointee's logAlignment : 0x0	Space : 0x0	cbank : 0x1f	Parameter Space : CBANK	
+	<0x10>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
+	Value:	Index : 0x0	Ordinal : 0x0	Offset  : 0x0	Size    : 0x8
+		Pointee's logAlignment : 0x0	Space : 0x0	cbank : 0x1f	Parameter Space : CBANK	
+	<0x11>
+	Attribute:	EIATTR_MAXREG_COUNT
+	Format:	EIFMT_HVAL
+	Value:	0xff
+	<0x12>
+	Attribute:	EIATTR_EXIT_INSTR_OFFSETS
+	Format:	EIFMT_SVAL
+	Value:	0x940 
+	<0x13>
+	Attribute:	EIATTR_EXTERNS
+	Format:	EIFMT_SVAL
+	Value:	externs:	vprintf(0xa)	
+	<0x14>
+	Attribute:	EIATTR_CRS_STACK_SIZE
+	Format:	EIFMT_SVAL
+	Value:	0x0 
+
+
+.text._Z17convertFp32ToFp16P6__halfPfi
+bar = 0	reg = 9	lmem=0	smem=0
+0xfffff389  0x000000ff  0x000e00ff  0x000fe200  
+0x00017a02  0x00000a00  0x00000f00  0x000fd000  
+0x00047919  0x00000000  0x00002500  0x000e2200  
+0x00027919  0x00000000  0x00002100  0x000e2400  
+0x04047a24  0x00000000  0x078e0202  0x001fca00  
+0x04007a0c  0x00005c00  0x03f062f0  0x000fd800  
+0x0000094d  0x00000000  0x03800000  0x000fea00  
+0x00027802  0x00000004  0x00000f00  0x000fca00  
+0x04027625  0x00005a00  0x078e0202  0x000fd400  
+0x02027381  0x00000000  0x001ee900  0x000e2200  
+0x00057802  0x00000002  0x00000f00  0x000fca00  
+0x04047625  0x00005800  0x078e0205  0x000fe200  
+0x00067304  0x00000002  0x00200800  0x001e3200  
+0x04007386  0x00000006  0x0010e500  0x0011e200  
+0x0000794d  0x00000000  0x03800000  0x000fea00  
+0x00007947  0xfffffff0  0x0383ffff  0x000fc000  
+
+
+
+.text._Z12wmma_exampleP6__halfS0_Pfiiiff
+bar = 0	reg = 32	lmem=0	smem=0
+0xfffff389  0x000000ff  0x000e00ff  0x000fe200  
+0xff017624  0x00000a00  0x078e00ff  0x000fd000  
+0x01017810  0xfffffff8  0x07ffe0ff  0x000fc800  
+0x01027a10  0x00000800  0x07f1e0ff  0x000fca00  
+0xff007624  0x00000900  0x000e06ff  0x000fd000  
+0x00037805  0x00000000  0x00005000  0x000fd000  
+0x00077906  0x00000020  0x00209000  0x000e2400  
+0x00077308  0x00000007  0x00001000  0x001e2200  
+0x00067919  0x00000000  0x00002500  0x000e6200  
+0x00097919  0x00000000  0x00002100  0x000e6200  
+0x07087810  0x0ffffffe  0x07ffe0ff  0x001fcc00  
+0x00057305  0x00000008  0x0021f000  0x0000a200  
+0xff047224  0x000000ff  0x078e00ff  0x000fe400  
+0x06067a24  0x00000000  0x078e0209  0x002fe400  
+0x050a7824  0xffffffe0  0x078e00ff  0x004fc800  
+0x05047225  0x0000000a  0x078e0004  0x000fd000  
+0x05047225  0x00000006  0x078e00ff  0x000fcc00  
+0xff047224  0x000000ff  0x078e0a05  0x000fc800  
+0x04067824  0x00000020  0x078e0206  0x000fca00  
+0x0600780c  0x00000020  0x03f060f0  0x040fe200  
+0x001c7919  0x00000000  0x00002600  0x000e2200  
+0x00077919  0x00000000  0x00002200  0x000e3400  
+0x06060810  0xffffffe0  0x07ffe0ff  0x000fc800  
+0x0600780c  0x00000020  0x03f260f0  0x000fe400  
+0x05050810  0x00000001  0x07ffe0ff  0x000fe400  
+0xff007a0c  0x00006000  0x03f012f0  0x000fd000  
+0x05051810  0x00000001  0x07ffe0ff  0x000fe200  
+0x1c1c7a24  0x00000100  0x078e0207  0x001fc600  
+0x051d7819  0x00000004  0x000006ff  0x000fe200  
+0x1c1c7824  0x00000010  0x078e00ff  0x000fc600  
+0x1d007a0c  0x00005e00  0x007012f0  0x000fc800  
+0x1c007a0c  0x00005f00  0x007012f0  0x000fe200  
+0x00007945  0x000003a0  0x03800000  0x000fe200  
+0xff077224  0x000000ff  0x078e00ff  0x000fe200  
+0x000b7202  0x000000ff  0x00000f00  0x000fe200  
+0xff067224  0x000000ff  0x078e00ff  0x000fe400  
+0xff057224  0x000000ff  0x078e00ff  0x000fe400  
+0xff047224  0x000000ff  0x078e00ff  0x000fe400  
+0xff0a7224  0x000000ff  0x078e00ff  0x000fc400  
+0xff097224  0x000000ff  0x078e00ff  0x000fe400  
+0xff087224  0x000000ff  0x078e00ff  0x000fe200  
+0x00008947  0x00000300  0x03800000  0x000fee00  
+0x00067919  0x00000000  0x00000000  0x000e2200  
+0xff0a7424  0x00000002  0x078e00ff  0x000fc800  
+0x1d107625  0x00005800  0x078e020a  0x000fe200  
+0xff047819  0x00000002  0x00011606  0x001fc800  
+0x04057812  0x00000003  0x078ec0ff  0x000fe400  
+0x06047812  0x00000003  0x078ec0ff  0x000fe400  
+0x05077812  0x00000001  0x078ec0ff  0x000fe400  
+0xff067819  0x00000004  0x00011606  0x000fe400  
+0xff057819  0x00000001  0x00011605  0x000fe200  
+0x07077824  0x00000008  0x078e0204  0x000fe200  
+0x06067812  0x00000001  0x078ec0ff  0x000fc400  
+0x05047211  0x00000004  0x078e18ff  0x000fe200  
+0x1c0c7625  0x00005a00  0x078e020a  0x000fe400  
+0x06077824  0x00000004  0x078e0207  0x040fe400  
+0x06047824  0x00000004  0x078e0204  0x000fe400  
+0x07077824  0x00000002  0x078e00ff  0x000fe400  
+0x04057824  0x00000002  0x078e00ff  0x000fe400  
+0x07107a25  0x00005e00  0x078e0010  0x000fc400  
+0x050c7a25  0x00006000  0x078e000c  0x000fd000  
+0x10187980  0x00000000  0x0010ed00  0x00006400  
+0x0c147980  0x00000000  0x0010ed00  0x00046200  
+0x10107980  0x00000010  0x0010ed00  0x001e2200  
+0x0c0c7980  0x00000010  0x0010ed00  0x004e2200  
+0xff087224  0x000000ff  0x078e00ff  0x000fe200  
+0x00097202  0x000000ff  0x00000f00  0x000fe200  
+0xff0a7224  0x000000ff  0x078e00ff  0x000fe400  
+0xff0b7224  0x000000ff  0x078e00ff  0x000fe200  
+0x00077202  0x000000ff  0x00000f00  0x000fe200  
+0xff047224  0x000000ff  0x078e00ff  0x000fc400  
+0xff057224  0x000000ff  0x078e00ff  0x000fe400  
+0xff067224  0x000000ff  0x078e00ff  0x000fe200  
+0x00007948  0xffffffff  0x03800000  0x000fe200  
+0x18087236  0x00000014  0x00005408  0x0c226400  
+0x180a7236  0x00000014  0x0000d40a  0x0c04a400  
+0x18047236  0x00000014  0x00015404  0x0c06e400  
+0x18067236  0x00000014  0x0001d406  0x00092800  
+0x1a087236  0x00000016  0x00005408  0x0c202400  
+0x1a0a7236  0x00000016  0x0000d40a  0x0c426400  
+0x1a047236  0x00000016  0x00015404  0x0c84a400  
+0x1a067236  0x00000016  0x0001d406  0x0106e800  
+0x10087236  0x0000000c  0x00005408  0x0c102400  
+0x100a7236  0x0000000c  0x0000d40a  0x0c226400  
+0x10047236  0x0000000c  0x00015404  0x0c44a400  
+0x10067236  0x0000000c  0x0001d406  0x0086e800  
+0x12087236  0x0000000e  0x00005408  0x0c102400  
+0x120a7236  0x0000000e  0x0000d40a  0x0c202400  
+0x12047236  0x0000000e  0x00015404  0x0c402400  
+0x12067236  0x0000000e  0x0001d406  0x00803400  
+0x00007941  0x00000000  0x03800000  0x001fea00  
+0x000c7919  0x00000000  0x00000000  0x000e2200  
+0x1c1c7a24  0x00005e00  0x078e02ff  0x000fe200  
+0xff0e7819  0x00000004  0x0001160c  0x001fc400  
+0xff0d7819  0x00000002  0x0001160c  0x000fe400  
+0x0c0c7812  0x00000003  0x078ec0ff  0x000fe400  
+0x0e0e7812  0x00000001  0x078ec0ff  0x000fe400  
+0x0d0d7812  0x00000003  0x078ec0ff  0x000fc600  
+0x0e0c7824  0x00000004  0x078e020c  0x000fe200  
+0x0d0f7812  0x00000001  0x078ec0ff  0x000fe400  
+0xff107819  0x00000001  0x0001160d  0x000fe400  
+0x0c0d7812  0x00000005  0x078ec0ff  0x040fe400  
+0x0c0e7812  0x00000002  0x078ec0ff  0x000fc600  
+0x0f0c7824  0x00000008  0x078e020d  0x000fe200  
+0xff0f7819  0x0000001f  0x0001141d  0x000fe200  
+0x100e7824  0x00000008  0x078e020e  0x000fe200  
+0x1d117210  0x0000001c  0x07f1e0ff  0x000fe200  
+0xff0d7224  0x000000ff  0x078e00ff  0x000fc600  
+0x1c0f7211  0x0000000f  0x000f0eff  0x000fe200  
+0x0e0c7a25  0x00005e00  0x078e000c  0x000fe200  
+0x110e7a11  0x00005c00  0x078010ff  0x000fe200  
+0xff127624  0x00005e00  0x078e00ff  0x000fc600  
+0x11117a11  0x00005d00  0x000f140f  0x000fe400  
+0x0c107211  0x0000000e  0x078010ff  0x000fe400  
+0x120e7819  0x00000002  0x000006ff  0x000fe400  
+0xff0f7819  0x0000001e  0x00011612  0x000fe400  
+0x0c0d7211  0x00000011  0x000f140d  0x000fe400  
+0x0e127211  0x00000010  0x078210ff  0x000fc400  
+0x0e117210  0x00000010  0x07f1e0ff  0x040fe400  
+0x0e137211  0x0000000d  0x008f140f  0x040fe400  
+0x0e157210  0x00000012  0x07f3e0ff  0x000fe200  
+0x0f147824  0x00000001  0x000e060d  0x040fe400  
+0xff0c7224  0x000000ff  0x078e0010  0x000fe400  
+0x0f167824  0x00000001  0x008e0613  0x000fe400  
+0xff0e7224  0x000000ff  0x078e0011  0x000fc400  
+0xff0f7224  0x000000ff  0x078e0014  0x000fe200  
+0x00107202  0x00000015  0x00000f00  0x000fe200  
+0xff117224  0x000000ff  0x078e0016  0x000fe200  
+0x0c007385  0x00000000  0x0010e908  0x0001e200  
+0x0c007385  0x00000008  0x0010e90a  0x0003e800  
+0x0e007385  0x00000000  0x0010e909  0x0003e200  
+0x0e007385  0x00000008  0x0010e90b  0x0003e200  
+0x12007385  0x00000000  0x0010e904  0x0003e200  
+0x12007385  0x00000008  0x0010e906  0x0003e200  
+0x10007385  0x00000000  0x0010e905  0x0003e200  
+0x10007385  0x00000008  0x0010e907  0x0003e200  
+0x00007948  0xffffffff  0x03800000  0x000fe200  
+0x02087a10  0x80000800  0x07ffe0ff  0x001fd000  
+0x00047805  0x00000000  0x00005000  0x002fd000  
+0x04037824  0x00000001  0x078e0a03  0x000fd000  
+0x08007387  0x00000003  0x00100800  0x0001e200  
+0xff067224  0x000000ff  0x078e0002  0x000fe200  
+0x00047802  0x00000000  0x00000f00  0x000fe200  
+0xff077224  0x000000ff  0x078e0000  0x000fe200  
+0x00057802  0x00000000  0x00000f00  0x000fe400  
+0x00147802  0x00000000  0x00000f00  0x000fe400  
+0x00157802  0x00000000  0x00000f00  0x000fd000  
+0x00007943  0x00000000  0x03c00000  0x001fea00  
+0x0000794d  0x00000000  0x03800000  0x000fea00  
+0x00007947  0xfffffff0  0x0383ffff  0x000fc000  
+0x00007918  0x00000000  0x00000000  0x000fc000  
+0x00007918  0x00000000  0x00000000  0x000fc000  
+
+
+.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff	REL
+2272    $str    R_CUDA_ABS32_LO_32
+2304    $str    R_CUDA_ABS32_HI_32
+2352    vprintf    R_CUDA_ABS47_34
+
+.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff	RELA
+2320    _Z12wmma_exampleP6__halfS0_Pfiiiff    R_CUDA_ABS32_LO_32    2368
+2336    _Z12wmma_exampleP6__halfS0_Pfiiiff    R_CUDA_ABS32_HI_32    2368
+
+.section .debug_frame
+decodeDebugFrame, frameBuf 0xffffffff, total_length 224
+CIE length 40, cie_id -1
+version 3
+augmentation slen 1
+augmentation 
+code_align_factor slen 1
+data_align_factor slen 1
+ Debug Frame Common Information Entry
+  length:                 40
+  CIE_id :                -1
+  version:                3
+  augmentation:           
+  code align factor:      4
+  data align factor:      -4
+  return address register 16777215
+  initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff
+  DW_CFA_def_cfa register R1, offset 0
+  DW_CFA_same_value R255
+  DW_CFA_same_value R1
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+ Debug Frame Description Entry
+  length:                 48
+  CIE_pointer:            0
+  initial_location:       0x0
+  address_range:          0x100
+  instructions: 24 bytes
+  DW_CFA_advance_loc4 delta 4
+  DW_CFA_advance_loc4 delta 0
+  DW_CFA_def_cfa register R1, offset 0
+  DW_CFA_advance_loc4 delta 52
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+CIE length 40, cie_id -1
+version 3
+augmentation slen 1
+augmentation 
+code_align_factor slen 1
+data_align_factor slen 1
+ Debug Frame Common Information Entry
+  length:                 40
+  CIE_id :                -1
+  version:                3
+  augmentation:           
+  code align factor:      4
+  data align factor:      -4
+  return address register 16777215
+  initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff
+  DW_CFA_def_cfa register R1, offset 0
+  DW_CFA_same_value R255
+  DW_CFA_same_value R1
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+ Debug Frame Description Entry
+  length:                 48
+  CIE_pointer:            0
+  initial_location:       0x0
+  address_range:          0x970
+  instructions: 24 bytes
+  DW_CFA_advance_loc4 delta 4
+  DW_CFA_advance_loc4 delta 2
+  DW_CFA_def_cfa register R1, offset 8
+  DW_CFA_advance_loc4 delta 586
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+.section .rel.debug_frame	REL
+72    _Z17convertFp32ToFp16P6__halfPfi    R_NV_64
+184    _Z12wmma_exampleP6__halfS0_Pfiiiff    R_NV_64
+
diff --git a/cuda-kernels/_cuobjdump_2.sass b/cuda-kernels/_cuobjdump_2.sass
new file mode 100644
index 0000000..1b50ed2
--- /dev/null
+++ b/cuda-kernels/_cuobjdump_2.sass
@@ -0,0 +1,348 @@
+	code for sm_70
+		Function : _Z17convertFp32ToFp16P6__halfPfi
+	.headerflags    @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)"
+        /*0000*/              @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ;                      /* 0x000000fffffff389 */
+                                                                                     /* 0x000fe200000e00ff */
+        /*0010*/                   MOV R1, c[0x0][0x28];                             /* 0x00000a0000017a02 */
+                                                                                     /* 0x000fd00000000f00 */
+        /*0020*/                   S2R R4, SR_CTAID.X;                               /* 0x0000000000047919 */
+                                                                                     /* 0x000e220000002500 */
+        /*0030*/                   S2R R2, SR_TID.X;                                 /* 0x0000000000027919 */
+                                                                                     /* 0x000e240000002100 */
+        /*0040*/                   IMAD R4, R4, c[0x0][0x0], R2;                     /* 0x0000000004047a24 */
+                                                                                     /* 0x001fca00078e0202 */
+        /*0050*/                   ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT;  /* 0x00005c0004007a0c */
+                                                                                     /* 0x000fd80003f062f0 */
+        /*0060*/               @P0 EXIT;                                             /* 0x000000000000094d */
+                                                                                     /* 0x000fea0003800000 */
+        /*0070*/                   MOV R2, 0x4;                                      /* 0x0000000400027802 */
+                                                                                     /* 0x000fca0000000f00 */
+        /*0080*/                   IMAD.WIDE R2, R4, R2, c[0x0][0x168];              /* 0x00005a0004027625 */
+                                                                                     /* 0x000fd400078e0202 */
+        /*0090*/                   LDG.E.SYS R2, [R2];                               /* 0x0000000002027381 */
+                                                                                     /* 0x000e2200001ee900 */
+        /*00a0*/                   MOV R5, 0x2;                                      /* 0x0000000200057802 */
+                                                                                     /* 0x000fca0000000f00 */
+        /*00b0*/                   IMAD.WIDE R4, R4, R5, c[0x0][0x160];              /* 0x0000580004047625 */
+                                                                                     /* 0x000fe200078e0205 */
+        /*00c0*/                   F2F.F16.F32 R6, R2;                               /* 0x0000000200067304 */
+                                                                                     /* 0x001e320000200800 */
+        /*00d0*/                   STG.E.U16.SYS [R4], R6;                           /* 0x0000000604007386 */
+                                                                                     /* 0x0011e2000010e500 */
+        /*00e0*/                   EXIT;                                             /* 0x000000000000794d */
+                                                                                     /* 0x000fea0003800000 */
+        /*00f0*/                   BRA 0xf0;                                         /* 0xfffffff000007947 */
+                                                                                     /* 0x000fc0000383ffff */
+		...........................................
+
+
+		Function : _Z12wmma_exampleP6__halfS0_Pfiiiff
+	.headerflags    @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)"
+        /*0000*/              @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ;                              /* 0x000000fffffff389 */
+                                                                                             /* 0x000fe200000e00ff */
+        /*0010*/                   IMAD.U32 R1, RZ, RZ, c[0x0][0x28];                        /* 0x00000a00ff017624 */
+                                                                                             /* 0x000fd000078e00ff */
+        /*0020*/                   IADD3 R1, R1, -0x8, RZ;                                   /* 0xfffffff801017810 */
+                                                                                             /* 0x000fc80007ffe0ff */
+        /*0030*/                   IADD3 R2, P0, R1, c[0x0][0x20], RZ;                       /* 0x0000080001027a10 */
+                                                                                             /* 0x000fca0007f1e0ff */
+        /*0040*/                   IMAD.X R0, RZ, RZ, c[0x0][0x24], P0;                      /* 0x00000900ff007624 */
+                                                                                             /* 0x000fd000000e06ff */
+        /*0050*/                   CS2R.32 R3, SR_CLOCKLO;                                   /* 0x0000000000037805 */
+                                                                                             /* 0x000fd00000005000 */
+        /*0060*/                   I2F.U32.RP R7, 0x20;                                      /* 0x0000002000077906 */
+                                                                                             /* 0x000e240000209000 */
+        /*0070*/                   MUFU.RCP R7, R7;                                          /* 0x0000000700077308 */
+                                                                                             /* 0x001e220000001000 */
+        /*0080*/                   S2R R6, SR_CTAID.X;                                       /* 0x0000000000067919 */
+                                                                                             /* 0x000e620000002500 */
+        /*0090*/                   S2R R9, SR_TID.X;                                         /* 0x0000000000097919 */
+                                                                                             /* 0x000e620000002100 */
+        /*00a0*/                   IADD3 R8, R7, 0xffffffe, RZ;                              /* 0x0ffffffe07087810 */
+                                                                                             /* 0x001fcc0007ffe0ff */
+        /*00b0*/                   F2I.FTZ.U32.TRUNC.NTZ R5, R8;                             /* 0x0000000800057305 */
+                                                                                             /* 0x0000a2000021f000 */
+        /*00c0*/                   IMAD.U32 R4, RZ, RZ, RZ;                                  /* 0x000000ffff047224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*00d0*/                   IMAD R6, R6, c[0x0][0x0], R9;                             /* 0x0000000006067a24 */
+                                                                                             /* 0x002fe400078e0209 */
+        /*00e0*/                   IMAD.U32 R10, R5, -0x20, RZ;                              /* 0xffffffe0050a7824 */
+                                                                                             /* 0x004fc800078e00ff */
+        /*00f0*/                   IMAD.WIDE.U32 R4, R5, R10, R4;                            /* 0x0000000a05047225 */
+                                                                                             /* 0x000fd000078e0004 */
+        /*0100*/                   IMAD.WIDE.U32 R4, R5, R6, RZ;                             /* 0x0000000605047225 */
+                                                                                             /* 0x000fcc00078e00ff */
+        /*0110*/                   IMAD R4, RZ, RZ, -R5;                                     /* 0x000000ffff047224 */
+                                                                                             /* 0x000fc800078e0a05 */
+        /*0120*/                   IMAD R6, R4, 0x20, R6;                                    /* 0x0000002004067824 */
+                                                                                             /* 0x000fca00078e0206 */
+        /*0130*/                   ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT;         /* 0x000000200600780c */
+                                                                                             /* 0x040fe20003f060f0 */
+        /*0140*/                   S2R R28, SR_CTAID.Y;                                      /* 0x00000000001c7919 */
+                                                                                             /* 0x000e220000002600 */
+        /*0150*/                   S2R R7, SR_TID.Y;                                         /* 0x0000000000077919 */
+                                                                                             /* 0x000e340000002200 */
+        /*0160*/               @P0 IADD3 R6, R6, -0x20, RZ;                                  /* 0xffffffe006060810 */
+                                                                                             /* 0x000fc80007ffe0ff */
+        /*0170*/                   ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT;               /* 0x000000200600780c */
+                                                                                             /* 0x000fe40003f260f0 */
+        /*0180*/               @P0 IADD3 R5, R5, 0x1, RZ;                                    /* 0x0000000105050810 */
+                                                                                             /* 0x000fe40007ffe0ff */
+        /*0190*/                   ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT;          /* 0x00006000ff007a0c */
+                                                                                             /* 0x000fd00003f012f0 */
+        /*01a0*/               @P1 IADD3 R5, R5, 0x1, RZ;                                    /* 0x0000000105051810 */
+                                                                                             /* 0x000fe20007ffe0ff */
+        /*01b0*/                   IMAD R28, R28, c[0x0][0x4], R7;                           /* 0x000001001c1c7a24 */
+                                                                                             /* 0x001fc600078e0207 */
+        /*01c0*/                   SHF.L.U32 R29, R5, 0x4, RZ;                               /* 0x00000004051d7819 */
+                                                                                             /* 0x000fe200000006ff */
+        /*01d0*/                   IMAD.U32 R28, R28, 0x10, RZ;                              /* 0x000000101c1c7824 */
+                                                                                             /* 0x000fc600078e00ff */
+        /*01e0*/                   ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT;         /* 0x00005e001d007a0c */
+                                                                                             /* 0x000fc800007012f0 */
+        /*01f0*/                   ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT;         /* 0x00005f001c007a0c */
+                                                                                             /* 0x000fe200007012f0 */
+        /*0200*/                   BSSY B0, 0x5b0;                                           /* 0x000003a000007945 */
+                                                                                             /* 0x000fe20003800000 */
+        /*0210*/                   IMAD.U32 R7, RZ, RZ, RZ;                                  /* 0x000000ffff077224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0220*/                   MOV R11, RZ;                                              /* 0x000000ff000b7202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*0230*/                   IMAD.U32 R6, RZ, RZ, RZ;                                  /* 0x000000ffff067224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0240*/                   IMAD.U32 R5, RZ, RZ, RZ;                                  /* 0x000000ffff057224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0250*/                   IMAD.U32 R4, RZ, RZ, RZ;                                  /* 0x000000ffff047224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0260*/                   IMAD.U32 R10, RZ, RZ, RZ;                                 /* 0x000000ffff0a7224 */
+                                                                                             /* 0x000fc400078e00ff */
+        /*0270*/                   IMAD.U32 R9, RZ, RZ, RZ;                                  /* 0x000000ffff097224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0280*/                   IMAD.U32 R8, RZ, RZ, RZ;                                  /* 0x000000ffff087224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0290*/              @!P0 BRA 0x5a0;                                                /* 0x0000030000008947 */
+                                                                                             /* 0x000fee0003800000 */
+        /*02a0*/                   S2R R6, SR_LANEID;                                        /* 0x0000000000067919 */
+                                                                                             /* 0x000e220000000000 */
+        /*02b0*/                   IMAD.U32 R10, RZ, RZ, 0x2;                                /* 0x00000002ff0a7424 */
+                                                                                             /* 0x000fc800078e00ff */
+        /*02c0*/                   IMAD.WIDE R16, R29, R10, c[0x0][0x160];                   /* 0x000058001d107625 */
+                                                                                             /* 0x000fe200078e020a */
+        /*02d0*/                   SHF.R.U32.HI R4, RZ, 0x2, R6;                             /* 0x00000002ff047819 */
+                                                                                             /* 0x001fc80000011606 */
+        /*02e0*/                   LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT;                      /* 0x0000000304057812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*02f0*/                   LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT;                      /* 0x0000000306047812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0300*/                   LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT;                      /* 0x0000000105077812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0310*/                   SHF.R.U32.HI R6, RZ, 0x4, R6;                             /* 0x00000004ff067819 */
+                                                                                             /* 0x000fe40000011606 */
+        /*0320*/                   SHF.R.U32.HI R5, RZ, 0x1, R5;                             /* 0x00000001ff057819 */
+                                                                                             /* 0x000fe20000011605 */
+        /*0330*/                   IMAD R7, R7, 0x8, R4;                                     /* 0x0000000807077824 */
+                                                                                             /* 0x000fe200078e0204 */
+        /*0340*/                   LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT;                      /* 0x0000000106067812 */
+                                                                                             /* 0x000fc400078ec0ff */
+        /*0350*/                   LEA R4, R5, R4, 0x3;                                      /* 0x0000000405047211 */
+                                                                                             /* 0x000fe200078e18ff */
+        /*0360*/                   IMAD.WIDE R12, R28, R10, c[0x0][0x168];                   /* 0x00005a001c0c7625 */
+                                                                                             /* 0x000fe400078e020a */
+        /*0370*/                   IMAD R7, R6.reuse, 0x4, R7;                               /* 0x0000000406077824 */
+                                                                                             /* 0x040fe400078e0207 */
+        /*0380*/                   IMAD R4, R6, 0x4, R4;                                     /* 0x0000000406047824 */
+                                                                                             /* 0x000fe400078e0204 */
+        /*0390*/                   IMAD.U32 R7, R7, 0x2, RZ;                                 /* 0x0000000207077824 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*03a0*/                   IMAD.U32 R5, R4, 0x2, RZ;                                 /* 0x0000000204057824 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*03b0*/                   IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16;                /* 0x00005e0007107a25 */
+                                                                                             /* 0x000fc400078e0010 */
+        /*03c0*/                   IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12;                /* 0x00006000050c7a25 */
+                                                                                             /* 0x000fd000078e000c */
+        /*03d0*/                   LD.E.128.SYS R24, [R16];                                  /* 0x0000000010187980 */
+                                                                                             /* 0x000064000010ed00 */
+        /*03e0*/                   LD.E.128.SYS R20, [R12];                                  /* 0x000000000c147980 */
+                                                                                             /* 0x000462000010ed00 */
+        /*03f0*/                   LD.E.128.SYS R16, [R16+0x10];                             /* 0x0000001010107980 */
+                                                                                             /* 0x001e22000010ed00 */
+        /*0400*/                   LD.E.128.SYS R12, [R12+0x10];                             /* 0x000000100c0c7980 */
+                                                                                             /* 0x004e22000010ed00 */
+        /*0410*/                   IMAD.U32 R8, RZ, RZ, RZ;                                  /* 0x000000ffff087224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0420*/                   MOV R9, RZ;                                               /* 0x000000ff00097202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*0430*/                   IMAD.U32 R10, RZ, RZ, RZ;                                 /* 0x000000ffff0a7224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0440*/                   IMAD.U32 R11, RZ, RZ, RZ;                                 /* 0x000000ffff0b7224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0450*/                   MOV R7, RZ;                                               /* 0x000000ff00077202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*0460*/                   IMAD.U32 R4, RZ, RZ, RZ;                                  /* 0x000000ffff047224 */
+                                                                                             /* 0x000fc400078e00ff */
+        /*0470*/                   IMAD.U32 R5, RZ, RZ, RZ;                                  /* 0x000000ffff057224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0480*/                   IMAD.U32 R6, RZ, RZ, RZ;                                  /* 0x000000ffff067224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0490*/                   WARPSYNC 0xffffffff;                                      /* 0xffffffff00007948 */
+                                                                                             /* 0x000fe20003800000 */
+        /*04a0*/                   HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8;    /* 0x0000001418087236 */
+                                                                                             /* 0x0c22640000005408 */
+        /*04b0*/                   HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10;  /* 0x00000014180a7236 */
+                                                                                             /* 0x0c04a4000000d40a */
+        /*04c0*/                   HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4;    /* 0x0000001418047236 */
+                                                                                             /* 0x0c06e40000015404 */
+        /*04d0*/                   HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6;                /* 0x0000001418067236 */
+                                                                                             /* 0x000928000001d406 */
+        /*04e0*/                   HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8;    /* 0x000000161a087236 */
+                                                                                             /* 0x0c20240000005408 */
+        /*04f0*/                   HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10;  /* 0x000000161a0a7236 */
+                                                                                             /* 0x0c4264000000d40a */
+        /*0500*/                   HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4;    /* 0x000000161a047236 */
+                                                                                             /* 0x0c84a40000015404 */
+        /*0510*/                   HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6;                /* 0x000000161a067236 */
+                                                                                             /* 0x0106e8000001d406 */
+        /*0520*/                   HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8;    /* 0x0000000c10087236 */
+                                                                                             /* 0x0c10240000005408 */
+        /*0530*/                   HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10;  /* 0x0000000c100a7236 */
+                                                                                             /* 0x0c2264000000d40a */
+        /*0540*/                   HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4;    /* 0x0000000c10047236 */
+                                                                                             /* 0x0c44a40000015404 */
+        /*0550*/                   HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6;                /* 0x0000000c10067236 */
+                                                                                             /* 0x0086e8000001d406 */
+        /*0560*/                   HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8;    /* 0x0000000e12087236 */
+                                                                                             /* 0x0c10240000005408 */
+        /*0570*/                   HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10;  /* 0x0000000e120a7236 */
+                                                                                             /* 0x0c2024000000d40a */
+        /*0580*/                   HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4;    /* 0x0000000e12047236 */
+                                                                                             /* 0x0c40240000015404 */
+        /*0590*/                   HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6;                /* 0x0000000e12067236 */
+                                                                                             /* 0x008034000001d406 */
+        /*05a0*/                   BSYNC B0;                                                 /* 0x0000000000007941 */
+                                                                                             /* 0x001fea0003800000 */
+        /*05b0*/                   S2R R12, SR_LANEID;                                       /* 0x00000000000c7919 */
+                                                                                             /* 0x000e220000000000 */
+        /*05c0*/                   IMAD R28, R28, c[0x0][0x178], RZ;                         /* 0x00005e001c1c7a24 */
+                                                                                             /* 0x000fe200078e02ff */
+        /*05d0*/                   SHF.R.U32.HI R14, RZ, 0x4, R12;                           /* 0x00000004ff0e7819 */
+                                                                                             /* 0x001fc4000001160c */
+        /*05e0*/                   SHF.R.U32.HI R13, RZ, 0x2, R12;                           /* 0x00000002ff0d7819 */
+                                                                                             /* 0x000fe4000001160c */
+        /*05f0*/                   LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT;                    /* 0x000000030c0c7812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0600*/                   LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT;                    /* 0x000000010e0e7812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0610*/                   LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT;                    /* 0x000000030d0d7812 */
+                                                                                             /* 0x000fc600078ec0ff */
+        /*0620*/                   IMAD R12, R14, 0x4, R12;                                  /* 0x000000040e0c7824 */
+                                                                                             /* 0x000fe200078e020c */
+        /*0630*/                   LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT;                    /* 0x000000010d0f7812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0640*/                   SHF.R.U32.HI R16, RZ, 0x1, R13;                           /* 0x00000001ff107819 */
+                                                                                             /* 0x000fe4000001160d */
+        /*0650*/                   LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT;              /* 0x000000050c0d7812 */
+                                                                                             /* 0x040fe400078ec0ff */
+        /*0660*/                   LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT;                    /* 0x000000020c0e7812 */
+                                                                                             /* 0x000fc600078ec0ff */
+        /*0670*/                   IMAD R12, R15, 0x8, R13;                                  /* 0x000000080f0c7824 */
+                                                                                             /* 0x000fe200078e020d */
+        /*0680*/                   SHF.R.S32.HI R15, RZ, 0x1f, R29;                          /* 0x0000001fff0f7819 */
+                                                                                             /* 0x000fe2000001141d */
+        /*0690*/                   IMAD R14, R16, 0x8, R14;                                  /* 0x00000008100e7824 */
+                                                                                             /* 0x000fe200078e020e */
+        /*06a0*/                   IADD3 R17, P0, R29, R28, RZ;                              /* 0x0000001c1d117210 */
+                                                                                             /* 0x000fe20007f1e0ff */
+        /*06b0*/                   IMAD.U32 R13, RZ, RZ, RZ;                                 /* 0x000000ffff0d7224 */
+                                                                                             /* 0x000fc600078e00ff */
+        /*06c0*/                   LEA.HI.X.SX32 R15, R28, R15, 0x1, P0;                     /* 0x0000000f1c0f7211 */
+                                                                                             /* 0x000fe200000f0eff */
+        /*06d0*/                   IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12;               /* 0x00005e000e0c7a25 */
+                                                                                             /* 0x000fe200078e000c */
+        /*06e0*/                   LEA R14, P0, R17, c[0x0][0x170], 0x2;                     /* 0x00005c00110e7a11 */
+                                                                                             /* 0x000fe200078010ff */
+        /*06f0*/                   IMAD.U32 R18, RZ, RZ, c[0x0][0x178];                      /* 0x00005e00ff127624 */
+                                                                                             /* 0x000fc600078e00ff */
+        /*0700*/                   LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0;           /* 0x00005d0011117a11 */
+                                                                                             /* 0x000fe400000f140f */
+        /*0710*/                   LEA R16, P0, R12, R14, 0x2;                               /* 0x0000000e0c107211 */
+                                                                                             /* 0x000fe400078010ff */
+        /*0720*/                   SHF.L.U32 R14, R18, 0x2, RZ;                              /* 0x00000002120e7819 */
+                                                                                             /* 0x000fe400000006ff */
+        /*0730*/                   SHF.R.U32.HI R15, RZ, 0x1e, R18;                          /* 0x0000001eff0f7819 */
+                                                                                             /* 0x000fe40000011612 */
+        /*0740*/                   LEA.HI.X R13, R12, R17, R13, 0x2, P0;                     /* 0x000000110c0d7211 */
+                                                                                             /* 0x000fe400000f140d */
+        /*0750*/                   LEA R18, P1, R14, R16, 0x2;                               /* 0x000000100e127211 */
+                                                                                             /* 0x000fc400078210ff */
+        /*0760*/                   IADD3 R17, P0, R14.reuse, R16, RZ;                        /* 0x000000100e117210 */
+                                                                                             /* 0x040fe40007f1e0ff */
+        /*0770*/                   LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1;               /* 0x0000000d0e137211 */
+                                                                                             /* 0x040fe400008f140f */
+        /*0780*/                   IADD3 R21, P1, R14, R18, RZ;                              /* 0x000000120e157210 */
+                                                                                             /* 0x000fe20007f3e0ff */
+        /*0790*/                   IMAD.X R20, R15.reuse, 0x1, R13, P0;                      /* 0x000000010f147824 */
+                                                                                             /* 0x040fe400000e060d */
+        /*07a0*/                   IMAD.U32 R12, RZ, RZ, R16;                                /* 0x000000ffff0c7224 */
+                                                                                             /* 0x000fe400078e0010 */
+        /*07b0*/                   IMAD.X R22, R15, 0x1, R19, P1;                            /* 0x000000010f167824 */
+                                                                                             /* 0x000fe400008e0613 */
+        /*07c0*/                   IMAD.U32 R14, RZ, RZ, R17;                                /* 0x000000ffff0e7224 */
+                                                                                             /* 0x000fc400078e0011 */
+        /*07d0*/                   IMAD.U32 R15, RZ, RZ, R20;                                /* 0x000000ffff0f7224 */
+                                                                                             /* 0x000fe200078e0014 */
+        /*07e0*/                   MOV R16, R21;                                             /* 0x0000001500107202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*07f0*/                   IMAD.U32 R17, RZ, RZ, R22;                                /* 0x000000ffff117224 */
+                                                                                             /* 0x000fe200078e0016 */
+        /*0800*/                   ST.E.SYS [R12], R8;                                       /* 0x000000000c007385 */
+                                                                                             /* 0x0001e2000010e908 */
+        /*0810*/                   ST.E.SYS [R12+0x8], R10;                                  /* 0x000000080c007385 */
+                                                                                             /* 0x0003e8000010e90a */
+        /*0820*/                   ST.E.SYS [R14], R9;                                       /* 0x000000000e007385 */
+                                                                                             /* 0x0003e2000010e909 */
+        /*0830*/                   ST.E.SYS [R14+0x8], R11;                                  /* 0x000000080e007385 */
+                                                                                             /* 0x0003e2000010e90b */
+        /*0840*/                   ST.E.SYS [R18], R4;                                       /* 0x0000000012007385 */
+                                                                                             /* 0x0003e2000010e904 */
+        /*0850*/                   ST.E.SYS [R18+0x8], R6;                                   /* 0x0000000812007385 */
+                                                                                             /* 0x0003e2000010e906 */
+        /*0860*/                   ST.E.SYS [R16], R5;                                       /* 0x0000000010007385 */
+                                                                                             /* 0x0003e2000010e905 */
+        /*0870*/                   ST.E.SYS [R16+0x8], R7;                                   /* 0x0000000810007385 */
+                                                                                             /* 0x0003e2000010e907 */
+        /*0880*/                   WARPSYNC 0xffffffff;                                      /* 0xffffffff00007948 */
+                                                                                             /* 0x000fe20003800000 */
+        /*0890*/                   IADD3 R8, R2, -c[0x0][0x20], RZ;                          /* 0x8000080002087a10 */
+                                                                                             /* 0x001fd00007ffe0ff */
+        /*08a0*/                   CS2R.32 R4, SR_CLOCKLO;                                   /* 0x0000000000047805 */
+                                                                                             /* 0x002fd00000005000 */
+        /*08b0*/                   IMAD R3, R4, 0x1, -R3;                                    /* 0x0000000104037824 */
+                                                                                             /* 0x000fd000078e0a03 */
+        /*08c0*/                   STL [R8], R3;                                             /* 0x0000000308007387 */
+                                                                                             /* 0x0001e20000100800 */
+        /*08d0*/                   IMAD.U32 R6, RZ, RZ, R2;                                  /* 0x000000ffff067224 */
+                                                                                             /* 0x000fe200078e0002 */
+        /*08e0*/                   MOV R4, 0x0;                                              /* 0x0000000000047802 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*08f0*/                   IMAD.U32 R7, RZ, RZ, R0;                                  /* 0x000000ffff077224 */
+                                                                                             /* 0x000fe200078e0000 */
+        /*0900*/                   MOV R5, 0x0;                                              /* 0x0000000000057802 */
+                                                                                             /* 0x000fe40000000f00 */
+        /*0910*/                   MOV R20, 0x0;                                             /* 0x0000000000147802 */
+                                                                                             /* 0x000fe40000000f00 */
+        /*0920*/                   MOV R21, 0x0;                                             /* 0x0000000000157802 */
+                                                                                             /* 0x000fd00000000f00 */
+        /*0930*/                   CALL.ABS.NOINC 0x0;                                       /* 0x0000000000007943 */
+                                                                                             /* 0x001fea0003c00000 */
+        /*0940*/                   EXIT;                                                     /* 0x000000000000794d */
+                                                                                             /* 0x000fea0003800000 */
+        /*0950*/                   BRA 0x950;                                                /* 0xfffffff000007947 */
+                                                                                             /* 0x000fc0000383ffff */
+        /*0960*/                   NOP;                                                      /* 0x0000000000007918 */
+                                                                                             /* 0x000fc00000000000 */
+        /*0970*/                   NOP;                                                      /* 0x0000000000007918 */
+                                                                                             /* 0x000fc00000000000 */
+		.............................................
+
+
+
diff --git a/cuda-kernels/_cuobjdump_complete_output_EIGzTK b/cuda-kernels/_cuobjdump_complete_output_EIGzTK
new file mode 100644
index 0000000..36999c0
--- /dev/null
+++ b/cuda-kernels/_cuobjdump_complete_output_EIGzTK
@@ -0,0 +1,1055 @@
+
+Fatbin elf code:
+================
+arch = sm_70
+code version = [1,7]
+producer = <unknown>
+host = linux
+compile_size = 64bit
+
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+Sections:
+Index Offset   Size ES Align   Type   Flags Link     Info Name
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+    2     72     32  0  1    STRTAB       0    0        0 .strtab
+    3     a8     18 18  8    SYMTAB       0    2        0 .symtab
+
+.section .strtab
+
+.section .shstrtab
+
+.section .symtab
+ index           value           size      info    other  shndx    name  
+   0               0               0        0        0      0     (null)
+
+	code for sm_70
+
+Fatbin elf code:
+================
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+code version = [1,7]
+producer = cuda
+host = linux
+compile_size = 64bit
+
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+    4    5d8     e0  0  1  PROGBITS       0    0        0 .debug_frame
+    5    6b8     48  0  4 CUDA_INFO       0    3        0 .nv.info
+    6    700     50  0  4 CUDA_INFO       0    3        d .nv.info._Z17convertFp32ToFp16P6__halfPfi
+    7    750     ac  0  4 CUDA_INFO       0    3        e .nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff
+    8    800     30 10  8       REL       0    3        e .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff
+    9    830     30 18  8      RELA       0    3        e .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff
+    a    860     20 10  8       REL       0    3        4 .rel.debug_frame
+    b    880    174  0  4  PROGBITS       2    0        d .nv.constant0._Z17convertFp32ToFp16P6__halfPfi
+    c    9f4    18c  0  4  PROGBITS       2    0        e .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff
+    d    b80    100  0 80  PROGBITS       6    3  9000008 .text._Z17convertFp32ToFp16P6__halfPfi
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+
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+
+.section .shstrtab
+
+.section .symtab
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+   4               0               0        3        0      b     .nv.constant0._Z17convertFp32ToFp16P6__halfPfi
+   5               0               0        3        0      e     .text._Z12wmma_exampleP6__halfS0_Pfiiiff
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+   9               0            2432       12       10      e     _Z12wmma_exampleP6__halfS0_Pfiiiff
+  10               0               0       12        0      0     vprintf
+
+
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+
+
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+	Format:	EIFMT_SVAL
+	Value:	0x9 0x0 
+	<0x2>
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+	Format:	EIFMT_SVAL
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+	Format:	EIFMT_SVAL
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+	Format:	EIFMT_SVAL
+	Value:	function: _Z17convertFp32ToFp16P6__halfPfi(0x8)	frame size: 0x0
+
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+	<0x7>
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+	<0x8>
+	Attribute:	EIATTR_KPARAM_INFO
+	Format:	EIFMT_SVAL
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+	<0x10>
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+	<0x11>
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+	<0x12>
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+	Format:	EIFMT_SVAL
+	Value:	0x940 
+	<0x13>
+	Attribute:	EIATTR_EXTERNS
+	Format:	EIFMT_SVAL
+	Value:	externs:	vprintf(0xa)	
+	<0x14>
+	Attribute:	EIATTR_CRS_STACK_SIZE
+	Format:	EIFMT_SVAL
+	Value:	0x0 
+
+
+.text._Z17convertFp32ToFp16P6__halfPfi
+bar = 0	reg = 9	lmem=0	smem=0
+0xfffff389  0x000000ff  0x000e00ff  0x000fe200  
+0x00017a02  0x00000a00  0x00000f00  0x000fd000  
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+0x00027802  0x00000004  0x00000f00  0x000fca00  
+0x04027625  0x00005a00  0x078e0202  0x000fd400  
+0x02027381  0x00000000  0x001ee900  0x000e2200  
+0x00057802  0x00000002  0x00000f00  0x000fca00  
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+0x0000794d  0x00000000  0x03800000  0x000fea00  
+0x00007947  0xfffffff0  0x0383ffff  0x000fc000  
+
+
+
+.text._Z12wmma_exampleP6__halfS0_Pfiiiff
+bar = 0	reg = 32	lmem=0	smem=0
+0xfffff389  0x000000ff  0x000e00ff  0x000fe200  
+0xff017624  0x00000a00  0x078e00ff  0x000fd000  
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+0x06067a24  0x00000000  0x078e0209  0x002fe400  
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+0x05047225  0x00000006  0x078e00ff  0x000fcc00  
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+0x06047812  0x00000003  0x078ec0ff  0x000fe400  
+0x05077812  0x00000001  0x078ec0ff  0x000fe400  
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+0x10187980  0x00000000  0x0010ed00  0x00006400  
+0x0c147980  0x00000000  0x0010ed00  0x00046200  
+0x10107980  0x00000010  0x0010ed00  0x001e2200  
+0x0c0c7980  0x00000010  0x0010ed00  0x004e2200  
+0xff087224  0x000000ff  0x078e00ff  0x000fe200  
+0x00097202  0x000000ff  0x00000f00  0x000fe200  
+0xff0a7224  0x000000ff  0x078e00ff  0x000fe400  
+0xff0b7224  0x000000ff  0x078e00ff  0x000fe200  
+0x00077202  0x000000ff  0x00000f00  0x000fe200  
+0xff047224  0x000000ff  0x078e00ff  0x000fc400  
+0xff057224  0x000000ff  0x078e00ff  0x000fe400  
+0xff067224  0x000000ff  0x078e00ff  0x000fe200  
+0x00007948  0xffffffff  0x03800000  0x000fe200  
+0x18087236  0x00000014  0x00005408  0x0c226400  
+0x180a7236  0x00000014  0x0000d40a  0x0c04a400  
+0x18047236  0x00000014  0x00015404  0x0c06e400  
+0x18067236  0x00000014  0x0001d406  0x00092800  
+0x1a087236  0x00000016  0x00005408  0x0c202400  
+0x1a0a7236  0x00000016  0x0000d40a  0x0c426400  
+0x1a047236  0x00000016  0x00015404  0x0c84a400  
+0x1a067236  0x00000016  0x0001d406  0x0106e800  
+0x10087236  0x0000000c  0x00005408  0x0c102400  
+0x100a7236  0x0000000c  0x0000d40a  0x0c226400  
+0x10047236  0x0000000c  0x00015404  0x0c44a400  
+0x10067236  0x0000000c  0x0001d406  0x0086e800  
+0x12087236  0x0000000e  0x00005408  0x0c102400  
+0x120a7236  0x0000000e  0x0000d40a  0x0c202400  
+0x12047236  0x0000000e  0x00015404  0x0c402400  
+0x12067236  0x0000000e  0x0001d406  0x00803400  
+0x00007941  0x00000000  0x03800000  0x001fea00  
+0x000c7919  0x00000000  0x00000000  0x000e2200  
+0x1c1c7a24  0x00005e00  0x078e02ff  0x000fe200  
+0xff0e7819  0x00000004  0x0001160c  0x001fc400  
+0xff0d7819  0x00000002  0x0001160c  0x000fe400  
+0x0c0c7812  0x00000003  0x078ec0ff  0x000fe400  
+0x0e0e7812  0x00000001  0x078ec0ff  0x000fe400  
+0x0d0d7812  0x00000003  0x078ec0ff  0x000fc600  
+0x0e0c7824  0x00000004  0x078e020c  0x000fe200  
+0x0d0f7812  0x00000001  0x078ec0ff  0x000fe400  
+0xff107819  0x00000001  0x0001160d  0x000fe400  
+0x0c0d7812  0x00000005  0x078ec0ff  0x040fe400  
+0x0c0e7812  0x00000002  0x078ec0ff  0x000fc600  
+0x0f0c7824  0x00000008  0x078e020d  0x000fe200  
+0xff0f7819  0x0000001f  0x0001141d  0x000fe200  
+0x100e7824  0x00000008  0x078e020e  0x000fe200  
+0x1d117210  0x0000001c  0x07f1e0ff  0x000fe200  
+0xff0d7224  0x000000ff  0x078e00ff  0x000fc600  
+0x1c0f7211  0x0000000f  0x000f0eff  0x000fe200  
+0x0e0c7a25  0x00005e00  0x078e000c  0x000fe200  
+0x110e7a11  0x00005c00  0x078010ff  0x000fe200  
+0xff127624  0x00005e00  0x078e00ff  0x000fc600  
+0x11117a11  0x00005d00  0x000f140f  0x000fe400  
+0x0c107211  0x0000000e  0x078010ff  0x000fe400  
+0x120e7819  0x00000002  0x000006ff  0x000fe400  
+0xff0f7819  0x0000001e  0x00011612  0x000fe400  
+0x0c0d7211  0x00000011  0x000f140d  0x000fe400  
+0x0e127211  0x00000010  0x078210ff  0x000fc400  
+0x0e117210  0x00000010  0x07f1e0ff  0x040fe400  
+0x0e137211  0x0000000d  0x008f140f  0x040fe400  
+0x0e157210  0x00000012  0x07f3e0ff  0x000fe200  
+0x0f147824  0x00000001  0x000e060d  0x040fe400  
+0xff0c7224  0x000000ff  0x078e0010  0x000fe400  
+0x0f167824  0x00000001  0x008e0613  0x000fe400  
+0xff0e7224  0x000000ff  0x078e0011  0x000fc400  
+0xff0f7224  0x000000ff  0x078e0014  0x000fe200  
+0x00107202  0x00000015  0x00000f00  0x000fe200  
+0xff117224  0x000000ff  0x078e0016  0x000fe200  
+0x0c007385  0x00000000  0x0010e908  0x0001e200  
+0x0c007385  0x00000008  0x0010e90a  0x0003e800  
+0x0e007385  0x00000000  0x0010e909  0x0003e200  
+0x0e007385  0x00000008  0x0010e90b  0x0003e200  
+0x12007385  0x00000000  0x0010e904  0x0003e200  
+0x12007385  0x00000008  0x0010e906  0x0003e200  
+0x10007385  0x00000000  0x0010e905  0x0003e200  
+0x10007385  0x00000008  0x0010e907  0x0003e200  
+0x00007948  0xffffffff  0x03800000  0x000fe200  
+0x02087a10  0x80000800  0x07ffe0ff  0x001fd000  
+0x00047805  0x00000000  0x00005000  0x002fd000  
+0x04037824  0x00000001  0x078e0a03  0x000fd000  
+0x08007387  0x00000003  0x00100800  0x0001e200  
+0xff067224  0x000000ff  0x078e0002  0x000fe200  
+0x00047802  0x00000000  0x00000f00  0x000fe200  
+0xff077224  0x000000ff  0x078e0000  0x000fe200  
+0x00057802  0x00000000  0x00000f00  0x000fe400  
+0x00147802  0x00000000  0x00000f00  0x000fe400  
+0x00157802  0x00000000  0x00000f00  0x000fd000  
+0x00007943  0x00000000  0x03c00000  0x001fea00  
+0x0000794d  0x00000000  0x03800000  0x000fea00  
+0x00007947  0xfffffff0  0x0383ffff  0x000fc000  
+0x00007918  0x00000000  0x00000000  0x000fc000  
+0x00007918  0x00000000  0x00000000  0x000fc000  
+
+
+.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff	REL
+2272    $str    R_CUDA_ABS32_LO_32
+2304    $str    R_CUDA_ABS32_HI_32
+2352    vprintf    R_CUDA_ABS47_34
+
+.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff	RELA
+2320    _Z12wmma_exampleP6__halfS0_Pfiiiff    R_CUDA_ABS32_LO_32    2368
+2336    _Z12wmma_exampleP6__halfS0_Pfiiiff    R_CUDA_ABS32_HI_32    2368
+
+.section .debug_frame
+decodeDebugFrame, frameBuf 0xffffffff, total_length 224
+CIE length 40, cie_id -1
+version 3
+augmentation slen 1
+augmentation 
+code_align_factor slen 1
+data_align_factor slen 1
+ Debug Frame Common Information Entry
+  length:                 40
+  CIE_id :                -1
+  version:                3
+  augmentation:           
+  code align factor:      4
+  data align factor:      -4
+  return address register 16777215
+  initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff
+  DW_CFA_def_cfa register R1, offset 0
+  DW_CFA_same_value R255
+  DW_CFA_same_value R1
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+ Debug Frame Description Entry
+  length:                 48
+  CIE_pointer:            0
+  initial_location:       0x0
+  address_range:          0x100
+  instructions: 24 bytes
+  DW_CFA_advance_loc4 delta 4
+  DW_CFA_advance_loc4 delta 0
+  DW_CFA_def_cfa register R1, offset 0
+  DW_CFA_advance_loc4 delta 52
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+CIE length 40, cie_id -1
+version 3
+augmentation slen 1
+augmentation 
+code_align_factor slen 1
+data_align_factor slen 1
+ Debug Frame Common Information Entry
+  length:                 40
+  CIE_id :                -1
+  version:                3
+  augmentation:           
+  code align factor:      4
+  data align factor:      -4
+  return address register 16777215
+  initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff
+  DW_CFA_def_cfa register R1, offset 0
+  DW_CFA_same_value R255
+  DW_CFA_same_value R1
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+ Debug Frame Description Entry
+  length:                 48
+  CIE_pointer:            0
+  initial_location:       0x0
+  address_range:          0x970
+  instructions: 24 bytes
+  DW_CFA_advance_loc4 delta 4
+  DW_CFA_advance_loc4 delta 2
+  DW_CFA_def_cfa register R1, offset 8
+  DW_CFA_advance_loc4 delta 586
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+.section .rel.debug_frame	REL
+72    _Z17convertFp32ToFp16P6__halfPfi    R_NV_64
+184    _Z12wmma_exampleP6__halfS0_Pfiiiff    R_NV_64
+
+	code for sm_70
+		Function : _Z17convertFp32ToFp16P6__halfPfi
+	.headerflags    @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)"
+        /*0000*/              @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ;                      /* 0x000000fffffff389 */
+                                                                                     /* 0x000fe200000e00ff */
+        /*0010*/                   MOV R1, c[0x0][0x28];                             /* 0x00000a0000017a02 */
+                                                                                     /* 0x000fd00000000f00 */
+        /*0020*/                   S2R R4, SR_CTAID.X;                               /* 0x0000000000047919 */
+                                                                                     /* 0x000e220000002500 */
+        /*0030*/                   S2R R2, SR_TID.X;                                 /* 0x0000000000027919 */
+                                                                                     /* 0x000e240000002100 */
+        /*0040*/                   IMAD R4, R4, c[0x0][0x0], R2;                     /* 0x0000000004047a24 */
+                                                                                     /* 0x001fca00078e0202 */
+        /*0050*/                   ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT;  /* 0x00005c0004007a0c */
+                                                                                     /* 0x000fd80003f062f0 */
+        /*0060*/               @P0 EXIT;                                             /* 0x000000000000094d */
+                                                                                     /* 0x000fea0003800000 */
+        /*0070*/                   MOV R2, 0x4;                                      /* 0x0000000400027802 */
+                                                                                     /* 0x000fca0000000f00 */
+        /*0080*/                   IMAD.WIDE R2, R4, R2, c[0x0][0x168];              /* 0x00005a0004027625 */
+                                                                                     /* 0x000fd400078e0202 */
+        /*0090*/                   LDG.E.SYS R2, [R2];                               /* 0x0000000002027381 */
+                                                                                     /* 0x000e2200001ee900 */
+        /*00a0*/                   MOV R5, 0x2;                                      /* 0x0000000200057802 */
+                                                                                     /* 0x000fca0000000f00 */
+        /*00b0*/                   IMAD.WIDE R4, R4, R5, c[0x0][0x160];              /* 0x0000580004047625 */
+                                                                                     /* 0x000fe200078e0205 */
+        /*00c0*/                   F2F.F16.F32 R6, R2;                               /* 0x0000000200067304 */
+                                                                                     /* 0x001e320000200800 */
+        /*00d0*/                   STG.E.U16.SYS [R4], R6;                           /* 0x0000000604007386 */
+                                                                                     /* 0x0011e2000010e500 */
+        /*00e0*/                   EXIT;                                             /* 0x000000000000794d */
+                                                                                     /* 0x000fea0003800000 */
+        /*00f0*/                   BRA 0xf0;                                         /* 0xfffffff000007947 */
+                                                                                     /* 0x000fc0000383ffff */
+		...........................................
+
+
+		Function : _Z12wmma_exampleP6__halfS0_Pfiiiff
+	.headerflags    @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)"
+        /*0000*/              @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ;                              /* 0x000000fffffff389 */
+                                                                                             /* 0x000fe200000e00ff */
+        /*0010*/                   IMAD.U32 R1, RZ, RZ, c[0x0][0x28];                        /* 0x00000a00ff017624 */
+                                                                                             /* 0x000fd000078e00ff */
+        /*0020*/                   IADD3 R1, R1, -0x8, RZ;                                   /* 0xfffffff801017810 */
+                                                                                             /* 0x000fc80007ffe0ff */
+        /*0030*/                   IADD3 R2, P0, R1, c[0x0][0x20], RZ;                       /* 0x0000080001027a10 */
+                                                                                             /* 0x000fca0007f1e0ff */
+        /*0040*/                   IMAD.X R0, RZ, RZ, c[0x0][0x24], P0;                      /* 0x00000900ff007624 */
+                                                                                             /* 0x000fd000000e06ff */
+        /*0050*/                   CS2R.32 R3, SR_CLOCKLO;                                   /* 0x0000000000037805 */
+                                                                                             /* 0x000fd00000005000 */
+        /*0060*/                   I2F.U32.RP R7, 0x20;                                      /* 0x0000002000077906 */
+                                                                                             /* 0x000e240000209000 */
+        /*0070*/                   MUFU.RCP R7, R7;                                          /* 0x0000000700077308 */
+                                                                                             /* 0x001e220000001000 */
+        /*0080*/                   S2R R6, SR_CTAID.X;                                       /* 0x0000000000067919 */
+                                                                                             /* 0x000e620000002500 */
+        /*0090*/                   S2R R9, SR_TID.X;                                         /* 0x0000000000097919 */
+                                                                                             /* 0x000e620000002100 */
+        /*00a0*/                   IADD3 R8, R7, 0xffffffe, RZ;                              /* 0x0ffffffe07087810 */
+                                                                                             /* 0x001fcc0007ffe0ff */
+        /*00b0*/                   F2I.FTZ.U32.TRUNC.NTZ R5, R8;                             /* 0x0000000800057305 */
+                                                                                             /* 0x0000a2000021f000 */
+        /*00c0*/                   IMAD.U32 R4, RZ, RZ, RZ;                                  /* 0x000000ffff047224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*00d0*/                   IMAD R6, R6, c[0x0][0x0], R9;                             /* 0x0000000006067a24 */
+                                                                                             /* 0x002fe400078e0209 */
+        /*00e0*/                   IMAD.U32 R10, R5, -0x20, RZ;                              /* 0xffffffe0050a7824 */
+                                                                                             /* 0x004fc800078e00ff */
+        /*00f0*/                   IMAD.WIDE.U32 R4, R5, R10, R4;                            /* 0x0000000a05047225 */
+                                                                                             /* 0x000fd000078e0004 */
+        /*0100*/                   IMAD.WIDE.U32 R4, R5, R6, RZ;                             /* 0x0000000605047225 */
+                                                                                             /* 0x000fcc00078e00ff */
+        /*0110*/                   IMAD R4, RZ, RZ, -R5;                                     /* 0x000000ffff047224 */
+                                                                                             /* 0x000fc800078e0a05 */
+        /*0120*/                   IMAD R6, R4, 0x20, R6;                                    /* 0x0000002004067824 */
+                                                                                             /* 0x000fca00078e0206 */
+        /*0130*/                   ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT;         /* 0x000000200600780c */
+                                                                                             /* 0x040fe20003f060f0 */
+        /*0140*/                   S2R R28, SR_CTAID.Y;                                      /* 0x00000000001c7919 */
+                                                                                             /* 0x000e220000002600 */
+        /*0150*/                   S2R R7, SR_TID.Y;                                         /* 0x0000000000077919 */
+                                                                                             /* 0x000e340000002200 */
+        /*0160*/               @P0 IADD3 R6, R6, -0x20, RZ;                                  /* 0xffffffe006060810 */
+                                                                                             /* 0x000fc80007ffe0ff */
+        /*0170*/                   ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT;               /* 0x000000200600780c */
+                                                                                             /* 0x000fe40003f260f0 */
+        /*0180*/               @P0 IADD3 R5, R5, 0x1, RZ;                                    /* 0x0000000105050810 */
+                                                                                             /* 0x000fe40007ffe0ff */
+        /*0190*/                   ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT;          /* 0x00006000ff007a0c */
+                                                                                             /* 0x000fd00003f012f0 */
+        /*01a0*/               @P1 IADD3 R5, R5, 0x1, RZ;                                    /* 0x0000000105051810 */
+                                                                                             /* 0x000fe20007ffe0ff */
+        /*01b0*/                   IMAD R28, R28, c[0x0][0x4], R7;                           /* 0x000001001c1c7a24 */
+                                                                                             /* 0x001fc600078e0207 */
+        /*01c0*/                   SHF.L.U32 R29, R5, 0x4, RZ;                               /* 0x00000004051d7819 */
+                                                                                             /* 0x000fe200000006ff */
+        /*01d0*/                   IMAD.U32 R28, R28, 0x10, RZ;                              /* 0x000000101c1c7824 */
+                                                                                             /* 0x000fc600078e00ff */
+        /*01e0*/                   ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT;         /* 0x00005e001d007a0c */
+                                                                                             /* 0x000fc800007012f0 */
+        /*01f0*/                   ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT;         /* 0x00005f001c007a0c */
+                                                                                             /* 0x000fe200007012f0 */
+        /*0200*/                   BSSY B0, 0x5b0;                                           /* 0x000003a000007945 */
+                                                                                             /* 0x000fe20003800000 */
+        /*0210*/                   IMAD.U32 R7, RZ, RZ, RZ;                                  /* 0x000000ffff077224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0220*/                   MOV R11, RZ;                                              /* 0x000000ff000b7202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*0230*/                   IMAD.U32 R6, RZ, RZ, RZ;                                  /* 0x000000ffff067224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0240*/                   IMAD.U32 R5, RZ, RZ, RZ;                                  /* 0x000000ffff057224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0250*/                   IMAD.U32 R4, RZ, RZ, RZ;                                  /* 0x000000ffff047224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0260*/                   IMAD.U32 R10, RZ, RZ, RZ;                                 /* 0x000000ffff0a7224 */
+                                                                                             /* 0x000fc400078e00ff */
+        /*0270*/                   IMAD.U32 R9, RZ, RZ, RZ;                                  /* 0x000000ffff097224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0280*/                   IMAD.U32 R8, RZ, RZ, RZ;                                  /* 0x000000ffff087224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0290*/              @!P0 BRA 0x5a0;                                                /* 0x0000030000008947 */
+                                                                                             /* 0x000fee0003800000 */
+        /*02a0*/                   S2R R6, SR_LANEID;                                        /* 0x0000000000067919 */
+                                                                                             /* 0x000e220000000000 */
+        /*02b0*/                   IMAD.U32 R10, RZ, RZ, 0x2;                                /* 0x00000002ff0a7424 */
+                                                                                             /* 0x000fc800078e00ff */
+        /*02c0*/                   IMAD.WIDE R16, R29, R10, c[0x0][0x160];                   /* 0x000058001d107625 */
+                                                                                             /* 0x000fe200078e020a */
+        /*02d0*/                   SHF.R.U32.HI R4, RZ, 0x2, R6;                             /* 0x00000002ff047819 */
+                                                                                             /* 0x001fc80000011606 */
+        /*02e0*/                   LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT;                      /* 0x0000000304057812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*02f0*/                   LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT;                      /* 0x0000000306047812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0300*/                   LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT;                      /* 0x0000000105077812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0310*/                   SHF.R.U32.HI R6, RZ, 0x4, R6;                             /* 0x00000004ff067819 */
+                                                                                             /* 0x000fe40000011606 */
+        /*0320*/                   SHF.R.U32.HI R5, RZ, 0x1, R5;                             /* 0x00000001ff057819 */
+                                                                                             /* 0x000fe20000011605 */
+        /*0330*/                   IMAD R7, R7, 0x8, R4;                                     /* 0x0000000807077824 */
+                                                                                             /* 0x000fe200078e0204 */
+        /*0340*/                   LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT;                      /* 0x0000000106067812 */
+                                                                                             /* 0x000fc400078ec0ff */
+        /*0350*/                   LEA R4, R5, R4, 0x3;                                      /* 0x0000000405047211 */
+                                                                                             /* 0x000fe200078e18ff */
+        /*0360*/                   IMAD.WIDE R12, R28, R10, c[0x0][0x168];                   /* 0x00005a001c0c7625 */
+                                                                                             /* 0x000fe400078e020a */
+        /*0370*/                   IMAD R7, R6.reuse, 0x4, R7;                               /* 0x0000000406077824 */
+                                                                                             /* 0x040fe400078e0207 */
+        /*0380*/                   IMAD R4, R6, 0x4, R4;                                     /* 0x0000000406047824 */
+                                                                                             /* 0x000fe400078e0204 */
+        /*0390*/                   IMAD.U32 R7, R7, 0x2, RZ;                                 /* 0x0000000207077824 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*03a0*/                   IMAD.U32 R5, R4, 0x2, RZ;                                 /* 0x0000000204057824 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*03b0*/                   IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16;                /* 0x00005e0007107a25 */
+                                                                                             /* 0x000fc400078e0010 */
+        /*03c0*/                   IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12;                /* 0x00006000050c7a25 */
+                                                                                             /* 0x000fd000078e000c */
+        /*03d0*/                   LD.E.128.SYS R24, [R16];                                  /* 0x0000000010187980 */
+                                                                                             /* 0x000064000010ed00 */
+        /*03e0*/                   LD.E.128.SYS R20, [R12];                                  /* 0x000000000c147980 */
+                                                                                             /* 0x000462000010ed00 */
+        /*03f0*/                   LD.E.128.SYS R16, [R16+0x10];                             /* 0x0000001010107980 */
+                                                                                             /* 0x001e22000010ed00 */
+        /*0400*/                   LD.E.128.SYS R12, [R12+0x10];                             /* 0x000000100c0c7980 */
+                                                                                             /* 0x004e22000010ed00 */
+        /*0410*/                   IMAD.U32 R8, RZ, RZ, RZ;                                  /* 0x000000ffff087224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0420*/                   MOV R9, RZ;                                               /* 0x000000ff00097202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*0430*/                   IMAD.U32 R10, RZ, RZ, RZ;                                 /* 0x000000ffff0a7224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0440*/                   IMAD.U32 R11, RZ, RZ, RZ;                                 /* 0x000000ffff0b7224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0450*/                   MOV R7, RZ;                                               /* 0x000000ff00077202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*0460*/                   IMAD.U32 R4, RZ, RZ, RZ;                                  /* 0x000000ffff047224 */
+                                                                                             /* 0x000fc400078e00ff */
+        /*0470*/                   IMAD.U32 R5, RZ, RZ, RZ;                                  /* 0x000000ffff057224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0480*/                   IMAD.U32 R6, RZ, RZ, RZ;                                  /* 0x000000ffff067224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0490*/                   WARPSYNC 0xffffffff;                                      /* 0xffffffff00007948 */
+                                                                                             /* 0x000fe20003800000 */
+        /*04a0*/                   HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8;    /* 0x0000001418087236 */
+                                                                                             /* 0x0c22640000005408 */
+        /*04b0*/                   HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10;  /* 0x00000014180a7236 */
+                                                                                             /* 0x0c04a4000000d40a */
+        /*04c0*/                   HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4;    /* 0x0000001418047236 */
+                                                                                             /* 0x0c06e40000015404 */
+        /*04d0*/                   HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6;                /* 0x0000001418067236 */
+                                                                                             /* 0x000928000001d406 */
+        /*04e0*/                   HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8;    /* 0x000000161a087236 */
+                                                                                             /* 0x0c20240000005408 */
+        /*04f0*/                   HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10;  /* 0x000000161a0a7236 */
+                                                                                             /* 0x0c4264000000d40a */
+        /*0500*/                   HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4;    /* 0x000000161a047236 */
+                                                                                             /* 0x0c84a40000015404 */
+        /*0510*/                   HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6;                /* 0x000000161a067236 */
+                                                                                             /* 0x0106e8000001d406 */
+        /*0520*/                   HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8;    /* 0x0000000c10087236 */
+                                                                                             /* 0x0c10240000005408 */
+        /*0530*/                   HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10;  /* 0x0000000c100a7236 */
+                                                                                             /* 0x0c2264000000d40a */
+        /*0540*/                   HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4;    /* 0x0000000c10047236 */
+                                                                                             /* 0x0c44a40000015404 */
+        /*0550*/                   HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6;                /* 0x0000000c10067236 */
+                                                                                             /* 0x0086e8000001d406 */
+        /*0560*/                   HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8;    /* 0x0000000e12087236 */
+                                                                                             /* 0x0c10240000005408 */
+        /*0570*/                   HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10;  /* 0x0000000e120a7236 */
+                                                                                             /* 0x0c2024000000d40a */
+        /*0580*/                   HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4;    /* 0x0000000e12047236 */
+                                                                                             /* 0x0c40240000015404 */
+        /*0590*/                   HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6;                /* 0x0000000e12067236 */
+                                                                                             /* 0x008034000001d406 */
+        /*05a0*/                   BSYNC B0;                                                 /* 0x0000000000007941 */
+                                                                                             /* 0x001fea0003800000 */
+        /*05b0*/                   S2R R12, SR_LANEID;                                       /* 0x00000000000c7919 */
+                                                                                             /* 0x000e220000000000 */
+        /*05c0*/                   IMAD R28, R28, c[0x0][0x178], RZ;                         /* 0x00005e001c1c7a24 */
+                                                                                             /* 0x000fe200078e02ff */
+        /*05d0*/                   SHF.R.U32.HI R14, RZ, 0x4, R12;                           /* 0x00000004ff0e7819 */
+                                                                                             /* 0x001fc4000001160c */
+        /*05e0*/                   SHF.R.U32.HI R13, RZ, 0x2, R12;                           /* 0x00000002ff0d7819 */
+                                                                                             /* 0x000fe4000001160c */
+        /*05f0*/                   LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT;                    /* 0x000000030c0c7812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0600*/                   LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT;                    /* 0x000000010e0e7812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0610*/                   LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT;                    /* 0x000000030d0d7812 */
+                                                                                             /* 0x000fc600078ec0ff */
+        /*0620*/                   IMAD R12, R14, 0x4, R12;                                  /* 0x000000040e0c7824 */
+                                                                                             /* 0x000fe200078e020c */
+        /*0630*/                   LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT;                    /* 0x000000010d0f7812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0640*/                   SHF.R.U32.HI R16, RZ, 0x1, R13;                           /* 0x00000001ff107819 */
+                                                                                             /* 0x000fe4000001160d */
+        /*0650*/                   LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT;              /* 0x000000050c0d7812 */
+                                                                                             /* 0x040fe400078ec0ff */
+        /*0660*/                   LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT;                    /* 0x000000020c0e7812 */
+                                                                                             /* 0x000fc600078ec0ff */
+        /*0670*/                   IMAD R12, R15, 0x8, R13;                                  /* 0x000000080f0c7824 */
+                                                                                             /* 0x000fe200078e020d */
+        /*0680*/                   SHF.R.S32.HI R15, RZ, 0x1f, R29;                          /* 0x0000001fff0f7819 */
+                                                                                             /* 0x000fe2000001141d */
+        /*0690*/                   IMAD R14, R16, 0x8, R14;                                  /* 0x00000008100e7824 */
+                                                                                             /* 0x000fe200078e020e */
+        /*06a0*/                   IADD3 R17, P0, R29, R28, RZ;                              /* 0x0000001c1d117210 */
+                                                                                             /* 0x000fe20007f1e0ff */
+        /*06b0*/                   IMAD.U32 R13, RZ, RZ, RZ;                                 /* 0x000000ffff0d7224 */
+                                                                                             /* 0x000fc600078e00ff */
+        /*06c0*/                   LEA.HI.X.SX32 R15, R28, R15, 0x1, P0;                     /* 0x0000000f1c0f7211 */
+                                                                                             /* 0x000fe200000f0eff */
+        /*06d0*/                   IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12;               /* 0x00005e000e0c7a25 */
+                                                                                             /* 0x000fe200078e000c */
+        /*06e0*/                   LEA R14, P0, R17, c[0x0][0x170], 0x2;                     /* 0x00005c00110e7a11 */
+                                                                                             /* 0x000fe200078010ff */
+        /*06f0*/                   IMAD.U32 R18, RZ, RZ, c[0x0][0x178];                      /* 0x00005e00ff127624 */
+                                                                                             /* 0x000fc600078e00ff */
+        /*0700*/                   LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0;           /* 0x00005d0011117a11 */
+                                                                                             /* 0x000fe400000f140f */
+        /*0710*/                   LEA R16, P0, R12, R14, 0x2;                               /* 0x0000000e0c107211 */
+                                                                                             /* 0x000fe400078010ff */
+        /*0720*/                   SHF.L.U32 R14, R18, 0x2, RZ;                              /* 0x00000002120e7819 */
+                                                                                             /* 0x000fe400000006ff */
+        /*0730*/                   SHF.R.U32.HI R15, RZ, 0x1e, R18;                          /* 0x0000001eff0f7819 */
+                                                                                             /* 0x000fe40000011612 */
+        /*0740*/                   LEA.HI.X R13, R12, R17, R13, 0x2, P0;                     /* 0x000000110c0d7211 */
+                                                                                             /* 0x000fe400000f140d */
+        /*0750*/                   LEA R18, P1, R14, R16, 0x2;                               /* 0x000000100e127211 */
+                                                                                             /* 0x000fc400078210ff */
+        /*0760*/                   IADD3 R17, P0, R14.reuse, R16, RZ;                        /* 0x000000100e117210 */
+                                                                                             /* 0x040fe40007f1e0ff */
+        /*0770*/                   LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1;               /* 0x0000000d0e137211 */
+                                                                                             /* 0x040fe400008f140f */
+        /*0780*/                   IADD3 R21, P1, R14, R18, RZ;                              /* 0x000000120e157210 */
+                                                                                             /* 0x000fe20007f3e0ff */
+        /*0790*/                   IMAD.X R20, R15.reuse, 0x1, R13, P0;                      /* 0x000000010f147824 */
+                                                                                             /* 0x040fe400000e060d */
+        /*07a0*/                   IMAD.U32 R12, RZ, RZ, R16;                                /* 0x000000ffff0c7224 */
+                                                                                             /* 0x000fe400078e0010 */
+        /*07b0*/                   IMAD.X R22, R15, 0x1, R19, P1;                            /* 0x000000010f167824 */
+                                                                                             /* 0x000fe400008e0613 */
+        /*07c0*/                   IMAD.U32 R14, RZ, RZ, R17;                                /* 0x000000ffff0e7224 */
+                                                                                             /* 0x000fc400078e0011 */
+        /*07d0*/                   IMAD.U32 R15, RZ, RZ, R20;                                /* 0x000000ffff0f7224 */
+                                                                                             /* 0x000fe200078e0014 */
+        /*07e0*/                   MOV R16, R21;                                             /* 0x0000001500107202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*07f0*/                   IMAD.U32 R17, RZ, RZ, R22;                                /* 0x000000ffff117224 */
+                                                                                             /* 0x000fe200078e0016 */
+        /*0800*/                   ST.E.SYS [R12], R8;                                       /* 0x000000000c007385 */
+                                                                                             /* 0x0001e2000010e908 */
+        /*0810*/                   ST.E.SYS [R12+0x8], R10;                                  /* 0x000000080c007385 */
+                                                                                             /* 0x0003e8000010e90a */
+        /*0820*/                   ST.E.SYS [R14], R9;                                       /* 0x000000000e007385 */
+                                                                                             /* 0x0003e2000010e909 */
+        /*0830*/                   ST.E.SYS [R14+0x8], R11;                                  /* 0x000000080e007385 */
+                                                                                             /* 0x0003e2000010e90b */
+        /*0840*/                   ST.E.SYS [R18], R4;                                       /* 0x0000000012007385 */
+                                                                                             /* 0x0003e2000010e904 */
+        /*0850*/                   ST.E.SYS [R18+0x8], R6;                                   /* 0x0000000812007385 */
+                                                                                             /* 0x0003e2000010e906 */
+        /*0860*/                   ST.E.SYS [R16], R5;                                       /* 0x0000000010007385 */
+                                                                                             /* 0x0003e2000010e905 */
+        /*0870*/                   ST.E.SYS [R16+0x8], R7;                                   /* 0x0000000810007385 */
+                                                                                             /* 0x0003e2000010e907 */
+        /*0880*/                   WARPSYNC 0xffffffff;                                      /* 0xffffffff00007948 */
+                                                                                             /* 0x000fe20003800000 */
+        /*0890*/                   IADD3 R8, R2, -c[0x0][0x20], RZ;                          /* 0x8000080002087a10 */
+                                                                                             /* 0x001fd00007ffe0ff */
+        /*08a0*/                   CS2R.32 R4, SR_CLOCKLO;                                   /* 0x0000000000047805 */
+                                                                                             /* 0x002fd00000005000 */
+        /*08b0*/                   IMAD R3, R4, 0x1, -R3;                                    /* 0x0000000104037824 */
+                                                                                             /* 0x000fd000078e0a03 */
+        /*08c0*/                   STL [R8], R3;                                             /* 0x0000000308007387 */
+                                                                                             /* 0x0001e20000100800 */
+        /*08d0*/                   IMAD.U32 R6, RZ, RZ, R2;                                  /* 0x000000ffff067224 */
+                                                                                             /* 0x000fe200078e0002 */
+        /*08e0*/                   MOV R4, 0x0;                                              /* 0x0000000000047802 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*08f0*/                   IMAD.U32 R7, RZ, RZ, R0;                                  /* 0x000000ffff077224 */
+                                                                                             /* 0x000fe200078e0000 */
+        /*0900*/                   MOV R5, 0x0;                                              /* 0x0000000000057802 */
+                                                                                             /* 0x000fe40000000f00 */
+        /*0910*/                   MOV R20, 0x0;                                             /* 0x0000000000147802 */
+                                                                                             /* 0x000fe40000000f00 */
+        /*0920*/                   MOV R21, 0x0;                                             /* 0x0000000000157802 */
+                                                                                             /* 0x000fd00000000f00 */
+        /*0930*/                   CALL.ABS.NOINC 0x0;                                       /* 0x0000000000007943 */
+                                                                                             /* 0x001fea0003c00000 */
+        /*0940*/                   EXIT;                                                     /* 0x000000000000794d */
+                                                                                             /* 0x000fea0003800000 */
+        /*0950*/                   BRA 0x950;                                                /* 0xfffffff000007947 */
+                                                                                             /* 0x000fc0000383ffff */
+        /*0960*/                   NOP;                                                      /* 0x0000000000007918 */
+                                                                                             /* 0x000fc00000000000 */
+        /*0970*/                   NOP;                                                      /* 0x0000000000007918 */
+                                                                                             /* 0x000fc00000000000 */
+		.............................................
+
+
+
+Fatbin ptx code:
+================
+arch = sm_70
+code version = [6,0]
+producer = cuda
+host = linux
+compile_size = 64bit
+compressed
+
+
+
+
+
+
+
+
+.version 6.0
+.target sm_70
+.address_size 64
+
+
+.extern .func (.param .b32 func_retval0) vprintf
+(
+.param .b64 vprintf_param_0,
+.param .b64 vprintf_param_1
+)
+;
+.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0};
+
+.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff(
+.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0,
+.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1,
+.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2,
+.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3,
+.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4,
+.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5,
+.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6,
+.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7
+)
+{
+.local .align 8 .b8 __local_depot0[8];
+.reg .b64 %SP;
+.reg .b64 %SPL;
+.reg .pred %p<6>;
+.reg .f32 %f<34>;
+.reg .b32 %r<38>;
+.reg .b64 %rd<18>;
+
+
+mov.u64 %rd17, __local_depot0;
+cvta.local.u64 %SP, %rd17;
+ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0];
+ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1];
+ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2];
+ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3];
+ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4];
+ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5];
+
+	mov.u32 %r6, %clock;
+
+	mov.u32 %r8, %ntid.x;
+mov.u32 %r9, %ctaid.x;
+mov.u32 %r10, %tid.x;
+mad.lo.s32 %r11, %r8, %r9, %r10;
+mov.u32 %r12, WARP_SZ;
+div.u32 %r13, %r11, %r12;
+mov.u32 %r14, %ntid.y;
+mov.u32 %r15, %ctaid.y;
+mov.u32 %r16, %tid.y;
+mad.lo.s32 %r17, %r14, %r15, %r16;
+shl.b32 %r2, %r13, 4;
+shl.b32 %r3, %r17, 4;
+setp.lt.s32	%p1, %r2, %r4;
+setp.gt.s32	%p2, %r5, 0;
+and.pred %p3, %p1, %p2;
+setp.lt.s32	%p4, %r3, %r7;
+and.pred %p5, %p3, %p4;
+mov.f32 %f26, 0f00000000;
+mov.f32 %f27, %f26;
+mov.f32 %f28, %f26;
+mov.f32 %f29, %f26;
+mov.f32 %f30, %f26;
+mov.f32 %f31, %f26;
+mov.f32 %f32, %f26;
+mov.f32 %f33, %f26;
+@!%p5 bra BB0_2;
+bra.uni BB0_1;
+
+BB0_1:
+mul.wide.s32 %rd4, %r2, 2;
+add.s64 %rd5, %rd1, %rd4;
+wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4;
+mul.wide.s32 %rd6, %r3, 2;
+add.s64 %rd7, %rd2, %rd6;
+wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5;
+mov.f32 %f25, 0f00000000;
+wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25};
+
+BB0_2:
+add.u64 %rd8, %SP, 0;
+cvta.to.local.u64 %rd9, %rd8;
+mul.lo.s32 %r35, %r3, %r4;
+cvt.s64.s32	%rd10, %r35;
+cvt.s64.s32	%rd11, %r2;
+add.s64 %rd12, %rd10, %rd11;
+shl.b64 %rd13, %rd12, 2;
+add.s64 %rd14, %rd3, %rd13;
+wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4;
+
+	mov.u32 %r34, %clock;
+
+	sub.s32 %r36, %r34, %r6;
+st.local.u32 [%rd9], %r36;
+mov.u64 %rd15, $str;
+cvta.global.u64 %rd16, %rd15;
+
+	{
+.reg .b32 temp_param_reg;
+
+	.param .b64 param0;
+st.param.b64	[param0+0], %rd16;
+.param .b64 param1;
+st.param.b64	[param1+0], %rd8;
+.param .b32 retval0;
+call.uni (retval0), 
+vprintf, 
+(
+param0, 
+param1
+);
+ld.param.b32	%r37, [retval0+0];
+
+
+	}
+	ret;
+}
+
+
+.visible .entry _Z17convertFp32ToFp16P6__halfPfi(
+.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0,
+.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1,
+.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2
+)
+{
+.reg .pred %p<2>;
+.reg .b16 %rs<2>;
+.reg .f32 %f<2>;
+.reg .b32 %r<6>;
+.reg .b64 %rd<9>;
+
+
+ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0];
+ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1];
+ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2];
+mov.u32 %r3, %ntid.x;
+mov.u32 %r4, %ctaid.x;
+mov.u32 %r5, %tid.x;
+mad.lo.s32 %r1, %r4, %r3, %r5;
+setp.ge.s32	%p1, %r1, %r2;
+@%p1 bra BB1_2;
+
+cvta.to.global.u64 %rd3, %rd2;
+mul.wide.s32 %rd4, %r1, 4;
+add.s64 %rd5, %rd3, %rd4;
+ld.global.f32 %f1, [%rd5];
+
+	{ cvt.rn.f16.f32 %rs1, %f1;}
+
+
+	cvta.to.global.u64 %rd6, %rd1;
+mul.wide.s32 %rd7, %r1, 2;
+add.s64 %rd8, %rd6, %rd7;
+st.global.u16 [%rd8], %rs1;
+
+BB1_2:
+ret;
+}
+
+
diff --git a/cuda-kernels/_cuobjdump_complete_output_rndQyq b/cuda-kernels/_cuobjdump_complete_output_rndQyq
new file mode 100644
index 0000000..36999c0
--- /dev/null
+++ b/cuda-kernels/_cuobjdump_complete_output_rndQyq
@@ -0,0 +1,1055 @@
+
+Fatbin elf code:
+================
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+
+.section .strtab
+
+.section .shstrtab
+
+.section .symtab
+ index           value           size      info    other  shndx    name  
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+
+	code for sm_70
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+Fatbin elf code:
+================
+arch = sm_70
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+producer = cuda
+host = linux
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+    a    860     20 10  8       REL       0    3        4 .rel.debug_frame
+    b    880    174  0  4  PROGBITS       2    0        d .nv.constant0._Z17convertFp32ToFp16P6__halfPfi
+    c    9f4    18c  0  4  PROGBITS       2    0        e .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff
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+
+.section .shstrtab
+
+.section .symtab
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+   4               0               0        3        0      b     .nv.constant0._Z17convertFp32ToFp16P6__halfPfi
+   5               0               0        3        0      e     .text._Z12wmma_exampleP6__halfS0_Pfiiiff
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+   9               0            2432       12       10      e     _Z12wmma_exampleP6__halfS0_Pfiiiff
+  10               0               0       12        0      0     vprintf
+
+
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+.text._Z17convertFp32ToFp16P6__halfPfi
+bar = 0	reg = 9	lmem=0	smem=0
+0xfffff389  0x000000ff  0x000e00ff  0x000fe200  
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+
+
+.text._Z12wmma_exampleP6__halfS0_Pfiiiff
+bar = 0	reg = 32	lmem=0	smem=0
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+0x0c107211  0x0000000e  0x078010ff  0x000fe400  
+0x120e7819  0x00000002  0x000006ff  0x000fe400  
+0xff0f7819  0x0000001e  0x00011612  0x000fe400  
+0x0c0d7211  0x00000011  0x000f140d  0x000fe400  
+0x0e127211  0x00000010  0x078210ff  0x000fc400  
+0x0e117210  0x00000010  0x07f1e0ff  0x040fe400  
+0x0e137211  0x0000000d  0x008f140f  0x040fe400  
+0x0e157210  0x00000012  0x07f3e0ff  0x000fe200  
+0x0f147824  0x00000001  0x000e060d  0x040fe400  
+0xff0c7224  0x000000ff  0x078e0010  0x000fe400  
+0x0f167824  0x00000001  0x008e0613  0x000fe400  
+0xff0e7224  0x000000ff  0x078e0011  0x000fc400  
+0xff0f7224  0x000000ff  0x078e0014  0x000fe200  
+0x00107202  0x00000015  0x00000f00  0x000fe200  
+0xff117224  0x000000ff  0x078e0016  0x000fe200  
+0x0c007385  0x00000000  0x0010e908  0x0001e200  
+0x0c007385  0x00000008  0x0010e90a  0x0003e800  
+0x0e007385  0x00000000  0x0010e909  0x0003e200  
+0x0e007385  0x00000008  0x0010e90b  0x0003e200  
+0x12007385  0x00000000  0x0010e904  0x0003e200  
+0x12007385  0x00000008  0x0010e906  0x0003e200  
+0x10007385  0x00000000  0x0010e905  0x0003e200  
+0x10007385  0x00000008  0x0010e907  0x0003e200  
+0x00007948  0xffffffff  0x03800000  0x000fe200  
+0x02087a10  0x80000800  0x07ffe0ff  0x001fd000  
+0x00047805  0x00000000  0x00005000  0x002fd000  
+0x04037824  0x00000001  0x078e0a03  0x000fd000  
+0x08007387  0x00000003  0x00100800  0x0001e200  
+0xff067224  0x000000ff  0x078e0002  0x000fe200  
+0x00047802  0x00000000  0x00000f00  0x000fe200  
+0xff077224  0x000000ff  0x078e0000  0x000fe200  
+0x00057802  0x00000000  0x00000f00  0x000fe400  
+0x00147802  0x00000000  0x00000f00  0x000fe400  
+0x00157802  0x00000000  0x00000f00  0x000fd000  
+0x00007943  0x00000000  0x03c00000  0x001fea00  
+0x0000794d  0x00000000  0x03800000  0x000fea00  
+0x00007947  0xfffffff0  0x0383ffff  0x000fc000  
+0x00007918  0x00000000  0x00000000  0x000fc000  
+0x00007918  0x00000000  0x00000000  0x000fc000  
+
+
+.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff	REL
+2272    $str    R_CUDA_ABS32_LO_32
+2304    $str    R_CUDA_ABS32_HI_32
+2352    vprintf    R_CUDA_ABS47_34
+
+.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff	RELA
+2320    _Z12wmma_exampleP6__halfS0_Pfiiiff    R_CUDA_ABS32_LO_32    2368
+2336    _Z12wmma_exampleP6__halfS0_Pfiiiff    R_CUDA_ABS32_HI_32    2368
+
+.section .debug_frame
+decodeDebugFrame, frameBuf 0xffffffff, total_length 224
+CIE length 40, cie_id -1
+version 3
+augmentation slen 1
+augmentation 
+code_align_factor slen 1
+data_align_factor slen 1
+ Debug Frame Common Information Entry
+  length:                 40
+  CIE_id :                -1
+  version:                3
+  augmentation:           
+  code align factor:      4
+  data align factor:      -4
+  return address register 16777215
+  initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff
+  DW_CFA_def_cfa register R1, offset 0
+  DW_CFA_same_value R255
+  DW_CFA_same_value R1
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+ Debug Frame Description Entry
+  length:                 48
+  CIE_pointer:            0
+  initial_location:       0x0
+  address_range:          0x100
+  instructions: 24 bytes
+  DW_CFA_advance_loc4 delta 4
+  DW_CFA_advance_loc4 delta 0
+  DW_CFA_def_cfa register R1, offset 0
+  DW_CFA_advance_loc4 delta 52
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+CIE length 40, cie_id -1
+version 3
+augmentation slen 1
+augmentation 
+code_align_factor slen 1
+data_align_factor slen 1
+ Debug Frame Common Information Entry
+  length:                 40
+  CIE_id :                -1
+  version:                3
+  augmentation:           
+  code align factor:      4
+  data align factor:      -4
+  return address register 16777215
+  initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff
+  DW_CFA_def_cfa register R1, offset 0
+  DW_CFA_same_value R255
+  DW_CFA_same_value R1
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+ Debug Frame Description Entry
+  length:                 48
+  CIE_pointer:            0
+  initial_location:       0x0
+  address_range:          0x970
+  instructions: 24 bytes
+  DW_CFA_advance_loc4 delta 4
+  DW_CFA_advance_loc4 delta 2
+  DW_CFA_def_cfa register R1, offset 8
+  DW_CFA_advance_loc4 delta 586
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+.section .rel.debug_frame	REL
+72    _Z17convertFp32ToFp16P6__halfPfi    R_NV_64
+184    _Z12wmma_exampleP6__halfS0_Pfiiiff    R_NV_64
+
+	code for sm_70
+		Function : _Z17convertFp32ToFp16P6__halfPfi
+	.headerflags    @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)"
+        /*0000*/              @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ;                      /* 0x000000fffffff389 */
+                                                                                     /* 0x000fe200000e00ff */
+        /*0010*/                   MOV R1, c[0x0][0x28];                             /* 0x00000a0000017a02 */
+                                                                                     /* 0x000fd00000000f00 */
+        /*0020*/                   S2R R4, SR_CTAID.X;                               /* 0x0000000000047919 */
+                                                                                     /* 0x000e220000002500 */
+        /*0030*/                   S2R R2, SR_TID.X;                                 /* 0x0000000000027919 */
+                                                                                     /* 0x000e240000002100 */
+        /*0040*/                   IMAD R4, R4, c[0x0][0x0], R2;                     /* 0x0000000004047a24 */
+                                                                                     /* 0x001fca00078e0202 */
+        /*0050*/                   ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT;  /* 0x00005c0004007a0c */
+                                                                                     /* 0x000fd80003f062f0 */
+        /*0060*/               @P0 EXIT;                                             /* 0x000000000000094d */
+                                                                                     /* 0x000fea0003800000 */
+        /*0070*/                   MOV R2, 0x4;                                      /* 0x0000000400027802 */
+                                                                                     /* 0x000fca0000000f00 */
+        /*0080*/                   IMAD.WIDE R2, R4, R2, c[0x0][0x168];              /* 0x00005a0004027625 */
+                                                                                     /* 0x000fd400078e0202 */
+        /*0090*/                   LDG.E.SYS R2, [R2];                               /* 0x0000000002027381 */
+                                                                                     /* 0x000e2200001ee900 */
+        /*00a0*/                   MOV R5, 0x2;                                      /* 0x0000000200057802 */
+                                                                                     /* 0x000fca0000000f00 */
+        /*00b0*/                   IMAD.WIDE R4, R4, R5, c[0x0][0x160];              /* 0x0000580004047625 */
+                                                                                     /* 0x000fe200078e0205 */
+        /*00c0*/                   F2F.F16.F32 R6, R2;                               /* 0x0000000200067304 */
+                                                                                     /* 0x001e320000200800 */
+        /*00d0*/                   STG.E.U16.SYS [R4], R6;                           /* 0x0000000604007386 */
+                                                                                     /* 0x0011e2000010e500 */
+        /*00e0*/                   EXIT;                                             /* 0x000000000000794d */
+                                                                                     /* 0x000fea0003800000 */
+        /*00f0*/                   BRA 0xf0;                                         /* 0xfffffff000007947 */
+                                                                                     /* 0x000fc0000383ffff */
+		...........................................
+
+
+		Function : _Z12wmma_exampleP6__halfS0_Pfiiiff
+	.headerflags    @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)"
+        /*0000*/              @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ;                              /* 0x000000fffffff389 */
+                                                                                             /* 0x000fe200000e00ff */
+        /*0010*/                   IMAD.U32 R1, RZ, RZ, c[0x0][0x28];                        /* 0x00000a00ff017624 */
+                                                                                             /* 0x000fd000078e00ff */
+        /*0020*/                   IADD3 R1, R1, -0x8, RZ;                                   /* 0xfffffff801017810 */
+                                                                                             /* 0x000fc80007ffe0ff */
+        /*0030*/                   IADD3 R2, P0, R1, c[0x0][0x20], RZ;                       /* 0x0000080001027a10 */
+                                                                                             /* 0x000fca0007f1e0ff */
+        /*0040*/                   IMAD.X R0, RZ, RZ, c[0x0][0x24], P0;                      /* 0x00000900ff007624 */
+                                                                                             /* 0x000fd000000e06ff */
+        /*0050*/                   CS2R.32 R3, SR_CLOCKLO;                                   /* 0x0000000000037805 */
+                                                                                             /* 0x000fd00000005000 */
+        /*0060*/                   I2F.U32.RP R7, 0x20;                                      /* 0x0000002000077906 */
+                                                                                             /* 0x000e240000209000 */
+        /*0070*/                   MUFU.RCP R7, R7;                                          /* 0x0000000700077308 */
+                                                                                             /* 0x001e220000001000 */
+        /*0080*/                   S2R R6, SR_CTAID.X;                                       /* 0x0000000000067919 */
+                                                                                             /* 0x000e620000002500 */
+        /*0090*/                   S2R R9, SR_TID.X;                                         /* 0x0000000000097919 */
+                                                                                             /* 0x000e620000002100 */
+        /*00a0*/                   IADD3 R8, R7, 0xffffffe, RZ;                              /* 0x0ffffffe07087810 */
+                                                                                             /* 0x001fcc0007ffe0ff */
+        /*00b0*/                   F2I.FTZ.U32.TRUNC.NTZ R5, R8;                             /* 0x0000000800057305 */
+                                                                                             /* 0x0000a2000021f000 */
+        /*00c0*/                   IMAD.U32 R4, RZ, RZ, RZ;                                  /* 0x000000ffff047224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*00d0*/                   IMAD R6, R6, c[0x0][0x0], R9;                             /* 0x0000000006067a24 */
+                                                                                             /* 0x002fe400078e0209 */
+        /*00e0*/                   IMAD.U32 R10, R5, -0x20, RZ;                              /* 0xffffffe0050a7824 */
+                                                                                             /* 0x004fc800078e00ff */
+        /*00f0*/                   IMAD.WIDE.U32 R4, R5, R10, R4;                            /* 0x0000000a05047225 */
+                                                                                             /* 0x000fd000078e0004 */
+        /*0100*/                   IMAD.WIDE.U32 R4, R5, R6, RZ;                             /* 0x0000000605047225 */
+                                                                                             /* 0x000fcc00078e00ff */
+        /*0110*/                   IMAD R4, RZ, RZ, -R5;                                     /* 0x000000ffff047224 */
+                                                                                             /* 0x000fc800078e0a05 */
+        /*0120*/                   IMAD R6, R4, 0x20, R6;                                    /* 0x0000002004067824 */
+                                                                                             /* 0x000fca00078e0206 */
+        /*0130*/                   ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT;         /* 0x000000200600780c */
+                                                                                             /* 0x040fe20003f060f0 */
+        /*0140*/                   S2R R28, SR_CTAID.Y;                                      /* 0x00000000001c7919 */
+                                                                                             /* 0x000e220000002600 */
+        /*0150*/                   S2R R7, SR_TID.Y;                                         /* 0x0000000000077919 */
+                                                                                             /* 0x000e340000002200 */
+        /*0160*/               @P0 IADD3 R6, R6, -0x20, RZ;                                  /* 0xffffffe006060810 */
+                                                                                             /* 0x000fc80007ffe0ff */
+        /*0170*/                   ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT;               /* 0x000000200600780c */
+                                                                                             /* 0x000fe40003f260f0 */
+        /*0180*/               @P0 IADD3 R5, R5, 0x1, RZ;                                    /* 0x0000000105050810 */
+                                                                                             /* 0x000fe40007ffe0ff */
+        /*0190*/                   ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT;          /* 0x00006000ff007a0c */
+                                                                                             /* 0x000fd00003f012f0 */
+        /*01a0*/               @P1 IADD3 R5, R5, 0x1, RZ;                                    /* 0x0000000105051810 */
+                                                                                             /* 0x000fe20007ffe0ff */
+        /*01b0*/                   IMAD R28, R28, c[0x0][0x4], R7;                           /* 0x000001001c1c7a24 */
+                                                                                             /* 0x001fc600078e0207 */
+        /*01c0*/                   SHF.L.U32 R29, R5, 0x4, RZ;                               /* 0x00000004051d7819 */
+                                                                                             /* 0x000fe200000006ff */
+        /*01d0*/                   IMAD.U32 R28, R28, 0x10, RZ;                              /* 0x000000101c1c7824 */
+                                                                                             /* 0x000fc600078e00ff */
+        /*01e0*/                   ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT;         /* 0x00005e001d007a0c */
+                                                                                             /* 0x000fc800007012f0 */
+        /*01f0*/                   ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT;         /* 0x00005f001c007a0c */
+                                                                                             /* 0x000fe200007012f0 */
+        /*0200*/                   BSSY B0, 0x5b0;                                           /* 0x000003a000007945 */
+                                                                                             /* 0x000fe20003800000 */
+        /*0210*/                   IMAD.U32 R7, RZ, RZ, RZ;                                  /* 0x000000ffff077224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0220*/                   MOV R11, RZ;                                              /* 0x000000ff000b7202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*0230*/                   IMAD.U32 R6, RZ, RZ, RZ;                                  /* 0x000000ffff067224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0240*/                   IMAD.U32 R5, RZ, RZ, RZ;                                  /* 0x000000ffff057224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0250*/                   IMAD.U32 R4, RZ, RZ, RZ;                                  /* 0x000000ffff047224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0260*/                   IMAD.U32 R10, RZ, RZ, RZ;                                 /* 0x000000ffff0a7224 */
+                                                                                             /* 0x000fc400078e00ff */
+        /*0270*/                   IMAD.U32 R9, RZ, RZ, RZ;                                  /* 0x000000ffff097224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0280*/                   IMAD.U32 R8, RZ, RZ, RZ;                                  /* 0x000000ffff087224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0290*/              @!P0 BRA 0x5a0;                                                /* 0x0000030000008947 */
+                                                                                             /* 0x000fee0003800000 */
+        /*02a0*/                   S2R R6, SR_LANEID;                                        /* 0x0000000000067919 */
+                                                                                             /* 0x000e220000000000 */
+        /*02b0*/                   IMAD.U32 R10, RZ, RZ, 0x2;                                /* 0x00000002ff0a7424 */
+                                                                                             /* 0x000fc800078e00ff */
+        /*02c0*/                   IMAD.WIDE R16, R29, R10, c[0x0][0x160];                   /* 0x000058001d107625 */
+                                                                                             /* 0x000fe200078e020a */
+        /*02d0*/                   SHF.R.U32.HI R4, RZ, 0x2, R6;                             /* 0x00000002ff047819 */
+                                                                                             /* 0x001fc80000011606 */
+        /*02e0*/                   LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT;                      /* 0x0000000304057812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*02f0*/                   LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT;                      /* 0x0000000306047812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0300*/                   LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT;                      /* 0x0000000105077812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0310*/                   SHF.R.U32.HI R6, RZ, 0x4, R6;                             /* 0x00000004ff067819 */
+                                                                                             /* 0x000fe40000011606 */
+        /*0320*/                   SHF.R.U32.HI R5, RZ, 0x1, R5;                             /* 0x00000001ff057819 */
+                                                                                             /* 0x000fe20000011605 */
+        /*0330*/                   IMAD R7, R7, 0x8, R4;                                     /* 0x0000000807077824 */
+                                                                                             /* 0x000fe200078e0204 */
+        /*0340*/                   LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT;                      /* 0x0000000106067812 */
+                                                                                             /* 0x000fc400078ec0ff */
+        /*0350*/                   LEA R4, R5, R4, 0x3;                                      /* 0x0000000405047211 */
+                                                                                             /* 0x000fe200078e18ff */
+        /*0360*/                   IMAD.WIDE R12, R28, R10, c[0x0][0x168];                   /* 0x00005a001c0c7625 */
+                                                                                             /* 0x000fe400078e020a */
+        /*0370*/                   IMAD R7, R6.reuse, 0x4, R7;                               /* 0x0000000406077824 */
+                                                                                             /* 0x040fe400078e0207 */
+        /*0380*/                   IMAD R4, R6, 0x4, R4;                                     /* 0x0000000406047824 */
+                                                                                             /* 0x000fe400078e0204 */
+        /*0390*/                   IMAD.U32 R7, R7, 0x2, RZ;                                 /* 0x0000000207077824 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*03a0*/                   IMAD.U32 R5, R4, 0x2, RZ;                                 /* 0x0000000204057824 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*03b0*/                   IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16;                /* 0x00005e0007107a25 */
+                                                                                             /* 0x000fc400078e0010 */
+        /*03c0*/                   IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12;                /* 0x00006000050c7a25 */
+                                                                                             /* 0x000fd000078e000c */
+        /*03d0*/                   LD.E.128.SYS R24, [R16];                                  /* 0x0000000010187980 */
+                                                                                             /* 0x000064000010ed00 */
+        /*03e0*/                   LD.E.128.SYS R20, [R12];                                  /* 0x000000000c147980 */
+                                                                                             /* 0x000462000010ed00 */
+        /*03f0*/                   LD.E.128.SYS R16, [R16+0x10];                             /* 0x0000001010107980 */
+                                                                                             /* 0x001e22000010ed00 */
+        /*0400*/                   LD.E.128.SYS R12, [R12+0x10];                             /* 0x000000100c0c7980 */
+                                                                                             /* 0x004e22000010ed00 */
+        /*0410*/                   IMAD.U32 R8, RZ, RZ, RZ;                                  /* 0x000000ffff087224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0420*/                   MOV R9, RZ;                                               /* 0x000000ff00097202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*0430*/                   IMAD.U32 R10, RZ, RZ, RZ;                                 /* 0x000000ffff0a7224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0440*/                   IMAD.U32 R11, RZ, RZ, RZ;                                 /* 0x000000ffff0b7224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0450*/                   MOV R7, RZ;                                               /* 0x000000ff00077202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*0460*/                   IMAD.U32 R4, RZ, RZ, RZ;                                  /* 0x000000ffff047224 */
+                                                                                             /* 0x000fc400078e00ff */
+        /*0470*/                   IMAD.U32 R5, RZ, RZ, RZ;                                  /* 0x000000ffff057224 */
+                                                                                             /* 0x000fe400078e00ff */
+        /*0480*/                   IMAD.U32 R6, RZ, RZ, RZ;                                  /* 0x000000ffff067224 */
+                                                                                             /* 0x000fe200078e00ff */
+        /*0490*/                   WARPSYNC 0xffffffff;                                      /* 0xffffffff00007948 */
+                                                                                             /* 0x000fe20003800000 */
+        /*04a0*/                   HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8;    /* 0x0000001418087236 */
+                                                                                             /* 0x0c22640000005408 */
+        /*04b0*/                   HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10;  /* 0x00000014180a7236 */
+                                                                                             /* 0x0c04a4000000d40a */
+        /*04c0*/                   HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4;    /* 0x0000001418047236 */
+                                                                                             /* 0x0c06e40000015404 */
+        /*04d0*/                   HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6;                /* 0x0000001418067236 */
+                                                                                             /* 0x000928000001d406 */
+        /*04e0*/                   HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8;    /* 0x000000161a087236 */
+                                                                                             /* 0x0c20240000005408 */
+        /*04f0*/                   HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10;  /* 0x000000161a0a7236 */
+                                                                                             /* 0x0c4264000000d40a */
+        /*0500*/                   HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4;    /* 0x000000161a047236 */
+                                                                                             /* 0x0c84a40000015404 */
+        /*0510*/                   HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6;                /* 0x000000161a067236 */
+                                                                                             /* 0x0106e8000001d406 */
+        /*0520*/                   HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8;    /* 0x0000000c10087236 */
+                                                                                             /* 0x0c10240000005408 */
+        /*0530*/                   HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10;  /* 0x0000000c100a7236 */
+                                                                                             /* 0x0c2264000000d40a */
+        /*0540*/                   HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4;    /* 0x0000000c10047236 */
+                                                                                             /* 0x0c44a40000015404 */
+        /*0550*/                   HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6;                /* 0x0000000c10067236 */
+                                                                                             /* 0x0086e8000001d406 */
+        /*0560*/                   HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8;    /* 0x0000000e12087236 */
+                                                                                             /* 0x0c10240000005408 */
+        /*0570*/                   HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10;  /* 0x0000000e120a7236 */
+                                                                                             /* 0x0c2024000000d40a */
+        /*0580*/                   HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4;    /* 0x0000000e12047236 */
+                                                                                             /* 0x0c40240000015404 */
+        /*0590*/                   HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6;                /* 0x0000000e12067236 */
+                                                                                             /* 0x008034000001d406 */
+        /*05a0*/                   BSYNC B0;                                                 /* 0x0000000000007941 */
+                                                                                             /* 0x001fea0003800000 */
+        /*05b0*/                   S2R R12, SR_LANEID;                                       /* 0x00000000000c7919 */
+                                                                                             /* 0x000e220000000000 */
+        /*05c0*/                   IMAD R28, R28, c[0x0][0x178], RZ;                         /* 0x00005e001c1c7a24 */
+                                                                                             /* 0x000fe200078e02ff */
+        /*05d0*/                   SHF.R.U32.HI R14, RZ, 0x4, R12;                           /* 0x00000004ff0e7819 */
+                                                                                             /* 0x001fc4000001160c */
+        /*05e0*/                   SHF.R.U32.HI R13, RZ, 0x2, R12;                           /* 0x00000002ff0d7819 */
+                                                                                             /* 0x000fe4000001160c */
+        /*05f0*/                   LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT;                    /* 0x000000030c0c7812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0600*/                   LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT;                    /* 0x000000010e0e7812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0610*/                   LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT;                    /* 0x000000030d0d7812 */
+                                                                                             /* 0x000fc600078ec0ff */
+        /*0620*/                   IMAD R12, R14, 0x4, R12;                                  /* 0x000000040e0c7824 */
+                                                                                             /* 0x000fe200078e020c */
+        /*0630*/                   LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT;                    /* 0x000000010d0f7812 */
+                                                                                             /* 0x000fe400078ec0ff */
+        /*0640*/                   SHF.R.U32.HI R16, RZ, 0x1, R13;                           /* 0x00000001ff107819 */
+                                                                                             /* 0x000fe4000001160d */
+        /*0650*/                   LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT;              /* 0x000000050c0d7812 */
+                                                                                             /* 0x040fe400078ec0ff */
+        /*0660*/                   LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT;                    /* 0x000000020c0e7812 */
+                                                                                             /* 0x000fc600078ec0ff */
+        /*0670*/                   IMAD R12, R15, 0x8, R13;                                  /* 0x000000080f0c7824 */
+                                                                                             /* 0x000fe200078e020d */
+        /*0680*/                   SHF.R.S32.HI R15, RZ, 0x1f, R29;                          /* 0x0000001fff0f7819 */
+                                                                                             /* 0x000fe2000001141d */
+        /*0690*/                   IMAD R14, R16, 0x8, R14;                                  /* 0x00000008100e7824 */
+                                                                                             /* 0x000fe200078e020e */
+        /*06a0*/                   IADD3 R17, P0, R29, R28, RZ;                              /* 0x0000001c1d117210 */
+                                                                                             /* 0x000fe20007f1e0ff */
+        /*06b0*/                   IMAD.U32 R13, RZ, RZ, RZ;                                 /* 0x000000ffff0d7224 */
+                                                                                             /* 0x000fc600078e00ff */
+        /*06c0*/                   LEA.HI.X.SX32 R15, R28, R15, 0x1, P0;                     /* 0x0000000f1c0f7211 */
+                                                                                             /* 0x000fe200000f0eff */
+        /*06d0*/                   IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12;               /* 0x00005e000e0c7a25 */
+                                                                                             /* 0x000fe200078e000c */
+        /*06e0*/                   LEA R14, P0, R17, c[0x0][0x170], 0x2;                     /* 0x00005c00110e7a11 */
+                                                                                             /* 0x000fe200078010ff */
+        /*06f0*/                   IMAD.U32 R18, RZ, RZ, c[0x0][0x178];                      /* 0x00005e00ff127624 */
+                                                                                             /* 0x000fc600078e00ff */
+        /*0700*/                   LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0;           /* 0x00005d0011117a11 */
+                                                                                             /* 0x000fe400000f140f */
+        /*0710*/                   LEA R16, P0, R12, R14, 0x2;                               /* 0x0000000e0c107211 */
+                                                                                             /* 0x000fe400078010ff */
+        /*0720*/                   SHF.L.U32 R14, R18, 0x2, RZ;                              /* 0x00000002120e7819 */
+                                                                                             /* 0x000fe400000006ff */
+        /*0730*/                   SHF.R.U32.HI R15, RZ, 0x1e, R18;                          /* 0x0000001eff0f7819 */
+                                                                                             /* 0x000fe40000011612 */
+        /*0740*/                   LEA.HI.X R13, R12, R17, R13, 0x2, P0;                     /* 0x000000110c0d7211 */
+                                                                                             /* 0x000fe400000f140d */
+        /*0750*/                   LEA R18, P1, R14, R16, 0x2;                               /* 0x000000100e127211 */
+                                                                                             /* 0x000fc400078210ff */
+        /*0760*/                   IADD3 R17, P0, R14.reuse, R16, RZ;                        /* 0x000000100e117210 */
+                                                                                             /* 0x040fe40007f1e0ff */
+        /*0770*/                   LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1;               /* 0x0000000d0e137211 */
+                                                                                             /* 0x040fe400008f140f */
+        /*0780*/                   IADD3 R21, P1, R14, R18, RZ;                              /* 0x000000120e157210 */
+                                                                                             /* 0x000fe20007f3e0ff */
+        /*0790*/                   IMAD.X R20, R15.reuse, 0x1, R13, P0;                      /* 0x000000010f147824 */
+                                                                                             /* 0x040fe400000e060d */
+        /*07a0*/                   IMAD.U32 R12, RZ, RZ, R16;                                /* 0x000000ffff0c7224 */
+                                                                                             /* 0x000fe400078e0010 */
+        /*07b0*/                   IMAD.X R22, R15, 0x1, R19, P1;                            /* 0x000000010f167824 */
+                                                                                             /* 0x000fe400008e0613 */
+        /*07c0*/                   IMAD.U32 R14, RZ, RZ, R17;                                /* 0x000000ffff0e7224 */
+                                                                                             /* 0x000fc400078e0011 */
+        /*07d0*/                   IMAD.U32 R15, RZ, RZ, R20;                                /* 0x000000ffff0f7224 */
+                                                                                             /* 0x000fe200078e0014 */
+        /*07e0*/                   MOV R16, R21;                                             /* 0x0000001500107202 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*07f0*/                   IMAD.U32 R17, RZ, RZ, R22;                                /* 0x000000ffff117224 */
+                                                                                             /* 0x000fe200078e0016 */
+        /*0800*/                   ST.E.SYS [R12], R8;                                       /* 0x000000000c007385 */
+                                                                                             /* 0x0001e2000010e908 */
+        /*0810*/                   ST.E.SYS [R12+0x8], R10;                                  /* 0x000000080c007385 */
+                                                                                             /* 0x0003e8000010e90a */
+        /*0820*/                   ST.E.SYS [R14], R9;                                       /* 0x000000000e007385 */
+                                                                                             /* 0x0003e2000010e909 */
+        /*0830*/                   ST.E.SYS [R14+0x8], R11;                                  /* 0x000000080e007385 */
+                                                                                             /* 0x0003e2000010e90b */
+        /*0840*/                   ST.E.SYS [R18], R4;                                       /* 0x0000000012007385 */
+                                                                                             /* 0x0003e2000010e904 */
+        /*0850*/                   ST.E.SYS [R18+0x8], R6;                                   /* 0x0000000812007385 */
+                                                                                             /* 0x0003e2000010e906 */
+        /*0860*/                   ST.E.SYS [R16], R5;                                       /* 0x0000000010007385 */
+                                                                                             /* 0x0003e2000010e905 */
+        /*0870*/                   ST.E.SYS [R16+0x8], R7;                                   /* 0x0000000810007385 */
+                                                                                             /* 0x0003e2000010e907 */
+        /*0880*/                   WARPSYNC 0xffffffff;                                      /* 0xffffffff00007948 */
+                                                                                             /* 0x000fe20003800000 */
+        /*0890*/                   IADD3 R8, R2, -c[0x0][0x20], RZ;                          /* 0x8000080002087a10 */
+                                                                                             /* 0x001fd00007ffe0ff */
+        /*08a0*/                   CS2R.32 R4, SR_CLOCKLO;                                   /* 0x0000000000047805 */
+                                                                                             /* 0x002fd00000005000 */
+        /*08b0*/                   IMAD R3, R4, 0x1, -R3;                                    /* 0x0000000104037824 */
+                                                                                             /* 0x000fd000078e0a03 */
+        /*08c0*/                   STL [R8], R3;                                             /* 0x0000000308007387 */
+                                                                                             /* 0x0001e20000100800 */
+        /*08d0*/                   IMAD.U32 R6, RZ, RZ, R2;                                  /* 0x000000ffff067224 */
+                                                                                             /* 0x000fe200078e0002 */
+        /*08e0*/                   MOV R4, 0x0;                                              /* 0x0000000000047802 */
+                                                                                             /* 0x000fe20000000f00 */
+        /*08f0*/                   IMAD.U32 R7, RZ, RZ, R0;                                  /* 0x000000ffff077224 */
+                                                                                             /* 0x000fe200078e0000 */
+        /*0900*/                   MOV R5, 0x0;                                              /* 0x0000000000057802 */
+                                                                                             /* 0x000fe40000000f00 */
+        /*0910*/                   MOV R20, 0x0;                                             /* 0x0000000000147802 */
+                                                                                             /* 0x000fe40000000f00 */
+        /*0920*/                   MOV R21, 0x0;                                             /* 0x0000000000157802 */
+                                                                                             /* 0x000fd00000000f00 */
+        /*0930*/                   CALL.ABS.NOINC 0x0;                                       /* 0x0000000000007943 */
+                                                                                             /* 0x001fea0003c00000 */
+        /*0940*/                   EXIT;                                                     /* 0x000000000000794d */
+                                                                                             /* 0x000fea0003800000 */
+        /*0950*/                   BRA 0x950;                                                /* 0xfffffff000007947 */
+                                                                                             /* 0x000fc0000383ffff */
+        /*0960*/                   NOP;                                                      /* 0x0000000000007918 */
+                                                                                             /* 0x000fc00000000000 */
+        /*0970*/                   NOP;                                                      /* 0x0000000000007918 */
+                                                                                             /* 0x000fc00000000000 */
+		.............................................
+
+
+
+Fatbin ptx code:
+================
+arch = sm_70
+code version = [6,0]
+producer = cuda
+host = linux
+compile_size = 64bit
+compressed
+
+
+
+
+
+
+
+
+.version 6.0
+.target sm_70
+.address_size 64
+
+
+.extern .func (.param .b32 func_retval0) vprintf
+(
+.param .b64 vprintf_param_0,
+.param .b64 vprintf_param_1
+)
+;
+.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0};
+
+.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff(
+.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0,
+.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1,
+.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2,
+.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3,
+.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4,
+.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5,
+.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6,
+.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7
+)
+{
+.local .align 8 .b8 __local_depot0[8];
+.reg .b64 %SP;
+.reg .b64 %SPL;
+.reg .pred %p<6>;
+.reg .f32 %f<34>;
+.reg .b32 %r<38>;
+.reg .b64 %rd<18>;
+
+
+mov.u64 %rd17, __local_depot0;
+cvta.local.u64 %SP, %rd17;
+ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0];
+ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1];
+ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2];
+ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3];
+ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4];
+ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5];
+
+	mov.u32 %r6, %clock;
+
+	mov.u32 %r8, %ntid.x;
+mov.u32 %r9, %ctaid.x;
+mov.u32 %r10, %tid.x;
+mad.lo.s32 %r11, %r8, %r9, %r10;
+mov.u32 %r12, WARP_SZ;
+div.u32 %r13, %r11, %r12;
+mov.u32 %r14, %ntid.y;
+mov.u32 %r15, %ctaid.y;
+mov.u32 %r16, %tid.y;
+mad.lo.s32 %r17, %r14, %r15, %r16;
+shl.b32 %r2, %r13, 4;
+shl.b32 %r3, %r17, 4;
+setp.lt.s32	%p1, %r2, %r4;
+setp.gt.s32	%p2, %r5, 0;
+and.pred %p3, %p1, %p2;
+setp.lt.s32	%p4, %r3, %r7;
+and.pred %p5, %p3, %p4;
+mov.f32 %f26, 0f00000000;
+mov.f32 %f27, %f26;
+mov.f32 %f28, %f26;
+mov.f32 %f29, %f26;
+mov.f32 %f30, %f26;
+mov.f32 %f31, %f26;
+mov.f32 %f32, %f26;
+mov.f32 %f33, %f26;
+@!%p5 bra BB0_2;
+bra.uni BB0_1;
+
+BB0_1:
+mul.wide.s32 %rd4, %r2, 2;
+add.s64 %rd5, %rd1, %rd4;
+wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4;
+mul.wide.s32 %rd6, %r3, 2;
+add.s64 %rd7, %rd2, %rd6;
+wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5;
+mov.f32 %f25, 0f00000000;
+wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25};
+
+BB0_2:
+add.u64 %rd8, %SP, 0;
+cvta.to.local.u64 %rd9, %rd8;
+mul.lo.s32 %r35, %r3, %r4;
+cvt.s64.s32	%rd10, %r35;
+cvt.s64.s32	%rd11, %r2;
+add.s64 %rd12, %rd10, %rd11;
+shl.b64 %rd13, %rd12, 2;
+add.s64 %rd14, %rd3, %rd13;
+wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4;
+
+	mov.u32 %r34, %clock;
+
+	sub.s32 %r36, %r34, %r6;
+st.local.u32 [%rd9], %r36;
+mov.u64 %rd15, $str;
+cvta.global.u64 %rd16, %rd15;
+
+	{
+.reg .b32 temp_param_reg;
+
+	.param .b64 param0;
+st.param.b64	[param0+0], %rd16;
+.param .b64 param1;
+st.param.b64	[param1+0], %rd8;
+.param .b32 retval0;
+call.uni (retval0), 
+vprintf, 
+(
+param0, 
+param1
+);
+ld.param.b32	%r37, [retval0+0];
+
+
+	}
+	ret;
+}
+
+
+.visible .entry _Z17convertFp32ToFp16P6__halfPfi(
+.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0,
+.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1,
+.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2
+)
+{
+.reg .pred %p<2>;
+.reg .b16 %rs<2>;
+.reg .f32 %f<2>;
+.reg .b32 %r<6>;
+.reg .b64 %rd<9>;
+
+
+ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0];
+ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1];
+ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2];
+mov.u32 %r3, %ntid.x;
+mov.u32 %r4, %ctaid.x;
+mov.u32 %r5, %tid.x;
+mad.lo.s32 %r1, %r4, %r3, %r5;
+setp.ge.s32	%p1, %r1, %r2;
+@%p1 bra BB1_2;
+
+cvta.to.global.u64 %rd3, %rd2;
+mul.wide.s32 %rd4, %r1, 4;
+add.s64 %rd5, %rd3, %rd4;
+ld.global.f32 %f1, [%rd5];
+
+	{ cvt.rn.f16.f32 %rs1, %f1;}
+
+
+	cvta.to.global.u64 %rd6, %rd1;
+mul.wide.s32 %rd7, %r1, 2;
+add.s64 %rd8, %rd6, %rd7;
+st.global.u16 [%rd8], %rs1;
+
+BB1_2:
+ret;
+}
+
+
diff --git a/cuda-kernels/config_fermi_islip.icnt b/cuda-kernels/config_fermi_islip.icnt
new file mode 100755
index 0000000..a788090
--- /dev/null
+++ b/cuda-kernels/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 62;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/cuda-kernels/gpgpu_inst_stats.txt b/cuda-kernels/gpgpu_inst_stats.txt
new file mode 100755
index 0000000..acb1839
--- /dev/null
+++ b/cuda-kernels/gpgpu_inst_stats.txt
@@ -0,0 +1 @@
+kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence
diff --git a/cuda-kernels/gpgpusim.config b/cuda-kernels/gpgpusim.config
new file mode 100755
index 0000000..306d7f9
--- /dev/null
+++ b/cuda-kernels/gpgpusim.config
@@ -0,0 +1,149 @@
+# This config models the Pascal GP102 (GeForceGTX 1080Ti)
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40 
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 11
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# SFU is 32-width in pascal, then dp units initiation is 1 cycle
+-ptx_opcode_latency_int 4,13,4,5,145,16,4
+-ptx_opcode_initiation_int 1,2,2,2,8,16,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 1,2,1,1,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory
+# Pascal GP102 has 64KB L1 cache
+# The default is to disable the L1 cache, unless cache modifieres is used
+-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,8
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
+-gpgpu_cache:dl2_texture_only 0 
+
+# 4 KB Inst.
+-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+
+# enable operand collector 
+## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
+-gpgpu_operand_collector_num_units_sp 20
+-gpgpu_operand_collector_num_units_sfu 4
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+# gpgpu_num_reg_banks should be increased to 32, but it gives an error!
+-gpgpu_num_reg_banks 32 
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits)
+# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing from hynix H5GQ1H24AFR
+# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
+
+# Pascal has four schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log
new file mode 100644
index 0000000..f754f0c
--- /dev/null
+++ b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log
@@ -0,0 +1,324 @@
+kernel_name = 
+kernel_launch_uid = 
+
+Kernel Average Power Data:
+kernel_avg_power = 0
+gpu_avg_IBP, = -nan
+gpu_avg_ICP, = -nan
+gpu_avg_DCP, = -nan
+gpu_avg_TCP, = -nan
+gpu_avg_CCP, = -nan
+gpu_avg_SHRDP, = -nan
+gpu_avg_RFP, = -nan
+gpu_avg_SPP, = -nan
+gpu_avg_SFUP, = -nan
+gpu_avg_FPUP, = -nan
+gpu_avg_SCHEDP, = -nan
+gpu_avg_L2CP, = -nan
+gpu_avg_MCP, = -nan
+gpu_avg_NOCP, = -nan
+gpu_avg_DRAMP, = -nan
+gpu_avg_PIPEP, = -nan
+gpu_avg_IDLE_COREP, = -nan
+gpu_avg_CONST_DYNAMICP = -nan
+gpu_avg_TOT_INST, = -nan
+gpu_avg_FP_INT, = -nan
+gpu_avg_IC_H, = -nan
+gpu_avg_IC_M, = -nan
+gpu_avg_DC_RH, = -nan
+gpu_avg_DC_RM, = -nan
+gpu_avg_DC_WH, = -nan
+gpu_avg_DC_WM, = -nan
+gpu_avg_TC_H, = -nan
+gpu_avg_TC_M, = -nan
+gpu_avg_CC_H, = -nan
+gpu_avg_CC_M, = -nan
+gpu_avg_SHRD_ACC, = -nan
+gpu_avg_REG_RD, = -nan
+gpu_avg_REG_WR, = -nan
+gpu_avg_NON_REG_OPs, = -nan
+gpu_avg_SP_ACC, = -nan
+gpu_avg_SFU_ACC, = -nan
+gpu_avg_FPU_ACC, = -nan
+gpu_avg_MEM_RD, = -nan
+gpu_avg_MEM_WR, = -nan
+gpu_avg_MEM_PRE, = -nan
+gpu_avg_L2_RH, = -nan
+gpu_avg_L2_RM, = -nan
+gpu_avg_L2_WH, = -nan
+gpu_avg_L2_WM, = -nan
+gpu_avg_NOC_A, = -nan
+gpu_avg_PIPE_A, = -nan
+gpu_avg_IDLE_CORE_N, = -nan
+gpu_avg_CONST_DYNAMICN = -nan
+
+Kernel Maximum Power Data:
+kernel_max_power = 0
+gpu_max_IBP, = 0
+gpu_max_ICP, = 0
+gpu_max_DCP, = 0
+gpu_max_TCP, = 0
+gpu_max_CCP, = 0
+gpu_max_SHRDP, = 0
+gpu_max_RFP, = 0
+gpu_max_SPP, = 0
+gpu_max_SFUP, = 0
+gpu_max_FPUP, = 0
+gpu_max_SCHEDP, = 0
+gpu_max_L2CP, = 0
+gpu_max_MCP, = 0
+gpu_max_NOCP, = 0
+gpu_max_DRAMP, = 0
+gpu_max_PIPEP, = 0
+gpu_max_IDLE_COREP, = 0
+gpu_max_CONST_DYNAMICP = 0
+gpu_max_TOT_INST, = 0
+gpu_max_FP_INT, = 0
+gpu_max_IC_H, = 0
+gpu_max_IC_M, = 0
+gpu_max_DC_RH, = 0
+gpu_max_DC_RM, = 0
+gpu_max_DC_WH, = 0
+gpu_max_DC_WM, = 0
+gpu_max_TC_H, = 0
+gpu_max_TC_M, = 0
+gpu_max_CC_H, = 0
+gpu_max_CC_M, = 0
+gpu_max_SHRD_ACC, = 0
+gpu_max_REG_RD, = 0
+gpu_max_REG_WR, = 0
+gpu_max_NON_REG_OPs, = 0
+gpu_max_SP_ACC, = 0
+gpu_max_SFU_ACC, = 0
+gpu_max_FPU_ACC, = 0
+gpu_max_MEM_RD, = 0
+gpu_max_MEM_WR, = 0
+gpu_max_MEM_PRE, = 0
+gpu_max_L2_RH, = 0
+gpu_max_L2_RM, = 0
+gpu_max_L2_WH, = 0
+gpu_max_L2_WM, = 0
+gpu_max_NOC_A, = 0
+gpu_max_PIPE_A, = 0
+gpu_max_IDLE_CORE_N, = 0
+gpu_max_CONST_DYNAMICN = 0
+
+Kernel Minimum Power Data:
+kernel_min_power = 0
+gpu_min_IBP, = 0
+gpu_min_ICP, = 0
+gpu_min_DCP, = 0
+gpu_min_TCP, = 0
+gpu_min_CCP, = 0
+gpu_min_SHRDP, = 0
+gpu_min_RFP, = 0
+gpu_min_SPP, = 0
+gpu_min_SFUP, = 0
+gpu_min_FPUP, = 0
+gpu_min_SCHEDP, = 0
+gpu_min_L2CP, = 0
+gpu_min_MCP, = 0
+gpu_min_NOCP, = 0
+gpu_min_DRAMP, = 0
+gpu_min_PIPEP, = 0
+gpu_min_IDLE_COREP, = 0
+gpu_min_CONST_DYNAMICP = 0
+gpu_min_TOT_INST, = 0
+gpu_min_FP_INT, = 0
+gpu_min_IC_H, = 0
+gpu_min_IC_M, = 0
+gpu_min_DC_RH, = 0
+gpu_min_DC_RM, = 0
+gpu_min_DC_WH, = 0
+gpu_min_DC_WM, = 0
+gpu_min_TC_H, = 0
+gpu_min_TC_M, = 0
+gpu_min_CC_H, = 0
+gpu_min_CC_M, = 0
+gpu_min_SHRD_ACC, = 0
+gpu_min_REG_RD, = 0
+gpu_min_REG_WR, = 0
+gpu_min_NON_REG_OPs, = 0
+gpu_min_SP_ACC, = 0
+gpu_min_SFU_ACC, = 0
+gpu_min_FPU_ACC, = 0
+gpu_min_MEM_RD, = 0
+gpu_min_MEM_WR, = 0
+gpu_min_MEM_PRE, = 0
+gpu_min_L2_RH, = 0
+gpu_min_L2_RM, = 0
+gpu_min_L2_WH, = 0
+gpu_min_L2_WM, = 0
+gpu_min_NOC_A, = 0
+gpu_min_PIPE_A, = 0
+gpu_min_IDLE_CORE_N, = 0
+gpu_min_CONST_DYNAMICN = 0
+
+Accumulative Power Statistics Over Previous Kernels:
+gpu_tot_avg_power = -nan
+gpu_tot_max_power = 0
+gpu_tot_min_power = 0
+
+
+kernel_name = 
+kernel_launch_uid = 
+
+Kernel Average Power Data:
+kernel_avg_power = 0
+gpu_avg_IBP, = -nan
+gpu_avg_ICP, = -nan
+gpu_avg_DCP, = -nan
+gpu_avg_TCP, = -nan
+gpu_avg_CCP, = -nan
+gpu_avg_SHRDP, = -nan
+gpu_avg_RFP, = -nan
+gpu_avg_SPP, = -nan
+gpu_avg_SFUP, = -nan
+gpu_avg_FPUP, = -nan
+gpu_avg_SCHEDP, = -nan
+gpu_avg_L2CP, = -nan
+gpu_avg_MCP, = -nan
+gpu_avg_NOCP, = -nan
+gpu_avg_DRAMP, = -nan
+gpu_avg_PIPEP, = -nan
+gpu_avg_IDLE_COREP, = -nan
+gpu_avg_CONST_DYNAMICP = -nan
+gpu_avg_TOT_INST, = -nan
+gpu_avg_FP_INT, = -nan
+gpu_avg_IC_H, = -nan
+gpu_avg_IC_M, = -nan
+gpu_avg_DC_RH, = -nan
+gpu_avg_DC_RM, = -nan
+gpu_avg_DC_WH, = -nan
+gpu_avg_DC_WM, = -nan
+gpu_avg_TC_H, = -nan
+gpu_avg_TC_M, = -nan
+gpu_avg_CC_H, = -nan
+gpu_avg_CC_M, = -nan
+gpu_avg_SHRD_ACC, = -nan
+gpu_avg_REG_RD, = -nan
+gpu_avg_REG_WR, = -nan
+gpu_avg_NON_REG_OPs, = -nan
+gpu_avg_SP_ACC, = -nan
+gpu_avg_SFU_ACC, = -nan
+gpu_avg_FPU_ACC, = -nan
+gpu_avg_MEM_RD, = -nan
+gpu_avg_MEM_WR, = -nan
+gpu_avg_MEM_PRE, = -nan
+gpu_avg_L2_RH, = -nan
+gpu_avg_L2_RM, = -nan
+gpu_avg_L2_WH, = -nan
+gpu_avg_L2_WM, = -nan
+gpu_avg_NOC_A, = -nan
+gpu_avg_PIPE_A, = -nan
+gpu_avg_IDLE_CORE_N, = -nan
+gpu_avg_CONST_DYNAMICN = -nan
+
+Kernel Maximum Power Data:
+kernel_max_power = 0
+gpu_max_IBP, = 0
+gpu_max_ICP, = 0
+gpu_max_DCP, = 0
+gpu_max_TCP, = 0
+gpu_max_CCP, = 0
+gpu_max_SHRDP, = 0
+gpu_max_RFP, = 0
+gpu_max_SPP, = 0
+gpu_max_SFUP, = 0
+gpu_max_FPUP, = 0
+gpu_max_SCHEDP, = 0
+gpu_max_L2CP, = 0
+gpu_max_MCP, = 0
+gpu_max_NOCP, = 0
+gpu_max_DRAMP, = 0
+gpu_max_PIPEP, = 0
+gpu_max_IDLE_COREP, = 0
+gpu_max_CONST_DYNAMICP = 0
+gpu_max_TOT_INST, = 0
+gpu_max_FP_INT, = 0
+gpu_max_IC_H, = 0
+gpu_max_IC_M, = 0
+gpu_max_DC_RH, = 0
+gpu_max_DC_RM, = 0
+gpu_max_DC_WH, = 0
+gpu_max_DC_WM, = 0
+gpu_max_TC_H, = 0
+gpu_max_TC_M, = 0
+gpu_max_CC_H, = 0
+gpu_max_CC_M, = 0
+gpu_max_SHRD_ACC, = 0
+gpu_max_REG_RD, = 0
+gpu_max_REG_WR, = 0
+gpu_max_NON_REG_OPs, = 0
+gpu_max_SP_ACC, = 0
+gpu_max_SFU_ACC, = 0
+gpu_max_FPU_ACC, = 0
+gpu_max_MEM_RD, = 0
+gpu_max_MEM_WR, = 0
+gpu_max_MEM_PRE, = 0
+gpu_max_L2_RH, = 0
+gpu_max_L2_RM, = 0
+gpu_max_L2_WH, = 0
+gpu_max_L2_WM, = 0
+gpu_max_NOC_A, = 0
+gpu_max_PIPE_A, = 0
+gpu_max_IDLE_CORE_N, = 0
+gpu_max_CONST_DYNAMICN = 0
+
+Kernel Minimum Power Data:
+kernel_min_power = 0
+gpu_min_IBP, = 0
+gpu_min_ICP, = 0
+gpu_min_DCP, = 0
+gpu_min_TCP, = 0
+gpu_min_CCP, = 0
+gpu_min_SHRDP, = 0
+gpu_min_RFP, = 0
+gpu_min_SPP, = 0
+gpu_min_SFUP, = 0
+gpu_min_FPUP, = 0
+gpu_min_SCHEDP, = 0
+gpu_min_L2CP, = 0
+gpu_min_MCP, = 0
+gpu_min_NOCP, = 0
+gpu_min_DRAMP, = 0
+gpu_min_PIPEP, = 0
+gpu_min_IDLE_COREP, = 0
+gpu_min_CONST_DYNAMICP = 0
+gpu_min_TOT_INST, = 0
+gpu_min_FP_INT, = 0
+gpu_min_IC_H, = 0
+gpu_min_IC_M, = 0
+gpu_min_DC_RH, = 0
+gpu_min_DC_RM, = 0
+gpu_min_DC_WH, = 0
+gpu_min_DC_WM, = 0
+gpu_min_TC_H, = 0
+gpu_min_TC_M, = 0
+gpu_min_CC_H, = 0
+gpu_min_CC_M, = 0
+gpu_min_SHRD_ACC, = 0
+gpu_min_REG_RD, = 0
+gpu_min_REG_WR, = 0
+gpu_min_NON_REG_OPs, = 0
+gpu_min_SP_ACC, = 0
+gpu_min_SFU_ACC, = 0
+gpu_min_FPU_ACC, = 0
+gpu_min_MEM_RD, = 0
+gpu_min_MEM_WR, = 0
+gpu_min_MEM_PRE, = 0
+gpu_min_L2_RH, = 0
+gpu_min_L2_RM, = 0
+gpu_min_L2_WH, = 0
+gpu_min_L2_WM, = 0
+gpu_min_NOC_A, = 0
+gpu_min_PIPE_A, = 0
+gpu_min_IDLE_CORE_N, = 0
+gpu_min_CONST_DYNAMICN = 0
+
+Accumulative Power Statistics Over Previous Kernels:
+gpu_tot_avg_power = -nan
+gpu_tot_max_power = 0
+gpu_tot_min_power = 0
+
+
diff --git a/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log
new file mode 100644
index 0000000..f754f0c
--- /dev/null
+++ b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log
@@ -0,0 +1,324 @@
+kernel_name = 
+kernel_launch_uid = 
+
+Kernel Average Power Data:
+kernel_avg_power = 0
+gpu_avg_IBP, = -nan
+gpu_avg_ICP, = -nan
+gpu_avg_DCP, = -nan
+gpu_avg_TCP, = -nan
+gpu_avg_CCP, = -nan
+gpu_avg_SHRDP, = -nan
+gpu_avg_RFP, = -nan
+gpu_avg_SPP, = -nan
+gpu_avg_SFUP, = -nan
+gpu_avg_FPUP, = -nan
+gpu_avg_SCHEDP, = -nan
+gpu_avg_L2CP, = -nan
+gpu_avg_MCP, = -nan
+gpu_avg_NOCP, = -nan
+gpu_avg_DRAMP, = -nan
+gpu_avg_PIPEP, = -nan
+gpu_avg_IDLE_COREP, = -nan
+gpu_avg_CONST_DYNAMICP = -nan
+gpu_avg_TOT_INST, = -nan
+gpu_avg_FP_INT, = -nan
+gpu_avg_IC_H, = -nan
+gpu_avg_IC_M, = -nan
+gpu_avg_DC_RH, = -nan
+gpu_avg_DC_RM, = -nan
+gpu_avg_DC_WH, = -nan
+gpu_avg_DC_WM, = -nan
+gpu_avg_TC_H, = -nan
+gpu_avg_TC_M, = -nan
+gpu_avg_CC_H, = -nan
+gpu_avg_CC_M, = -nan
+gpu_avg_SHRD_ACC, = -nan
+gpu_avg_REG_RD, = -nan
+gpu_avg_REG_WR, = -nan
+gpu_avg_NON_REG_OPs, = -nan
+gpu_avg_SP_ACC, = -nan
+gpu_avg_SFU_ACC, = -nan
+gpu_avg_FPU_ACC, = -nan
+gpu_avg_MEM_RD, = -nan
+gpu_avg_MEM_WR, = -nan
+gpu_avg_MEM_PRE, = -nan
+gpu_avg_L2_RH, = -nan
+gpu_avg_L2_RM, = -nan
+gpu_avg_L2_WH, = -nan
+gpu_avg_L2_WM, = -nan
+gpu_avg_NOC_A, = -nan
+gpu_avg_PIPE_A, = -nan
+gpu_avg_IDLE_CORE_N, = -nan
+gpu_avg_CONST_DYNAMICN = -nan
+
+Kernel Maximum Power Data:
+kernel_max_power = 0
+gpu_max_IBP, = 0
+gpu_max_ICP, = 0
+gpu_max_DCP, = 0
+gpu_max_TCP, = 0
+gpu_max_CCP, = 0
+gpu_max_SHRDP, = 0
+gpu_max_RFP, = 0
+gpu_max_SPP, = 0
+gpu_max_SFUP, = 0
+gpu_max_FPUP, = 0
+gpu_max_SCHEDP, = 0
+gpu_max_L2CP, = 0
+gpu_max_MCP, = 0
+gpu_max_NOCP, = 0
+gpu_max_DRAMP, = 0
+gpu_max_PIPEP, = 0
+gpu_max_IDLE_COREP, = 0
+gpu_max_CONST_DYNAMICP = 0
+gpu_max_TOT_INST, = 0
+gpu_max_FP_INT, = 0
+gpu_max_IC_H, = 0
+gpu_max_IC_M, = 0
+gpu_max_DC_RH, = 0
+gpu_max_DC_RM, = 0
+gpu_max_DC_WH, = 0
+gpu_max_DC_WM, = 0
+gpu_max_TC_H, = 0
+gpu_max_TC_M, = 0
+gpu_max_CC_H, = 0
+gpu_max_CC_M, = 0
+gpu_max_SHRD_ACC, = 0
+gpu_max_REG_RD, = 0
+gpu_max_REG_WR, = 0
+gpu_max_NON_REG_OPs, = 0
+gpu_max_SP_ACC, = 0
+gpu_max_SFU_ACC, = 0
+gpu_max_FPU_ACC, = 0
+gpu_max_MEM_RD, = 0
+gpu_max_MEM_WR, = 0
+gpu_max_MEM_PRE, = 0
+gpu_max_L2_RH, = 0
+gpu_max_L2_RM, = 0
+gpu_max_L2_WH, = 0
+gpu_max_L2_WM, = 0
+gpu_max_NOC_A, = 0
+gpu_max_PIPE_A, = 0
+gpu_max_IDLE_CORE_N, = 0
+gpu_max_CONST_DYNAMICN = 0
+
+Kernel Minimum Power Data:
+kernel_min_power = 0
+gpu_min_IBP, = 0
+gpu_min_ICP, = 0
+gpu_min_DCP, = 0
+gpu_min_TCP, = 0
+gpu_min_CCP, = 0
+gpu_min_SHRDP, = 0
+gpu_min_RFP, = 0
+gpu_min_SPP, = 0
+gpu_min_SFUP, = 0
+gpu_min_FPUP, = 0
+gpu_min_SCHEDP, = 0
+gpu_min_L2CP, = 0
+gpu_min_MCP, = 0
+gpu_min_NOCP, = 0
+gpu_min_DRAMP, = 0
+gpu_min_PIPEP, = 0
+gpu_min_IDLE_COREP, = 0
+gpu_min_CONST_DYNAMICP = 0
+gpu_min_TOT_INST, = 0
+gpu_min_FP_INT, = 0
+gpu_min_IC_H, = 0
+gpu_min_IC_M, = 0
+gpu_min_DC_RH, = 0
+gpu_min_DC_RM, = 0
+gpu_min_DC_WH, = 0
+gpu_min_DC_WM, = 0
+gpu_min_TC_H, = 0
+gpu_min_TC_M, = 0
+gpu_min_CC_H, = 0
+gpu_min_CC_M, = 0
+gpu_min_SHRD_ACC, = 0
+gpu_min_REG_RD, = 0
+gpu_min_REG_WR, = 0
+gpu_min_NON_REG_OPs, = 0
+gpu_min_SP_ACC, = 0
+gpu_min_SFU_ACC, = 0
+gpu_min_FPU_ACC, = 0
+gpu_min_MEM_RD, = 0
+gpu_min_MEM_WR, = 0
+gpu_min_MEM_PRE, = 0
+gpu_min_L2_RH, = 0
+gpu_min_L2_RM, = 0
+gpu_min_L2_WH, = 0
+gpu_min_L2_WM, = 0
+gpu_min_NOC_A, = 0
+gpu_min_PIPE_A, = 0
+gpu_min_IDLE_CORE_N, = 0
+gpu_min_CONST_DYNAMICN = 0
+
+Accumulative Power Statistics Over Previous Kernels:
+gpu_tot_avg_power = -nan
+gpu_tot_max_power = 0
+gpu_tot_min_power = 0
+
+
+kernel_name = 
+kernel_launch_uid = 
+
+Kernel Average Power Data:
+kernel_avg_power = 0
+gpu_avg_IBP, = -nan
+gpu_avg_ICP, = -nan
+gpu_avg_DCP, = -nan
+gpu_avg_TCP, = -nan
+gpu_avg_CCP, = -nan
+gpu_avg_SHRDP, = -nan
+gpu_avg_RFP, = -nan
+gpu_avg_SPP, = -nan
+gpu_avg_SFUP, = -nan
+gpu_avg_FPUP, = -nan
+gpu_avg_SCHEDP, = -nan
+gpu_avg_L2CP, = -nan
+gpu_avg_MCP, = -nan
+gpu_avg_NOCP, = -nan
+gpu_avg_DRAMP, = -nan
+gpu_avg_PIPEP, = -nan
+gpu_avg_IDLE_COREP, = -nan
+gpu_avg_CONST_DYNAMICP = -nan
+gpu_avg_TOT_INST, = -nan
+gpu_avg_FP_INT, = -nan
+gpu_avg_IC_H, = -nan
+gpu_avg_IC_M, = -nan
+gpu_avg_DC_RH, = -nan
+gpu_avg_DC_RM, = -nan
+gpu_avg_DC_WH, = -nan
+gpu_avg_DC_WM, = -nan
+gpu_avg_TC_H, = -nan
+gpu_avg_TC_M, = -nan
+gpu_avg_CC_H, = -nan
+gpu_avg_CC_M, = -nan
+gpu_avg_SHRD_ACC, = -nan
+gpu_avg_REG_RD, = -nan
+gpu_avg_REG_WR, = -nan
+gpu_avg_NON_REG_OPs, = -nan
+gpu_avg_SP_ACC, = -nan
+gpu_avg_SFU_ACC, = -nan
+gpu_avg_FPU_ACC, = -nan
+gpu_avg_MEM_RD, = -nan
+gpu_avg_MEM_WR, = -nan
+gpu_avg_MEM_PRE, = -nan
+gpu_avg_L2_RH, = -nan
+gpu_avg_L2_RM, = -nan
+gpu_avg_L2_WH, = -nan
+gpu_avg_L2_WM, = -nan
+gpu_avg_NOC_A, = -nan
+gpu_avg_PIPE_A, = -nan
+gpu_avg_IDLE_CORE_N, = -nan
+gpu_avg_CONST_DYNAMICN = -nan
+
+Kernel Maximum Power Data:
+kernel_max_power = 0
+gpu_max_IBP, = 0
+gpu_max_ICP, = 0
+gpu_max_DCP, = 0
+gpu_max_TCP, = 0
+gpu_max_CCP, = 0
+gpu_max_SHRDP, = 0
+gpu_max_RFP, = 0
+gpu_max_SPP, = 0
+gpu_max_SFUP, = 0
+gpu_max_FPUP, = 0
+gpu_max_SCHEDP, = 0
+gpu_max_L2CP, = 0
+gpu_max_MCP, = 0
+gpu_max_NOCP, = 0
+gpu_max_DRAMP, = 0
+gpu_max_PIPEP, = 0
+gpu_max_IDLE_COREP, = 0
+gpu_max_CONST_DYNAMICP = 0
+gpu_max_TOT_INST, = 0
+gpu_max_FP_INT, = 0
+gpu_max_IC_H, = 0
+gpu_max_IC_M, = 0
+gpu_max_DC_RH, = 0
+gpu_max_DC_RM, = 0
+gpu_max_DC_WH, = 0
+gpu_max_DC_WM, = 0
+gpu_max_TC_H, = 0
+gpu_max_TC_M, = 0
+gpu_max_CC_H, = 0
+gpu_max_CC_M, = 0
+gpu_max_SHRD_ACC, = 0
+gpu_max_REG_RD, = 0
+gpu_max_REG_WR, = 0
+gpu_max_NON_REG_OPs, = 0
+gpu_max_SP_ACC, = 0
+gpu_max_SFU_ACC, = 0
+gpu_max_FPU_ACC, = 0
+gpu_max_MEM_RD, = 0
+gpu_max_MEM_WR, = 0
+gpu_max_MEM_PRE, = 0
+gpu_max_L2_RH, = 0
+gpu_max_L2_RM, = 0
+gpu_max_L2_WH, = 0
+gpu_max_L2_WM, = 0
+gpu_max_NOC_A, = 0
+gpu_max_PIPE_A, = 0
+gpu_max_IDLE_CORE_N, = 0
+gpu_max_CONST_DYNAMICN = 0
+
+Kernel Minimum Power Data:
+kernel_min_power = 0
+gpu_min_IBP, = 0
+gpu_min_ICP, = 0
+gpu_min_DCP, = 0
+gpu_min_TCP, = 0
+gpu_min_CCP, = 0
+gpu_min_SHRDP, = 0
+gpu_min_RFP, = 0
+gpu_min_SPP, = 0
+gpu_min_SFUP, = 0
+gpu_min_FPUP, = 0
+gpu_min_SCHEDP, = 0
+gpu_min_L2CP, = 0
+gpu_min_MCP, = 0
+gpu_min_NOCP, = 0
+gpu_min_DRAMP, = 0
+gpu_min_PIPEP, = 0
+gpu_min_IDLE_COREP, = 0
+gpu_min_CONST_DYNAMICP = 0
+gpu_min_TOT_INST, = 0
+gpu_min_FP_INT, = 0
+gpu_min_IC_H, = 0
+gpu_min_IC_M, = 0
+gpu_min_DC_RH, = 0
+gpu_min_DC_RM, = 0
+gpu_min_DC_WH, = 0
+gpu_min_DC_WM, = 0
+gpu_min_TC_H, = 0
+gpu_min_TC_M, = 0
+gpu_min_CC_H, = 0
+gpu_min_CC_M, = 0
+gpu_min_SHRD_ACC, = 0
+gpu_min_REG_RD, = 0
+gpu_min_REG_WR, = 0
+gpu_min_NON_REG_OPs, = 0
+gpu_min_SP_ACC, = 0
+gpu_min_SFU_ACC, = 0
+gpu_min_FPU_ACC, = 0
+gpu_min_MEM_RD, = 0
+gpu_min_MEM_WR, = 0
+gpu_min_MEM_PRE, = 0
+gpu_min_L2_RH, = 0
+gpu_min_L2_RM, = 0
+gpu_min_L2_WH, = 0
+gpu_min_L2_WM, = 0
+gpu_min_NOC_A, = 0
+gpu_min_PIPE_A, = 0
+gpu_min_IDLE_CORE_N, = 0
+gpu_min_CONST_DYNAMICN = 0
+
+Accumulative Power Statistics Over Previous Kernels:
+gpu_tot_avg_power = -nan
+gpu_tot_max_power = 0
+gpu_tot_min_power = 0
+
+
diff --git a/cuda-kernels/gpuwattch_gtx1080Ti.xml b/cuda-kernels/gpuwattch_gtx1080Ti.xml
new file mode 100755
index 0000000..02619ff
--- /dev/null
+++ b/cuda-kernels/gpuwattch_gtx1080Ti.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+	<component id="system" name="system">
+		<!--McPAT will skip the components if number is set to 0 -->
+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+		<param name="number_of_cores" value="28"/>
+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+		<param name="number_of_L1Directories" value="0"/>
+		<param name="number_of_L2Directories" value="0"/>
+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+		<param name="number_of_NoCs" value="1"/> 
+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
+		<param name="homogeneous_L2s" value="1"/>
+		<param name="homogeneous_L1Directorys" value="1"/>
+		<param name="homogeneous_L2Directorys" value="1"/>
+		<param name="homogeneous_L3s" value="1"/>
+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+		<param name="homogeneous_NoCs" value="1"/>
+		<param name="core_tech_node" value="23"/><!-- nm -->
+		<param name="target_core_clockrate" value="1481"/><!--MHz -->
+		<param name="temperature" value="380"/> <!-- Kelvin -->
+		<param name="number_cache_levels" value="2"/>
+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+		<param name="machine_bits" value="32"/>
+		<param name="virtual_address_width" value="32"/>
+		<param name="physical_address_width" value="32"/>
+		<param name="virtual_memory_page_size" value="4096"/>
+		<param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+		<!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+		<param name="TOT_INST" value="10" />
+		<param name="FP_INT" value="10" />
+		<param name="IC_H" value="0.001" />
+		<param name="IC_M" value="10" />
+		<param name="DC_RH" value="1" />
+		<param name="DC_RM" value="1" />
+		<param name="DC_WH" value="1" />
+		<param name="DC_WM" value="1" />
+		<param name="TC_H" value="0.001" />
+		<param name="TC_M" value="10" />
+		<param name="CC_H" value="4.5071" />
+		<param name="CC_M" value="10" />
+		<param name="SHRD_ACC" value="10" />
+		<param name="REG_RD" value="1.6294" />
+		<param name="REG_WR" value="0.5031" />
+		<param name="NON_REG_OPs" value="0.01" />
+		<param name="SP_ACC" value="10" />
+		<param name="SFU_ACC" value="0.0082" />
+		<param name="FPU_ACC" value="0.4126" />
+		<param name="MEM_RD" value="0.1234" />
+		<param name="MEM_WR" value="0.001" />
+		<param name="MEM_PRE" value="0.001" />
+		<param name="L2_RH" value="100" />
+		<param name="L2_RM" value="100" />
+		<param name="L2_WH" value="100" />
+		<param name="L2_WM" value="42.6966" />
+		<param name="NOC_A" value="100" />
+		<param name="PIPE_A" value="44.8085" />
+		<param name="IDLE_CORE_N" value="2.0382"/>
+		<param name="CONST_DYNAMICN" value="5.0005" />
+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
+		<!-- *********************** cores ******************* -->
+		<component id="system.core0" name="core0">
+			<!-- Core property -->
+			<param name="clock_rate" value="1481"/>
+			<param name="instruction_length" value="32"/>
+			<param name="opcode_width" value="9"/>
+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
+			default value is machine_bits, if not set --> 
+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+			<!-- inorder/OoO -->
+			<param name="number_hardware_threads" value="32"/>
+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
+			<param name="fetch_width" value="1"/>
+			<!-- fetch_width determins the size of cachelines of L1 cache block -->
+			<param name="number_instruction_fetch_ports" value="1"/>
+			<param name="decode_width" value="1"/>
+			<!-- decode_width determins the number of ports of the 
+			renaming table (both RAM and CAM) scheme -->
+			<param name="issue_width" value="2"/>
+			<!-- issue_width determins the number of ports of Issue window and other logic 
+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+			<param name="commit_width" value="2"/>
+			<!-- commit_width determins the number of ports of register files -->
+			<param name="fp_issue_width" value="1"/>
+			<param name="prediction_width" value="0"/> 
+			<!-- number of branch instructions can be predicted simultannouesl-->
+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
+			Theses parameters are reserved for future use.--> 
+			<param name="pipelines_per_core" value="1,1"/>
+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+			<param name="pipeline_depth" value="8,8"/>
+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+			<!-- issue and exe unit-->
+			<param name="ALU_per_core" value="32"/>
+			<!-- contains an adder, a shifter, and a logical unit -->
+			<param name="MUL_per_core" value="4"/>
+			<!-- For MUL and Div -->
+			<param name="FPU_per_core" value="32"/>		
+			<!-- buffer between IF and ID stage -->
+			<param name="instruction_buffer_size" value="1"/>
+			<!-- buffer between ID and sche/exe stage -->
+			<param name="decoded_stream_buffer_size" value="1"/>
+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+			<param name="instruction_window_size" value="1"/>
+			<param name="fp_instruction_window_size" value="1"/>
+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+			<param name="ROB_size" value="0"/>
+			<!-- each in-flight instruction has an entry in ROB -->
+			<!-- registers -->
+			<!-- SM parameters  Added by Syed Gilani -->
+			<param name="rf_banks" value="32"/>
+			<param name="simd_width" value="32"/>
+			<param name="collector_units" value="32"/>
+			<param name="core_clock_ratio" value="2"/>
+			<param name="warp_size" value="32"/>
+
+			<param name="archi_Regs_IRF_size" value="65536"/>			
+			<param name="archi_Regs_FRF_size" value="32"/>
+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
+			renaming logic is for both integer and floating point insts.  -->
+			<param name="phy_Regs_IRF_size" value="32"/>
+			<param name="phy_Regs_FRF_size" value="32"/>
+			<!-- rename logic -->
+			<param name="rename_scheme" value="0"/>
+			<!-- can be RAM based(0) or CAM based(1) rename scheme 
+			RAM-based scheme will have free list, status table;
+			CAM-based scheme have the valid bit in the data field of the CAM 
+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+			Detailed RAT Implementation see TR -->
+			<param name="register_windows_size" value="0"/>
+			<!-- how many windows in the windowed register file, sun processors;
+			no register windowing is used when this number is 0 -->
+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+			They will always try to exeute out-of-order though. -->
+			<param name="LSU_order" value="inorder"/>
+			<param name="store_buffer_size" value="32"/>
+			<!-- By default, in-order cores do not have load buffers -->
+			<param name="load_buffer_size" value="32"/>	
+			<!-- number of ports refer to sustainable concurrent memory accesses --> 
+			<param name="memory_ports" value="2"/>	
+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+			as well as the ports of Dcache which is connected to LSU -->	
+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+			<param name="RAS_size" value="1"/>						
+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+			<stat name="branch_mispredictions" value="0"/>
+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>
+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>
+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+			<!-- the following cycle stats are used for heterogeneouse cores only, 
+				please ignore them if homogeneouse cores -->
+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>
+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>
+			<!-- instruction buffer stats -->
+			<!-- ROB stats, both RS and Phy based OoOs have ROB
+			performance simulator should capture the difference on accesses,
+			otherwise, McPAT has to guess based on number of commited instructions. -->
+			<stat name="ROB_reads" value="263886"/>
+			<stat name="ROB_writes" value="263886"/>
+			<!-- RAT accesses -->
+			<stat name="rename_accesses" value="263886"/>
+			<stat name="fp_rename_accesses" value="263886"/>
+			<!-- decode and rename stage use this, should be total ic - nop -->
+			<!-- Inst window stats -->
+			<stat name="inst_window_reads" value="263886"/>
+			<stat name="inst_window_writes" value="263886"/>
+			<stat name="inst_window_wakeup_accesses" value="263886"/>
+			<stat name="fp_inst_window_reads" value="263886"/>
+			<stat name="fp_inst_window_writes" value="263886"/>
+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+			<!--  RF accesses -->
+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+			
+			<!-- The following stat is for operand collector power - Added by Syed -->
+			<stat name="non_rf_operands" value="0"/>
+
+			<!-- accesses to the working reg -->
+			<stat name="function_calls" value="0"/>
+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+			<!-- Number of Windowes switches (number of function calls and returns)-->
+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			
+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+			<stat name="cdb_alu_accesses" value="0"/>
+			<stat name="cdb_mul_accesses" value="0"/>
+			<stat name="cdb_fpu_accesses" value="0"/>
+			<!-- multiple cycle accesses should be counted multiple times, 
+			otherwise, McPAT can use internal counter for different floating point instructions 
+			to get final accesses. But that needs detailed info for floating point inst mix -->
+			<!--  currently the performance simulator should 
+			make sure all the numbers are final numbers, 
+			including the explicit read/write accesses, 
+			and the implicite accesses such as replacements and etc.
+			Future versions of McPAT may be able to reason the implicite access
+			based on param and stats of last level cache
+			The same rule applies to all cache access stats too!  -->
+			<!-- following is AF for max power computation. 
+				Do not change them, unless you understand them-->
+			<stat name="IFU_duty_cycle" value="0.25"/>			
+			<stat name="LSU_duty_cycle" value="0.25"/>
+			<stat name="MemManU_I_duty_cycle" value="1"/>
+			<stat name="MemManU_D_duty_cycle" value="0.25"/>
+			<stat name="ALU_duty_cycle" value="0.9"/>
+			<stat name="MUL_duty_cycle" value="0.5"/>
+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>
+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>
+			<stat name="FPU_cdb_duty_cycle" value="15"/>	
+			<component id="system.core0.predictor" name="PBT">
+				<!-- branch predictor; tournament predictor see Alpha implementation -->
+				<param name="local_predictor_size" value="10,3"/>
+				<param name="local_predictor_entries" value="1024"/>
+				<param name="global_predictor_entries" value="4096"/>
+				<param name="global_predictor_bits" value="2"/>
+				<param name="chooser_predictor_entries" value="4096"/>
+				<param name="chooser_predictor_bits" value="2"/>
+				<!-- These parameters can be combined like below in next version
+				<param name="load_predictor" value="10,3,1024"/>
+				<param name="global_predictor" value="4096,2"/>
+				<param name="predictor_chooser" value="4096,2"/>
+				-->
+			</component>
+			<component id="system.core0.itlb" name="itlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
+				which is actually a replacement -->
+			</component>
+			<component id="system.core0.icache" name="icache">
+				<!-- there is no write requests to itlb although writes happen to it after miss, 
+				which is actually a replacement -->
+				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+				<param name="buffer_sizes" value="16, 16, 16,0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="conflicts" value="0"/>				
+			</component>
+			<component id="system.core0.dtlb" name="dtlb">
+				<param name="number_entries" value="1"/>
+				<stat name="total_accesses" value="0"/>
+				<stat name="total_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.ccache" name="ccache">
+			        <!-- all the buffer related are optional -->
+				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.tcache" name="tcache">
+			        <!-- all the buffer related are optional -->
+				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+      <!--model the shared memory by mimicing dcache-->
+			<component id="system.core0.sharedmemory" name="sharedmemory">
+			        <!-- all the buffer related are optional -->
+				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.dcache" name="dcache">
+			        <!-- all the buffer related are optional -->
+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 0"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+				<stat name="conflicts" value="0"/>	
+			</component>
+			<component id="system.core0.BTB" name="BTB">
+			        <!-- all the buffer related are optional -->
+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>
+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			</component>
+	</component>
+		<component id="system.L1Directory0" name="L1Directory0">
+				<param name="Directory_type" value="0"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="800000"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="20"/>	
+				<stat name="duty_cycle" value="0.45"/>	
+		</component>
+		<component id="system.L2Directory0" name="L2Directory0">
+				<param name="Directory_type" value="1"/>
+			    <!--0 cam based shadowed tag. 1 directory cache -->	
+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
+				<!-- all the buffer related are optional -->
+			    <param name="clockrate" value="1400"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw search ports -->
+				<param name="device_type" value="0"/>
+				<!-- altough there are multiple access types, 
+				Performance simulator needs to cast them into reads or writes
+				e.g. the invalidates can be considered as writes -->
+				<stat name="read_accesses" value="0"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>
+			    <stat name="duty_cycle" value="0.45"/>		
+		</component>
+		<component id="system.L20" name="L20">
+			<!-- all the buffer related are optional -->
+				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>
+			    <!-- consider 4-way bank interleaving for Niagara 1 -->
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<param name="clockrate" value="2962"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<stat name="read_accesses" value="200000"/>
+				<stat name="write_accesses" value="0"/>
+				<stat name="read_misses" value="0"/>
+				<stat name="write_misses" value="0"/>
+				<stat name="conflicts" value="0"/>	
+			    <stat name="duty_cycle" value="0.5"/>	
+		</component>
+		
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+				<param name="clockrate" value="3500"/>
+				<param name="ports" value="1,1,1"/>
+				<!-- number of r, w, and rw ports -->
+				<param name="device_type" value="0"/>
+				<param name="buffer_sizes" value="16, 16, 16, 16"/>
+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
+				<stat name="read_accesses" value="58824"/>
+				<stat name="write_accesses" value="27276"/>
+				<stat name="read_misses" value="1632"/>
+				<stat name="write_misses" value="183"/>
+				<stat name="conflicts" value="0"/>	
+	            <stat name="duty_cycle" value="0.35"/>	
+		</component>
+
+
+<!--**********************************************************************-->
+		<component id="system.NoC0" name="noc0">
+			<param name="clockrate" value="700"/>
+			<param name="type" value="1"/>
+			<!-- 1 NoC, O bus -->
+			<param name="horizontal_nodes" value="2"/>
+			<param name="vertical_nodes" value="1"/>
+			<param name="has_global_link" value="0"/>
+			<!-- 1 has global link, 0 does not have global link -->
+			<param name="link_throughput" value="1"/><!--w.r.t clock -->
+			<param name="link_latency" value="1"/><!--w.r.t clock -->
+			<!-- througput >= latency -->
+			<!-- Router architecture -->
+			<param name="input_ports" value="6"/>
+			<param name="output_ports" value="6"/>
+			<param name="virtual_channel_per_port" value="1"/>
+			<!-- input buffer; in classic routers only input ports need buffers -->
+			<param name="flit_bits" value="32"/>
+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+			<param name="chip_coverage" value="1"/>
+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+			<stat name="total_accesses" value="0"/>
+			<!-- This is the number of total accesses within the whole network not for each router -->
+			<stat name="duty_cycle" value="0.6"/>
+		</component>	
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+		<component id="system.mem" name="mem">
+			<!-- Main memory property -->
+			<param name="mem_tech_node" value="23"/>
+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+			<!-- above numbers can be easily found from Wikipedia -->
+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+			Current McPAT assumes single DIMMs are used.--> 		
+			<param name="number_ranks" value="2"/>
+			<param name="num_banks_of_DRAM_chip" value="6"/>			
+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+			<param name="output_width_of_DRAM_chip" value="8"/>
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+			<param name="burstlength_of_DRAM_chip" value="8"/>
+			<stat name="memory_accesses" value="1052"/>
+			<stat name="memory_reads" value="1052"/>
+			<stat name="memory_writes" value="1052"/>									
+		</component>
+		<component id="system.mc" name="mc">
+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+			<!-- current version of McPAT uses published values for base parameters of memory controller
+			improvments on MC will be added in later versions. -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 
+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+			<param name="block_size" value="64"/><!--B-->
+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->
+			<!-- current McPAT only supports homogeneous memory controllers -->
+			<param name="memory_channels_per_mc" value="2"/>
+			<param name="number_ranks" value="1"/>
+			<param name="withPHY" value="0"/>
+			<!-- # of ranks of each channel-->
+			<param name="req_window_size_per_channel" value="16"/>
+			<param name="IO_buffer_size_per_channel" value="16"/>
+			<param name="databus_width" value="32"/>
+			<param name="addressbus_width" value="32"/>
+			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
+
+			<!-- McPAT will add the control bus width to the addressbus width automatically -->
+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>
+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>
+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
+			the average power per MC or per channel. This is sufficent for most application. 
+			Further trackdown can be easily added in later versions. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.niu" name="niu">
+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->
+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 
+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 
+			the average power per nic or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.pcie" name="pcie">
+			<!-- On chip PCIe controller, including Phy-->
+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 
+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+			<param name="withPHY" value="1"/>
+			<param name="clockrate" value="350"/>
+			<param name="number_units" value="0"/>
+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 
+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			
+		</component>
+<!--**********************************************************************-->
+		<component id="system.flashc" name="flashc">
+		    <param name="number_flashcs" value="0"/>
+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+            <param name="withPHY" value="1"/>
+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->
+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 
+			the average power per fc or per channel. This is sufficent for most application -->  			
+		</component>
+<!--**********************************************************************-->
+
+		</component>
+</component>
diff --git a/cuda-kernels/tensor_core b/cuda-kernels/tensor_core
new file mode 100755
index 0000000..b25f3d9
Binary files /dev/null and b/cuda-kernels/tensor_core differ
diff --git a/cuda-kernels/tensor_core.cu b/cuda-kernels/tensor_core.cu
new file mode 100644
index 0000000..483a42b
--- /dev/null
+++ b/cuda-kernels/tensor_core.cu
@@ -0,0 +1,250 @@
+/* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+
+// Define some error checking macros.
+#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); }
+void cudaErrCheck_(cudaError_t stat, const char *file, int line) {
+   if (stat != cudaSuccess) {
+      fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line);
+   }
+}
+
+
+
+
+#include <mma.h>
+using namespace nvcuda;
+
+// Must be multiples of 16 for wmma code to work
+#define MATRIX_M (16)
+#define MATRIX_N (16)
+#define MATRIX_K (16)
+
+
+
+// The only dimensions currently supported by WMMA
+const int WMMA_M = 16;
+const int WMMA_N = 16;
+const int WMMA_K = 16;
+
+
+// Performs an MxNxK GEMM (C=alpha*A*B + beta*C) assuming:
+//  1) Matrices are packed in memory.
+//  2) M, N and K are multiples of 16. 
+//  3) Neither A nor B are transposed.
+// Note: This is NOT a high performance example but is for demonstration purposes only
+//       For a high performance code please use the GEMM provided in cuBLAS.
+__global__ void wmma_example(half *a, half *b, float *c, int M, int N, int K, float alpha, float beta) {
+   unsigned int start_time=0,end_time=0;
+   // Leading dimensions. Packed with no transpositions.
+   start_time=clock();
+   int lda = M;
+   int ldb = K;
+   int ldc = M;
+
+   // Tile using a 2D grid/
+   int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize;
+   int warpN = (blockIdx.y * blockDim.y + threadIdx.y);
+ 
+   // Declare the fragments
+   wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag;
+   wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag;
+   wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> acc_frag;
+   wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag;
+
+   wmma::fill_fragment(c_frag, 0.0f);
+   
+   int i=0;
+   int aRow = warpM * WMMA_M;
+   int bCol = warpN * WMMA_N;
+   int aCol = i;
+   int bRow = i;
+
+
+   // Bounds checking
+   if (aRow < M && aCol < K && bRow < K && bCol < N) {
+      wmma::load_matrix_sync(a_frag, a+aRow+aCol*lda, lda);
+      wmma::load_matrix_sync(b_frag, b+bRow*ldb+bCol, ldb);
+      wmma::mma_sync(c_frag, a_frag, b_frag, c_frag);
+      //wmma::mma_sync(acc_frag, a_frag, b_frag, acc_frag);
+   }
+   int cRow = warpM * WMMA_M;
+   int cCol = warpN * WMMA_N;
+   wmma::store_matrix_sync(c + cRow + cCol * ldc, c_frag, ldc, wmma::mem_col_major);
+   end_time=clock();
+   printf("clock=%d",end_time-start_time);
+}
+
+__global__ void convertFp32ToFp16 (half *out, float *in, int n) {
+   int idx = blockDim.x * blockIdx.x + threadIdx.x;
+   if (idx < n) {
+      out[idx] = in[idx];
+   }
+}
+
+int main(int argc, char* argv[]) {
+   float *a_fp32;
+   float *b_fp32;
+   half *a_fp16;
+   half *b_fp16;
+
+   float *c;
+   float *c_cublas;
+   float *c_wmma;
+
+   float *c_host_cublas;
+   float *c_host_wmma;
+   float *a_host_wmma;
+   float *b_host_wmma;
+   float *c_init_host_wmma;
+   
+   
+   cudaEvent_t startWMMA;
+   cudaEvent_t stopWMMA;
+   
+   
+   cudaErrCheck(cudaEventCreate(&startWMMA));
+   cudaErrCheck(cudaEventCreate(&stopWMMA));
+   
+   
+   
+   
+   // Use tensor cores
+  
+ 
+   cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float)));
+   cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float)));
+   cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half)));
+   cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half)));
+
+   cudaErrCheck(cudaMalloc((void**)&c, MATRIX_M * MATRIX_N * sizeof(float)));
+   cudaErrCheck(cudaMalloc((void**)&c_wmma, MATRIX_M * MATRIX_N * sizeof(float)));
+
+   c_host_wmma      = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float));
+   c_init_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float));
+   a_host_wmma      = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float));
+   b_host_wmma      = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float));
+
+
+   
+//   printf("a_fp32\n");
+   for(int m=0;m<MATRIX_M;m++){
+	for(int n=0;n<MATRIX_K;n++){
+		a_host_wmma[m*MATRIX_K+n]=m*MATRIX_K+n;
+	}
+	//printf(";\n");
+   }
+  // printf("b_fp32\n");
+   for(int m=0;m<MATRIX_K;m++){
+	for(int n=0;n<MATRIX_N;n++){
+		b_host_wmma[m*MATRIX_N+n]=m*MATRIX_N+n;
+//		printf("%f ",b_host_wmma[m*MATRIX_N+n]);
+	}
+//	printf(";\n");
+   }
+   cudaErrCheck(cudaMemcpy(a_fp32,a_host_wmma,  MATRIX_M * MATRIX_K * sizeof(float), cudaMemcpyHostToDevice));
+   cudaErrCheck(cudaMemcpy(b_fp32,b_host_wmma,  MATRIX_K * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice));
+
+   // curand doesn't currently support fp16 so we generate in fp32 and convert to fp16.
+   convertFp32ToFp16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K);
+   convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N);
+
+   for(int m=0;m<MATRIX_M;m++){
+	for(int n=0;n<MATRIX_N;n++){
+		c_init_host_wmma[m*MATRIX_N+n]=0;
+	}
+   }
+   cudaErrCheck(cudaMemcpy(c, c_init_host_wmma,  MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice));
+   cudaErrCheck(cudaMemcpy(c_wmma, c, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToDevice));
+
+   float alpha = 1.0f;
+   float beta = 1.0f;
+
+
+   printf("\nM = %d, N = %d, K = %d. alpha = %f, beta = %f\n\n", MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta);
+   
+   // First: using WMMA
+   dim3 gridDim;
+   dim3 blockDim;
+ 
+   // blockDim.x must be a multple of warpSize
+   // 128x4 means we have 16 warps and a block computes a 64x64 output tile
+   blockDim.x = 128;
+   blockDim.y = 4;
+
+   gridDim.x = (MATRIX_M + (WMMA_M * blockDim.x / 32 - 1)) / (WMMA_M * blockDim.x / 32);
+   gridDim.y = (MATRIX_N + WMMA_N * blockDim.y - 1) / (WMMA_N * blockDim.y);
+   
+   printf("Running with wmma...\n");
+   cudaErrCheck(cudaEventRecord(startWMMA));
+   wmma_example <<< 1, 32>>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta);
+  // wmma_example <<< gridDim, blockDim >>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta);
+   cudaErrCheck(cudaEventRecord(stopWMMA));
+
+
+   
+
+   // Error checking
+   printf("\nChecking results...\n");
+   cudaErrCheck(cudaMemcpy(c_host_wmma, c_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost));
+  // printf("c_host\n");
+  // for(int m=0;m<MATRIX_M;m++){
+//	for(int n=0;n<MATRIX_N;n++){
+//	printf("%f ",c_host_wmma[m*MATRIX_N+n]);
+//	}
+//	printf(";\n");
+  // }
+   
+      float wmmaTime;
+      cudaErrCheck(cudaEventSynchronize(stopWMMA));
+      cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA));
+      printf("wmma took %fms\n", wmmaTime);
+      //printf("Clock=%d",stopWMMA-startWMMA);
+      printf("\nFor a faster code using wmma you should check out the cudaTensorCoreGemm sample in the CUDA Toolkit.\nThis code was written as a demo only!\n\n");
+   
+   
+   cudaErrCheck(cudaEventDestroy(startWMMA));
+   cudaErrCheck(cudaEventDestroy(stopWMMA));
+
+   
+   cudaErrCheck(cudaFree(a_fp32));
+   cudaErrCheck(cudaFree(b_fp32));
+   cudaErrCheck(cudaFree(a_fp16));
+   cudaErrCheck(cudaFree(b_fp16));
+
+   cudaErrCheck(cudaFree(c));
+   cudaErrCheck(cudaFree(c_wmma));
+   
+   free(c_host_wmma);
+
+   cudaErrCheck(cudaDeviceReset());
+   return 0;
+}
+
+
diff --git a/cuobjdump_to_ptxplus/ptx_parser.h b/cuobjdump_to_ptxplus/ptx_parser.h
index 7cfb5c5..a534e92 100644
--- a/cuobjdump_to_ptxplus/ptx_parser.h
+++ b/cuobjdump_to_ptxplus/ptx_parser.h
@@ -82,6 +82,7 @@ void add_file( unsigned a, const char *b ) {PTX_PARSE_DPRINTF(" ");}
 void add_variables() {PTX_PARSE_DPRINTF(" ");}
 void set_variable_type() {PTX_PARSE_DPRINTF(" ");}
 void add_option(int a ) {PTX_PARSE_DPRINTF(" ");}
+void add_wmma_option(int a ) {PTX_PARSE_DPRINTF(" ");}
 void add_array_initializer() {PTX_PARSE_DPRINTF(" ");}
 void add_label( const char *a ) {PTX_PARSE_DPRINTF(" ");}
 void set_return() {PTX_PARSE_DPRINTF(" ");}
@@ -99,6 +100,7 @@ void add_1vector_operand( const char *a ) {PTX_PARSE_DPRINTF(" ");}
 void add_2vector_operand( const char *a, const char *b ) {PTX_PARSE_DPRINTF(" ");}
 void add_3vector_operand( const char *a, const char *b, const char *c ) {PTX_PARSE_DPRINTF(" ");}
 void add_4vector_operand( const char *a, const char *b, const char *c, const char *d ) {PTX_PARSE_DPRINTF(" ");}
+void add_8vector_operand( const char *a, const char *b, const char *c, const char *d ,const char *e,const char *f,const char *g,const char *h) {PTX_PARSE_DPRINTF(" ");}
 void add_builtin_operand( int a, int b ) {PTX_PARSE_DPRINTF(" ");}
 void add_memory_operand() {PTX_PARSE_DPRINTF(" ");}
 void change_memory_addr_space( const char *a ) {PTX_PARSE_DPRINTF(" ");}
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index bddaf8c..7407269 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -1493,6 +1493,12 @@ unsigned trunc(unsigned num, unsigned precision) {
 	}
 	return num;
 }
+void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
+{
+}
+void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
+{
+}
 
 void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 {
@@ -1565,7 +1571,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 	for (i=0;i<16;i++){
 		for(j=0;j<16;j++){
 			for(k=0;k<16;k++){
-				matrix_d[i][j].f32=matrix_d[i][j].f32+matrix_a[i][k].f32*matrix_b[k][j].f32;
+				matrix_d[i][j].f32=matrix_d[i][j].f32+matrix_a[i][k].f32*matrix_b[j][k].f32;
 			}
 			matrix_d[i][j].f32+=matrix_c[i][j].f32;
 		}
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index a3cc83f..e6f957a 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -53,6 +53,8 @@ OP_DEF(BRX_OP,brx_impl,"brx",0,3)
 OP_DEF(BREV_OP,brev_impl,"brev",1,1)
 OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9)
 OP_W_DEF(MMA_OP,mma_impl,"mma",1,1)
+OP_W_DEF(MMA_LD_OP,mma_ld_impl,"mma_load",1,5)
+OP_W_DEF(MMA_ST_OP,mma_st_impl,"mma_store",0,5)
 OP_DEF(CALL_OP,call_impl,"call",1,3)
 OP_DEF(CALLP_OP,callp_impl,"callp",1,3)
 OP_DEF(CLZ_OP,clz_impl,"clz",1,1)
diff --git a/src/cuda-sim/opcodes.h b/src/cuda-sim/opcodes.h
index aa133da..b91d92f 100644
--- a/src/cuda-sim/opcodes.h
+++ b/src/cuda-sim/opcodes.h
@@ -60,5 +60,14 @@ enum special_regs {
    WARPID_REG,
    WARPSZ_REG
 };
-
+enum wmma_type{
+	LOAD_A,
+	LOAD_B,
+	LOAD_C,
+	STORE_D,
+	MMA,
+	ROW,
+	COL,
+	M16N16K16
+};
 #endif
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index e07e339..f67dddd 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -60,7 +60,7 @@ addc    TC; ptx_lval.int_value = ADDC_OP; return OPCODE;
 and	TC; ptx_lval.int_value = AND_OP; return OPCODE;
 andn	TC; ptx_lval.int_value = ANDN_OP; return OPCODE;
 atom	TC; ptx_lval.int_value = ATOM_OP; return OPCODE;
-bar TC; ptx_lval.int_value = BAR_OP; return OPCODE;
+bar 	TC; ptx_lval.int_value = BAR_OP; return OPCODE;
 bfe     TC; ptx_lval.int_value = BFE_OP; return OPCODE;
 bfi     TC; ptx_lval.int_value = BFI_OP; return OPCODE;
 bfind   TC; ptx_lval.int_value = BFIND_OP; return OPCODE;
@@ -68,9 +68,12 @@ bra     TC; ptx_lval.int_value = BRA_OP; return OPCODE;
 brx     TC; ptx_lval.int_value = BRX_OP; return OPCODE;
 brev    TC; ptx_lval.int_value = BREV_OP; return OPCODE;
 brkpt   TC; ptx_lval.int_value = BRKPT_OP; return OPCODE;
-mma	TC; ptx_lval.int_value = MMA_OP; return OPCODE;
+wmma\.mma	TC; ptx_lval.int_value = MMA_OP; return OPCODE;
+wmma\.load	TC; ptx_lval.int_value = MMA_LD_OP; return OPCODE;
+wmma\.store 	TC; ptx_lval.int_value = MMA_ST_OP; return OPCODE;
+
 call	TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode
-callp    TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE;
+callp   TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE;
 clz	TC; ptx_lval.int_value = CLZ_OP; return OPCODE;
 cnot	TC; ptx_lval.int_value = CNOT_OP; return OPCODE;
 cos	TC; ptx_lval.int_value = COS_OP; return OPCODE;
@@ -153,6 +156,15 @@ breakaddr  TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE;
 "CPTX_END"	printf("ENDING CUSTOM PTX.\n"); BEGIN(IN_COMMENT);
 
 <INITIAL,NOT_OPCODE,IN_INST,IN_FUNC_DECL>{
+\.a\.sync TC; ptx_lval.int_value = LOAD_A; return WMMA_DIRECTIVE;
+\.b\.sync TC; ptx_lval.int_value = LOAD_B; return WMMA_DIRECTIVE;
+\.c\.sync TC; ptx_lval.int_value = LOAD_C; return WMMA_DIRECTIVE;
+\.d\.sync TC; ptx_lval.int_value = STORE_D; return WMMA_DIRECTIVE;
+\.sync TC;ptx_lval.int_value=MMA; return WMMA_DIRECTIVE;
+\.row TC; ptx_lval.int_value = ROW; return LAYOUT;
+\.col TC; ptx_lval.int_value = COL; return LAYOUT;
+\.m16n16k16 TC; ptx_lval.int_value = M16N16K16; return CONFIGURATION;
+
 
 \.align TC; return ALIGN_DIRECTIVE;
 \.branchtargets TC; return BRANCHTARGETS_DIRECTIVE;
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index 3360c55..737657c 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -37,6 +37,9 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 %token <string_value> STRING
 %token <int_value>  OPCODE
+%token <int_value>  WMMA_DIRECTIVE
+%token <int_value>  LAYOUT 
+%token <int_value>  CONFIGURATION 
 %token  ALIGN_DIRECTIVE
 %token  BRANCHTARGETS_DIRECTIVE
 %token  BYTE_DIRECTIVE
@@ -428,6 +431,7 @@ option: type_spec
 	| compare_spec
 	| addressable_spec
 	| rounding_mode
+	| wmma_spec 
 	| SYNC_OPTION { add_option(SYNC_OPTION); }	
 	| ARRIVE_OPTION { add_option(ARRIVE_OPTION); }
 	| RED_OPTION { add_option(RED_OPTION); }	
@@ -483,6 +487,7 @@ atomic_operation_spec: ATOMIC_AND { add_option(ATOMIC_AND); }
 rounding_mode: floating_point_rounding_mode
 	| integer_rounding_mode;
 
+
 floating_point_rounding_mode: RN_OPTION { add_option(RN_OPTION); } 
  	| RZ_OPTION { add_option(RZ_OPTION); } 
  	| RM_OPTION { add_option(RM_OPTION); } 
@@ -515,6 +520,10 @@ compare_spec:EQ_OPTION { add_option(EQ_OPTION); }
 	| NAN_OPTION { add_option(NAN_OPTION); } 
 	;
 
+wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);}
+	| WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)}
+	;
+
 operand_list: operand
 	| operand COMMA operand_list;
 
@@ -543,6 +552,7 @@ operand: IDENTIFIER  { add_scalar_operand( $1 ); }
 vector_operand: LEFT_BRACE IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_2vector_operand($2,$4); }
 		| LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_3vector_operand($2,$4,$6); }
 		| LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_4vector_operand($2,$4,$6,$8); }
+		| LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_8vector_operand($2,$4,$6,$8,$10,$12,$14,$16); }
 		| LEFT_BRACE IDENTIFIER RIGHT_BRACE { add_1vector_operand($2); }
 	;
 
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index 8ebdcf8..9a4d8d3 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -995,7 +995,7 @@ static std::list<operand_info> check_operands( int opcode,
                                         const std::list<operand_info> &operands )
 {
    static int g_warn_literal_operands_two_type_inst;
-    if( (opcode == CVT_OP) || (opcode == SET_OP) || (opcode == SLCT_OP) || (opcode == TEX_OP) ) {
+    if( (opcode == CVT_OP) || (opcode == SET_OP) || (opcode == SLCT_OP) || (opcode == TEX_OP) || (opcode==MMA_OP)) {
         // just make sure these do not have have const operands... 
         if( !g_warn_literal_operands_two_type_inst ) {
             std::list<operand_info>::const_iterator o;
@@ -1043,6 +1043,7 @@ ptx_instruction::ptx_instruction( int opcode,
                                   const std::list<operand_info> &operands, 
                                   const operand_info &return_var,
                                   const std::list<int> &options, 
+                                  const std::list<int> &wmma_options, 
                                   const std::list<int> &scalar_type,
                                   memory_space_t space_spec,
                                   const char *file, 
@@ -1061,6 +1062,7 @@ ptx_instruction::ptx_instruction( int opcode,
    m_operands.insert(m_operands.begin(), checked_operands.begin(), checked_operands.end() );
    m_return_var = return_var;
    m_options = options;
+   m_wmma_options = wmma_options;
    m_wide = false;
    m_hi = false;
    m_lo = false;
@@ -1078,7 +1080,7 @@ ptx_instruction::ptx_instruction( int opcode,
    m_atomic_spec = 0;
    m_membar_level = 0;
    m_inst_size = 8; // bytes
-
+   int rr=0;
    std::list<int>::const_iterator i;
    unsigned n=1;
    for ( i=options.begin(); i!= options.end(); i++, n++ ) {
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 0601b97..ff24a66 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -582,6 +582,34 @@ public:
       m_is_return_var = false;
       m_immediate_address=false;
    }
+   operand_info( const symbol *s1, const symbol *s2, const symbol *s3, const symbol *s4 ,const symbol *s5,const symbol *s6,const symbol *s7, const symbol *s8)
+   {
+      init();
+      m_is_non_arch_reg = false;
+      m_addr_space = undefined_space;
+      m_operand_lohi = 0;
+      m_double_operand_type = 0;
+      m_operand_neg = false;
+      m_const_mem_offset = 0;
+      m_uid = get_uid();
+      m_valid = true;
+      m_vector = true;
+      m_type = vector_t;
+      m_value.m_vector_symbolic = new const symbol*[8];
+      m_value.m_vector_symbolic[0] = s1;
+      m_value.m_vector_symbolic[1] = s2;
+      m_value.m_vector_symbolic[2] = s3;
+      m_value.m_vector_symbolic[3] = s4;
+      m_value.m_vector_symbolic[4] = s5;
+      m_value.m_vector_symbolic[5] = s6;
+      m_value.m_vector_symbolic[6] = s7;
+      m_value.m_vector_symbolic[7] = s8;
+      m_addr_offset = 0;
+      m_neg_pred = false;
+      m_is_return_var = false;
+      m_immediate_address=false;
+   }
+
    void init()
    {
        m_uid=(unsigned)-1;
@@ -866,6 +894,7 @@ public:
                     const std::list<operand_info> &operands, 
                     const operand_info &return_var,
                     const std::list<int> &options, 
+                    const std::list<int> &wmma_options, 
                     const std::list<int> &scalar_type,
                     memory_space_t space_spec,
                     const char *file, 
@@ -1087,6 +1116,7 @@ private:
    operand_info m_return_var;
 
    std::list<int>          m_options;
+   std::list<int>          m_wmma_options;
    bool                m_wide;
    bool                m_hi;
    bool                m_lo;
@@ -1096,6 +1126,9 @@ private:
    bool                m_uni; //if branch instruction, this evaluates to true for uniform branches (ie jumps)
    bool                m_to_option;
    unsigned            m_cache_option;
+   unsigned	       m_wmma_type;
+   unsigned 	       m_wmma_layout[2];
+   unsigned            m_wmma_configuration;
    unsigned            m_rounding_mode;
    unsigned            m_compare_op;
    unsigned            m_saturation_mode;
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index 7fc54e9..6757091 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -72,6 +72,7 @@ symbol *g_label;
 int g_opcode = -1;
 std::list<operand_info> g_operands;
 std::list<int> g_options;
+std::list<int> g_wmma_options;
 std::list<int> g_scalar_type;
 
 #define PTX_PARSE_DPRINTF(...) \
@@ -162,6 +163,7 @@ void init_instruction_state()
    g_label = NULL;
    g_opcode = -1;
    g_options.clear();
+   g_wmma_options.clear();
    g_return_var = operand_info();
    init_directive_state();
 }
@@ -300,6 +302,7 @@ void add_instruction()
                                              g_operands,
                                              g_return_var,
                                              g_options, 
+                                             g_wmma_options, 
                                              g_scalar_type,
                                              g_space_spec,
                                              g_filename,
@@ -629,7 +632,7 @@ void add_scalar_type_spec( int type_spec )
    g_scalar_type.push_back( type_spec );
    if ( g_scalar_type.size() > 1 ) {
       parse_assert( (g_opcode == -1) || (g_opcode == CVT_OP) || (g_opcode == SET_OP) || (g_opcode == SLCT_OP)
-                    || (g_opcode == TEX_OP), 
+                    || (g_opcode == TEX_OP)|| (g_opcode==MMA_OP),
                     "only cvt, set, slct, and tex can have more than one type specifier.");
    }
    g_scalar_type_spec = type_spec;
@@ -669,7 +672,11 @@ void add_option( int option )
    PTX_PARSE_DPRINTF("add_option");
    g_options.push_back( option );
 }
-
+void add_wmma_option( int option ) 
+{
+   PTX_PARSE_DPRINTF("add_option");
+   g_wmma_options.push_back( option );
+}
 void add_double_operand( const char *d1, const char *d2 )
 {
    //operands that access two variables.
@@ -725,6 +732,28 @@ void add_4vector_operand( const char *d1, const char *d2, const char *d3, const
    if ( s4 == null_op ) s4 = NULL;
    g_operands.push_back( operand_info(s1,s2,s3,s4) );
 }
+void add_8vector_operand( const char *d1, const char *d2, const char *d3, const char *d4,const char *d5,const char *d6,const char *d7,const char *d8 ) 
+{
+   PTX_PARSE_DPRINTF("add_8vector_operand");
+   const symbol *s1 = g_current_symbol_table->lookup(d1);
+   const symbol *s2 = g_current_symbol_table->lookup(d2);
+   const symbol *s3 = g_current_symbol_table->lookup(d3);
+   const symbol *s4 = g_current_symbol_table->lookup(d4);
+   const symbol *s5 = g_current_symbol_table->lookup(d5);
+   const symbol *s6 = g_current_symbol_table->lookup(d6);
+   const symbol *s7 = g_current_symbol_table->lookup(d7);
+   const symbol *s8 = g_current_symbol_table->lookup(d8);
+   parse_assert( s1 != NULL && s2 != NULL && s3 != NULL && s4 != NULL && s5 !=NULL && s6 !=NULL && s7 !=NULL && s8 !=NULL, "v4 component(s) missing declarations.");
+   const symbol *null_op = g_current_symbol_table->lookup("_");
+   if ( s2 == null_op ) s2 = NULL;
+   if ( s3 == null_op ) s3 = NULL;
+   if ( s4 == null_op ) s4 = NULL;
+   if ( s5 == null_op ) s5 = NULL;
+   if ( s6 == null_op ) s6 = NULL;
+   if ( s7 == null_op ) s7 = NULL;
+   if ( s8 == null_op ) s8 = NULL;
+   g_operands.push_back( operand_info(s1,s2,s3,s4,s5,s6,s7,s8) );
+}
 
 void add_builtin_operand( int builtin, int dim_modifier ) 
 {
diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h
index 32f3903..8094b43 100644
--- a/src/cuda-sim/ptx_parser.h
+++ b/src/cuda-sim/ptx_parser.h
@@ -57,7 +57,9 @@ void add_1vector_operand( const char *d1 );
 void add_2vector_operand( const char *d1, const char *d2 );
 void add_3vector_operand( const char *d1, const char *d2, const char *d3 );
 void add_4vector_operand( const char *d1, const char *d2, const char *d3, const char *d4 );
+void add_8vector_operand( const char *d1, const char *d2, const char *d3, const char *d4 ,const char *d5,const char *d6,const char *d7,const char *d8);
 void add_option(int option );
+void add_wmma_option(int option );
 void add_builtin_operand( int builtin, int dim_modifier );
 void add_memory_operand( );
 void add_literal_int( int value );
-- 
cgit v1.3


From 73fea7152926dbc41cf008a4ed3402cc1feeefa7 Mon Sep 17 00:00:00 2001
From: Jonathan <jonathanslew@outlook.com>
Date: Mon, 4 Jun 2018 16:53:23 -0700
Subject: parses through all ptx files, TODO: need to impl dp4a

---
 libcuda/cuda_runtime_api.cc  |  1 -
 src/cuda-sim/instructions.cc |  7 +++++++
 src/cuda-sim/opcodes.def     |  1 +
 src/cuda-sim/ptx.l           |  1 +
 src/cuda-sim/ptx_loader.cc   | 13 -------------
 src/cuda-sim/ptx_parser.cc   |  6 ++++++
 6 files changed, 15 insertions(+), 14 deletions(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc
index ece958e..d03caf7 100644
--- a/libcuda/cuda_runtime_api.cc
+++ b/libcuda/cuda_runtime_api.cc
@@ -1546,7 +1546,6 @@ void extract_ptx_files_using_cuobjdump(bool g_cdp_enabled){
 
 void cuobjdumpParseBinary(unsigned int handle){
 
-
 	if(fatbin_registered[handle]) return;
 	fatbin_registered[handle] = true;
 	CUctx_st *context = GPGPUSim_Context();
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 35d1782..37438fa 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -2289,6 +2289,13 @@ void div_impl( const ptx_instruction *pI, ptx_thread_info *thread )
    thread->set_operand_value(dst,data, i_type, thread,pI);
 }
 
+void dp4a_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
+{ 
+   printf("instruction not implemented yet");
+   assert(0);
+
+}
+
 void ex2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
 { 
    ptx_reg_t src1_data, src2_data, data;
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index e1b1422..2dbfb78 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -60,6 +60,7 @@ OP_DEF(COS_OP,cos_impl,"cos",1,4)
 OP_DEF(CVT_OP,cvt_impl,"cvt",1,1)
 OP_DEF(CVTA_OP,cvta_impl,"cvta",1,1)
 OP_DEF(DIV_OP,div_impl,"div",1,1)
+OP_DEF(DP4A_OP,dp4a_impl,"dp4a",1,1)
 OP_DEF(EX2_OP,ex2_impl,"ex2",1,4)
 OP_DEF(EXIT_OP,exit_impl,"exit",1,3)
 OP_DEF(FMA_OP,fma_impl,"fma",1,2)
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index 908c5be..3bb0d17 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -77,6 +77,7 @@ cos	TC; ptx_lval.int_value = COS_OP; return OPCODE;
 cvt	TC; ptx_lval.int_value = CVT_OP; return OPCODE;
 cvta	TC; ptx_lval.int_value = CVTA_OP; return OPCODE;
 div	TC; ptx_lval.int_value = DIV_OP; return OPCODE;
+dp4a	TC; ptx_lval.int_value = DP4A_OP; return OPCODE;
 ex2	TC; ptx_lval.int_value = EX2_OP; return OPCODE;
 exit	TC; ptx_lval.int_value = EXIT_OP; return OPCODE;
 fma     TC; ptx_lval.int_value = FMA_OP; return OPCODE;
diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc
index 8deafc6..0348af0 100644
--- a/src/cuda-sim/ptx_loader.cc
+++ b/src/cuda-sim/ptx_loader.cc
@@ -188,19 +188,6 @@ symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source
 symbol_table *gpgpu_ptx_sim_load_ptx_from_filename( const char *filename )
 {
     symbol_table *symtab=init_parser(filename);
-    int errors = ptx_parse ();
-    if ( errors ) {
-        char fname[1024];
-        snprintf(fname,1024,"_ptx_errors_XXXXXX");
-        int fd=mkstemp(fname); 
-        close(fd);
-        printf("GPGPU-Sim PTX: parser error detected, exiting... but first extracting .ptx to \"%s\"\n", fname);
-        FILE *ptxfile = fopen(fname,"w");
-        fclose(ptxfile);
-        abort();
-        exit(40);
-    }
-
     printf("GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file %s\n",filename);
     return symtab;
 }
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index a180da9..a51799a 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -32,6 +32,8 @@
 
 extern int ptx_error( const char *s );
 extern int ptx_lineno;
+extern int ptx_parse();
+extern FILE *ptx_in;
 
 static const struct core_config *g_shader_core_config;
 void set_ptx_warp_size(const struct core_config * warp_size)
@@ -135,6 +137,10 @@ symbol_table *init_parser( const char *ptx_filename )
    g_ptx_token_decode[generic_space] = "generic_space";
    g_ptx_token_decode[instruction_space] = "instruction_space";
 
+
+   ptx_in = fopen(ptx_filename, "r");
+   ptx_parse();
+   fclose(ptx_in);
    return g_global_symbol_table;
 }
 
-- 
cgit v1.3


From 12a8816c32a134693011d8b9e587f109e4d7e7f9 Mon Sep 17 00:00:00 2001
From: aamir <araihan@ece.ubc.ca>
Date: Thu, 9 Aug 2018 20:07:20 -0700
Subject: added load

---
 cuda-kernels/v4p_kernel.cu   | 109 +++++++++++++++++++++++-------
 src/cuda-sim/cuda-sim.cc     |   7 +-
 src/cuda-sim/instructions.cc | 155 +++++++++++++++++++++++++++++++++++++++++--
 src/cuda-sim/opcodes.def     |   3 +
 src/cuda-sim/opcodes.h       |   4 ++
 src/cuda-sim/ptx.l           |   8 +++
 src/cuda-sim/ptx.y           |   6 ++
 src/cuda-sim/ptx_ir.cc       |   4 ++
 src/cuda-sim/ptx_parser.cc   |   2 +-
 9 files changed, 266 insertions(+), 32 deletions(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/cuda-kernels/v4p_kernel.cu b/cuda-kernels/v4p_kernel.cu
index bb9064b..2e84eda 100644
--- a/cuda-kernels/v4p_kernel.cu
+++ b/cuda-kernels/v4p_kernel.cu
@@ -30,23 +30,30 @@ const int WMMA_M = 16;
 const int WMMA_N = 16;
 const int WMMA_K = 16;
 
-__global__ void wmma_example(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) {
-   //unsigned int start_time=0,end_time=0;
-   //start_time=clock();
-
-   // Declare the fragments
-   wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag;
-   wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag;
-   wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag;
-
-   // Bounds checking
-   wmma::load_matrix_sync(a_frag, a, K);
-   wmma::load_matrix_sync(b_frag, b, K);
-   wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major);
-   wmma::mma_sync(c_frag, a_frag, b_frag, c_frag);
-
-   wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major);
-   //printf("clock=%d",end_time-start_time);
+__global__ void v4p_example(int *a_int32, int *b_int8, int *c,int *d_int32, int M, int N, int K) {
+	
+	int registers_a[8];
+	int register_b;		//contains 8 4bit b elements
+   	int idx = blockDim.x * blockIdx.x + threadIdx.x;
+	
+	asm("/*");
+	asm("CPTX_BEGIN");
+	asm("vp.load.b4.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : 
+	"=r"(registers_a[0]), "=r"(registers_a[1]),"=r"(registers_a[2]),"=r"(registers_a[3]),
+	"=r"(registers_a[4]),"=r"(registers_a[5]),"=r"(registers_a[6]),"=r"(registers_a[7]):
+	"l"(b_int8),"r"(M)
+	);
+	asm("CPTX_END");
+	asm("*/");
+
+	b_int8[0]=registers_a[7];
+	b_int8[1]=registers_a[7];
+	b_int8[2]=registers_a[7];
+	b_int8[3]=registers_a[7];
+	b_int8[4]=registers_a[7];
+	b_int8[5]=registers_a[7];
+	b_int8[6]=registers_a[7];
+	b_int8[7]=registers_a[7];
 }
 
 __global__ void convertFp32ToFp16 (half *out, float *in, int n) {
@@ -62,13 +69,35 @@ __global__ void convertFp16ToFp32 (float *out, half *in, int n) {
    }
 }
 
+__global__ void convertInt32ToInt4 (int *out, int *in, int n) {
+   int idx = blockDim.x * blockIdx.x + threadIdx.x;
+   if (idx < n/8) {
+      		out[idx] =(in[8*idx]&0xf)|(in[8*idx+1]&0xf)<<4|(in[8*idx+2]&0xf)<<8|(in[8*idx+3]&0xf)<<12|
+      			  (in[8*idx+4]&0xf)<<16|(in[8*idx+5]&0xf)<<20|(in[8*idx+6]&0xf)<<24|(in[8*idx+7]&0xf)<<28;
+//		printf("thread%d:%x\n",idx,out[idx]);
+   }
+}
 __global__ void convertInt32ToInt8 (int *out, int *in, int n) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;
    if (idx < n/4) {
       		out[idx] =(in[4*idx]&0xff)|(in[4*idx+1]&0xff)<<8|(in[4*idx+2]&0xff)<<16|(in[4*idx+3]&0xff)<<24;
    }
 }
+__global__ void convertInt32ToInt16 (int *out, int *in, int n) {
+   int idx = blockDim.x * blockIdx.x + threadIdx.x;
+   if (idx < n/2) {
+      		out[idx] =(in[2*idx]&0xffff)|(in[2*idx+1]&0xffff)<<16;
+   }
+}
 
+__global__ void convertInt4ToInt32 (int *out, int *in, int n) {
+   int idx = blockDim.x * blockIdx.x + threadIdx.x;
+   int shft_amt=4*(idx%8);
+   int shft_mask=0xf<<shft_amt;
+   if (idx < n) {
+      	out[idx]= (in[idx/8]&shft_mask)>>shft_amt;
+   }
+}
 __global__ void convertInt8ToInt32 (int *out, int *in, int n) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;
    int shft_amt=8*(idx%4);
@@ -77,6 +106,14 @@ __global__ void convertInt8ToInt32 (int *out, int *in, int n) {
       	out[idx]= (in[idx/4]&shft_mask)>>shft_amt;
    }
 }
+__global__ void convertInt16ToInt32 (int *out, int *in, int n) {
+   int idx = blockDim.x * blockIdx.x + threadIdx.x;
+   int shft_amt=16*(idx%2);
+   int shft_mask=0xffff<<shft_amt;
+   if (idx < n) {
+      	out[idx]= (in[idx/2]&shft_mask)>>shft_amt;
+   }
+}
 
 int main(int argc, char* argv[]) {
    int *a_int32;
@@ -84,8 +121,12 @@ int main(int argc, char* argv[]) {
    int *c_int32;
    int *d_int32;
 
+   int *a_int4;
+   int *b_int4;
    int *a_int8;
    int *b_int8;
+   int *a_int16;
+   int *b_int16;
    
    int  *a_host_wmma;
    int  *b_host_wmma;
@@ -105,15 +146,19 @@ int main(int argc, char* argv[]) {
    cudaErrCheck(cudaMalloc((void**)&b_int32, MATRIX_K * MATRIX_N * sizeof(int)));
    cudaErrCheck(cudaMalloc((void**)&c_int32, MATRIX_K * MATRIX_N * sizeof(int)));
    cudaErrCheck(cudaMalloc((void**)&d_int32, MATRIX_K * MATRIX_N * sizeof(int)));
+   cudaErrCheck(cudaMalloc((void**)&a_int4, MATRIX_M * MATRIX_K * sizeof(int)/8));
+   cudaErrCheck(cudaMalloc((void**)&b_int4, MATRIX_K * MATRIX_N * sizeof(int)/8));
    cudaErrCheck(cudaMalloc((void**)&a_int8, MATRIX_M * MATRIX_K * sizeof(int)/4));
    cudaErrCheck(cudaMalloc((void**)&b_int8, MATRIX_K * MATRIX_N * sizeof(int)/4));
+   cudaErrCheck(cudaMalloc((void**)&a_int16, MATRIX_M * MATRIX_K * sizeof(int)/2));
+   cudaErrCheck(cudaMalloc((void**)&b_int16, MATRIX_K * MATRIX_N * sizeof(int)/2));
 
 
    a_host_wmma      = (int *)malloc(MATRIX_M * MATRIX_K * sizeof(int));
    b_host_wmma      = (int *)malloc(MATRIX_K * MATRIX_N * sizeof(int));
    c_host_wmma      = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int));
    d_host_wmma      = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int));
-   d_cal_host_wmma      = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int));
+   d_cal_host_wmma  = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int));
 
    printf("a_int32\n");
    for(int m=0;m<MATRIX_M;m++){
@@ -156,20 +201,34 @@ int main(int argc, char* argv[]) {
    cudaErrCheck(cudaMemcpy(b_int32,b_host_wmma,  MATRIX_K * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice));
    cudaErrCheck(cudaMemcpy(c_int32,c_host_wmma,  MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice));
 
-   convertInt32ToInt8 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int8, a_int32, MATRIX_M * MATRIX_K);
-   convertInt8ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int8, MATRIX_M * MATRIX_K);
+   #define TEST8
+   #ifdef TEST16
+   	convertInt32ToInt16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int16, a_int32, MATRIX_M * MATRIX_K);
+   	convertInt16ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int16, MATRIX_M * MATRIX_K);
+   	cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost));
+   #endif
+   #ifdef TEST8
+   	convertInt32ToInt8 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int8, a_int32, MATRIX_M * MATRIX_K);
+  	convertInt8ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int8, MATRIX_M * MATRIX_K);
+ 	cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost));
+   #endif
+   #ifdef TEST4
+   	convertInt32ToInt4 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int4, a_int32, MATRIX_M * MATRIX_K);
+  	convertInt4ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int4, MATRIX_M * MATRIX_K);
+ 	cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost));
+   #endif
    //convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N);
    //convertFp32ToFp16 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (c_fp16, c_fp32, MATRIX_K * MATRIX_N);
-   cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost));
 
 
 //AAMIR   printf("\nM = %d, N = %d, K = %d. \n", MATRIX_M, MATRIX_N, MATRIX_K);
 //AAMIR   
 //AAMIR   printf("Running with wmma...\n");
-//AAMIR   cudaErrCheck(cudaEventRecord(startWMMA));
-//AAMIR   wmma_example <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K);
-//AAMIR   cudaErrCheck(cudaEventRecord(stopWMMA));
-//AAMIR   cudaErrCheck(cudaEventSynchronize(stopWMMA));
+   //cudaErrCheck(cudaEventRecord(startWMMA));
+   //v4p_example <<< 1, 32>>> (a_int32, a_int8, a_int32, d_int32, MATRIX_M, MATRIX_N, MATRIX_K);
+   //cudaErrCheck(cudaEventRecord(stopWMMA));
+   //cudaErrCheck(cudaEventSynchronize(stopWMMA));
+
 //AAMIR
 //AAMIR   // Error checking
 //AAMIR   printf("\nChecking results...\n");
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 8284ad5..2fe5667 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -1323,8 +1323,11 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
          *((warp_inst_t*)pJ) = inst; // copy active mask information
          pI = pJ;
       }
-      if(((pI->get_opcode()!=MMA_OP)&&(pI->get_opcode()!=MMA_LD_OP)&&(pI->get_opcode()!=MMA_ST_OP))||((pI->get_opcode()==MMA_OP||pI->get_opcode()==MMA_LD_OP||pI->get_opcode()==MMA_ST_OP)&&(lane_id==0))){
-      switch ( pI->get_opcode() ) {
+     
+      int inst_opcode=pI->get_opcode();
+
+      if(((inst_opcode!=MMA_OP)&&(inst_opcode!=MMA_LD_OP)&&(inst_opcode!=MMA_ST_OP)&&(inst_opcode!=VP_LD_OP)&&(inst_opcode!=VP_ST_OP)&&(inst_opcode!=VP_MMA_OP))||((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_MMA_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP)&&(lane_id==0))){
+      switch ( inst_opcode ) {
 #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break;
 #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break;
 #include "opcodes.def"
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index aaee2a2..d0396a5 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -48,7 +48,7 @@
 using half_float::half;
 
 unsigned ptx_instruction::g_num_ptx_inst_uid=0;
-bool g_debug_instruction = 0;
+bool g_debug_instruction = 1;
 
 
 const char *g_opcode_string[NUM_OPCODES] = {
@@ -129,6 +129,12 @@ unsigned thread_group_offset(int thread,unsigned  wmma_type,unsigned wmma_layout
 				}
 			}
 			break;	
+		case VP_MMA:
+				if(wmma_layout==ROW)
+					offset=load_c_float_row[thread_group]+16*in_tg_index;
+				else	
+					offset=load_c_float_col[thread_group]+16*in_tg_index;
+			break;	
 
          	default:
          	   abort();
@@ -1709,6 +1715,14 @@ void mapping(int thread,int wmma_type,int wmma_layout,int type,int index,int str
 	}
 }
 
+void vp_mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
+{
+	unsigned wmma_type = pI->get_wmma_type();
+	unsigned a_layout = pI->get_wmma_layout(0);
+	unsigned b_layout = pI->get_wmma_layout(1);
+	
+
+}
 void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 {
 	int i,j,k,thrd;
@@ -1752,7 +1766,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 			int hex_val;
 
 			if(!((i==3)&&(type2==F32_TYPE))){
-				for(k=0;k<2*nelem;k++){
+					for(k=0;k<2*nelem;k++){
 					if(k%2==1)
 						hex_val=(v[k/2].s64&0xffff);
 					else
@@ -2958,6 +2972,12 @@ void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread )
    ld_exec(pI,thread);
 }
 
+void vp_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
+{
+   const operand_info &src  = pI->operand_lookup(1);
+   const operand_info &src1 = pI->operand_lookup(0);
+   const operand_info &src2 = pI->operand_lookup(2);
+}
 void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 {
    size_t size;
@@ -3000,7 +3020,7 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 
    	type_info_key::type_decode(type,size,t);
    	if(g_debug_instruction)
-		printf("mma_st: thrd=%d,addr=%d, fp(size=%d), stride=%d\n",thrd,addr_reg.u32,size,src2_data.u32);
+		printf("mma_st: thrd=%d,addr=%x, fp(size=%d), stride=%d\n",thrd,addr_reg.u32,size,src2_data.u32);
 	addr_t new_addr = addr+thread_group_offset(thrd,wmma_type,wmma_layout,type,stride)*size/8;  
 
 	ptx_reg_t nw_v[8];
@@ -3041,6 +3061,133 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
    	thread->m_last_effective_address = addr;
    	thread->m_last_memory_space = space;
    } 
+}
+void vp_ld_impl(const ptx_instruction *pI, core_t *core, warp_inst_t inst)
+{
+   size_t size;
+   int t,i;
+   unsigned smid;
+   const operand_info &dst = pI->dst();
+   const operand_info &src1 = pI->src1();
+   const operand_info &src2 = pI->src2();
+   unsigned type = pI->get_type();
+   unsigned wmma_type = pI->get_wmma_type();
+   unsigned wmma_layout = pI->get_wmma_layout(0);
+   int tid = inst.warp_id_func()*core->get_warp_size();
+   int thrd,stride;
+   ptx_thread_info *thread;
+   for (thrd=0; thrd < core->get_warp_size(); thrd++){
+   	thread = core->get_thread_info()[tid+thrd];
+   	ptx_reg_t src1_data = thread->get_operand_value(src1, dst, U32_TYPE, thread, 1);
+   	ptx_reg_t src2_data = thread->get_operand_value(src2, dst, U32_TYPE, thread, 1);
+	stride=src2_data.u32;
+   	memory_space_t space = pI->get_space();
+
+   	memory_space *mem = NULL;
+   	addr_t addr = src1_data.u32;
+   	
+        smid = thread->get_hw_sid();
+        if( whichspace(addr) == shared_space ) {
+          addr= generic_to_shared(smid,addr);
+          space = shared_space;
+	}
+
+	decode_space(space,thread,src1,mem,addr);
+   	type_info_key::type_decode(type,size,t);
+	
+	ptx_reg_t data[8];
+	addr_t new_addr;	
+	//note we are using distribution of VP_MMA for every type of load!
+	if(wmma_type==LOAD_A||wmma_type==LOAD_C){
+		 new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)*size/8;  
+	}
+	else if(wmma_type==LOAD_B4){
+		new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)/8;  
+	}
+	else if (wmma_type==LOAD_B8){
+		new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)/4;  
+	}
+	else if (wmma_type==LOAD_B16){
+		new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)/2;  
+	}
+
+   	if(g_debug_instruction)	
+		printf("vp_ld: thrx=%d,addr=%x, base_addr=%x, size=%d, stride=%d\n",thrd,new_addr,addr,size,src2_data.u32);
+
+	if(wmma_type==LOAD_A||wmma_type==LOAD_C){
+		for(i=0;i<8;i++){
+			mem->read(new_addr+4*i,size/8,&data[i].s64);
+		}
+	}
+	else if(wmma_type==LOAD_B4){
+			mem->read(new_addr,size/8,&data[0].s64);
+	}
+	else if(wmma_type==LOAD_B8){
+			mem->read(new_addr,size/8,&data[0].s64);
+			mem->read(new_addr+4,size/8,&data[1].s64);
+	}
+	else if(wmma_type==LOAD_B16){
+			mem->read(new_addr,size/8,&data[0].s64);
+			mem->read(new_addr+4,size/8,&data[1].s64);
+			mem->read(new_addr+8,size/8,&data[2].s64);
+			mem->read(new_addr+12,size/8,&data[3].s64);
+	}
+	else{
+		printf("wrong vp_load type\n");;
+		abort();
+	}
+
+	int num_reg;
+	if(g_debug_instruction){
+		printf("\nvp_ld:thread%d= ",thrd);
+		if((wmma_type==LOAD_A)||(wmma_type==LOAD_C)){	
+			num_reg=8;	
+		}	
+		else if(wmma_type==LOAD_B4){
+			num_reg=1;	
+		}
+		else if(wmma_type==LOAD_B8){
+			num_reg=2;	
+		}
+		else if(wmma_type==LOAD_B16){
+			num_reg=4;	
+		}
+	
+		for(i=0;i<num_reg;i++){
+			printf("%x ",data[i].s32);
+		}
+		printf("\n");
+	}
+
+	if((wmma_type==LOAD_A)||(wmma_type==LOAD_C)){
+   		thread->set_wmma_vector_operand_values(dst,data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7]);
+	}
+	else if(wmma_type==LOAD_B4){
+      		thread->set_operand_value(dst,data[0], type, thread, pI);
+	}
+	else if(wmma_type==LOAD_B8){
+   		thread->set_vector_operand_values(dst,data[0],data[1],data[1],data[1]);
+	}
+	else if (wmma_type==LOAD_B16){
+   		thread->set_vector_operand_values(dst,data[0],data[1],data[2],data[3]);
+	}
+	else
+		abort();	
+
+	
+
+	if(g_debug_instruction){
+		for(int i=0;i<num_reg;i++)
+			printf("vp_ld:data[%i].s64=%x\n",i,data[i].u64);	
+	}
+	
+
+   	thread->m_last_effective_address = addr;
+   	thread->m_last_memory_space = space;
+    }
+
+
+
 }
 
 void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
@@ -3080,7 +3227,7 @@ void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 	
 	ptx_reg_t data[16];
    	if(g_debug_instruction)	
-		printf("mma_ld: thrd=%d,addr=%d, fpsize=%d, stride=%d\n",thrd,src1_data.u32,size,src2_data.u32);
+		printf("mma_ld: thrd=%d,addr=%x, fpsize=%d, stride=%d\n",thrd,src1_data.u32,size,src2_data.u32);
 	
 	addr_t new_addr = addr+thread_group_offset(thrd,wmma_type,wmma_layout,type,stride)*size/8;  
 
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index e6f957a..73f6161 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -55,6 +55,9 @@ OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9)
 OP_W_DEF(MMA_OP,mma_impl,"mma",1,1)
 OP_W_DEF(MMA_LD_OP,mma_ld_impl,"mma_load",1,5)
 OP_W_DEF(MMA_ST_OP,mma_st_impl,"mma_store",0,5)
+OP_W_DEF(VP_MMA_OP,vp_mma_impl,"vp_mma",1,1)
+OP_W_DEF(VP_LD_OP,vp_ld_impl,"vp_load",1,5)
+OP_W_DEF(VP_ST_OP,vp_st_impl,"vp_store",0,5)
 OP_DEF(CALL_OP,call_impl,"call",1,3)
 OP_DEF(CALLP_OP,callp_impl,"callp",1,3)
 OP_DEF(CLZ_OP,clz_impl,"clz",1,1)
diff --git a/src/cuda-sim/opcodes.h b/src/cuda-sim/opcodes.h
index b91d92f..31b71d0 100644
--- a/src/cuda-sim/opcodes.h
+++ b/src/cuda-sim/opcodes.h
@@ -63,9 +63,13 @@ enum special_regs {
 enum wmma_type{
 	LOAD_A,
 	LOAD_B,
+	LOAD_B4,//vp
+	LOAD_B8,//vp
+	LOAD_B16,//vp
 	LOAD_C,
 	STORE_D,
 	MMA,
+	VP_MMA,
 	ROW,
 	COL,
 	M16N16K16
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index a6b6fcc..fea2420 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -68,9 +68,13 @@ bra     TC; ptx_lval.int_value = BRA_OP; return OPCODE;
 brx     TC; ptx_lval.int_value = BRX_OP; return OPCODE;
 brev    TC; ptx_lval.int_value = BREV_OP; return OPCODE;
 brkpt   TC; ptx_lval.int_value = BRKPT_OP; return OPCODE;
+
 wmma	TC; ptx_lval.int_value = MMA_OP; return OPCODE;
 wmma\.load	TC; ptx_lval.int_value = MMA_LD_OP; return OPCODE;
 wmma\.store 	TC; ptx_lval.int_value = MMA_ST_OP; return OPCODE;
+vp\.load TC; ptx_lval.int_value=VP_LD_OP; return OPCODE;
+vp\.store TC; ptx_lval.int_value=VP_ST_OP; return OPCODE;
+vp 	TC; ptx_lval.int_value=VP_MMA_OP; return OPCODE;
 
 call	TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode
 callp   TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE;
@@ -161,6 +165,10 @@ breakaddr  TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE;
 \.c\.sync TC; ptx_lval.int_value = LOAD_C; return WMMA_DIRECTIVE;
 \.d\.sync TC; ptx_lval.int_value = STORE_D; return WMMA_DIRECTIVE;
 \.mma\.sync TC;ptx_lval.int_value=MMA; return WMMA_DIRECTIVE;
+\.b4\.sync TC; ptx_lval.int_value=LOAD_B4;	return WMMA_DIRECTIVE;
+\.b8\.sync TC; ptx_lval.int_value=LOAD_B8;	return WMMA_DIRECTIVE;
+\.b16\.sync TC; ptx_lval.int_value=LOAD_B16;	return WMMA_DIRECTIVE;
+
 \.row TC; ptx_lval.int_value = ROW; return LAYOUT;
 \.col TC; ptx_lval.int_value = COL; return LAYOUT;
 \.m16n16k16 TC; ptx_lval.int_value = M16N16K16; return CONFIGURATION;
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index cd455dd..54ac2bc 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -538,6 +538,12 @@ wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_space_spec(global_space,0);ad
 	| WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);add_wmma_option($4);}
 	;
 
+vp_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_space_spec(global_space,0);add_ptr_spec(global_space);add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);}
+	| WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);add_wmma_option($4);}
+	;
+
+
+
 operand_list: operand
 	| operand COMMA operand_list;
 
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index d12c741..55b8e11 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -1089,9 +1089,13 @@ ptx_instruction::ptx_instruction( int opcode,
       		case SYNC_OPTION:
       		case LOAD_A:
       		case LOAD_B:
+      		case LOAD_B4:
+      		case LOAD_B8:
+      		case LOAD_B16:
       		case LOAD_C:
       		case STORE_D:
       		case MMA:
+      		case VP_MMA:
       		  m_wmma_type=last_ptx_inst_option;
       		  break;
       		case ROW:
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index 6757091..eb81961 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -39,7 +39,7 @@ void set_ptx_warp_size(const struct core_config * warp_size)
    g_shader_core_config=warp_size;
 }
 
-static bool g_debug_ir_generation=false;
+static bool g_debug_ir_generation=true;
 const char *g_filename;
 unsigned g_max_regs_per_thread = 0;
 
-- 
cgit v1.3


From 52bee41cfea17f13e93cc1fb812c125fd44bac7b Mon Sep 17 00:00:00 2001
From: Lucy Liu <lucy@aamodt-pc18.ece.ubc.ca>
Date: Fri, 3 Jul 2020 13:09:18 -0700
Subject: add activemask, bfind, vmin, and vmax implementations from Francois

---
 cuobjdump_to_ptxplus/cuobjdumpInst.cc |  41 +++++-----
 src/abstract_hardware_model.h         |   1 +
 src/cuda-sim/cuda-sim.cc              |   6 +-
 src/cuda-sim/instructions.cc          | 137 ++++++++++++++++++++++++++++++++--
 src/cuda-sim/opcodes.def              |  11 +--
 src/cuda-sim/ptx.l                    |   9 ++-
 src/cuda-sim/ptx.y                    |  36 ++++-----
 src/cuda-sim/ptx_ir.cc                |   3 +-
 src/cuda-sim/ptx_ir.h                 |   3 +
 src/cuda-sim/ptx_parser.cc            |   5 +-
 10 files changed, 195 insertions(+), 57 deletions(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/cuobjdump_to_ptxplus/cuobjdumpInst.cc b/cuobjdump_to_ptxplus/cuobjdumpInst.cc
index 392f829..969313c 100644
--- a/cuobjdump_to_ptxplus/cuobjdumpInst.cc
+++ b/cuobjdump_to_ptxplus/cuobjdumpInst.cc
@@ -742,18 +742,18 @@ void cuobjdumpInst::printCuobjdumpOutputModifiers(const char* defaultMod)
 {
 	std::list<std::string>::iterator typemod = m_typeModifiers->begin();
 	if (*typemod == ".U16" or *typemod == ".S16") {
-		std::list<std::string>::iterator dest_op = m_operands->begin(); 
-		std::string& destination = *dest_op; 
+		std::list<std::string>::iterator dest_op = m_operands->begin();
+		std::string& destination = *dest_op;
 		if (destination[destination.length()-1] == 'l') {
-			output(".lo");  // write to the lower 16-bits 
+			output(".lo");  // write to the lower 16-bits
 		} else if (destination[destination.length()-1] == 'h') {
-			output(".hi");  // write to the upper 16-bits 
+			output(".hi");  // write to the upper 16-bits
 		} else {
-			output(".wide");  // write to the whole 32-bits 
+			output(".wide");  // write to the whole 32-bits
 		}
-		return; 
+		return;
 	}
-	output(defaultMod);  // default output modifier for mul 
+	output(defaultMod);  // default output modifier for mul
 }
 
 std::string int_default_mod () { return ".u32" ;}
@@ -1357,9 +1357,9 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 			/*if(type1Size==16 && type2Size==16)
 				output(".lo");*/
 			if(tempString[1] >= 'A' && tempString[1] <= 'Z')
-				tempString[1] += 32;			
+				tempString[1] += 32;
 			output(tempString);
-		}	
+		}
 		else
 		{
 			printCuobjdumpTypeModifiers();
@@ -1393,9 +1393,9 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 			type = (type1Size > type2Size) ? type1 : type2;
 			strcpy(tempString, type.c_str());
 			if(tempString[1] >= 'A' && tempString[1] <= 'Z')
-				tempString[1] += 32;			
+				tempString[1] += 32;
 			output(tempString);
-		}	
+		}
 		else
 		{
 			printCuobjdumpTypeModifiers();
@@ -1407,7 +1407,7 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 	{
 		printCuobjdumpPredicate();
 		output("mul");
-      printCuobjdumpOutputModifiers(".lo"); 
+      printCuobjdumpOutputModifiers(".lo");
 		printCuobjdumpBaseModifiers();
 
 		if(m_typeModifiers->size() == 0)
@@ -1434,9 +1434,9 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 			/*if(type1Size==16 && type2Size==16)
 					output(".lo");*/
 			if(tempString[1] >= 'A' && tempString[1] <= 'Z')
-				tempString[1] += 32;			
+				tempString[1] += 32;
 			output(tempString);
-		}	
+		}
 		else
 		{
 			printCuobjdumpTypeModifiers();
@@ -1468,10 +1468,10 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 			/*if(type1Size==16 && type2Size==16)
 				output(".lo");*/
 			if(tempString[1] >= 'A' && tempString[1] <= 'Z')
-				tempString[1] += 32;			
+				tempString[1] += 32;
 			output(tempString);
 
-		}	
+		}
 		else
 			printCuobjdumpTypeModifiers();
 
@@ -1506,10 +1506,10 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 			/*if(type1Size==16 && type2Size==16)
 				output(".lo");*/
 			if(tempString[1] >= 'A' && tempString[1] <= 'Z')
-				tempString[1] += 32;			
+				tempString[1] += 32;
 			output(tempString);
 
-		}	
+		}
 		else
 			printCuobjdumpTypeModifiers();
 
@@ -2071,6 +2071,11 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 		printCuobjdumpTypeModifiers();
 		printCuobjdumpOperands();
 		output(";");
+	} else if(m_base == "ACTIVEMASK") {
+		printCuobjdumpPredicate();
+		output("activemask.b32");
+		printCuobjdumpOperands();
+		output(";");
 	}
 	else if(m_base == "DFMA")
 	{
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 46534ab..c6e3b43 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -1132,6 +1132,7 @@ class warp_inst_t : public inst_t {
   void print(FILE *fout) const;
   unsigned get_uid() const { return m_uid; }
   unsigned get_schd_id() const { return m_scheduler_id; }
+  active_mask_t get_warp_active_mask() const { return m_warp_active_mask; }
 
  protected:
   unsigned m_uid;
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 75dd3c8..451feb5 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -346,11 +346,11 @@ void function_info::ptx_assemble() {
    printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() );
    create_basic_blocks();
    connect_basic_blocks();
-   bool modified = false; 
+   bool modified = false;
    do {
       find_dominators();
       find_idominators();
-      modified = connect_break_targets(); 
+      modified = connect_break_targets();
    } while (modified == true);
 
    if ( g_debug_execution>=50 ) {
@@ -1741,7 +1741,7 @@ void ptx_thread_info::ptx_exec_inst(warp_inst_t &inst, unsigned lane_id) {
     } else {
       const ptx_instruction *pI_saved = pI;
       ptx_instruction *pJ = NULL;
-      if (pI->get_opcode() == VOTE_OP) {
+      if( pI->get_opcode() == VOTE_OP || pI->get_opcode() == ACTIVEMASK_OP ) {
         pJ = new ptx_instruction(*pI);
         *((warp_inst_t *)pJ) = inst;  // copy active mask information
         pI = pJ;
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index bf9a040..886c6c0 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -166,6 +166,7 @@ void inst_not_implemented(const ptx_instruction *pI);
 ptx_reg_t srcOperandModifiers(ptx_reg_t opData, operand_info opInfo,
                               operand_info dstInfo, unsigned type,
                               ptx_thread_info *thread);
+void video_mem_instruction(const ptx_instruction *pI, ptx_thread_info *thread, int op_code);
 
 void sign_extend(ptx_reg_t &data, unsigned src_size, const operand_info &dst);
 
@@ -1709,8 +1710,40 @@ void bfi_impl(const ptx_instruction *pI, ptx_thread_info *thread) {
   }
   thread->set_operand_value(dst, data, i_type, thread, pI);
 }
-void bfind_impl(const ptx_instruction *pI, ptx_thread_info *thread) {
-  inst_not_implemented(pI);
+void bfind_impl(const ptx_instruction *pI, ptx_thread_info *thread)
+{
+  const operand_info &dst  = pI->dst();
+  const operand_info &src1 = pI->src1();
+  const unsigned i_type = pI->get_type();
+
+  const ptx_reg_t src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1);
+  const int msb = ( i_type == U32_TYPE || i_type == S32_TYPE) ? 31 : 63;
+
+  unsigned long a = 0;
+  switch (i_type)
+  {
+    case S32_TYPE: a = src1_data.s32; break;
+    case U32_TYPE: a = src1_data.u32; break;
+    case S64_TYPE: a = src1_data.s64; break;
+    case U64_TYPE: a = src1_data.u64; break;
+    default: assert(false); abort();
+  }
+
+  // negate negative signed inputs
+  if ( ( i_type == S32_TYPE || i_type == S64_TYPE ) && ( a & ( 1 << msb ) ) ) {
+      a = ~a;
+  }
+  uint32_t d_data = 0xffffffff;
+  for (uint32_t i = msb; i >= 0; i--) {
+      if (a & (1<<i))  { d_data = i; break; }
+  }
+
+  // if (.shiftamt && d != 0xffffffff)  { d = msb - d; }
+
+  // store d
+  thread->set_operand_value(dst, d_data, U32_TYPE, thread, pI);
+
+
 }
 
 void bra_impl(const ptx_instruction *pI, ptx_thread_info *thread) {
@@ -6301,11 +6334,17 @@ void vadd_impl(const ptx_instruction *pI, ptx_thread_info *thread) {
 void vmad_impl(const ptx_instruction *pI, ptx_thread_info *thread) {
   inst_not_implemented(pI);
 }
-void vmax_impl(const ptx_instruction *pI, ptx_thread_info *thread) {
-  inst_not_implemented(pI);
+
+#define VMAX 0
+#define VMIN 1
+
+void vmax_impl(const ptx_instruction *pI, ptx_thread_info *thread)
+{
+   video_mem_instruction(pI, thread, VMAX);
 }
-void vmin_impl(const ptx_instruction *pI, ptx_thread_info *thread) {
-  inst_not_implemented(pI);
+void vmin_impl(const ptx_instruction *pI, ptx_thread_info *thread)
+{
+  video_mem_instruction(pI, thread, VMIN);
 }
 void vset_impl(const ptx_instruction *pI, ptx_thread_info *thread) {
   inst_not_implemented(pI);
@@ -6400,6 +6439,15 @@ void vote_impl(const ptx_instruction *pI, ptx_thread_info *thread) {
   }
 }
 
+void activemask_impl( const ptx_instruction *pI, ptx_thread_info *thread )
+{
+  active_mask_t l_activemask_bitset = pI->get_warp_active_mask();
+  uint32_t l_activemask_uint = static_cast<uint32_t>(l_activemask_bitset.to_ulong());
+
+  const operand_info &dst  = pI->dst();
+  thread->set_operand_value(dst, l_activemask_uint, U32_TYPE, thread, pI);
+}
+
 void xor_impl(const ptx_instruction *pI, ptx_thread_info *thread) {
   ptx_reg_t src1_data, src2_data, data;
 
@@ -6477,3 +6525,80 @@ ptx_reg_t srcOperandModifiers(ptx_reg_t opData, operand_info opInfo,
 
   return result;
 }
+
+void video_mem_instruction(const ptx_instruction *pI, ptx_thread_info *thread, int op_code)
+{
+  const operand_info &dst  = pI->dst(); // d
+  const operand_info &src1 = pI->src1(); // a
+  const operand_info &src2 = pI->src2(); // b
+  const operand_info &src3 = pI->src3(); // c
+
+  const unsigned i_type = pI->get_type();
+
+  std::list<int> scalar_type;
+  std::list<int> options;
+
+  ptx_reg_t a, b, ta, tb, c, data;
+
+  a = thread->get_operand_value(src1, dst, i_type, thread, 1);
+  b = thread->get_operand_value(src2, dst, i_type, thread, 1);
+  c = thread->get_operand_value(src3, dst, i_type, thread, 1);
+
+  // TODO: implement this
+  // ta = partSelectSignExtend( a, atype );
+  // tb = partSelectSignExtend( b, btype );
+  ta = a;
+  tb = b;
+
+  options = pI->get_options();
+  assert(options.size() == 1);
+
+  auto option = options.begin();
+  assert(*option == ATOMIC_MAX || *option == ATOMIC_MIN);
+
+  switch ( i_type ) {
+    case S32_TYPE: {
+      // assert all operands are S32_TYPE:
+      scalar_type = pI->get_scalar_type();
+      for (auto scalar : scalar_type)
+      {
+        assert(scalar == S32_TYPE);
+      }
+      assert(scalar_type.size() == 3);
+      scalar_type.clear();
+
+      switch (op_code)
+      {
+        case VMAX:
+          data.s32 = MY_MAX_I(ta.s32, tb.s32);
+          break;
+        case VMIN:
+          data.s32 = MY_MIN_I(ta.s32, tb.s32);
+          break;
+        default:
+          assert(0);
+      }
+
+      switch (*option)
+      {
+        case ATOMIC_MAX:
+          data.s32 = MY_MAX_I(data.s32, c.s32);
+        break;
+        case ATOMIC_MIN:
+          data.s32 = MY_MIN_I(data.s32, c.s32);
+        break;
+        default:
+          assert(0); // not yet implemented
+      }
+      break;
+
+    }
+    default:
+      assert(0); // not yet implemented
+  }
+
+  thread->set_operand_value(dst, data, i_type, thread, pI);
+
+  return;
+}
+
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index c4d6a83..aa85512 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -1,10 +1,10 @@
-// Copyright (c) 2009-2011, Tor M. Aamodt, Ali Bakhoda 
+// Copyright (c) 2009-2011, Tor M. Aamodt, Ali Bakhoda
 // The University of British Columbia
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are met:
-// 
+//
 // Redistributions of source code must retain the above copyright notice, this
 // list of conditions and the following disclaimer.
 // Redistributions in binary form must reproduce the above copyright notice, this
@@ -13,7 +13,7 @@
 // Neither the name of The University of British Columbia nor the names of its
 // contributors may be used to endorse or promote products derived from this
 // software without specific prior written permission.
-// 
+//
 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -27,7 +27,7 @@
 
 
 /*6th operand of each OP_DEF  reflects its classification  */
-/*Type 
+/*Type
 ALU 1
 MAD 2
 Control 3
@@ -129,6 +129,7 @@ OP_DEF(VSHL_OP,vshl_impl,"vshl",0,11)
 OP_DEF(VSHR_OP,vshr_impl,"vshr",0,11)
 OP_DEF(VSUB_OP,vsub_impl,"vsub",0,11)
 OP_DEF(VOTE_OP,vote_impl,"vote",0,3)
+OP_DEF(ACTIVEMASK_OP,activemask_impl,"activemask",1,3)
 OP_DEF(XOR_OP,xor_impl,"xor",1,1)
 OP_DEF(NOP_OP,nop_impl,"nop",0,7)
 OP_DEF(BREAK_OP,break_impl,"break",0,3)
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index 2dadda4..3592501 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -158,6 +158,7 @@ vshl    TC; yylval->int_value = VSHL_OP; return OPCODE;
 vshr    TC; yylval->int_value = VSHR_OP; return OPCODE;
 vsub    TC; yylval->int_value = VSUB_OP; return OPCODE;
 vote	TC; yylval->int_value = VOTE_OP; return OPCODE;
+activemask TC; yylval->int_value = ACTIVEMASK_OP; return OPCODE;
 xor     TC; yylval->int_value = XOR_OP; return OPCODE;
 nop     TC; yylval->int_value = NOP_OP; return OPCODE;
 break  TC; yylval->int_value = BREAK_OP; return OPCODE;
@@ -252,7 +253,7 @@ breakaddr  TC; yylval->int_value = BREAKADDR_OP; return OPCODE;
 [$%][a-zA-Z0-9_$]+  TC; yylval->string_value = strdup(yytext); return IDENTIFIER;
 
 [0-9]+\.[0-9]+ 	 TC; sscanf(yytext,"%lf", &yylval->double_value); return DOUBLE_OPERAND;
-	
+
 0[xX][0-9a-fA-F]+U? TC; CHECK_UNSIGNED; sscanf(yytext,"%x", &yylval->int_value); return INT_OPERAND;
 0[0-7]+U?   	TC; printf("GPGPU-Sim: ERROR ** parsing octal not (yet) implemented\n"); abort(); return INT_OPERAND;
 0[bB][01]+U?  	TC; printf("GPGPU-Sim: ERROR ** parsing binary not (yet) implemented\n"); abort(); return INT_OPERAND;
@@ -438,9 +439,9 @@ breakaddr  TC; yylval->int_value = BREAKADDR_OP; return OPCODE;
 "*/"      BEGIN(INITIAL);
 "CPTX_BEGIN" printf("BEGINNING CUSTOM PTX.\n"); BEGIN(INITIAL);
 [^C*\n]+	// eat comment in chunks
-"C"			// eat the lone C 
+"C"			// eat the lone C
 "*"			// eat the lone star
-\n        TC; 
+\n        TC;
 }
 
 <INITIAL>{
@@ -470,7 +471,7 @@ int ptx_error( yyscan_t yyscanner, ptx_recognizer* recognizer, const char *s )
 		if( recognizer->linebuf[i] == '\t' ) printf("\t");
 		else printf(" ");
 	}
-			
+
 	printf("^\n\n");
 	fflush(stdout);
 	//exit(1);
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index b38f783..90accc9 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -50,8 +50,8 @@ class ptx_recognizer;
 %token <string_value> STRING
 %token <int_value>  OPCODE
 %token <int_value>  WMMA_DIRECTIVE
-%token <int_value>  LAYOUT 
-%token <int_value>  CONFIGURATION 
+%token <int_value>  LAYOUT
+%token <int_value>  CONFIGURATION
 %token  ALIGN_DIRECTIVE
 %token  BRANCHTARGETS_DIRECTIVE
 %token  BYTE_DIRECTIVE
@@ -295,7 +295,7 @@ ptr_space_spec: GLOBAL_DIRECTIVE { recognizer->add_ptr_spec(global_space); }
 
 ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND
 
-statement_block: LEFT_BRACE statement_list RIGHT_BRACE 
+statement_block: LEFT_BRACE statement_list RIGHT_BRACE
 
 statement_list: directive_statement { recognizer->add_directive(); }
     | statement_list prototype_block {printf("Prototype statement detected. WARNING: this is not supported yet on GPGPU-SIM\n"); }
@@ -315,7 +315,7 @@ directive_statement: variable_declaration SEMI_COLON
 	| TARGET_DIRECTIVE IDENTIFIER { recognizer->target_header($2); }
 	| FILE_DIRECTIVE INT_OPERAND STRING { recognizer->add_file($2,$3); }
 	| FILE_DIRECTIVE INT_OPERAND STRING COMMA INT_OPERAND COMMA INT_OPERAND { recognizer->add_file($2,$3); }
-	| LOC_DIRECTIVE INT_OPERAND INT_OPERAND INT_OPERAND 
+	| LOC_DIRECTIVE INT_OPERAND INT_OPERAND INT_OPERAND
 	| PRAGMA_DIRECTIVE STRING SEMI_COLON { recognizer->add_pragma($2); }
 	| function_decl SEMI_COLON {/*Do nothing*/}
 	;
@@ -336,7 +336,7 @@ identifier_spec: IDENTIFIER { recognizer->add_identifier($1,0,NON_ARRAY_IDENTIFI
 		int i,lbase,l;
 		char *id = NULL;
 		lbase = strlen($1);
-		for( i=0; i < $3; i++ ) { 
+		for( i=0; i < $3; i++ ) {
 			l = lbase + (int)log10(i+1)+10;
 			id = (char*) malloc(l);
 			snprintf(id,l,"%s%u",$1,i);
@@ -348,10 +348,10 @@ identifier_spec: IDENTIFIER { recognizer->add_identifier($1,0,NON_ARRAY_IDENTIFI
 	| IDENTIFIER LEFT_SQUARE_BRACKET INT_OPERAND RIGHT_SQUARE_BRACKET { recognizer->add_identifier($1,$3,ARRAY_IDENTIFIER); recognizer->func_header_info($1); recognizer->func_header_info_int("[",$3); recognizer->func_header_info("]");}
 	;
 
-var_spec_list: var_spec 
+var_spec_list: var_spec
 	 | var_spec_list var_spec;
 
-var_spec: space_spec 
+var_spec: space_spec
 	| type_spec
 	| align_spec
 	| VISIBLE_DIRECTIVE
@@ -376,8 +376,8 @@ addressable_spec: CONST_DIRECTIVE {  recognizer->add_space_spec(const_space,$1);
 	| TEX_DIRECTIVE 	  {  recognizer->add_space_spec(tex_space,0); }
 	;
 
-type_spec: scalar_type 
-	|  vector_spec scalar_type 
+type_spec: scalar_type
+	|  vector_spec scalar_type
 	;
 
 vector_spec:  V2_TYPE {  recognizer->add_option(V2_TYPE); recognizer->func_header_info(".v2");}
@@ -417,14 +417,14 @@ literal_list: literal_operand
 
 // TODO: This is currently hardcoded to handle and ignore one specific case
 // that all prototype statements follow in the PTX from Pytorch. As a
-// workaround, this parses and ignores both the prototype declaration 
-// and calling of the prototype (which conveniently comes right after the 
-// declaration for all cases.) This should be changed to handle both 
+// workaround, this parses and ignores both the prototype declaration
+// and calling of the prototype (which conveniently comes right after the
+// declaration for all cases.) This should be changed to handle both
 // declaring the prototype, and actually calling it.
 prototype_block: prototype_decl prototype_call
 
-prototype_decl: IDENTIFIER COLON CALLPROTOTYPE_DIRECTIVE LEFT_PAREN prototype_param RIGHT_PAREN IDENTIFIER LEFT_PAREN prototype_param RIGHT_PAREN SEMI_COLON 
-	      
+prototype_decl: IDENTIFIER COLON CALLPROTOTYPE_DIRECTIVE LEFT_PAREN prototype_param RIGHT_PAREN IDENTIFIER LEFT_PAREN prototype_param RIGHT_PAREN SEMI_COLON
+
 prototype_call: OPCODE LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA operand COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON
 	      | OPCODE IDENTIFIER COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON
 
@@ -439,7 +439,7 @@ instruction_statement:  instruction SEMI_COLON
 instruction: opcode_spec LEFT_PAREN operand RIGHT_PAREN { recognizer->set_return(); } COMMA operand COMMA LEFT_PAREN operand_list RIGHT_PAREN
 	| opcode_spec operand COMMA LEFT_PAREN operand_list RIGHT_PAREN
 	| opcode_spec operand COMMA LEFT_PAREN RIGHT_PAREN
-	| opcode_spec operand_list 
+	| opcode_spec operand_list
 	| opcode_spec
 	;
 
@@ -468,8 +468,8 @@ option: type_spec
 	| compare_spec
 	| addressable_spec
 	| rounding_mode
-	| wmma_spec 
-	| prmt_spec 
+	| wmma_spec
+	| prmt_spec
 	| SYNC_OPTION { recognizer->add_option(SYNC_OPTION); }
 	| ARRIVE_OPTION { recognizer->add_option(ARRIVE_OPTION); }
 	| RED_OPTION { recognizer->add_option(RED_OPTION); }
@@ -609,7 +609,7 @@ vector_operand: LEFT_BRACE IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { recognizer-
 	;
 
 tex_operand: LEFT_SQUARE_BRACKET IDENTIFIER COMMA { recognizer->add_scalar_operand($2); }
-		vector_operand 
+		vector_operand
 	     RIGHT_SQUARE_BRACKET
 	;
 
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index aa1c25a..e5b5fb7 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -1147,7 +1147,8 @@ static std::list<operand_info> check_operands(
     const std::list<operand_info> &operands, gpgpu_context *ctx) {
   static int g_warn_literal_operands_two_type_inst;
   if ((opcode == CVT_OP) || (opcode == SET_OP) || (opcode == SLCT_OP) ||
-      (opcode == TEX_OP) || (opcode == MMA_OP) || (opcode == DP4A_OP)) {
+      (opcode == TEX_OP) || (opcode == MMA_OP) || (opcode == DP4A_OP) || 
+      (opcode == VMIN_OP) || (opcode == VMAX_OP) ) {
     // just make sure these do not have have const operands...
     if (!g_warn_literal_operands_two_type_inst) {
       std::list<operand_info>::const_iterator o;
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 6627847..26283a6 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -965,6 +965,9 @@ class ptx_instruction : public warp_inst_t {
   bool get_pred_neg() const { return m_neg_pred; }
   int get_pred_mod() const { return m_pred_mod; }
   const char *get_source() const { return m_source.c_str(); }
+  
+  const std::list<int> get_scalar_type() const {return m_scalar_type;}
+  const std::list<int> get_options() const {return m_options;}
 
   typedef std::vector<operand_info>::const_iterator const_iterator;
 
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index 3ae8de3..549c08c 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -624,8 +624,9 @@ void ptx_recognizer::add_scalar_type_spec(int type_spec) {
     parse_assert((g_opcode == -1) || (g_opcode == CVT_OP) ||
                      (g_opcode == SET_OP) || (g_opcode == SLCT_OP) ||
                      (g_opcode == TEX_OP) || (g_opcode == MMA_OP) ||
-                     (g_opcode == DP4A_OP),
-                 "only cvt, set, slct, tex and dp4a can have more than one "
+                     (g_opcode == DP4A_OP) || (g_opcode == VMIN_OP) || 
+                     (g_opcode == VMAX_OP),
+                 "only cvt, set, slct, tex, vmin, vmax and dp4a can have more than one "
                  "type specifier.");
   }
   g_scalar_type_spec = type_spec;
-- 
cgit v1.3


From a8f98c3d111c9238ad79908e690b22c5e43f1522 Mon Sep 17 00:00:00 2001
From: Lucy Liu <lucy@aamodt-pc18.ece.ubc.ca>
Date: Fri, 3 Jul 2020 13:53:02 -0700
Subject: removed whitespace changes

---
 cuobjdump_to_ptxplus/cuobjdumpInst.cc | 36 +++++++++++++++++------------------
 src/cuda-sim/cuda-sim.cc              |  6 +++---
 src/cuda-sim/instructions.cc          |  1 +
 src/cuda-sim/opcodes.def              | 10 +++++-----
 src/cuda-sim/ptx.l                    |  8 ++++----
 src/cuda-sim/ptx.y                    | 36 +++++++++++++++++------------------
 src/cuda-sim/ptx_ir.h                 |  2 +-
 7 files changed, 50 insertions(+), 49 deletions(-)

(limited to 'src/cuda-sim/opcodes.def')

diff --git a/cuobjdump_to_ptxplus/cuobjdumpInst.cc b/cuobjdump_to_ptxplus/cuobjdumpInst.cc
index 969313c..eb70199 100644
--- a/cuobjdump_to_ptxplus/cuobjdumpInst.cc
+++ b/cuobjdump_to_ptxplus/cuobjdumpInst.cc
@@ -742,18 +742,18 @@ void cuobjdumpInst::printCuobjdumpOutputModifiers(const char* defaultMod)
 {
 	std::list<std::string>::iterator typemod = m_typeModifiers->begin();
 	if (*typemod == ".U16" or *typemod == ".S16") {
-		std::list<std::string>::iterator dest_op = m_operands->begin();
-		std::string& destination = *dest_op;
+		std::list<std::string>::iterator dest_op = m_operands->begin(); 
+		std::string& destination = *dest_op; 
 		if (destination[destination.length()-1] == 'l') {
-			output(".lo");  // write to the lower 16-bits
+			output(".lo");  // write to the lower 16-bits 
 		} else if (destination[destination.length()-1] == 'h') {
-			output(".hi");  // write to the upper 16-bits
+			output(".hi");  // write to the upper 16-bits 
 		} else {
-			output(".wide");  // write to the whole 32-bits
+			output(".wide");  // write to the whole 32-bits 
 		}
-		return;
+		return; 
 	}
-	output(defaultMod);  // default output modifier for mul
+	output(defaultMod);  // default output modifier for mul 
 }
 
 std::string int_default_mod () { return ".u32" ;}
@@ -1357,9 +1357,9 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 			/*if(type1Size==16 && type2Size==16)
 				output(".lo");*/
 			if(tempString[1] >= 'A' && tempString[1] <= 'Z')
-				tempString[1] += 32;
+				tempString[1] += 32;			
 			output(tempString);
-		}
+		}	
 		else
 		{
 			printCuobjdumpTypeModifiers();
@@ -1393,9 +1393,9 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 			type = (type1Size > type2Size) ? type1 : type2;
 			strcpy(tempString, type.c_str());
 			if(tempString[1] >= 'A' && tempString[1] <= 'Z')
-				tempString[1] += 32;
+				tempString[1] += 32;			
 			output(tempString);
-		}
+		}	
 		else
 		{
 			printCuobjdumpTypeModifiers();
@@ -1407,7 +1407,7 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 	{
 		printCuobjdumpPredicate();
 		output("mul");
-      printCuobjdumpOutputModifiers(".lo");
+      printCuobjdumpOutputModifiers(".lo"); 
 		printCuobjdumpBaseModifiers();
 
 		if(m_typeModifiers->size() == 0)
@@ -1434,9 +1434,9 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 			/*if(type1Size==16 && type2Size==16)
 					output(".lo");*/
 			if(tempString[1] >= 'A' && tempString[1] <= 'Z')
-				tempString[1] += 32;
+				tempString[1] += 32;			
 			output(tempString);
-		}
+		}	
 		else
 		{
 			printCuobjdumpTypeModifiers();
@@ -1468,10 +1468,10 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 			/*if(type1Size==16 && type2Size==16)
 				output(".lo");*/
 			if(tempString[1] >= 'A' && tempString[1] <= 'Z')
-				tempString[1] += 32;
+				tempString[1] += 32;			
 			output(tempString);
 
-		}
+		}	
 		else
 			printCuobjdumpTypeModifiers();
 
@@ -1506,10 +1506,10 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std:
 			/*if(type1Size==16 && type2Size==16)
 				output(".lo");*/
 			if(tempString[1] >= 'A' && tempString[1] <= 'Z')
-				tempString[1] += 32;
+				tempString[1] += 32;			
 			output(tempString);
 
-		}
+		}	
 		else
 			printCuobjdumpTypeModifiers();
 
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 451feb5..71f0703 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -346,11 +346,11 @@ void function_info::ptx_assemble() {
    printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() );
    create_basic_blocks();
    connect_basic_blocks();
-   bool modified = false;
+   bool modified = false; 
    do {
       find_dominators();
       find_idominators();
-      modified = connect_break_targets();
+      modified = connect_break_targets(); 
    } while (modified == true);
 
    if ( g_debug_execution>=50 ) {
@@ -1741,7 +1741,7 @@ void ptx_thread_info::ptx_exec_inst(warp_inst_t &inst, unsigned lane_id) {
     } else {
       const ptx_instruction *pI_saved = pI;
       ptx_instruction *pJ = NULL;
-      if( pI->get_opcode() == VOTE_OP || pI->get_opcode() == ACTIVEMASK_OP ) {
+      if (pI->get_opcode() == VOTE_OP || pI->get_opcode() == ACTIVEMASK_OP) {
         pJ = new ptx_instruction(*pI);
         *((warp_inst_t *)pJ) = inst;  // copy active mask information
         pI = pJ;
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 886c6c0..1090ba4 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -166,6 +166,7 @@ void inst_not_implemented(const ptx_instruction *pI);
 ptx_reg_t srcOperandModifiers(ptx_reg_t opData, operand_info opInfo,
                               operand_info dstInfo, unsigned type,
                               ptx_thread_info *thread);
+                              
 void video_mem_instruction(const ptx_instruction *pI, ptx_thread_info *thread, int op_code);
 
 void sign_extend(ptx_reg_t &data, unsigned src_size, const operand_info &dst);
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index aa85512..f5bf156 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -1,10 +1,10 @@
-// Copyright (c) 2009-2011, Tor M. Aamodt, Ali Bakhoda
+// Copyright (c) 2009-2011, Tor M. Aamodt, Ali Bakhoda 
 // The University of British Columbia
 // All rights reserved.
-//
+// 
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are met:
-//
+// 
 // Redistributions of source code must retain the above copyright notice, this
 // list of conditions and the following disclaimer.
 // Redistributions in binary form must reproduce the above copyright notice, this
@@ -13,7 +13,7 @@
 // Neither the name of The University of British Columbia nor the names of its
 // contributors may be used to endorse or promote products derived from this
 // software without specific prior written permission.
-//
+// 
 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -27,7 +27,7 @@
 
 
 /*6th operand of each OP_DEF  reflects its classification  */
-/*Type
+/*Type 
 ALU 1
 MAD 2
 Control 3
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index 3592501..6754045 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -253,7 +253,7 @@ breakaddr  TC; yylval->int_value = BREAKADDR_OP; return OPCODE;
 [$%][a-zA-Z0-9_$]+  TC; yylval->string_value = strdup(yytext); return IDENTIFIER;
 
 [0-9]+\.[0-9]+ 	 TC; sscanf(yytext,"%lf", &yylval->double_value); return DOUBLE_OPERAND;
-
+	
 0[xX][0-9a-fA-F]+U? TC; CHECK_UNSIGNED; sscanf(yytext,"%x", &yylval->int_value); return INT_OPERAND;
 0[0-7]+U?   	TC; printf("GPGPU-Sim: ERROR ** parsing octal not (yet) implemented\n"); abort(); return INT_OPERAND;
 0[bB][01]+U?  	TC; printf("GPGPU-Sim: ERROR ** parsing binary not (yet) implemented\n"); abort(); return INT_OPERAND;
@@ -439,9 +439,9 @@ breakaddr  TC; yylval->int_value = BREAKADDR_OP; return OPCODE;
 "*/"      BEGIN(INITIAL);
 "CPTX_BEGIN" printf("BEGINNING CUSTOM PTX.\n"); BEGIN(INITIAL);
 [^C*\n]+	// eat comment in chunks
-"C"			// eat the lone C
+"C"			// eat the lone C 
 "*"			// eat the lone star
-\n        TC;
+\n        TC; 
 }
 
 <INITIAL>{
@@ -471,7 +471,7 @@ int ptx_error( yyscan_t yyscanner, ptx_recognizer* recognizer, const char *s )
 		if( recognizer->linebuf[i] == '\t' ) printf("\t");
 		else printf(" ");
 	}
-
+			
 	printf("^\n\n");
 	fflush(stdout);
 	//exit(1);
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index 90accc9..b38f783 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -50,8 +50,8 @@ class ptx_recognizer;
 %token <string_value> STRING
 %token <int_value>  OPCODE
 %token <int_value>  WMMA_DIRECTIVE
-%token <int_value>  LAYOUT
-%token <int_value>  CONFIGURATION
+%token <int_value>  LAYOUT 
+%token <int_value>  CONFIGURATION 
 %token  ALIGN_DIRECTIVE
 %token  BRANCHTARGETS_DIRECTIVE
 %token  BYTE_DIRECTIVE
@@ -295,7 +295,7 @@ ptr_space_spec: GLOBAL_DIRECTIVE { recognizer->add_ptr_spec(global_space); }
 
 ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND
 
-statement_block: LEFT_BRACE statement_list RIGHT_BRACE
+statement_block: LEFT_BRACE statement_list RIGHT_BRACE 
 
 statement_list: directive_statement { recognizer->add_directive(); }
     | statement_list prototype_block {printf("Prototype statement detected. WARNING: this is not supported yet on GPGPU-SIM\n"); }
@@ -315,7 +315,7 @@ directive_statement: variable_declaration SEMI_COLON
 	| TARGET_DIRECTIVE IDENTIFIER { recognizer->target_header($2); }
 	| FILE_DIRECTIVE INT_OPERAND STRING { recognizer->add_file($2,$3); }
 	| FILE_DIRECTIVE INT_OPERAND STRING COMMA INT_OPERAND COMMA INT_OPERAND { recognizer->add_file($2,$3); }
-	| LOC_DIRECTIVE INT_OPERAND INT_OPERAND INT_OPERAND
+	| LOC_DIRECTIVE INT_OPERAND INT_OPERAND INT_OPERAND 
 	| PRAGMA_DIRECTIVE STRING SEMI_COLON { recognizer->add_pragma($2); }
 	| function_decl SEMI_COLON {/*Do nothing*/}
 	;
@@ -336,7 +336,7 @@ identifier_spec: IDENTIFIER { recognizer->add_identifier($1,0,NON_ARRAY_IDENTIFI
 		int i,lbase,l;
 		char *id = NULL;
 		lbase = strlen($1);
-		for( i=0; i < $3; i++ ) {
+		for( i=0; i < $3; i++ ) { 
 			l = lbase + (int)log10(i+1)+10;
 			id = (char*) malloc(l);
 			snprintf(id,l,"%s%u",$1,i);
@@ -348,10 +348,10 @@ identifier_spec: IDENTIFIER { recognizer->add_identifier($1,0,NON_ARRAY_IDENTIFI
 	| IDENTIFIER LEFT_SQUARE_BRACKET INT_OPERAND RIGHT_SQUARE_BRACKET { recognizer->add_identifier($1,$3,ARRAY_IDENTIFIER); recognizer->func_header_info($1); recognizer->func_header_info_int("[",$3); recognizer->func_header_info("]");}
 	;
 
-var_spec_list: var_spec
+var_spec_list: var_spec 
 	 | var_spec_list var_spec;
 
-var_spec: space_spec
+var_spec: space_spec 
 	| type_spec
 	| align_spec
 	| VISIBLE_DIRECTIVE
@@ -376,8 +376,8 @@ addressable_spec: CONST_DIRECTIVE {  recognizer->add_space_spec(const_space,$1);
 	| TEX_DIRECTIVE 	  {  recognizer->add_space_spec(tex_space,0); }
 	;
 
-type_spec: scalar_type
-	|  vector_spec scalar_type
+type_spec: scalar_type 
+	|  vector_spec scalar_type 
 	;
 
 vector_spec:  V2_TYPE {  recognizer->add_option(V2_TYPE); recognizer->func_header_info(".v2");}
@@ -417,14 +417,14 @@ literal_list: literal_operand
 
 // TODO: This is currently hardcoded to handle and ignore one specific case
 // that all prototype statements follow in the PTX from Pytorch. As a
-// workaround, this parses and ignores both the prototype declaration
-// and calling of the prototype (which conveniently comes right after the
-// declaration for all cases.) This should be changed to handle both
+// workaround, this parses and ignores both the prototype declaration 
+// and calling of the prototype (which conveniently comes right after the 
+// declaration for all cases.) This should be changed to handle both 
 // declaring the prototype, and actually calling it.
 prototype_block: prototype_decl prototype_call
 
-prototype_decl: IDENTIFIER COLON CALLPROTOTYPE_DIRECTIVE LEFT_PAREN prototype_param RIGHT_PAREN IDENTIFIER LEFT_PAREN prototype_param RIGHT_PAREN SEMI_COLON
-
+prototype_decl: IDENTIFIER COLON CALLPROTOTYPE_DIRECTIVE LEFT_PAREN prototype_param RIGHT_PAREN IDENTIFIER LEFT_PAREN prototype_param RIGHT_PAREN SEMI_COLON 
+	      
 prototype_call: OPCODE LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA operand COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON
 	      | OPCODE IDENTIFIER COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON
 
@@ -439,7 +439,7 @@ instruction_statement:  instruction SEMI_COLON
 instruction: opcode_spec LEFT_PAREN operand RIGHT_PAREN { recognizer->set_return(); } COMMA operand COMMA LEFT_PAREN operand_list RIGHT_PAREN
 	| opcode_spec operand COMMA LEFT_PAREN operand_list RIGHT_PAREN
 	| opcode_spec operand COMMA LEFT_PAREN RIGHT_PAREN
-	| opcode_spec operand_list
+	| opcode_spec operand_list 
 	| opcode_spec
 	;
 
@@ -468,8 +468,8 @@ option: type_spec
 	| compare_spec
 	| addressable_spec
 	| rounding_mode
-	| wmma_spec
-	| prmt_spec
+	| wmma_spec 
+	| prmt_spec 
 	| SYNC_OPTION { recognizer->add_option(SYNC_OPTION); }
 	| ARRIVE_OPTION { recognizer->add_option(ARRIVE_OPTION); }
 	| RED_OPTION { recognizer->add_option(RED_OPTION); }
@@ -609,7 +609,7 @@ vector_operand: LEFT_BRACE IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { recognizer-
 	;
 
 tex_operand: LEFT_SQUARE_BRACKET IDENTIFIER COMMA { recognizer->add_scalar_operand($2); }
-		vector_operand
+		vector_operand 
 	     RIGHT_SQUARE_BRACKET
 	;
 
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 26283a6..8c4ad4d 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -965,7 +965,7 @@ class ptx_instruction : public warp_inst_t {
   bool get_pred_neg() const { return m_neg_pred; }
   int get_pred_mod() const { return m_pred_mod; }
   const char *get_source() const { return m_source.c_str(); }
-  
+
   const std::list<int> get_scalar_type() const {return m_scalar_type;}
   const std::list<int> get_options() const {return m_options;}
 
-- 
cgit v1.3

