From b3ce70a797756285ea9b15b3e5cf515d8b6a2b63 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sun, 10 Oct 2010 21:19:52 -0800 Subject: 1. create function unit classes for SP, SFU, LD/ST. 2. refactor memory stage into a ld/st function unit 3. refactor memory access generation (moved into warp_inst_t class) the above should make supporting fermi uarch much easier passing CUDA 3.1 regression still need to... (a) update scoreboard to keep count of outstanding memory requests and use operand collector for writebacks into register file (b) add back shared memory pipeline delay (c) remove use of MSHR's for non-cached global/local accesses (d) replace texture cache with a split tag/data array pipe (e) re-implement memory_partition stuff so it makes more sense [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7844] --- src/cuda-sim/ptx_parser.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/cuda-sim/ptx_parser.cc') diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 5a65481..c4486a2 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -68,10 +68,10 @@ extern "C" int ptx_error( const char *s ); extern int ptx_lineno; -static unsigned g_warp_size; -void set_ptx_warp_size(unsigned warp_size) +static const struct shader_core_config *g_shader_core_config; +void set_ptx_warp_size(const struct shader_core_config * warp_size) { - g_warp_size=warp_size; + g_shader_core_config=warp_size; } static bool g_debug_ir_generation=false; @@ -292,7 +292,7 @@ const ptx_instruction *ptx_instruction_lookup( const char *filename, unsigned li void add_instruction() { DPRINTF("add_instruction: %s", ((g_opcode>0)?g_opcode_string[g_opcode]:"