From 35cf76f383ec8de6de901bbbcd8fb478f69e46e4 Mon Sep 17 00:00:00 2001 From: sspenst Date: Wed, 6 Jul 2016 13:56:52 -0700 Subject: Added sstarr memory, which works the same as shared memory --- src/cuda-sim/ptx_sim.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cuda-sim/ptx_sim.h') diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index f926e6d..c66b68c 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -424,6 +424,7 @@ public: memory_space_t m_last_memory_space; dram_callback_t m_last_dram_callback; memory_space *m_shared_mem; + memory_space *m_sstarr_mem; memory_space *m_local_mem; ptx_cta_info *m_cta_info; ptx_reg_t m_last_set_operand_value; -- cgit v1.3 From adc311951d67b0685ebf2fab4ce6410f96f0039a Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 11 Jul 2016 11:16:46 -0700 Subject: Reverted the previous commit to add a cleaner way of getting NUM_THREADS. Now, sst_impl doesn't functionally execute on the last indexed element of an array, but instead on the actual last thread that executes --- libcuda/cuda_runtime_api.cc | 7 ++----- src/abstract_hardware_model.h | 3 --- src/cuda-sim/instructions.cc | 13 ++++++++----- src/cuda-sim/ptx_sim.cc | 16 ++++++++++++++++ src/cuda-sim/ptx_sim.h | 4 ++++ 5 files changed, 30 insertions(+), 13 deletions(-) (limited to 'src/cuda-sim/ptx_sim.h') diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 3eff4af..e8a0e91 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -180,9 +180,6 @@ cudaError_t g_last_cudaError = cudaSuccess; extern stream_manager *g_stream_manager; -dim3 gridDim = (dim3){1,1,1}; -dim3 blockDim = (dim3){1,1,1}; - void register_ptx_function( const char *name, function_info *impl ) { // no longer need this @@ -962,8 +959,8 @@ __host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun ) g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 ); kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context); std::string kname = grid->name(); - gridDim = config.grid_dim(); - blockDim = config.block_dim(); + dim3 gridDim = config.grid_dim(); + dim3 blockDim = config.block_dim(); printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n", kname.c_str(), stream?stream->get_uid():0, gridDim.x,gridDim.y,gridDim.z,blockDim.x,blockDim.y,blockDim.z ); stream_operation op(grid,g_ptx_sim_mode,stream); diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 46c3279..6ed9b8e 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -162,9 +162,6 @@ struct dim3 { }; #endif -extern dim3 gridDim; -extern dim3 blockDim; - void increment_x_then_y_then_z( dim3 &i, const dim3 &bound); class kernel_info_t { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index fd3b1fa..b5a3db4 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3754,6 +3754,7 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) memory_space_t space = pI->get_space(); memory_space *mem = NULL; addr_t addr = src2_data.u32 * 4; // this assumes sstarr memory starts at address 0 + ptx_cta_info *cta_info = thread->m_cta_info; decode_space(space,thread,src1,mem,addr); @@ -3765,18 +3766,19 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) mem->write(addr,size/8,&src3_data.s64,thread,pI); // sync threads - cpI->set_bar_id(dst_data.u32); + cpI->set_bar_id(16); // use 16 for sst because bar uses an int from 0-15 thread->m_last_effective_address = addr; thread->m_last_memory_space = space; thread->m_last_dram_callback.function = bar_callback; thread->m_last_dram_callback.instruction = cpI; - int NUM_THREADS = blockDim.x * blockDim.y * blockDim.z; - if (src2_data.s64 == NUM_THREADS-1) { - // pick only one thread to load all of the data back from sstarr memory + // the last thread that executes loads all of the data back from sstarr memory + int NUM_THREADS = cta_info->num_threads(); + cta_info->inc_bar_threads(); + if (NUM_THREADS == cta_info->get_bar_threads()) { unsigned offset = 0; - addr -= (NUM_THREADS-1)*4; + addr = 0; ptx_reg_t data; float sstarr_fdata[NUM_THREADS]; signed long long sstarr_ldata[NUM_THREADS]; @@ -3812,6 +3814,7 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) offset++; } + cta_info->reset_bar_threads(); thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; thread->m_last_memory_space = space; } diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index 511e8d6..f48115b 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -44,6 +44,7 @@ ptx_cta_info::ptx_cta_info( unsigned sm_idx ) m_sm_idx = sm_idx; m_uid = g_ptx_cta_info_uid++; + m_bar_threads = 0; } void ptx_cta_info::add_thread( ptx_thread_info *thd ) @@ -128,6 +129,21 @@ unsigned ptx_cta_info::get_sm_idx() const return m_sm_idx; } +unsigned ptx_cta_info::get_bar_threads() const +{ + return m_bar_threads; +} + +void ptx_cta_info::inc_bar_threads() +{ + m_bar_threads++; +} + +void ptx_cta_info::reset_bar_threads() +{ + m_bar_threads = 0; +} + unsigned g_ptx_thread_info_uid_next=1; unsigned g_ptx_thread_info_delete_count=0; diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index c66b68c..4e748e9 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -158,8 +158,12 @@ public: void register_thread_exit( ptx_thread_info *thd ); void register_deleted_thread( ptx_thread_info *thd ); unsigned get_sm_idx() const; + unsigned get_bar_threads() const; + void inc_bar_threads(); + void reset_bar_threads(); private: + unsigned m_bar_threads; unsigned long long m_uid; unsigned m_sm_idx; std::set m_threads_in_cta; -- cgit v1.3 From d1b45cf53a39261663a3eff0d409d6c1220d923d Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 5 Aug 2016 14:45:56 -0700 Subject: Added ptx_warp_info to know how many threads within a warp have executed --- src/abstract_hardware_model.h | 2 + src/cuda-sim/cuda-sim.cc | 10 +++++ src/cuda-sim/instructions.cc | 95 +++++++++++++++++++++++-------------------- src/cuda-sim/ptx_sim.cc | 21 ++++++++++ src/cuda-sim/ptx_sim.h | 12 ++++++ 5 files changed, 95 insertions(+), 45 deletions(-) (limited to 'src/cuda-sim/ptx_sim.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 13dfce3..cfa8c9f 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1028,6 +1028,7 @@ class core_t { m_warp_count += 1; } assert( m_warp_count * m_warp_size > 0 ); + //m_warp = ( ptx_warp_info** )calloc( m_warp_count, sizeof( ptx_warp_info* ) ); m_thread = ( ptx_thread_info** ) calloc( m_warp_count * m_warp_size, sizeof( ptx_thread_info* ) ); @@ -1063,6 +1064,7 @@ class core_t { class gpgpu_sim *m_gpu; kernel_info_t *m_kernel; simt_stack **m_simt_stack; // pdom based reconvergence context for each warp + //class ptx_warp_info ** m_warp; class ptx_thread_info ** m_thread; unsigned m_warp_size; unsigned m_warp_count; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 337463b..ba0d00b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1417,6 +1417,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, static std::map shared_memory_lookup; static std::map sstarr_memory_lookup; static std::map ptx_cta_lookup; + static std::map ptx_warp_lookup; static std::map > local_memory_lookup; if ( *thread_info != NULL ) { @@ -1501,6 +1502,15 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, new_tid += tid; ptx_thread_info *thd = new ptx_thread_info(kernel); + ptx_warp_info *warp_info = NULL; + if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { + warp_info = new ptx_warp_info(); // num_threads should be threads in the warp + ptx_warp_lookup[hw_warp_id] = warp_info; + } else { + warp_info = ptx_warp_lookup[hw_warp_id]; + } + thd->m_warp_info = warp_info; + memory_space *local_mem = NULL; std::map::iterator l = local_mem_lookup.find(new_tid); if ( l != local_mem_lookup.end() ) { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index f58c4f5..9dcc25c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1471,74 +1471,81 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) // 7 = synapse value // 8 = output value - // TODO: what should happen when the output precision is larger than the input precision? - // TODO: create a ptx_warp_info that can do the same thing that ptx_cta_info does here - ptx_cta_info *cta_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_cta_info; - const int NUM_THREADS = cta_info->num_threads(); - const int NUM_BUFFERS = 4; - cta_info->inc_bar_threads(); + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + unsigned type = pI->get_type(); + int tid = inst.warp_id() * core->get_warp_size(); + ptx_thread_info *thread = core->get_thread_info()[tid]; + const int ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; + const int op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; + const int THREADS = inst.active_count(); + const int INBUFFERS = 4; + const int OUTBUFFERS = (((32/ip)*INBUFFERS) / (32/op)) + ((((32/ip)*INBUFFERS) % (32/op)) != 0); + if (OUTBUFFERS > THREADS) { + printf("GPGPU-Sim PTX: BSMAD ERROR - Number of output registers required (%d) is greater than the number available (%d)\n", OUTBUFFERS, THREADS); + abort(); + } + ptx_warp_info *warp_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_warp_info; + warp_info->inc_done_threads(); // threads within the warp are executed sequentially by the simulator, store output in first four registers - if (cta_info->get_bar_threads() <= NUM_BUFFERS) { - unsigned ip, op; // only get these when i = 0 - unsigned buffer[inst.active_count()][NUM_BUFFERS]; + if (warp_info->get_done_threads() <= OUTBUFFERS) { + unsigned buffer[inst.active_count()][INBUFFERS]; unsigned synapse[inst.active_count()]; - unsigned output[NUM_BUFFERS]; + unsigned output; // loop through all threads in the warp and get all data for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { if (inst.active(i)) { - const operand_info dst = pI->dst(); - const operand_info src1 = pI->operand_lookup(1); - const operand_info src2 = pI->operand_lookup(2); - const operand_info src3 = pI->operand_lookup(3); - const operand_info src4 = pI->operand_lookup(4); - const operand_info src5 = pI->operand_lookup(5); - const operand_info src6 = pI->operand_lookup(6); - const operand_info src7 = pI->operand_lookup(7); - const operand_info src8 = pI->operand_lookup(8); - unsigned type = pI->get_type(); - - int tid = inst.warp_id() * core->get_warp_size() + i; - ptx_thread_info *thread = core->get_thread_info()[tid]; - - // only get precision data once - if (j == 0) { - ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; - op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; - } + const operand_info &src3 = pI->operand_lookup(3); + const operand_info &src4 = pI->operand_lookup(4); + const operand_info &src5 = pI->operand_lookup(5); + const operand_info &src6 = pI->operand_lookup(6); + const operand_info &src7 = pI->operand_lookup(7); + const operand_info &src8 = pI->operand_lookup(8); + + thread = core->get_thread_info()[tid+i]; // get buffer data and synapse data from each thread buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32; buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32; buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32; buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32; synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32; + j++; // get output data from the first 4 threads - if (j < NUM_BUFFERS) { - output[j] = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; + if (j == warp_info->get_done_threads()) { + output = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; } - j++; } } // unpack registers, compute enough outputs to fill an output register unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned)); - unsigned buffer_data_start = (32/op)*(cta_info->get_bar_threads()-1); - for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*NUM_BUFFERS; i++) { + unsigned buffer_data_start = (32/op)*(warp_info->get_done_threads()-1); + for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*INBUFFERS; i++) { unsigned buf = i/(32/ip); unsigned pos = i%(32/ip); - unsigned mask = 0; + int sum = 0; + // sum values from the buffers for (int b = 0; b < ip; b++) { mask |= (1 << b); } mask <<= (pos*ip); - int sum = 0; - for (int j = 0; j < NUM_THREADS; j++) { + for (int j = 0; j < THREADS; j++) { sum += (mask & buffer[j][buf]) >> (pos*ip); } - unpacked_output[i - buffer_data_start] = sum; + // get the previous output + mask = 0; + for (int b = 0; b < op; b++) { + mask |= (1 << b); + } + mask <<= (op*(i-buffer_data_start)); + int past_output = (mask & output) >> (op*(i-buffer_data_start)); + + unpacked_output[i-buffer_data_start] = sum + past_output; } // truncate output @@ -1575,11 +1582,8 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) // store the result in the correct thread's output register for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { if (inst.active(i)) j++; - if (j == cta_info->get_bar_threads()) { - const operand_info &dst = pI->dst(); - unsigned type = pI->get_type(); - int tid = inst.warp_id() * core->get_warp_size() + i; - ptx_thread_info *thread = core->get_thread_info()[tid]; + if (j == warp_info->get_done_threads()) { + thread = core->get_thread_info()[tid+i]; ptx_reg_t data; data.u32 = output_data; thread->set_operand_value(dst, data, type, thread, pI); @@ -1588,8 +1592,9 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) } } - if (cta_info->get_bar_threads() == NUM_THREADS) { - cta_info->reset_bar_threads(); + // once the warp has finished, set the number of completed threads back to 0 for the next warp + if (warp_info->get_done_threads() == THREADS) { + warp_info->reset_done_threads(); } } diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index f48115b..820287d 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -144,6 +144,26 @@ void ptx_cta_info::reset_bar_threads() m_bar_threads = 0; } +ptx_warp_info::ptx_warp_info() +{ + reset_done_threads(); +} + +unsigned ptx_warp_info::get_done_threads() const +{ + return m_done_threads; +} + +void ptx_warp_info::inc_done_threads() +{ + m_done_threads++; +} + +void ptx_warp_info::reset_done_threads() +{ + m_done_threads = 0; +} + unsigned g_ptx_thread_info_uid_next=1; unsigned g_ptx_thread_info_delete_count=0; @@ -170,6 +190,7 @@ ptx_thread_info::ptx_thread_info( kernel_info_t &kernel ) m_branch_taken = 0; m_shared_mem = NULL; m_sstarr_mem = NULL; + m_warp_info = NULL; m_cta_info = NULL; m_local_mem = NULL; m_symbol_table = NULL; diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index 4e748e9..c62fa57 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -171,6 +171,17 @@ private: std::set m_dangling_pointers; }; +class ptx_warp_info { +public: + ptx_warp_info(); // add get_core or something, or threads? + unsigned get_done_threads() const; + void inc_done_threads(); + void reset_done_threads(); + +private: + unsigned m_done_threads; +}; + class symbol; struct stack_entry { @@ -430,6 +441,7 @@ public: memory_space *m_shared_mem; memory_space *m_sstarr_mem; memory_space *m_local_mem; + ptx_warp_info *m_warp_info; ptx_cta_info *m_cta_info; ptx_reg_t m_last_set_operand_value; -- cgit v1.3 From fa0089a5d3a86ef348fae9a83a862f5219892bab Mon Sep 17 00:00:00 2001 From: aamir Date: Wed, 30 May 2018 23:07:44 -0700 Subject: adding code for wmma_ld_impl, error at decode space --- cuda-kernels/.tensor_core_ptx.swp | Bin 0 -> 16384 bytes cuda-kernels/Makefile | 3 +- cuda-kernels/tensor_core | Bin 48541 -> 2750968 bytes cuda-kernels/tensor_core_ptx | 171 +++++++++++ src/Makefile | 2 +- src/cuda-sim/.ptx.y.swp | Bin 0 -> 36864 bytes src/cuda-sim/Makefile | 2 +- src/cuda-sim/instructions.cc | 72 ++++- src/cuda-sim/ptx.y~ | 608 ++++++++++++++++++++++++++++++++++++++ src/cuda-sim/ptx_ir.h | 4 +- src/cuda-sim/ptx_sim.h | 9 + src/gpgpu-sim/Makefile | 2 +- src/intersim2/Makefile | 2 +- 13 files changed, 865 insertions(+), 10 deletions(-) create mode 100644 cuda-kernels/.tensor_core_ptx.swp create mode 100644 cuda-kernels/tensor_core_ptx create mode 100644 src/cuda-sim/.ptx.y.swp create mode 100644 src/cuda-sim/ptx.y~ (limited to 'src/cuda-sim/ptx_sim.h') diff --git a/cuda-kernels/.tensor_core_ptx.swp b/cuda-kernels/.tensor_core_ptx.swp new file mode 100644 index 0000000..6d7bad4 Binary files /dev/null and b/cuda-kernels/.tensor_core_ptx.swp differ diff --git a/cuda-kernels/Makefile b/cuda-kernels/Makefile index 51a7760..673460f 100755 --- a/cuda-kernels/Makefile +++ b/cuda-kernels/Makefile @@ -1,5 +1,6 @@ all: tensor_core.cu - nvcc -arch=sm_70 -lcudart -g -o tensor_core tensor_core.cu + nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o tensor_core tensor_core.cu +# nvcc -arch=sm_70 -lcudart -g -o tensor_core tensor_core.cu .PHONY: clean: diff --git a/cuda-kernels/tensor_core b/cuda-kernels/tensor_core index b25f3d9..cb53851 100755 Binary files a/cuda-kernels/tensor_core and b/cuda-kernels/tensor_core differ diff --git a/cuda-kernels/tensor_core_ptx b/cuda-kernels/tensor_core_ptx new file mode 100644 index 0000000..36074cb --- /dev/null +++ b/cuda-kernels/tensor_core_ptx @@ -0,0 +1,171 @@ +// +// Generated by NVIDIA NVVM Compiler +// +// Compiler Build ID: CL-22781540 +// Cuda compilation tools, release 9.0, V9.0.176 +// Based on LLVM 3.4svn +// + +.version 6.0 +.target sm_70 +.address_size 64 + + // .globl _Z12wmma_exampleP6__halfS0_Pfiiiff +.extern .func (.param .b32 func_retval0) vprintf +( + .param .b64 vprintf_param_0, + .param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( + .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, + .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, + .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, + .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, + .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, + .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, + .param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, + .param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ + .local .align 8 .b8 __local_depot0[8]; + .reg .b64 %SP; + .reg .b64 %SPL; + .reg .pred %p<6>; + .reg .f32 %f<34>; + .reg .b32 %r<38>; + .reg .b64 %rd<18>; + + + mov.u64 %rd17, __local_depot0; + cvta.local.u64 %SP, %rd17; + ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; + ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; + ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; + ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; + ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; + ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + // inline asm + mov.u32 %r6, %clock; + // inline asm + mov.u32 %r8, %ntid.x; + mov.u32 %r9, %ctaid.x; + mov.u32 %r10, %tid.x; + mad.lo.s32 %r11, %r8, %r9, %r10; + mov.u32 %r12, WARP_SZ; + div.u32 %r13, %r11, %r12; + mov.u32 %r14, %ntid.y; + mov.u32 %r15, %ctaid.y; + mov.u32 %r16, %tid.y; + mad.lo.s32 %r17, %r14, %r15, %r16; + shl.b32 %r2, %r13, 4; + shl.b32 %r3, %r17, 4; + setp.lt.s32 %p1, %r2, %r4; + setp.gt.s32 %p2, %r5, 0; + and.pred %p3, %p1, %p2; + setp.lt.s32 %p4, %r3, %r7; + and.pred %p5, %p3, %p4; + mov.f32 %f26, 0f00000000; + mov.f32 %f27, %f26; + mov.f32 %f28, %f26; + mov.f32 %f29, %f26; + mov.f32 %f30, %f26; + mov.f32 %f31, %f26; + mov.f32 %f32, %f26; + mov.f32 %f33, %f26; + @!%p5 bra BB0_2; + bra.uni BB0_1; + +BB0_1: + mul.wide.s32 %rd4, %r2, 2; + add.s64 %rd5, %rd1, %rd4; + wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; + mul.wide.s32 %rd6, %r3, 2; + add.s64 %rd7, %rd2, %rd6; + wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; + mov.f32 %f25, 0f00000000; + wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: + add.u64 %rd8, %SP, 0; + cvta.to.local.u64 %rd9, %rd8; + mul.lo.s32 %r35, %r3, %r4; + cvt.s64.s32 %rd10, %r35; + cvt.s64.s32 %rd11, %r2; + add.s64 %rd12, %rd10, %rd11; + shl.b64 %rd13, %rd12, 2; + add.s64 %rd14, %rd3, %rd13; + wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + // inline asm + mov.u32 %r34, %clock; + // inline asm + sub.s32 %r36, %r34, %r6; + st.local.u32 [%rd9], %r36; + mov.u64 %rd15, $str; + cvta.global.u64 %rd16, %rd15; + // Callseq Start 0 + { + .reg .b32 temp_param_reg; + // } + .param .b64 param0; + st.param.b64 [param0+0], %rd16; + .param .b64 param1; + st.param.b64 [param1+0], %rd8; + .param .b32 retval0; + call.uni (retval0), + vprintf, + ( + param0, + param1 + ); + ld.param.b32 %r37, [retval0+0]; + + //{ + }// Callseq End 0 + ret; +} + + // .globl _Z17convertFp32ToFp16P6__halfPfi +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( + .param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, + .param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, + .param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ + .reg .pred %p<2>; + .reg .b16 %rs<2>; + .reg .f32 %f<2>; + .reg .b32 %r<6>; + .reg .b64 %rd<9>; + + + ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; + ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; + ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; + mov.u32 %r3, %ntid.x; + mov.u32 %r4, %ctaid.x; + mov.u32 %r5, %tid.x; + mad.lo.s32 %r1, %r4, %r3, %r5; + setp.ge.s32 %p1, %r1, %r2; + @%p1 bra BB1_2; + + cvta.to.global.u64 %rd3, %rd2; + mul.wide.s32 %rd4, %r1, 4; + add.s64 %rd5, %rd3, %rd4; + ld.global.f32 %f1, [%rd5]; + // inline asm + { cvt.rn.f16.f32 %rs1, %f1;} + + // inline asm + cvta.to.global.u64 %rd6, %rd1; + mul.wide.s32 %rd7, %r1, 2; + add.s64 %rd8, %rd6, %rd7; + st.global.u16 [%rd8], %rs1; + +BB1_2: + ret; +} + + diff --git a/src/Makefile b/src/Makefile index 6001669..09194f3 100644 --- a/src/Makefile +++ b/src/Makefile @@ -46,7 +46,7 @@ ifeq ($(TRACE),1) endif ifneq ($(DEBUG),1) - OPTFLAGS += -O3 + OPTFLAGS += -O0 else CXXFLAGS += endif diff --git a/src/cuda-sim/.ptx.y.swp b/src/cuda-sim/.ptx.y.swp new file mode 100644 index 0000000..c8a83b5 Binary files /dev/null and b/src/cuda-sim/.ptx.y.swp differ diff --git a/src/cuda-sim/Makefile b/src/cuda-sim/Makefile index 999dad7..a65e8e1 100644 --- a/src/cuda-sim/Makefile +++ b/src/cuda-sim/Makefile @@ -42,7 +42,7 @@ include ../../version_detection.mk OUTPUT_DIR=$(SIM_OBJ_FILES_DIR)/cuda-sim -OPT := -O3 -g3 -Wall -Wno-unused-function -Wno-sign-compare +OPT := -O0 -g3 -Wall -Wno-unused-function -Wno-sign-compare ifeq ($(DEBUG),1) OPT := -g3 -Wall -Wno-unused-function -Wno-sign-compare endif diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 446cdbf..16f33c6 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -643,6 +643,33 @@ void ptx_thread_info::set_vector_operand_values( const operand_info &dst, m_last_set_operand_value = data1; } +void ptx_thread_info::set_wmma_vector_operand_values( const operand_info &dst, + const ptx_reg_t &data1, + const ptx_reg_t &data2, + const ptx_reg_t &data3, + const ptx_reg_t &data4, + const ptx_reg_t &data5, + const ptx_reg_t &data6, + const ptx_reg_t &data7, + const ptx_reg_t &data8 ) +{ + unsigned num_elements = dst.get_vect_nelem(); + if (num_elements > 7) { + set_reg(dst.vec_symbol(0), data1); + set_reg(dst.vec_symbol(1), data2); + set_reg(dst.vec_symbol(2), data3); + set_reg(dst.vec_symbol(3), data4); + set_reg(dst.vec_symbol(4), data5); + set_reg(dst.vec_symbol(5), data6); + set_reg(dst.vec_symbol(6), data7); + set_reg(dst.vec_symbol(7), data8); + } + else{ + printf("error:set_wmma_vector_operands"); + } + + m_last_set_operand_value = data1; +} #define my_abs(a) (((a)<0)?(-a):(a)) @@ -1493,9 +1520,6 @@ unsigned trunc(unsigned num, unsigned precision) { } return num; } -void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) -{ -} void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { } @@ -2595,6 +2619,48 @@ void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ld_exec(pI,thread); } +void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned type = pI->get_type(); + + int tid = inst.warp_id_func() * core->get_warp_size(); + int thrd; + ptx_thread_info *thread; + thread = core->get_thread_info()[tid]; + + ptx_reg_t src1_data = thread->get_operand_value(src1, dst, type, thread, 1); + + ptx_reg_t data; + memory_space_t space = pI->get_space(); + + memory_space *mem = NULL; + addr_t addr = src1_data.u32; + + decode_space(space,thread,src1,mem,addr); + + size_t size; + int t; + data.u64=0; + type_info_key::type_decode(type,size,t); + ptx_reg_t data1, data2, data3, data4; + ptx_reg_t data5, data6, data7, data8; + mem->read(addr,size/8,&data1.s64); + mem->read(addr+size/8,size/8,&data2.s64); + mem->read(addr+2*size/8,size/8,&data3.s64); + mem->read(addr+3*size/8,size/8,&data4.s64); + mem->read(addr+4*size/8,size/8,&data5.s64); + mem->read(addr+5*size/8,size/8,&data6.s64); + mem->read(addr+6*size/8,size/8,&data7.s64); + mem->read(addr+7*size/8,size/8,&data8.s64); + thread->set_wmma_vector_operand_values(dst,data1,data2,data3,data4,data5,data6,data7,data8); + + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; +} void lg2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { diff --git a/src/cuda-sim/ptx.y~ b/src/cuda-sim/ptx.y~ new file mode 100644 index 0000000..0710ecd --- /dev/null +++ b/src/cuda-sim/ptx.y~ @@ -0,0 +1,608 @@ +/* +Copyright (c) 2009-2011, Tor M. Aamodt +The University of British Columbia +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. +Redistributions in binary form must reproduce the above copyright notice, this +list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. +Neither the name of The University of British Columbia nor the names of its +contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +%union { + double double_value; + float float_value; + int int_value; + char * string_value; + void * ptr_value; +} + +%token STRING +%token OPCODE +%token WMMA_DIRECTIVE +%token LAYOUT +%token CONFIGURATION +%token ALIGN_DIRECTIVE +%token BRANCHTARGETS_DIRECTIVE +%token BYTE_DIRECTIVE +%token CALLPROTOTYPE_DIRECTIVE +%token CALLTARGETS_DIRECTIVE +%token CONST_DIRECTIVE +%token CONSTPTR_DIRECTIVE +%token PTR_DIRECTIVE +%token ENTRY_DIRECTIVE +%token EXTERN_DIRECTIVE +%token WEAK_DIRECTIVE +%token FILE_DIRECTIVE +%token FUNC_DIRECTIVE +%token GLOBAL_DIRECTIVE +%token LOCAL_DIRECTIVE +%token LOC_DIRECTIVE +%token MAXNCTAPERSM_DIRECTIVE +%token MAXNNREG_DIRECTIVE +%token MAXNTID_DIRECTIVE +%token MINNCTAPERSM_DIRECTIVE +%token PARAM_DIRECTIVE +%token PRAGMA_DIRECTIVE +%token REG_DIRECTIVE +%token REQNTID_DIRECTIVE +%token SECTION_DIRECTIVE +%token SHARED_DIRECTIVE +%token SREG_DIRECTIVE +%token SSTARR_DIRECTIVE +%token STRUCT_DIRECTIVE +%token SURF_DIRECTIVE +%token TARGET_DIRECTIVE +%token TEX_DIRECTIVE +%token UNION_DIRECTIVE +%token VERSION_DIRECTIVE +%token ADDRESS_SIZE_DIRECTIVE +%token VISIBLE_DIRECTIVE +%token WEAK_DIRECTIVE +%token IDENTIFIER +%token INT_OPERAND +%token FLOAT_OPERAND +%token DOUBLE_OPERAND +%token S8_TYPE +%token S16_TYPE +%token S32_TYPE +%token S64_TYPE +%token U8_TYPE +%token U16_TYPE +%token U32_TYPE +%token U64_TYPE +%token F16_TYPE +%token F32_TYPE +%token F64_TYPE +%token FF64_TYPE +%token B8_TYPE +%token B16_TYPE +%token B32_TYPE +%token B64_TYPE +%token BB64_TYPE +%token BB128_TYPE +%token PRED_TYPE +%token TEXREF_TYPE +%token SAMPLERREF_TYPE +%token SURFREF_TYPE +%token V2_TYPE +%token V3_TYPE +%token V4_TYPE +%token COMMA +%token PRED +%token HALF_OPTION +%token EXTP_OPTION +%token EQ_OPTION +%token NE_OPTION +%token LT_OPTION +%token LE_OPTION +%token GT_OPTION +%token GE_OPTION +%token LO_OPTION +%token LS_OPTION +%token HI_OPTION +%token HS_OPTION +%token EQU_OPTION +%token NEU_OPTION +%token LTU_OPTION +%token LEU_OPTION +%token GTU_OPTION +%token GEU_OPTION +%token NUM_OPTION +%token NAN_OPTION +%token CF_OPTION +%token SF_OPTION +%token NSF_OPTION +%token LEFT_SQUARE_BRACKET +%token RIGHT_SQUARE_BRACKET +%token WIDE_OPTION +%token SPECIAL_REGISTER +%token MINUS +%token PLUS +%token COLON +%token SEMI_COLON +%token EXCLAMATION +%token PIPE +%token RIGHT_BRACE +%token LEFT_BRACE +%token EQUALS +%token PERIOD +%token BACKSLASH +%token DIMENSION_MODIFIER +%token RN_OPTION +%token RZ_OPTION +%token RM_OPTION +%token RP_OPTION +%token RNI_OPTION +%token RZI_OPTION +%token RMI_OPTION +%token RPI_OPTION +%token UNI_OPTION +%token GEOM_MODIFIER_1D +%token GEOM_MODIFIER_2D +%token GEOM_MODIFIER_3D +%token SAT_OPTION +%token FTZ_OPTION +%token NEG_OPTION +%token SYNC_OPTION +%token RED_OPTION +%token ARRIVE_OPTION +%token ATOMIC_POPC +%token ATOMIC_AND +%token ATOMIC_OR +%token ATOMIC_XOR +%token ATOMIC_CAS +%token ATOMIC_EXCH +%token ATOMIC_ADD +%token ATOMIC_INC +%token ATOMIC_DEC +%token ATOMIC_MIN +%token ATOMIC_MAX +%token LEFT_ANGLE_BRACKET +%token RIGHT_ANGLE_BRACKET +%token LEFT_PAREN +%token RIGHT_PAREN +%token APPROX_OPTION +%token FULL_OPTION +%token ANY_OPTION +%token ALL_OPTION +%token BALLOT_OPTION +%token GLOBAL_OPTION +%token CTA_OPTION +%token SYS_OPTION +%token EXIT_OPTION +%token ABS_OPTION +%token TO_OPTION +%token CA_OPTION; +%token CG_OPTION; +%token CS_OPTION; +%token LU_OPTION; +%token CV_OPTION; +%token WB_OPTION; +%token WT_OPTION; +%token NC_OPTION; +%token UP_OPTION; +%token DOWN_OPTION; +%token BFLY_OPTION; +%token IDX_OPTION; + +%type function_decl_header +%type function_decl + +%{ + #include "ptx_parser.h" + #include + #include + #include + void syntax_not_implemented(); + extern int g_func_decl; + int ptx_lex(void); + int ptx_error(const char *); +%} + +%% + +input: /* empty */ + | input directive_statement + | input function_defn + | input function_decl + ; + +function_defn: function_decl { set_symtab($1); func_header(".skip"); } statement_block { end_function(); } + | function_decl { set_symtab($1); } block_spec_list { func_header(".skip"); } statement_block { end_function(); } + ; + +block_spec: MAXNTID_DIRECTIVE INT_OPERAND COMMA INT_OPERAND COMMA INT_OPERAND {func_header_info_int(".maxntid", $2); + func_header_info_int(",", $4); + func_header_info_int(",", $6); } + | MINNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".minnctapersm", $2); printf("GPGPU-Sim: Warning: .minnctapersm ignored. \n"); } + | MAXNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".maxnctapersm", $2); printf("GPGPU-Sim: Warning: .maxnctapersm ignored. \n"); } + ; + +block_spec_list: block_spec + | block_spec_list block_spec + ; + +function_decl: function_decl_header LEFT_PAREN { start_function($1); func_header_info("(");} param_entry RIGHT_PAREN {func_header_info(")");} function_ident_param { $$ = reset_symtab(); } + | function_decl_header { start_function($1); } function_ident_param { $$ = reset_symtab(); } + | function_decl_header { start_function($1); add_function_name(""); g_func_decl=0; $$ = reset_symtab(); } + ; + +function_ident_param: IDENTIFIER { add_function_name($1); } LEFT_PAREN {func_header_info("(");} param_list RIGHT_PAREN { g_func_decl=0; func_header_info(")"); } + | IDENTIFIER { add_function_name($1); g_func_decl=0; } + ; + +function_decl_header: ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } + | VISIBLE_DIRECTIVE ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } + | WEAK_DIRECTIVE ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } + | FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + | VISIBLE_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + | WEAK_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + | EXTERN_DIRECTIVE FUNC_DIRECTIVE { $$ = 2; g_func_decl=1; func_header(".func"); } + | WEAK_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + ; + +param_list: /*empty*/ + | param_entry { add_directive(); } + | param_list COMMA {func_header_info(",");} param_entry { add_directive(); } + +param_entry: PARAM_DIRECTIVE { add_space_spec(param_space_unclassified,0); } variable_spec ptr_spec identifier_spec { add_function_arg(); } + | REG_DIRECTIVE { add_space_spec(reg_space,0); } variable_spec identifier_spec { add_function_arg(); } + +ptr_spec: /*empty*/ + | PTR_DIRECTIVE ptr_space_spec ptr_align_spec + | PTR_DIRECTIVE ptr_align_spec + +ptr_space_spec: GLOBAL_DIRECTIVE { add_ptr_spec(global_space); } + | LOCAL_DIRECTIVE { add_ptr_spec(local_space); } + | SHARED_DIRECTIVE { add_ptr_spec(shared_space); } + +ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND + +statement_block: LEFT_BRACE statement_list RIGHT_BRACE + +statement_list: directive_statement { add_directive(); } + | instruction_statement { add_instruction(); } + | statement_list directive_statement { add_directive(); } + | statement_list instruction_statement { add_instruction(); } + | statement_list {start_inst_group();} statement_block {end_inst_group();} + | {start_inst_group();} statement_block {end_inst_group();} + ; + +directive_statement: variable_declaration SEMI_COLON + | VERSION_DIRECTIVE DOUBLE_OPERAND { add_version_info($2, 0); } + | VERSION_DIRECTIVE DOUBLE_OPERAND PLUS { add_version_info($2,1); } + | ADDRESS_SIZE_DIRECTIVE INT_OPERAND {/*Do nothing*/} + | TARGET_DIRECTIVE IDENTIFIER COMMA IDENTIFIER { target_header2($2,$4); } + | TARGET_DIRECTIVE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER { target_header3($2,$4,$6); } + | TARGET_DIRECTIVE IDENTIFIER { target_header($2); } + | FILE_DIRECTIVE INT_OPERAND STRING { add_file($2,$3); } + | FILE_DIRECTIVE INT_OPERAND STRING COMMA INT_OPERAND COMMA INT_OPERAND { add_file($2,$3); } + | LOC_DIRECTIVE INT_OPERAND INT_OPERAND INT_OPERAND + | PRAGMA_DIRECTIVE STRING SEMI_COLON { add_pragma($2); } + | function_decl SEMI_COLON {/*Do nothing*/} + ; + +variable_declaration: variable_spec identifier_list { add_variables(); } + | variable_spec identifier_spec EQUALS initializer_list { add_variables(); } + | variable_spec identifier_spec EQUALS literal_operand { add_variables(); } + | CONSTPTR_DIRECTIVE IDENTIFIER COMMA IDENTIFIER COMMA INT_OPERAND { add_constptr($2, $4, $6); } + ; + +variable_spec: var_spec_list { set_variable_type(); } + +identifier_list: identifier_spec + | identifier_list COMMA identifier_spec; + +identifier_spec: IDENTIFIER { add_identifier($1,0,NON_ARRAY_IDENTIFIER); func_header_info($1);} + | IDENTIFIER LEFT_ANGLE_BRACKET INT_OPERAND RIGHT_ANGLE_BRACKET { func_header_info($1); func_header_info_int("<", $3); func_header_info(">"); + int i,lbase,l; + char *id = NULL; + lbase = strlen($1); + for( i=0; i < $3; i++ ) { + l = lbase + (int)log10(i+1)+10; + id = (char*) malloc(l); + snprintf(id,l,"%s%u",$1,i); + add_identifier(id,0,NON_ARRAY_IDENTIFIER); + } + free($1); + } + | IDENTIFIER LEFT_SQUARE_BRACKET RIGHT_SQUARE_BRACKET { add_identifier($1,0,ARRAY_IDENTIFIER_NO_DIM); func_header_info($1); func_header_info("["); func_header_info("]");} + | IDENTIFIER LEFT_SQUARE_BRACKET INT_OPERAND RIGHT_SQUARE_BRACKET { add_identifier($1,$3,ARRAY_IDENTIFIER); func_header_info($1); func_header_info_int("[",$3); func_header_info("]");} + ; + +var_spec_list: var_spec + | var_spec_list var_spec; + +var_spec: space_spec + | type_spec + | align_spec + | EXTERN_DIRECTIVE { add_extern_spec(); } + | WEAK_DIRECTIVE + ; + +align_spec: ALIGN_DIRECTIVE INT_OPERAND { add_alignment_spec($2); } + +space_spec: REG_DIRECTIVE { add_space_spec(reg_space,0); } + | SREG_DIRECTIVE { add_space_spec(reg_space,0); } + | addressable_spec + ; + +addressable_spec: CONST_DIRECTIVE { add_space_spec(const_space,$1); } + | GLOBAL_DIRECTIVE { add_space_spec(global_space,0); } + | LOCAL_DIRECTIVE { add_space_spec(local_space,0); } + | PARAM_DIRECTIVE { add_space_spec(param_space_unclassified,0); } + | SHARED_DIRECTIVE { add_space_spec(shared_space,0); } + | SSTARR_DIRECTIVE { add_space_spec(sstarr_space,0); } + | SURF_DIRECTIVE { add_space_spec(surf_space,0); } + | TEX_DIRECTIVE { add_space_spec(tex_space,0); } + ; + +type_spec: scalar_type + | vector_spec scalar_type + ; + +vector_spec: V2_TYPE { add_option(V2_TYPE); func_header_info(".v2");} + | V3_TYPE { add_option(V3_TYPE); func_header_info(".v3");} + | V4_TYPE { add_option(V4_TYPE); func_header_info(".v4");} + ; + +scalar_type: S8_TYPE { add_scalar_type_spec( S8_TYPE ); } + | S16_TYPE { add_scalar_type_spec( S16_TYPE ); } + | S32_TYPE { add_scalar_type_spec( S32_TYPE ); } + | S64_TYPE { add_scalar_type_spec( S64_TYPE ); } + | U8_TYPE { add_scalar_type_spec( U8_TYPE ); } + | U16_TYPE { add_scalar_type_spec( U16_TYPE ); } + | U32_TYPE { add_scalar_type_spec( U32_TYPE ); } + | U64_TYPE { add_scalar_type_spec( U64_TYPE ); } + | F16_TYPE { add_scalar_type_spec( F16_TYPE ); } + | F32_TYPE { add_scalar_type_spec( F32_TYPE ); } + | F64_TYPE { add_scalar_type_spec( F64_TYPE ); } + | FF64_TYPE { add_scalar_type_spec( FF64_TYPE ); } + | B8_TYPE { add_scalar_type_spec( B8_TYPE ); } + | B16_TYPE { add_scalar_type_spec( B16_TYPE ); } + | B32_TYPE { add_scalar_type_spec( B32_TYPE ); } + | B64_TYPE { add_scalar_type_spec( B64_TYPE ); } + | BB64_TYPE { add_scalar_type_spec( BB64_TYPE ); } + | BB128_TYPE { add_scalar_type_spec( BB128_TYPE ); } + | PRED_TYPE { add_scalar_type_spec( PRED_TYPE ); } + | TEXREF_TYPE { add_scalar_type_spec( TEXREF_TYPE ); } + | SAMPLERREF_TYPE { add_scalar_type_spec( SAMPLERREF_TYPE ); } + | SURFREF_TYPE { add_scalar_type_spec( SURFREF_TYPE ); } + ; + +initializer_list: LEFT_BRACE literal_list RIGHT_BRACE { add_array_initializer(); } + | LEFT_BRACE initializer_list RIGHT_BRACE { syntax_not_implemented(); } + +literal_list: literal_operand + | literal_list COMMA literal_operand; + +instruction_statement: instruction SEMI_COLON + | IDENTIFIER COLON { add_label($1); } + | pred_spec instruction SEMI_COLON; + +instruction: opcode_spec LEFT_PAREN operand RIGHT_PAREN { set_return(); } COMMA operand COMMA LEFT_PAREN operand_list RIGHT_PAREN + | opcode_spec operand COMMA LEFT_PAREN operand_list RIGHT_PAREN + | opcode_spec operand COMMA LEFT_PAREN RIGHT_PAREN + | opcode_spec operand_list + | opcode_spec + ; + +opcode_spec: OPCODE { add_opcode($1); } option_list + | OPCODE { add_opcode($1); } + +pred_spec: PRED IDENTIFIER { add_pred($2,0, -1); } + | PRED EXCLAMATION IDENTIFIER { add_pred($3,1, -1); } + | PRED IDENTIFIER LT_OPTION { add_pred($2,0,1); } + | PRED IDENTIFIER EQ_OPTION { add_pred($2,0,2); } + | PRED IDENTIFIER LE_OPTION { add_pred($2,0,3); } + | PRED IDENTIFIER NE_OPTION { add_pred($2,0,5); } + | PRED IDENTIFIER GE_OPTION { add_pred($2,0,6); } + | PRED IDENTIFIER EQU_OPTION { add_pred($2,0,10); } + | PRED IDENTIFIER GTU_OPTION { add_pred($2,0,12); } + | PRED IDENTIFIER NEU_OPTION { add_pred($2,0,13); } + | PRED IDENTIFIER CF_OPTION { add_pred($2,0,17); } + | PRED IDENTIFIER SF_OPTION { add_pred($2,0,19); } + | PRED IDENTIFIER NSF_OPTION { add_pred($2,0,28); } + ; + +option_list: option + | option option_list ; + +option: type_spec + | compare_spec + | addressable_spec + | rounding_mode + | wmma_spec + | SYNC_OPTION { add_option(SYNC_OPTION); } + | ARRIVE_OPTION { add_option(ARRIVE_OPTION); } + | RED_OPTION { add_option(RED_OPTION); } + | UNI_OPTION { add_option(UNI_OPTION); } + | WIDE_OPTION { add_option(WIDE_OPTION); } + | ANY_OPTION { add_option(ANY_OPTION); } + | ALL_OPTION { add_option(ALL_OPTION); } + | BALLOT_OPTION { add_option(BALLOT_OPTION); } + | GLOBAL_OPTION { add_option(GLOBAL_OPTION); } + | CTA_OPTION { add_option(CTA_OPTION); } + | SYS_OPTION { add_option(SYS_OPTION); } + | GEOM_MODIFIER_1D { add_option(GEOM_MODIFIER_1D); } + | GEOM_MODIFIER_2D { add_option(GEOM_MODIFIER_2D); } + | GEOM_MODIFIER_3D { add_option(GEOM_MODIFIER_3D); } + | SAT_OPTION { add_option(SAT_OPTION); } + | FTZ_OPTION { add_option(FTZ_OPTION); } + | NEG_OPTION { add_option(NEG_OPTION); } + | APPROX_OPTION { add_option(APPROX_OPTION); } + | FULL_OPTION { add_option(FULL_OPTION); } + | EXIT_OPTION { add_option(EXIT_OPTION); } + | ABS_OPTION { add_option(ABS_OPTION); } + | atomic_operation_spec ; + | TO_OPTION { add_option(TO_OPTION); } + | HALF_OPTION { add_option(HALF_OPTION); } + | EXTP_OPTION { add_option(EXTP_OPTION); } + | CA_OPTION { add_option(CA_OPTION); } + | CG_OPTION { add_option(CG_OPTION); } + | CS_OPTION { add_option(CS_OPTION); } + | LU_OPTION { add_option(LU_OPTION); } + | CV_OPTION { add_option(CV_OPTION); } + | WB_OPTION { add_option(WB_OPTION); } + | WT_OPTION { add_option(WT_OPTION); } + | NC_OPTION { add_option(NC_OPTION); } + | UP_OPTION { add_option(UP_OPTION); } + | DOWN_OPTION { add_option(DOWN_OPTION); } + | BFLY_OPTION { add_option(BFLY_OPTION); } + | IDX_OPTION { add_option(IDX_OPTION); } + ; + +atomic_operation_spec: ATOMIC_AND { add_option(ATOMIC_AND); } + | ATOMIC_POPC { add_option(ATOMIC_POPC); } + | ATOMIC_OR { add_option(ATOMIC_OR); } + | ATOMIC_XOR { add_option(ATOMIC_XOR); } + | ATOMIC_CAS { add_option(ATOMIC_CAS); } + | ATOMIC_EXCH { add_option(ATOMIC_EXCH); } + | ATOMIC_ADD { add_option(ATOMIC_ADD); } + | ATOMIC_INC { add_option(ATOMIC_INC); } + | ATOMIC_DEC { add_option(ATOMIC_DEC); } + | ATOMIC_MIN { add_option(ATOMIC_MIN); } + | ATOMIC_MAX { add_option(ATOMIC_MAX); } + ; + +rounding_mode: floating_point_rounding_mode + | integer_rounding_mode; + + +floating_point_rounding_mode: RN_OPTION { add_option(RN_OPTION); } + | RZ_OPTION { add_option(RZ_OPTION); } + | RM_OPTION { add_option(RM_OPTION); } + | RP_OPTION { add_option(RP_OPTION); } + ; + +integer_rounding_mode: RNI_OPTION { add_option(RNI_OPTION); } + | RZI_OPTION { add_option(RZI_OPTION); } + | RMI_OPTION { add_option(RMI_OPTION); } + | RPI_OPTION { add_option(RPI_OPTION); } + ; + +compare_spec:EQ_OPTION { add_option(EQ_OPTION); } + | NE_OPTION { add_option(NE_OPTION); } + | LT_OPTION { add_option(LT_OPTION); } + | LE_OPTION { add_option(LE_OPTION); } + | GT_OPTION { add_option(GT_OPTION); } + | GE_OPTION { add_option(GE_OPTION); } + | LO_OPTION { add_option(LO_OPTION); } + | LS_OPTION { add_option(LS_OPTION); } + | HI_OPTION { add_option(HI_OPTION); } + | HS_OPTION { add_option(HS_OPTION); } + | EQU_OPTION { add_option(EQU_OPTION); } + | NEU_OPTION { add_option(NEU_OPTION); } + | LTU_OPTION { add_option(LTU_OPTION); } + | LEU_OPTION { add_option(LEU_OPTION); } + | GTU_OPTION { add_option(GTU_OPTION); } + | GEU_OPTION { add_option(GEU_OPTION); } + | NUM_OPTION { add_option(NUM_OPTION); } + | NAN_OPTION { add_option(NAN_OPTION); } + ; + +wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);} + | WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + | WMMA_DIRECTIVE LAYOUT CONFIGURATION ptr_space_spec{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + | WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION ptr_space_spec{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + ; + +operand_list: operand + | operand COMMA operand_list; + +operand: IDENTIFIER { add_scalar_operand( $1 ); } + | EXCLAMATION IDENTIFIER { add_neg_pred_operand( $2 ); } + | MINUS IDENTIFIER { add_scalar_operand( $2 ); change_operand_neg(); } + | memory_operand + | literal_operand + | builtin_operand + | vector_operand + | MINUS vector_operand { change_operand_neg(); } + | tex_operand + | IDENTIFIER PLUS INT_OPERAND { add_address_operand($1,$3); } + | IDENTIFIER LO_OPTION { add_scalar_operand( $1 ); change_operand_lohi(1);} + | MINUS IDENTIFIER LO_OPTION { add_scalar_operand( $2 ); change_operand_lohi(1); change_operand_neg();} + | IDENTIFIER HI_OPTION { add_scalar_operand( $1 ); change_operand_lohi(2);} + | MINUS IDENTIFIER HI_OPTION { add_scalar_operand( $2 ); change_operand_lohi(2); change_operand_neg();} + | IDENTIFIER PIPE IDENTIFIER { add_2vector_operand($1,$3); change_double_operand_type(-1);} + | IDENTIFIER PIPE IDENTIFIER LO_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-1); change_operand_lohi(1);} + | IDENTIFIER PIPE IDENTIFIER HI_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-1); change_operand_lohi(2);} + | IDENTIFIER BACKSLASH IDENTIFIER { add_2vector_operand($1,$3); change_double_operand_type(-3);} + | IDENTIFIER BACKSLASH IDENTIFIER LO_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-3); change_operand_lohi(1);} + | IDENTIFIER BACKSLASH IDENTIFIER HI_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-3); change_operand_lohi(2);} + ; + +vector_operand: LEFT_BRACE IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_2vector_operand($2,$4); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_3vector_operand($2,$4,$6); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_4vector_operand($2,$4,$6,$8); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_8vector_operand($2,$4,$6,$8,$10,$12,$14,$16); } + | LEFT_BRACE IDENTIFIER RIGHT_BRACE { add_1vector_operand($2); } + ; + +tex_operand: LEFT_SQUARE_BRACKET IDENTIFIER COMMA { add_scalar_operand($2); } + vector_operand + RIGHT_SQUARE_BRACKET + ; + +builtin_operand: SPECIAL_REGISTER DIMENSION_MODIFIER { add_builtin_operand($1,$2); } + | SPECIAL_REGISTER { add_builtin_operand($1,-1); } + ; + +memory_operand : LEFT_SQUARE_BRACKET address_expression RIGHT_SQUARE_BRACKET { add_memory_operand(); } + | IDENTIFIER LEFT_SQUARE_BRACKET address_expression RIGHT_SQUARE_BRACKET { add_memory_operand(); change_memory_addr_space($1); } + | IDENTIFIER LEFT_SQUARE_BRACKET literal_operand RIGHT_SQUARE_BRACKET { change_memory_addr_space($1); } + | IDENTIFIER LEFT_SQUARE_BRACKET twin_operand RIGHT_SQUARE_BRACKET { change_memory_addr_space($1); add_memory_operand();} + | MINUS memory_operand { change_operand_neg(); } + ; + +twin_operand : IDENTIFIER PLUS IDENTIFIER { add_double_operand($1,$3); change_double_operand_type(1); } + | IDENTIFIER PLUS IDENTIFIER LO_OPTION { add_double_operand($1,$3); change_double_operand_type(1); change_operand_lohi(1); } + | IDENTIFIER PLUS IDENTIFIER HI_OPTION { add_double_operand($1,$3); change_double_operand_type(1); change_operand_lohi(2); } + | IDENTIFIER PLUS EQUALS IDENTIFIER { add_double_operand($1,$4); change_double_operand_type(2); } + | IDENTIFIER PLUS EQUALS IDENTIFIER LO_OPTION { add_double_operand($1,$4); change_double_operand_type(2); change_operand_lohi(1); } + | IDENTIFIER PLUS EQUALS IDENTIFIER HI_OPTION { add_double_operand($1,$4); change_double_operand_type(2); change_operand_lohi(2); } + | IDENTIFIER PLUS EQUALS INT_OPERAND { add_address_operand($1,$4); change_double_operand_type(3); } + ; + +literal_operand : INT_OPERAND { add_literal_int($1); } + | FLOAT_OPERAND { add_literal_float($1); } + | DOUBLE_OPERAND { add_literal_double($1); } + ; + +address_expression: IDENTIFIER { add_address_operand($1,0); } + | IDENTIFIER LO_OPTION { add_address_operand($1,0); change_operand_lohi(1);} + | IDENTIFIER HI_OPTION { add_address_operand($1,0); change_operand_lohi(2); } + | IDENTIFIER PLUS INT_OPERAND { add_address_operand($1,$3); } + | INT_OPERAND { add_address_operand2($1); } + ; + +%% + +extern int ptx_lineno; +extern const char *g_filename; + +void syntax_not_implemented() +{ + printf("Parse error (%s:%u): this syntax is not (yet) implemented:\n",g_filename,ptx_lineno); + ptx_error(NULL); + abort(); +} diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 833f175..16cc975 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1078,7 +1078,7 @@ public: int membar_level() const { return m_membar_level; } bool has_memory_read() const { - if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP ) + if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP|| m_opcode==MMA_LD_OP) return true; // Check PTXPlus operand type below // Source operands are memory operands @@ -1090,7 +1090,7 @@ public: return false; } bool has_memory_write() const { - if( m_opcode == ST_OP ) return true; + if( m_opcode == ST_OP || m_opcode==MMA_ST_OP ) return true; // Check PTXPlus operand type below // Destination operand is a memory operand ptx_instruction::const_iterator op=op_iter_begin(); diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index 05acf20..403ce5b 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -303,6 +303,15 @@ public: const ptx_reg_t &data2, const ptx_reg_t &data3, const ptx_reg_t &data4 ); + void set_wmma_vector_operand_values( const operand_info &dst, + const ptx_reg_t &data1, + const ptx_reg_t &data2, + const ptx_reg_t &data3, + const ptx_reg_t &data4, + const ptx_reg_t &data5, + const ptx_reg_t &data6, + const ptx_reg_t &data7, + const ptx_reg_t &data8 ); function_info *func_info() { diff --git a/src/gpgpu-sim/Makefile b/src/gpgpu-sim/Makefile index f10a8a4..4f77699 100644 --- a/src/gpgpu-sim/Makefile +++ b/src/gpgpu-sim/Makefile @@ -48,7 +48,7 @@ ifeq ($(GNUC_CPP0X), 1) endif ifneq ($(DEBUG),1) - OPTFLAGS += -O3 + OPTFLAGS += -O0 else CXXFLAGS += endif diff --git a/src/intersim2/Makefile b/src/intersim2/Makefile index bd42000..4ef21ac 100644 --- a/src/intersim2/Makefile +++ b/src/intersim2/Makefile @@ -44,7 +44,7 @@ endif CPPFLAGS += -Wall $(INCPATH) $(DEFINE) ifneq ($(DEBUG),1) -CPPFLAGS += -O3 +CPPFLAGS += -O0 endif CPPFLAGS += -g CPPFLAGS += -fPIC -- cgit v1.3 From e5f532a3b65e17f49991ed08a275f87ac2d68d0a Mon Sep 17 00:00:00 2001 From: aamir Date: Fri, 1 Jun 2018 09:52:12 -0700 Subject: wmma load working --- cuda-kernels/gpgpu_inst_stats.txt | 19 + cuda-kernels/log | 6328 +++++++++++++++++++++++++++++++++++++ cuda-kernels/log1 | 512 +++ cuda-kernels/tensor_core | Bin 2750968 -> 2750968 bytes src/cuda-sim/Makefile | 2 +- src/cuda-sim/cuda-math.h | 1 + src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/half.hpp | 3067 ++++++++++++++++++ src/cuda-sim/instructions.cc | 96 +- src/cuda-sim/ptx_sim.h | 6 +- 10 files changed, 9988 insertions(+), 45 deletions(-) create mode 100644 cuda-kernels/log create mode 100644 cuda-kernels/log1 create mode 100644 src/cuda-sim/half.hpp (limited to 'src/cuda-sim/ptx_sim.h') diff --git a/cuda-kernels/gpgpu_inst_stats.txt b/cuda-kernels/gpgpu_inst_stats.txt index acb1839..41f06a4 100755 --- a/cuda-kernels/gpgpu_inst_stats.txt +++ b/cuda-kernels/gpgpu_inst_stats.txt @@ -1 +1,20 @@ kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence +_1.ptx 164 : 512 2560 1024 0 0 16 16 0 0 +_1.ptx 163 : 512 5696 0 0 0 0 0 0 0 +_1.ptx 162 : 512 5664 0 0 0 0 0 0 0 +_1.ptx 161 : 512 3616 0 0 0 0 0 0 0 +_1.ptx 158 : 512 3616 0 0 0 0 0 0 0 +_1.ptx 156 : 512 134048 2048 0 0 16 16 0 0 +_1.ptx 155 : 512 5632 0 0 0 0 0 0 0 +_1.ptx 154 : 512 5376 0 0 0 0 0 0 0 +_1.ptx 143 : 512 100864 128 0 0 0 0 0 0 +_1.ptx 167 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 144 : 512 100864 0 0 0 0 0 0 0 +_1.ptx 145 : 512 1536 0 0 0 0 0 0 0 +_1.ptx 146 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 147 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 148 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 149 : 512 8384 0 0 0 0 0 0 0 +_1.ptx 150 : 512 4096 0 0 0 0 0 0 0 +_1.ptx 151 : 512 0 0 0 0 0 0 0 0 +_1.ptx 153 : 512 3968 0 0 0 0 0 0 0 diff --git a/cuda-kernels/log b/cuda-kernels/log new file mode 100644 index 0000000..98df26a --- /dev/null +++ b/cuda-kernels/log @@ -0,0 +1,6328 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-03de5ae03420ba5666d669c6f76faccf2704fa58_modified_17] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 70 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 40 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,16,4 # Opcode latencies for integers Default 1,1,19,25,145,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,16,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +a9478053306cbb4803bedf0d6ea12100 /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +Running md5sum using "md5sum /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core " +Parsing file _cuobjdump_complete_output_c7ZC8M +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_70 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z17convertFp32ToFp16P6__halfPfi : hostFun 0x0x401dd7, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 70 + _1.ptx:13 => (ptx_parser.cc:175) start_function + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:13 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:13 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B32_TYPE + _1.ptx:14 => (ptx_parser.cc:189) add_function_name vprintf (extern) + _1.ptx:14 => (ptx_parser.cc:381) add_identifier "func_retval0" (0) +GPGPU-Sim PTX: allocating stack frame region for .param "func_retval0" from 0x0 to 0x4 + _1.ptx:14 => (ptx_parser.cc:144) init_directive_state + _1.ptx:15 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:15 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:15 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:15 => (ptx_parser.cc:381) add_identifier "vprintf_param_0" (1) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_0" from 0x4 to 0xc + _1.ptx:15 => (ptx_parser.cc:577) add_function_arg "vprintf_param_0" + _1.ptx:15 => (ptx_parser.cc:219) add_directive + _1.ptx:15 => (ptx_parser.cc:144) init_directive_state + _1.ptx:16 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:16 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:16 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:17 => (ptx_parser.cc:381) add_identifier "vprintf_param_1" (2) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_1" from 0xc to 0x14 + _1.ptx:17 => (ptx_parser.cc:577) add_function_arg "vprintf_param_1" + _1.ptx:17 => (ptx_parser.cc:219) add_directive + _1.ptx:17 => (ptx_parser.cc:144) init_directive_state + _1.ptx:19 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:19 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:19 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:19 => (ptx_parser.cc:331) set_variable_type space_spec=global_space scalar_type_spec=B8_TYPE + _1.ptx:19 => (ptx_parser.cc:381) add_identifier "$str" (3) +GPGPU-Sim PTX: allocating global region for "$str" from 0x100 to 0x109 (global memory space) + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:319) add_variables + _1.ptx:19 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:175) start_function + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:189) add_function_name _Z12wmma_exampleP6__halfS0_Pfiiiff (entrypoint) + _1.ptx:22 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:22 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:22 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:22 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" (4) + _1.ptx:22 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" + _1.ptx:22 => (ptx_parser.cc:219) add_directive + _1.ptx:22 => (ptx_parser.cc:144) init_directive_state + _1.ptx:23 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:23 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:23 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:23 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" (5) + _1.ptx:23 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" + _1.ptx:23 => (ptx_parser.cc:219) add_directive + _1.ptx:23 => (ptx_parser.cc:144) init_directive_state + _1.ptx:24 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:24 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:24 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:24 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" (6) + _1.ptx:24 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" + _1.ptx:24 => (ptx_parser.cc:219) add_directive + _1.ptx:24 => (ptx_parser.cc:144) init_directive_state + _1.ptx:25 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:25 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:25 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:25 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" (7) + _1.ptx:25 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" + _1.ptx:25 => (ptx_parser.cc:219) add_directive + _1.ptx:25 => (ptx_parser.cc:144) init_directive_state + _1.ptx:26 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:26 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:26 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:26 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" (8) + _1.ptx:26 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" + _1.ptx:26 => (ptx_parser.cc:219) add_directive + _1.ptx:26 => (ptx_parser.cc:144) init_directive_state + _1.ptx:27 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:27 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:27 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:27 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" (9) + _1.ptx:27 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" + _1.ptx:27 => (ptx_parser.cc:219) add_directive + _1.ptx:27 => (ptx_parser.cc:144) init_directive_state + _1.ptx:28 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:28 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:28 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:28 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" (10) + _1.ptx:28 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" + _1.ptx:28 => (ptx_parser.cc:219) add_directive + _1.ptx:28 => (ptx_parser.cc:144) init_directive_state + _1.ptx:29 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:29 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:29 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:30 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" (11) + _1.ptx:30 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" + _1.ptx:30 => (ptx_parser.cc:219) add_directive + _1.ptx:30 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:32 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:32 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:32 => (ptx_parser.cc:331) set_variable_type space_spec=local_space scalar_type_spec=B8_TYPE + _1.ptx:32 => (ptx_parser.cc:381) add_identifier "__local_depot0" (12) +GPGPU-Sim PTX: allocating stack frame region for .local "__local_depot0" from 0x0 to 0x8 + _1.ptx:32 => (ptx_parser.cc:319) add_variables + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:219) add_directive + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:33 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:33 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:33 => (ptx_parser.cc:381) add_identifier "%SP" (13) + _1.ptx:33 => (ptx_parser.cc:319) add_variables + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:219) add_directive + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:34 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:34 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:34 => (ptx_parser.cc:381) add_identifier "%SPL" (14) + _1.ptx:34 => (ptx_parser.cc:319) add_variables + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:219) add_directive + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:35 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:35 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=PRED_TYPE + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p0" (15) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p1" (16) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p2" (17) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p3" (18) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p4" (19) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p5" (20) + _1.ptx:35 => (ptx_parser.cc:319) add_variables + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:219) add_directive + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:36 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:36 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=F32_TYPE + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f0" (21) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f1" (22) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f2" (23) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f3" (24) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f4" (25) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f5" (26) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f6" (27) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f7" (28) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f8" (29) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f9" (30) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f10" (31) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f11" (32) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f12" (33) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f13" (34) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f14" (35) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f15" (36) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f16" (37) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f17" (38) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f18" (39) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f19" (40) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f20" (41) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f21" (42) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f22" (43) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f23" (44) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f24" (45) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f25" (46) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f26" (47) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f27" (48) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f28" (49) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f29" (50) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f30" (51) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f31" (52) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f32" (53) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f33" (54) + _1.ptx:36 => (ptx_parser.cc:319) add_variables + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:219) add_directive + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:37 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:37 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B32_TYPE + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r0" (55) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r1" (56) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r2" (57) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r3" (58) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r4" (59) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r5" (60) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r6" (61) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r7" (62) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r8" (63) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r9" (64) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r10" (65) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r11" (66) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r12" (67) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r13" (68) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r14" (69) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r15" (70) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r16" (71) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r17" (72) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r18" (73) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r19" (74) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r20" (75) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r21" (76) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r22" (77) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r23" (78) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r24" (79) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r25" (80) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r26" (81) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r27" (82) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r28" (83) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r29" (84) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r30" (85) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r31" (86) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r32" (87) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r33" (88) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r34" (89) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r35" (90) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r36" (91) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r37" (92) + _1.ptx:37 => (ptx_parser.cc:319) add_variables + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:219) add_directive + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:38 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:38 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd0" (93) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd1" (94) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd2" (95) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd3" (96) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd4" (97) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd5" (98) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd6" (99) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd7" (100) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd8" (101) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd9" (102) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd10" (103) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd11" (104) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd12" (105) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd13" (106) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd14" (107) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd15" (108) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd16" (109) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd17" (110) + _1.ptx:38 => (ptx_parser.cc:319) add_variables + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:219) add_directive + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:41 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:41 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:41 => (ptx_parser.cc:144) init_directive_state + _1.ptx:42 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:42 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:42 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:42 => (ptx_parser.cc:144) init_directive_state + _1.ptx:43 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:43 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:43 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:43 => (ptx_parser.cc:929) add_address_operand + _1.ptx:43 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:43 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:43 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:43 => (ptx_parser.cc:144) init_directive_state + _1.ptx:44 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:44 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:44 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:44 => (ptx_parser.cc:929) add_address_operand + _1.ptx:44 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:44 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:44 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:44 => (ptx_parser.cc:144) init_directive_state + _1.ptx:45 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:45 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:45 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:45 => (ptx_parser.cc:929) add_address_operand + _1.ptx:45 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:45 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:45 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:45 => (ptx_parser.cc:144) init_directive_state + _1.ptx:46 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:46 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:46 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:46 => (ptx_parser.cc:929) add_address_operand + _1.ptx:46 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:46 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:46 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:46 => (ptx_parser.cc:144) init_directive_state + _1.ptx:47 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:47 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:47 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:47 => (ptx_parser.cc:929) add_address_operand + _1.ptx:47 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:47 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:47 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:47 => (ptx_parser.cc:144) init_directive_state + _1.ptx:48 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:48 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:48 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:48 => (ptx_parser.cc:929) add_address_operand + _1.ptx:48 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:48 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:48 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:48 => (ptx_parser.cc:144) init_directive_state + _1.ptx:50 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:50 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:50 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:50 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:50 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:50 => (ptx_parser.cc:144) init_directive_state + _1.ptx:52 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:52 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:52 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:52 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:52 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:52 => (ptx_parser.cc:144) init_directive_state + _1.ptx:53 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:53 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:53 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:53 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:53 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:53 => (ptx_parser.cc:144) init_directive_state + _1.ptx:54 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:54 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:54 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:54 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:54 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:54 => (ptx_parser.cc:144) init_directive_state + _1.ptx:55 => (ptx_parser.cc:672) add_option + _1.ptx:55 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:55 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:55 => (ptx_parser.cc:144) init_directive_state + _1.ptx:56 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:56 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:56 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:56 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:56 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:56 => (ptx_parser.cc:144) init_directive_state + _1.ptx:57 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:295) add_instruction: div + _1.ptx:57 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:57 => (ptx_parser.cc:144) init_directive_state + _1.ptx:58 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:58 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:58 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:58 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:58 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:58 => (ptx_parser.cc:144) init_directive_state + _1.ptx:59 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:59 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:59 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:59 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:59 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:59 => (ptx_parser.cc:144) init_directive_state + _1.ptx:60 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:60 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:60 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:60 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:60 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:60 => (ptx_parser.cc:144) init_directive_state + _1.ptx:61 => (ptx_parser.cc:672) add_option + _1.ptx:61 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:61 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:61 => (ptx_parser.cc:144) init_directive_state + _1.ptx:62 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:883) add_literal_int + _1.ptx:62 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:62 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:62 => (ptx_parser.cc:144) init_directive_state + _1.ptx:63 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:883) add_literal_int + _1.ptx:63 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:63 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:63 => (ptx_parser.cc:144) init_directive_state + _1.ptx:64 => (ptx_parser.cc:672) add_option + _1.ptx:64 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:64 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:64 => (ptx_parser.cc:144) init_directive_state + _1.ptx:65 => (ptx_parser.cc:672) add_option + _1.ptx:65 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:883) add_literal_int + _1.ptx:65 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:65 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:65 => (ptx_parser.cc:144) init_directive_state + _1.ptx:66 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:66 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:66 => (ptx_parser.cc:144) init_directive_state + _1.ptx:67 => (ptx_parser.cc:672) add_option + _1.ptx:67 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:67 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:67 => (ptx_parser.cc:144) init_directive_state + _1.ptx:68 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:68 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:68 => (ptx_parser.cc:144) init_directive_state + _1.ptx:69 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:69 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:69 => (ptx_parser.cc:889) add_literal_float + _1.ptx:69 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:69 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:69 => (ptx_parser.cc:144) init_directive_state + _1.ptx:70 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:70 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:70 => (ptx_parser.cc:144) init_directive_state + _1.ptx:71 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:71 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:71 => (ptx_parser.cc:144) init_directive_state + _1.ptx:72 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:72 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:72 => (ptx_parser.cc:144) init_directive_state + _1.ptx:73 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:73 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:73 => (ptx_parser.cc:144) init_directive_state + _1.ptx:74 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:74 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:74 => (ptx_parser.cc:144) init_directive_state + _1.ptx:75 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:75 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:75 => (ptx_parser.cc:144) init_directive_state + _1.ptx:76 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:76 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:76 => (ptx_parser.cc:144) init_directive_state + _1.ptx:77 => (ptx_parser.cc:659) add_pred + _1.ptx:77 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:77 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:77 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:77 => (ptx_parser.cc:144) init_directive_state + _1.ptx:78 => (ptx_parser.cc:672) add_option + _1.ptx:78 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:78 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:78 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:78 => (ptx_parser.cc:144) init_directive_state + _1.ptx:80 => (ptx_parser.cc:643) add_label + _1.ptx:80 => (ptx_parser.cc:295) add_instruction: