From b0cf792926caf74b393a14e36de676c7afd68164 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Tue, 12 Oct 2010 00:46:24 -0800 Subject: 1. adding simt_core_cluster, which models a TPC or (for fermi) GPC... this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845] --- src/cuda-sim/instructions.cc | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/cuda-sim') diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index e67c779..1ae1919 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1082,8 +1082,6 @@ void atom_callback( const inst_t* inst, ptx_thread_info* thread ) // Write operation result into global memory // (i.e. copy src1_data to dst) thread->get_global_memory()->write(src1_data.u32,size/8,&op_result.s64,thread,pI); - gpgpu_sim *gpu = thread->get_gpu(); - gpu->decrement_atomic_count(thread->get_hw_sid(),thread->get_hw_wid()); } // atom_impl will now result in a callback being called in mem_ctrl_pop (gpu-sim.c) -- cgit v1.3