From 5236516fd0895a285aa6a204db52ec8097bbbe37 Mon Sep 17 00:00:00 2001 From: Tayler Hetherington Date: Tue, 5 Feb 2013 12:06:35 -0800 Subject: Fixing L2 WriteBack bug caused by using the partition address for both set index generation and storing tag/block address. - Added l2_cache_config class to extend the baseline - Allow custom set_index per cache. Modified L2 set_index function to use the memory partition address - Modified the cache tag to now be tag+set_index (same as the block address). Useful for more complex set index generation functions that can allow different indexes to map to the same set. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15182] --- src/gpgpu-sim/dram.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/gpgpu-sim/dram.cc') diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 745bec4..35b1d55 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -168,6 +168,8 @@ dram_req_t::dram_req_t( class mem_fetch *mf ) void dram_t::push( class mem_fetch *data ) { + assert(id == data->get_tlx_addr().chip); // Ensure request is in correct memory partition + dram_req_t *mrq = new dram_req_t(data); data->set_status(IN_PARTITION_MC_INTERFACE_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); mrqq->push(mrq); -- cgit v1.3