From 6eee7514ea8b72fbecd761c50ccfd3394edf2307 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sun, 24 Oct 2010 00:36:19 -0800 Subject: 1. adding top level configuration class and making shader and memory configuration components of this class. 2. clock memory pipeline no. subwarp times for each shader clock and increase rob-size for texture cache (trying to improve correlation, currently at 0.9218) 3. start to modify shader stats to add back features for visualizer (warp divergence distribution kind of working again) passing cuda 3.1 regression and ptxplus correlation tests [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909] --- src/gpgpu-sim/dram.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'src/gpgpu-sim/dram.cc') diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index a1187ec..9227310 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -102,9 +102,9 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m rwq = new fifo_pipeline("rwq",m_config->CL,m_config->CL+1); mrqq = new fifo_pipeline("mrqq",0,2); returnq = new fifo_pipeline("dramreturnq",0,m_config->gpgpu_dram_sched_queue_size); - m_fast_ideal_scheduler = NULL; + m_frfcfs_scheduler = NULL; if ( m_config->scheduler_type == DRAM_FRFCFS ) - m_fast_ideal_scheduler = new frfcfs_scheduler(m_config,this,stats); + m_frfcfs_scheduler = new frfcfs_scheduler(m_config,this,stats); n_cmd = 0; n_activity = 0; n_nop = 0; @@ -143,7 +143,7 @@ bool dram_t::full() const if( m_config->gpgpu_dram_sched_queue_size == 0 ) return false; if( m_config->scheduler_type == DRAM_FRFCFS ) - return m_fast_ideal_scheduler->num_pending() >= m_config->gpgpu_dram_sched_queue_size; + return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_dram_sched_queue_size; else return mrqq->full(); } @@ -152,7 +152,7 @@ unsigned dram_t::que_length() const { unsigned nreqs = 0; if (m_config->scheduler_type == DRAM_FRFCFS ) { - nreqs = m_fast_ideal_scheduler->num_pending(); + nreqs = m_frfcfs_scheduler->num_pending(); } else { nreqs = mrqq->get_length(); } @@ -199,7 +199,7 @@ void dram_t::push( class mem_fetch *data ) n_req += 1; n_req_partial += 1; if ( m_config->scheduler_type == DRAM_FRFCFS ) { - unsigned nreqs = m_fast_ideal_scheduler->num_pending(); + unsigned nreqs = m_frfcfs_scheduler->num_pending(); if ( nreqs > max_mrqs_temp) max_mrqs_temp = nreqs; } else { @@ -252,13 +252,13 @@ void dram_t::cycle() switch (m_config->scheduler_type) { case DRAM_FIFO: scheduler_fifo(); break; - case DRAM_FRFCFS: fast_scheduler_ideal(); break; + case DRAM_FRFCFS: scheduler_frfcfs(); break; default: printf("Error: Unknown DRAM scheduler type\n"); assert(0); } if ( m_config->scheduler_type == DRAM_FRFCFS ) { - unsigned nreqs = m_fast_ideal_scheduler->num_pending(); + unsigned nreqs = m_frfcfs_scheduler->num_pending(); if ( nreqs > max_mrqs) { max_mrqs = nreqs; } @@ -464,8 +464,8 @@ void dram_t::visualize() const printf("txf: %d %d", bk[i]->mrq->nbytes, bk[i]->mrq->txbytes); printf("\n"); } - if ( m_fast_ideal_scheduler ) - m_fast_ideal_scheduler->print(stdout); + if ( m_frfcfs_scheduler ) + m_frfcfs_scheduler->print(stdout); } void dram_t::print_stat( FILE* simFile ) -- cgit v1.3