From 0b65fd56c3e9c7e5d3fe22ff17b594bb84e9af69 Mon Sep 17 00:00:00 2001 From: Wilson Fung Date: Tue, 2 Aug 2011 14:25:44 -0800 Subject: Fixed the DRAM timing model to add the write-read turn and write-precharge delay. Still need to update/validate the Quadro config for this. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9921] --- src/gpgpu-sim/dram.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/gpgpu-sim/dram.h') diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index 4cbcbb3..6a28058 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -65,6 +65,7 @@ struct bank_t unsigned int RASc; unsigned int RPc; unsigned int RCc; + unsigned int WTPc; // write to precharge unsigned char rw; //is the bank reading or writing? unsigned char state; //is the bank active or idle? -- cgit v1.3