From 6eee7514ea8b72fbecd761c50ccfd3394edf2307 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sun, 24 Oct 2010 00:36:19 -0800 Subject: 1. adding top level configuration class and making shader and memory configuration components of this class. 2. clock memory pipeline no. subwarp times for each shader clock and increase rob-size for texture cache (trying to improve correlation, currently at 0.9218) 3. start to modify shader stats to add back features for visualizer (warp divergence distribution kind of working again) passing cuda 3.1 regression and ptxplus correlation tests [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909] --- src/gpgpu-sim/dram_sched.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/gpgpu-sim/dram_sched.cc') diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc index 8881e8f..9801313 100644 --- a/src/gpgpu-sim/dram_sched.cc +++ b/src/gpgpu-sim/dram_sched.cc @@ -166,10 +166,10 @@ void frfcfs_scheduler::print( FILE *fp ) } } -void dram_t::fast_scheduler_ideal() +void dram_t::scheduler_frfcfs() { unsigned mrq_latency; - frfcfs_scheduler *sched = m_fast_ideal_scheduler; + frfcfs_scheduler *sched = m_frfcfs_scheduler; while ( !mrqq->empty() && (!m_config->gpgpu_dram_sched_queue_size || sched->num_pending() < m_config->gpgpu_dram_sched_queue_size)) { dram_req_t *req = mrqq->pop(); req->data->set_status(IN_PARTITION_MC_INPUT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); -- cgit v1.3