From 58459bf7a55010eccf9940cfdb53cbc854b0989c Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sat, 16 Oct 2010 11:59:28 -0800 Subject: 1. moving address decoding into a class (and out of cache entirely) 2. moving DRAM timing parameters into memory_config class 3. removing some likely useless statistics 4. other cleaning up of code passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7868] --- src/gpgpu-sim/dram_sched.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/gpgpu-sim/dram_sched.h') diff --git a/src/gpgpu-sim/dram_sched.h b/src/gpgpu-sim/dram_sched.h index 49cae22..eaad744 100644 --- a/src/gpgpu-sim/dram_sched.h +++ b/src/gpgpu-sim/dram_sched.h @@ -76,7 +76,7 @@ class ideal_dram_scheduler { public: - ideal_dram_scheduler( dram_t *dm ); + ideal_dram_scheduler( const memory_config *config, dram_t *dm, memory_stats_t *stats ); void add_req( dram_req_t *req ); std::list::iterator binarysort_VFTF(dram_req_t *req); std::list::iterator sort_VFTF(dram_req_t *req); @@ -86,7 +86,7 @@ public: unsigned num_pending() const { return m_num_pending;} private: - + const memory_config *m_config; dram_t *m_dram; unsigned m_num_pending; std::list *m_queue; @@ -94,6 +94,8 @@ private: std::list::iterator> **m_last_row; unsigned *curr_row_service_time; //one set of variables for each bank. unsigned *row_service_timestamp; //tracks when scheduler began servicing current row + + memory_stats_t *m_stats; }; #endif -- cgit v1.3