From 87e4da5fc6086c3d0a661af1929255a8cbd728d7 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Mon, 18 Oct 2010 02:43:17 -0800 Subject: Re-designed cache model: - read only cache model with integrated mshrs (no L1D, yet); new cache interface should be easily extendable to support texture cache with latency fifo and separate tag/data arrays, though this is not yet added (currently tags and data arrays are not decoupled for texture) - new partition model using the above removes all old MSHRs, L1D etc... passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875] --- src/gpgpu-sim/dram_sched.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'src/gpgpu-sim/dram_sched.h') diff --git a/src/gpgpu-sim/dram_sched.h b/src/gpgpu-sim/dram_sched.h index eaad744..9f99209 100644 --- a/src/gpgpu-sim/dram_sched.h +++ b/src/gpgpu-sim/dram_sched.h @@ -74,13 +74,11 @@ #include #include -class ideal_dram_scheduler { +class frfcfs_scheduler { public: - ideal_dram_scheduler( const memory_config *config, dram_t *dm, memory_stats_t *stats ); + frfcfs_scheduler( const memory_config *config, dram_t *dm, memory_stats_t *stats ); void add_req( dram_req_t *req ); - std::list::iterator binarysort_VFTF(dram_req_t *req); - std::list::iterator sort_VFTF(dram_req_t *req); - inline void data_collection(unsigned bank); + void data_collection(unsigned bank); dram_req_t *schedule( unsigned bank, unsigned curr_row ); void print( FILE *fp ); unsigned num_pending() const { return m_num_pending;} -- cgit v1.3