From 36ce0f2243fd0723a746b3c2f5f0651577312400 Mon Sep 17 00:00:00 2001 From: Tayler Hetherington Date: Fri, 30 Nov 2012 21:29:42 -0800 Subject: Merging Power model into Fermi //depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723] --- src/gpgpu-sim/gpu-cache.cc | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) (limited to 'src/gpgpu-sim/gpu-cache.cc') diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index fc2d032..3f44eea 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -201,6 +201,13 @@ void tag_array::print( FILE *stream, unsigned &total_access, unsigned &total_mis total_access+=m_access; } +void tag_array::get_stats(unsigned &total_access, unsigned &total_misses) const{ + // Get the access and miss counts from the tag array + total_misses = m_miss; + total_access = m_access; +} + + bool was_write_sent( const std::list &events ) { for( std::list::const_iterator e=events.begin(); e!=events.end(); e++ ) { @@ -293,6 +300,7 @@ void baseline_cache::cycle(){ if ( !m_memport->full(mf->get_data_size(),mf->get_is_write()) ) { m_miss_queue.pop_front(); m_memport->push(mf); + n_simt_to_mem+=mf->get_num_flits(true); // Interconnect power stats } } } @@ -393,6 +401,7 @@ cache_request_status data_cache::wr_hit_wb(new_addr_type addr, unsigned cache_in cache_block_t &block = m_tag_array.get_block(cache_index); block.m_status = MODIFIED; + m_write_access++; return HIT; } @@ -409,6 +418,7 @@ cache_request_status data_cache::wr_hit_wt(new_addr_type addr, unsigned cache_in // generate a write-through send_write_request(mf, WRITE_REQUEST_SENT, time, events); + m_write_access++; return HIT; } @@ -423,6 +433,8 @@ cache_request_status data_cache::wr_hit_we(new_addr_type addr, unsigned cache_in // Invalidate block block.m_status = INVALID; + + m_write_access++; return HIT; } @@ -481,8 +493,11 @@ enum cache_request_status data_cache::wr_miss_wa(new_addr_type addr, unsigned ca m_miss_queue.push_back(wb); wb->set_status(m_miss_queue_status,time); } - if( do_miss ) + if( do_miss ){ + m_write_access++; + m_write_miss++; return MISS; + } return RESERVATION_FAIL; } @@ -494,6 +509,9 @@ enum cache_request_status data_cache::wr_miss_no_wa(new_addr_type addr, unsigned // on miss, generate write through (no write buffering -- too many threads for that) send_write_request(mf, WRITE_REQUEST_SENT, time, events); + + m_write_access++; + m_write_miss++; return MISS; } @@ -508,6 +526,8 @@ enum cache_request_status data_cache::rd_hit_base(new_addr_type addr, unsigned c cache_block_t &block = m_tag_array.get_block(cache_index); block.m_status = MODIFIED; // mark line as dirty } + + m_read_access++; return HIT; } @@ -528,8 +548,11 @@ enum cache_request_status data_cache::rd_miss_base(new_addr_type addr, unsigned mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr, L1_WRBK_ACC,m_config.get_line_sz(),true); send_write_request(wb, WRITE_BACK_REQUEST_SENT, time, events); } - if( do_miss ) + if( do_miss ){ + m_read_access++; + m_read_miss++; return MISS; + } return RESERVATION_FAIL; } @@ -565,7 +588,6 @@ enum cache_request_status l1_cache::access( new_addr_type addr, mem_fetch *mf, u unsigned cache_index = (unsigned)-1; enum cache_request_status status = m_tag_array.probe(block_addr,cache_index); - // Each function pointer ( m_[rd/wr]_[hit/miss] ) is set in the data_cache constructor to reflect the corresponding cache configuration options. // Function pointers were used to avoid many long conditional branches resulting from many cache configuration options. if(wr){ // Write @@ -652,6 +674,7 @@ void tex_cache::cycle(){ if ( !m_memport->full(mf->get_ctrl_size(),false) ) { m_request_fifo.pop(); m_memport->push(mf); + n_simt_to_mem+=mf->get_num_flits(true); // Interconnect power stats } } // read ready lines from cache -- cgit v1.3