From c2a1e3a668f9a88239184e13460f7e1725b15c90 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 26 Aug 2019 12:17:52 -0400 Subject: Banked L1, adding iSLIP and RR arbiteratio and adding some comments --- src/gpgpu-sim/gpu-cache.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/gpgpu-sim/gpu-cache.cc') diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 370f6e6..db9701d 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -63,6 +63,14 @@ const char * cache_fail_status_str(enum cache_reservation_fail_reason status) return static_cache_reservation_fail_reason_str[status]; } +unsigned l1d_cache_config::set_bank(new_addr_type addr) const{ + + if(m_cache_type == SECTOR) + return (addr >> m_sector_sz_log2) & (l1_banks-1); + else + return (addr >> m_line_sz_log2) & (l1_banks-1); +} + unsigned l1d_cache_config::set_index(new_addr_type addr) const{ unsigned set_index = m_nset; // Default to linear set index function unsigned lower_xor = 0; -- cgit v1.3