From c2a1e3a668f9a88239184e13460f7e1725b15c90 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 26 Aug 2019 12:17:52 -0400 Subject: Banked L1, adding iSLIP and RR arbiteratio and adding some comments --- src/gpgpu-sim/gpu-cache.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/gpgpu-sim/gpu-cache.h') diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 337f710..90adbb5 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -584,6 +584,7 @@ public: m_nset_log2 = LOGB2(m_nset); m_valid = true; m_atom_sz = (m_cache_type == SECTOR)? SECTOR_SIZE : m_line_sz; + m_sector_sz_log2 = LOGB2(SECTOR_SIZE); original_m_assoc = m_assoc; //For more details about difference between FETCH_ON_WRITE and WRITE VALIDAE policies @@ -734,6 +735,7 @@ protected: unsigned m_nset_log2; unsigned m_assoc; unsigned m_atom_sz; + unsigned m_sector_sz_log2; unsigned original_m_assoc; bool m_is_streaming; @@ -775,7 +777,9 @@ class l1d_cache_config : public cache_config{ public: l1d_cache_config() : cache_config(){} virtual unsigned set_index(new_addr_type addr) const; + unsigned set_bank(new_addr_type addr) const; unsigned l1_latency; + unsigned l1_banks; }; class l2_cache_config : public cache_config { -- cgit v1.3