From 0b65fd56c3e9c7e5d3fe22ff17b594bb84e9af69 Mon Sep 17 00:00:00 2001 From: Wilson Fung Date: Tue, 2 Aug 2011 14:25:44 -0800 Subject: Fixed the DRAM timing model to add the write-read turn and write-precharge delay. Still need to update/validate the Quadro config for this. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9921] --- src/gpgpu-sim/gpu-sim.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 243574e..d29247c 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -123,8 +123,8 @@ void memory_config::reg_options(class OptionParser * opp) "Burst length of each DRAM request (default = 4 DDR cycle)", "4"); option_parser_register(opp, "-gpgpu_dram_timing_opt", OPT_CSTR, &gpgpu_dram_timing_opt, - "DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tWTR}", - "4:2:8:12:21:13:34:9:4:5"); + "DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR}", + "4:2:8:12:21:13:34:9:4:5:13"); m_address_mapping.addrdec_setoption(opp); } -- cgit v1.3