From 13f07a2c820422db7e4e88e43d692dfe8e1b8cad Mon Sep 17 00:00:00 2001 From: Nick Date: Tue, 19 Feb 2019 18:40:45 -0500 Subject: Add initial infrastrucutre to support L2 (and other) cache statistics for AerialVision --- src/gpgpu-sim/gpu-sim.cc | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index ec570bf..c253367 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1148,6 +1148,9 @@ void gpgpu_sim::gpu_print_stat() cache_stats l2_stats; struct cache_sub_stats l2_css; struct cache_sub_stats total_l2_css; + cache_stats l2_stats_pw; + struct cache_sub_stats l2_css_pw; + struct cache_sub_stats total_l2_css_pw; l2_stats.clear(); l2_css.clear(); total_l2_css.clear(); @@ -1156,11 +1159,15 @@ void gpgpu_sim::gpu_print_stat() for (unsigned i=0;im_n_mem_sub_partition;i++){ m_memory_sub_partition[i]->accumulate_L2cache_stats(l2_stats); m_memory_sub_partition[i]->get_L2cache_sub_stats(l2_css); + m_memory_sub_partition[i]->get_L2cache_sub_stats_pw(l2_css_pw); fprintf( stdout, "L2_cache_bank[%d]: Access = %u, Miss = %u, Miss_rate = %.3lf, Pending_hits = %u, Reservation_fails = %u\n", i, l2_css.accesses, l2_css.misses, (double)l2_css.misses / (double)l2_css.accesses, l2_css.pending_hits, l2_css.res_fails); + fprintf( stdout, "L2_cache_bank[%d]: Access = %u, Miss = %u, Miss_rate = %.3lf, Pending_hits = %u, Reservation_fails = %u\n", + i, l2_css_pw.accesses, l2_css_pw.misses, (double)l2_css_pw.misses / (double)l2_css_pw.accesses, l2_css_pw.pending_hits, l2_css_pw.res_fails); total_l2_css += l2_css; + total_l2_css_pw += l2_css_pw; } if (!m_memory_config->m_L2_config.disabled() && m_memory_config->m_L2_config.get_num_lines()) { //L2c_print_cache_stat(); -- cgit v1.3