From 960a1492fbbf2a4d098c8d060bc22782211ca60b Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Tue, 10 Apr 2018 14:52:49 -0500 Subject: added config -gpgpu_shmem_per_block and fixed cudaGetDeviceAttributes function --- src/gpgpu-sim/gpu-sim.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 3829861..5d63ab7 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -265,6 +265,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_n_ldst_response_buffer_size", OPT_UINT32, &ldst_unit_response_queue_size, "number of response packets in ld/st unit ejection buffer", "2"); + option_parser_register(opp, "-gpgpu_shmem_per_block", OPT_UINT32, &gpgpu_shmem_per_block, + "Size of shared memory per thread block or CTA (default 48kB)", + "49152"); option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); @@ -661,6 +664,11 @@ int gpgpu_sim::shared_mem_size() const return m_shader_config->gpgpu_shmem_size; } +int gpgpu_sim::shared_mem_per_block() const +{ + return m_shader_config->gpgpu_shmem_per_block; +} + int gpgpu_sim::num_registers_per_core() const { return m_shader_config->gpgpu_shader_registers; -- cgit v1.3 From 70e036c6007135c43d213139e1a6963090721f59 Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Tue, 1 May 2018 14:58:35 -0500 Subject: Added support for -gpgpu_registers_per_block config --- libcuda/cuda_runtime_api.cc | 27 ++++++++------------------- src/gpgpu-sim/gpu-sim.cc | 8 ++++++++ src/gpgpu-sim/gpu-sim.h | 1 + src/gpgpu-sim/shader.h | 1 + 4 files changed, 18 insertions(+), 19 deletions(-) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index ef46f00..e3c2542 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -349,24 +349,13 @@ class _cuda_device_id *GPGPUSim_Init() prop->maxGridSize[2] = 0x40000000; prop->totalConstMem = 0x40000000; prop->textureAlignment = 0; - /* - - * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock. - - * Previously, this was thought as sharedMemPerMultiprocessor and is being used in many places. - - * Check whether all the instances of shared_mem_size(), gpgpu_shmem_size or sharedMemPerBlock are meant to use sharedMemPerBlock or sharedMemPerMultiprocessor. - - */ - - prop->sharedMemPerBlock = the_gpu->shared_mem_per_block(); - - #if (CUDART_VERSION > 5000) - - prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); - - #endif - +// * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock and regsPerBlock + prop->sharedMemPerBlock = the_gpu->shared_mem_per_block(); +#if (CUDART_VERSION > 5000) + prop->regsPerMultiprocessor = the_gpu->num_registers_per_core(); + prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); +#endif + prop->sharedMemPerBlock = the_gpu->shared_mem_per_block(); prop->regsPerBlock = the_gpu->num_registers_per_core(); prop->warpSize = the_gpu->wrp_size(); prop->clockRate = the_gpu->shader_clock(); @@ -912,7 +901,7 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic *value= prop->sharedMemPerMultiprocessor; break; case 82: - *value= prop->regsPerBlock; + *value= prop->regsPerMultiprocessor; break; default: printf("ERROR: Attribute number %d unimplemented \n",attr); diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 5d63ab7..b283964 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -247,6 +247,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shader_registers", OPT_UINT32, &gpgpu_shader_registers, "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); + option_parser_register(opp, "-gpgpu_registers_per_block", OPT_UINT32, &gpgpu_registers_per_block, + "Maximum number of registers per thread block. (default 8192)", + "8192"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", "8"); @@ -674,6 +677,11 @@ int gpgpu_sim::num_registers_per_core() const return m_shader_config->gpgpu_shader_registers; } +int gpgpu_sim::num_registers_per_block() const +{ + return m_shader_config->gpgpu_registers_per_block; +} + int gpgpu_sim::wrp_size() const { return m_shader_config->warp_size; diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 8d1c4fc..5908fd5 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -391,6 +391,7 @@ public: int shared_mem_size() const; int shared_mem_per_block() const; int num_registers_per_core() const; + int num_registers_per_block() const; int wrp_size() const; int shader_clock() const; const struct cudaDeviceProp *get_prop() const; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index fbddd18..6201840 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1286,6 +1286,7 @@ struct shader_core_config : public core_config unsigned max_barriers_per_cta; char * gpgpu_scheduler_string; unsigned gpgpu_shmem_per_block; + unsigned gpgpu_registers_per_block; char* pipeline_widths_string; int pipe_widths[N_PIPELINE_STAGES]; -- cgit v1.3 From f405cb9484a8b0f961bd7c143bebf1fcb17546da Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Wed, 2 May 2018 12:23:59 -0500 Subject: Minor change in config description --- src/gpgpu-sim/gpu-sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index b283964..07a0c57 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -248,7 +248,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); option_parser_register(opp, "-gpgpu_registers_per_block", OPT_UINT32, &gpgpu_registers_per_block, - "Maximum number of registers per thread block. (default 8192)", + "Maximum number of registers per CTA. (default 8192)", "8192"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", -- cgit v1.3